1 /*
2 * tc35874x - Toshiba HDMI to CSI-2 bridge
3 *
4 * Copyright 2015 Cisco Systems, Inc. and/or its affiliates. All rights
5 * reserved.
6 *
7 * This program is free software; you may redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
12 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
13 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
14 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
15 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
16 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
17 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
18 * SOFTWARE.
19 *
20 */
21
22 /*
23 * References (c = chapter, p = page):
24 * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60
25 * REF_02 - Toshiba, TC358743XBG_HDMI-CSI_Tv11p_nm.xls
26 * REF_02 - Toshiba, TC358749XBG (H2C+), Functional Specification, Rev 0.74
27 */
28
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/slab.h>
32 #include <linux/i2c.h>
33 #include <linux/clk.h>
34 #include <linux/delay.h>
35 #include <linux/gpio/consumer.h>
36 #include <linux/interrupt.h>
37 #include <linux/timer.h>
38 #include <linux/of_graph.h>
39 #include <linux/videodev2.h>
40 #include <linux/workqueue.h>
41 #include <linux/v4l2-dv-timings.h>
42 #include <linux/hdmi.h>
43 #include <linux/version.h>
44 #include <linux/compat.h>
45 #include <linux/rk-camera-module.h>
46 #include <media/v4l2-dv-timings.h>
47 #include <media/v4l2-device.h>
48 #include <media/v4l2-ctrls.h>
49 #include <media/v4l2-event.h>
50 #include <media/v4l2-fwnode.h>
51 #include <media/tc35874x.h>
52
53 #include "tc35874x_regs.h"
54
55 static int debug;
56 module_param(debug, int, 0644);
57 MODULE_PARM_DESC(debug, "debug level (0-3)");
58
59 MODULE_DESCRIPTION("Toshiba TC35874X HDMI to CSI-2 bridge driver");
60 MODULE_AUTHOR("Ramakrishnan Muthukrishnan <ram@rkrishnan.org>");
61 MODULE_AUTHOR("Mikhail Khelik <mkhelik@cisco.com>");
62 MODULE_AUTHOR("Mats Randgaard <matrandg@cisco.com>");
63 MODULE_LICENSE("GPL");
64
65 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x1)
66
67 #define EDID_NUM_BLOCKS_MAX 8
68 #define EDID_BLOCK_SIZE 128
69
70 #define I2C_MAX_XFER_SIZE (EDID_BLOCK_SIZE + 2)
71
72 #define POLL_INTERVAL_CEC_MS 10
73 #define POLL_INTERVAL_MS 1000
74
75 /* PIXEL_RATE = MIPI_FREQ * 2 * lane / 8bit */
76 #define TC35874X_LINK_FREQ_310MHZ 310000000
77 #define TC35874X_PIXEL_RATE_310M TC35874X_LINK_FREQ_310MHZ
78
79 #define TC35874X_NAME "tc35874x"
80
81 static const s64 link_freq_menu_items[] = {
82 TC35874X_LINK_FREQ_310MHZ,
83 };
84
85 static const struct v4l2_dv_timings_cap tc35874x_timings_cap = {
86 .type = V4L2_DV_BT_656_1120,
87 /* keep this initialization for compatibility with GCC < 4.4.6 */
88 .reserved = { 0 },
89 /* Pixel clock from REF_01 p. 20. Min/max height/width are unknown */
90 V4L2_INIT_BT_TIMINGS(1, 10000, 1, 10000, 0, 310000000,
91 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
92 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
93 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_INTERLACED |
94 V4L2_DV_BT_CAP_REDUCED_BLANKING |
95 V4L2_DV_BT_CAP_CUSTOM)
96 };
97
98 static u8 EDID_1920x1080_60[] = {
99 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
100 0x52, 0x62, 0x01, 0x88, 0x00, 0x88, 0x88, 0x88,
101 0x1C, 0x15, 0x01, 0x03, 0x80, 0x00, 0x00, 0x78,
102 0x0A, 0x0D, 0xC9, 0xA0, 0x57, 0x47, 0x98, 0x27,
103 0x12, 0x48, 0x4C, 0x00, 0x00, 0x00, 0x01, 0x01,
104 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
105 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x3A,
106 0x80, 0x18, 0x71, 0x38, 0x2D, 0x40, 0x58, 0x2C,
107 0x45, 0x00, 0xC4, 0x8E, 0x21, 0x00, 0x00, 0x1E,
108 0x01, 0x1D, 0x00, 0x72, 0x51, 0xD0, 0x1E, 0x20,
109 0x6E, 0x28, 0x55, 0x00, 0xC4, 0x8E, 0x21, 0x00,
110 0x00, 0x1E, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x54,
111 0x37, 0x34, 0x39, 0x2D, 0x66, 0x48, 0x44, 0x37,
112 0x32, 0x30, 0x0A, 0x20, 0x00, 0x00, 0x00, 0xFD,
113 0x00, 0x14, 0x78, 0x01, 0xFF, 0x1D, 0x00, 0x0A,
114 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x01, 0x7B,
115 };
116
117 static u8 EDID_extend[] = {
118 0x02, 0x03, 0x1A, 0x71, 0x47, 0x90, 0x04, 0x02,
119 0x01, 0x11, 0x22, 0x05, 0x23, 0x09, 0x07, 0x01,
120 0x83, 0x01, 0x00, 0x00, 0x65, 0x03, 0x0C, 0x00,
121 0x10, 0x00, 0x8C, 0x0A, 0xD0, 0x8A, 0x20, 0xE0,
122 0x2D, 0x10, 0x10, 0x3E, 0x96, 0x00, 0x13, 0x8E,
123 0x21, 0x00, 0x00, 0x1E, 0xD8, 0x09, 0x80, 0xA0,
124 0x20, 0xE0, 0x2D, 0x10, 0x10, 0x60, 0xA2, 0x00,
125 0xC4, 0x8E, 0x21, 0x00, 0x00, 0x18, 0x8C, 0x0A,
126 0xD0, 0x90, 0x20, 0x40, 0x31, 0x20, 0x0C, 0x40,
127 0x55, 0x00, 0x48, 0x39, 0x00, 0x00, 0x00, 0x18,
128 0x01, 0x1D, 0x80, 0x18, 0x71, 0x38, 0x2D, 0x40,
129 0x58, 0x2C, 0x45, 0x00, 0xC0, 0x6C, 0x00, 0x00,
130 0x00, 0x18, 0x01, 0x1D, 0x80, 0x18, 0x71, 0x1C,
131 0x16, 0x20, 0x58, 0x2C, 0x25, 0x00, 0xC0, 0x6C,
132 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00,
133 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x32,
134 };
135
136 struct tc35874x_mode {
137 u32 width;
138 u32 height;
139 struct v4l2_fract max_fps;
140 u32 hts_def;
141 u32 vts_def;
142 u32 exp_def;
143 };
144
145 static const struct tc35874x_mode supported_modes[] = {
146 {
147 .width = 1920,
148 .height = 1080,
149 .max_fps = {
150 .numerator = 10000,
151 .denominator = 600000,
152 },
153 .exp_def = 0x470,
154 .hts_def = 0x898,
155 .vts_def = 0x465,
156 }, {
157 .width = 1280,
158 .height = 720,
159 .max_fps = {
160 .numerator = 10000,
161 .denominator = 600000,
162 },
163 .exp_def = 0x2f0,
164 .hts_def = 0x672,
165 .vts_def = 0x2ee,
166 }, {
167 .width = 720,
168 .height = 576,
169 .max_fps = {
170 .numerator = 10000,
171 .denominator = 500000,
172 },
173 .exp_def = 0x275,
174 .hts_def = 0x360,
175 .vts_def = 0x271,
176 }, {
177 .width = 720,
178 .height = 480,
179 .max_fps = {
180 .numerator = 10000,
181 .denominator = 600000,
182 },
183 .exp_def = 0x210,
184 .hts_def = 0x35a,
185 .vts_def = 0x20d,
186 },
187 };
188
189 struct tc35874x_state {
190 struct tc35874x_platform_data pdata;
191 struct v4l2_fwnode_bus_mipi_csi2 bus;
192 struct v4l2_subdev sd;
193 struct media_pad pad;
194 struct v4l2_ctrl_handler hdl;
195 struct i2c_client *i2c_client;
196 /* CONFCTL is modified in ops and tc35874x_hdmi_sys_int_handler */
197 struct mutex confctl_mutex;
198
199 /* controls */
200 struct v4l2_ctrl *detect_tx_5v_ctrl;
201 struct v4l2_ctrl *audio_sampling_rate_ctrl;
202 struct v4l2_ctrl *audio_present_ctrl;
203
204 struct delayed_work delayed_work_enable_hotplug;
205
206 struct timer_list timer;
207 struct work_struct work_i2c_poll;
208
209 /* edid */
210 u8 edid_blocks_written;
211
212 struct v4l2_dv_timings timings;
213 u32 mbus_fmt_code;
214 u8 csi_lanes_in_use;
215
216 struct gpio_desc *reset_gpio;
217 struct cec_adapter *cec_adap;
218
219 u32 module_index;
220 const char *module_facing;
221 const char *module_name;
222 const char *len_name;
223 struct v4l2_ctrl *link_freq;
224 struct v4l2_ctrl *pixel_rate;
225 const struct tc35874x_mode *cur_mode;
226 };
227
228 static void tc35874x_enable_interrupts(struct v4l2_subdev *sd,
229 bool cable_connected);
230 static int tc35874x_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd);
231 static int tc35874x_s_dv_timings(struct v4l2_subdev *sd,
232 struct v4l2_dv_timings *timings);
233
to_state(struct v4l2_subdev * sd)234 static inline struct tc35874x_state *to_state(struct v4l2_subdev *sd)
235 {
236 return container_of(sd, struct tc35874x_state, sd);
237 }
238
239 /* --------------- I2C --------------- */
240
i2c_rd(struct v4l2_subdev * sd,u16 reg,u8 * values,u32 n)241 static void i2c_rd(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
242 {
243 struct tc35874x_state *state = to_state(sd);
244 struct i2c_client *client = state->i2c_client;
245 int err;
246 u8 buf[2] = { reg >> 8, reg & 0xff };
247 struct i2c_msg msgs[] = {
248 {
249 .addr = client->addr,
250 .flags = 0,
251 .len = 2,
252 .buf = buf,
253 },
254 {
255 .addr = client->addr,
256 .flags = I2C_M_RD,
257 .len = n,
258 .buf = values,
259 },
260 };
261
262 err = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
263 if (err != ARRAY_SIZE(msgs)) {
264 v4l2_err(sd, "%s: reading register 0x%x from 0x%x failed\n",
265 __func__, reg, client->addr);
266 }
267 }
268
i2c_wr(struct v4l2_subdev * sd,u16 reg,u8 * values,u32 n)269 static void i2c_wr(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
270 {
271 struct tc35874x_state *state = to_state(sd);
272 struct i2c_client *client = state->i2c_client;
273 int err, i;
274 struct i2c_msg msg;
275 u8 data[I2C_MAX_XFER_SIZE];
276
277 if ((2 + n) > I2C_MAX_XFER_SIZE) {
278 n = I2C_MAX_XFER_SIZE - 2;
279 v4l2_warn(sd, "i2c wr reg=%04x: len=%d is too big!\n",
280 reg, 2 + n);
281 }
282
283 msg.addr = client->addr;
284 msg.buf = data;
285 msg.len = 2 + n;
286 msg.flags = 0;
287
288 data[0] = reg >> 8;
289 data[1] = reg & 0xff;
290
291 for (i = 0; i < n; i++)
292 data[2 + i] = values[i];
293
294 err = i2c_transfer(client->adapter, &msg, 1);
295 if (err != 1) {
296 v4l2_err(sd, "%s: writing register 0x%x from 0x%x failed\n",
297 __func__, reg, client->addr);
298 return;
299 }
300
301 if (debug < 3)
302 return;
303
304 switch (n) {
305 case 1:
306 v4l2_info(sd, "I2C write 0x%04x = 0x%02x\n",
307 reg, data[2]);
308 break;
309 case 2:
310 v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x\n",
311 reg, data[3], data[2]);
312 break;
313 case 4:
314 v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x%02x%02x\n",
315 reg, data[5], data[4], data[3], data[2]);
316 break;
317 default:
318 v4l2_info(sd, "I2C write %d bytes from address 0x%04x\n",
319 n, reg);
320 }
321 }
322
i2c_rdreg(struct v4l2_subdev * sd,u16 reg,u32 n)323 static noinline u32 i2c_rdreg(struct v4l2_subdev *sd, u16 reg, u32 n)
324 {
325 __le32 val = 0;
326
327 i2c_rd(sd, reg, (u8 __force *)&val, n);
328
329 return le32_to_cpu(val);
330 }
331
i2c_wrreg(struct v4l2_subdev * sd,u16 reg,u32 val,u32 n)332 static noinline void i2c_wrreg(struct v4l2_subdev *sd, u16 reg, u32 val, u32 n)
333 {
334 __le32 raw = cpu_to_le32(val);
335
336 i2c_wr(sd, reg, (u8 __force *)&raw, n);
337 }
338
i2c_rd8(struct v4l2_subdev * sd,u16 reg)339 static u8 i2c_rd8(struct v4l2_subdev *sd, u16 reg)
340 {
341 return i2c_rdreg(sd, reg, 1);
342 }
343
i2c_wr8(struct v4l2_subdev * sd,u16 reg,u8 val)344 static void i2c_wr8(struct v4l2_subdev *sd, u16 reg, u8 val)
345 {
346 i2c_wrreg(sd, reg, val, 1);
347 }
348
i2c_wr8_and_or(struct v4l2_subdev * sd,u16 reg,u8 mask,u8 val)349 static void i2c_wr8_and_or(struct v4l2_subdev *sd, u16 reg,
350 u8 mask, u8 val)
351 {
352 i2c_wrreg(sd, reg, (i2c_rdreg(sd, reg, 1) & mask) | val, 1);
353 }
354
i2c_rd16(struct v4l2_subdev * sd,u16 reg)355 static u16 i2c_rd16(struct v4l2_subdev *sd, u16 reg)
356 {
357 return i2c_rdreg(sd, reg, 2);
358 }
359
i2c_wr16(struct v4l2_subdev * sd,u16 reg,u16 val)360 static void i2c_wr16(struct v4l2_subdev *sd, u16 reg, u16 val)
361 {
362 i2c_wrreg(sd, reg, val, 2);
363 }
364
i2c_wr16_and_or(struct v4l2_subdev * sd,u16 reg,u16 mask,u16 val)365 static void i2c_wr16_and_or(struct v4l2_subdev *sd, u16 reg, u16 mask, u16 val)
366 {
367 i2c_wrreg(sd, reg, (i2c_rdreg(sd, reg, 2) & mask) | val, 2);
368 }
369
i2c_rd32(struct v4l2_subdev * sd,u16 reg)370 static u32 i2c_rd32(struct v4l2_subdev *sd, u16 reg)
371 {
372 return i2c_rdreg(sd, reg, 4);
373 }
374
i2c_wr32(struct v4l2_subdev * sd,u16 reg,u32 val)375 static void i2c_wr32(struct v4l2_subdev *sd, u16 reg, u32 val)
376 {
377 i2c_wrreg(sd, reg, val, 4);
378 }
379
380 /* --------------- STATUS --------------- */
381
is_hdmi(struct v4l2_subdev * sd)382 static inline bool is_hdmi(struct v4l2_subdev *sd)
383 {
384 return i2c_rd8(sd, SYS_STATUS) & MASK_S_HDMI;
385 }
386
tx_5v_power_present(struct v4l2_subdev * sd)387 static inline bool tx_5v_power_present(struct v4l2_subdev *sd)
388 {
389 return i2c_rd8(sd, SYS_STATUS) & MASK_S_DDC5V;
390 }
391
no_signal(struct v4l2_subdev * sd)392 static inline bool no_signal(struct v4l2_subdev *sd)
393 {
394 return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_TMDS);
395 }
396
no_sync(struct v4l2_subdev * sd)397 static inline bool no_sync(struct v4l2_subdev *sd)
398 {
399 return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_SYNC);
400 }
401
audio_present(struct v4l2_subdev * sd)402 static inline bool audio_present(struct v4l2_subdev *sd)
403 {
404 return i2c_rd8(sd, AU_STATUS0) & MASK_S_A_SAMPLE;
405 }
406
get_audio_sampling_rate(struct v4l2_subdev * sd)407 static int get_audio_sampling_rate(struct v4l2_subdev *sd)
408 {
409 static const int code_to_rate[] = {
410 44100, 0, 48000, 32000, 22050, 384000, 24000, 352800,
411 88200, 768000, 96000, 705600, 176400, 0, 192000, 0
412 };
413
414 /* Register FS_SET is not cleared when the cable is disconnected */
415 if (no_signal(sd))
416 return 0;
417
418 return code_to_rate[i2c_rd8(sd, FS_SET) & MASK_FS];
419 }
420
421 /* --------------- TIMINGS --------------- */
422
fps(const struct v4l2_bt_timings * t)423 static inline unsigned fps(const struct v4l2_bt_timings *t)
424 {
425 if (!V4L2_DV_BT_FRAME_HEIGHT(t) || !V4L2_DV_BT_FRAME_WIDTH(t))
426 return 0;
427
428 return DIV_ROUND_CLOSEST((unsigned)t->pixelclock,
429 V4L2_DV_BT_FRAME_HEIGHT(t) * V4L2_DV_BT_FRAME_WIDTH(t));
430 }
431
tc35874x_get_detected_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)432 static int tc35874x_get_detected_timings(struct v4l2_subdev *sd,
433 struct v4l2_dv_timings *timings)
434 {
435 struct v4l2_bt_timings *bt = &timings->bt;
436 unsigned width, height, frame_width, frame_height, frame_interval, fps;
437 struct tc35874x_state *state = to_state(sd);
438 u16 fifo_level;
439
440 memset(timings, 0, sizeof(struct v4l2_dv_timings));
441
442 if (no_signal(sd)) {
443 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
444 return -ENOLINK;
445 }
446 if (no_sync(sd)) {
447 v4l2_dbg(1, debug, sd, "%s: no sync on signal\n", __func__);
448 return -ENOLCK;
449 }
450
451 timings->type = V4L2_DV_BT_656_1120;
452 bt->interlaced = i2c_rd8(sd, VI_STATUS1) & MASK_S_V_INTERLACE ?
453 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
454
455 width = ((i2c_rd8(sd, DE_WIDTH_H_HI) & 0x1f) << 8) +
456 i2c_rd8(sd, DE_WIDTH_H_LO);
457 height = ((i2c_rd8(sd, DE_WIDTH_V_HI) & 0x1f) << 8) +
458 i2c_rd8(sd, DE_WIDTH_V_LO);
459 frame_width = ((i2c_rd8(sd, H_SIZE_HI) & 0x1f) << 8) +
460 i2c_rd8(sd, H_SIZE_LO);
461 frame_height = (((i2c_rd8(sd, V_SIZE_HI) & 0x3f) << 8) +
462 i2c_rd8(sd, V_SIZE_LO)) / 2;
463 /* frame interval in milliseconds * 10
464 * Require SYS_FREQ0 and SYS_FREQ1 are precisely set */
465 frame_interval = ((i2c_rd8(sd, FV_CNT_HI) & 0x3) << 8) +
466 i2c_rd8(sd, FV_CNT_LO);
467 fps = (frame_interval > 0) ?
468 DIV_ROUND_CLOSEST(10000, frame_interval) : 0;
469
470 bt->width = width;
471 bt->height = height;
472 bt->vsync = frame_height - height;
473 bt->hsync = frame_width - width;
474 bt->pixelclock = frame_width * frame_height * fps;
475 if (bt->interlaced == V4L2_DV_INTERLACED) {
476 bt->height *= 2;
477 bt->il_vsync = bt->vsync + 1;
478 bt->pixelclock /= 2;
479
480 /* frame count number: FS = FE 1,2,1,2... */
481 i2c_wr16(sd, FCCTL, 0x0002);
482 /* packet id for interlace mode only */
483 i2c_wr16(sd, PACKETID1, 0x1e1e);
484 } else {
485 i2c_wr16(sd, FCCTL, 0);
486 }
487
488 if (state->csi_lanes_in_use == 4) {
489 if ((width == 1920 && height == 1080) ||
490 (width == 1280 && height == 720)) {
491 fifo_level = 370;
492 } else if ((width == 720 && height == 576) ||
493 (width == 720 && height == 480)) {
494 fifo_level = 350;
495 } else {
496 fifo_level = 300;
497 }
498
499 if ((bt->interlaced == V4L2_DV_INTERLACED) || (fps <= 33))
500 fifo_level = 300;
501
502 v4l2_dbg(2, debug, sd, "%s interlaced:%d, fifo_level:%d\n",
503 __func__, bt->interlaced, fifo_level);
504 i2c_wr16(sd, FIFOCTL, fifo_level);
505 }
506
507 return 0;
508 }
509
510 /* --------------- HOTPLUG / HDCP / EDID --------------- */
511
tc35874x_delayed_work_enable_hotplug(struct work_struct * work)512 static void tc35874x_delayed_work_enable_hotplug(struct work_struct *work)
513 {
514 struct delayed_work *dwork = to_delayed_work(work);
515 struct tc35874x_state *state = container_of(dwork,
516 struct tc35874x_state, delayed_work_enable_hotplug);
517 struct v4l2_subdev *sd = &state->sd;
518
519 v4l2_dbg(2, debug, sd, "%s:\n", __func__);
520
521 i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, MASK_HPD_OUT0);
522 }
523
tc35874x_set_hdmi_hdcp(struct v4l2_subdev * sd,bool enable)524 static void tc35874x_set_hdmi_hdcp(struct v4l2_subdev *sd, bool enable)
525 {
526 v4l2_dbg(2, debug, sd, "%s: %s\n", __func__, enable ?
527 "enable" : "disable");
528
529 if (enable) {
530 i2c_wr8_and_or(sd, HDCP_REG3, ~KEY_RD_CMD, KEY_RD_CMD);
531
532 i2c_wr8_and_or(sd, HDCP_MODE, ~MASK_MANUAL_AUTHENTICATION, 0);
533
534 i2c_wr8_and_or(sd, HDCP_REG1, 0xff,
535 MASK_AUTH_UNAUTH_SEL_16_FRAMES |
536 MASK_AUTH_UNAUTH_AUTO);
537
538 i2c_wr8_and_or(sd, HDCP_REG2, ~MASK_AUTO_P3_RESET,
539 SET_AUTO_P3_RESET_FRAMES(0x0f));
540 } else {
541 i2c_wr8_and_or(sd, HDCP_MODE, ~MASK_MANUAL_AUTHENTICATION,
542 MASK_MANUAL_AUTHENTICATION);
543 }
544 }
545
tc35874x_disable_edid(struct v4l2_subdev * sd)546 static void tc35874x_disable_edid(struct v4l2_subdev *sd)
547 {
548 struct tc35874x_state *state = to_state(sd);
549
550 v4l2_dbg(2, debug, sd, "%s:\n", __func__);
551
552 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
553
554 /* DDC access to EDID is also disabled when hotplug is disabled. See
555 * register DDC_CTL */
556 i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, 0x0);
557 }
558
tc35874x_enable_edid(struct v4l2_subdev * sd)559 static void tc35874x_enable_edid(struct v4l2_subdev *sd)
560 {
561 struct tc35874x_state *state = to_state(sd);
562
563 if (state->edid_blocks_written == 0) {
564 v4l2_dbg(2, debug, sd, "%s: no EDID -> no hotplug\n", __func__);
565 tc35874x_s_ctrl_detect_tx_5v(sd);
566 return;
567 }
568
569 v4l2_dbg(2, debug, sd, "%s:\n", __func__);
570
571 /* Enable hotplug after 100 ms. DDC access to EDID is also enabled when
572 * hotplug is enabled. See register DDC_CTL */
573 schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 10);
574
575 tc35874x_enable_interrupts(sd, true);
576 tc35874x_s_ctrl_detect_tx_5v(sd);
577 }
578
tc35874x_erase_bksv(struct v4l2_subdev * sd)579 static void tc35874x_erase_bksv(struct v4l2_subdev *sd)
580 {
581 int i;
582
583 for (i = 0; i < 5; i++)
584 i2c_wr8(sd, BKSV + i, 0);
585 }
586
587 /* --------------- AVI infoframe --------------- */
588
print_avi_infoframe(struct v4l2_subdev * sd)589 static void print_avi_infoframe(struct v4l2_subdev *sd)
590 {
591 struct i2c_client *client = v4l2_get_subdevdata(sd);
592 struct device *dev = &client->dev;
593 union hdmi_infoframe frame;
594 u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
595
596 if (!is_hdmi(sd)) {
597 v4l2_info(sd, "DVI-D signal - AVI infoframe not supported\n");
598 return;
599 }
600
601 i2c_rd(sd, PK_AVI_0HEAD, buffer, HDMI_INFOFRAME_SIZE(AVI));
602
603 if (hdmi_infoframe_unpack(&frame, buffer, sizeof(buffer)) < 0) {
604 v4l2_err(sd, "%s: unpack of AVI infoframe failed\n", __func__);
605 return;
606 }
607
608 hdmi_infoframe_log(KERN_INFO, dev, &frame);
609 }
610
611 /* --------------- CTRLS --------------- */
612
tc35874x_s_ctrl_detect_tx_5v(struct v4l2_subdev * sd)613 static int tc35874x_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd)
614 {
615 struct tc35874x_state *state = to_state(sd);
616
617 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
618 tx_5v_power_present(sd));
619 }
620
tc35874x_s_ctrl_audio_sampling_rate(struct v4l2_subdev * sd)621 static int tc35874x_s_ctrl_audio_sampling_rate(struct v4l2_subdev *sd)
622 {
623 struct tc35874x_state *state = to_state(sd);
624
625 return v4l2_ctrl_s_ctrl(state->audio_sampling_rate_ctrl,
626 get_audio_sampling_rate(sd));
627 }
628
tc35874x_s_ctrl_audio_present(struct v4l2_subdev * sd)629 static int tc35874x_s_ctrl_audio_present(struct v4l2_subdev *sd)
630 {
631 struct tc35874x_state *state = to_state(sd);
632
633 return v4l2_ctrl_s_ctrl(state->audio_present_ctrl,
634 audio_present(sd));
635 }
636
tc35874x_update_controls(struct v4l2_subdev * sd)637 static int tc35874x_update_controls(struct v4l2_subdev *sd)
638 {
639 int ret = 0;
640
641 ret |= tc35874x_s_ctrl_detect_tx_5v(sd);
642 ret |= tc35874x_s_ctrl_audio_sampling_rate(sd);
643 ret |= tc35874x_s_ctrl_audio_present(sd);
644
645 return ret;
646 }
647
648 /* --------------- INIT --------------- */
649
tc35874x_reset_phy(struct v4l2_subdev * sd)650 static void tc35874x_reset_phy(struct v4l2_subdev *sd)
651 {
652 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
653
654 i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, 0);
655 i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, MASK_RESET_CTRL);
656 }
657
tc35874x_reset(struct v4l2_subdev * sd,uint16_t mask)658 static void tc35874x_reset(struct v4l2_subdev *sd, uint16_t mask)
659 {
660 u16 sysctl = i2c_rd16(sd, SYSCTL);
661
662 i2c_wr16(sd, SYSCTL, sysctl | mask);
663 i2c_wr16(sd, SYSCTL, sysctl & ~mask);
664 }
665
tc35874x_sleep_mode(struct v4l2_subdev * sd,bool enable)666 static inline void tc35874x_sleep_mode(struct v4l2_subdev *sd, bool enable)
667 {
668 i2c_wr16_and_or(sd, SYSCTL, ~MASK_SLEEP,
669 enable ? MASK_SLEEP : 0);
670 }
671
enable_stream(struct v4l2_subdev * sd,bool enable)672 static inline void enable_stream(struct v4l2_subdev *sd, bool enable)
673 {
674 struct tc35874x_state *state = to_state(sd);
675
676 v4l2_dbg(3, debug, sd, "%s: %sable\n",
677 __func__, enable ? "en" : "dis");
678
679 if (enable) {
680 /* It is critical for CSI receiver to see lane transition
681 * LP11->HS. Set to non-continuous mode to enable clock lane
682 * LP11 state. */
683 i2c_wr32(sd, TXOPTIONCNTRL, 0);
684 /* Set to continuous mode to trigger LP11->HS transition */
685 i2c_wr32(sd, TXOPTIONCNTRL, MASK_CONTCLKMODE);
686 /* Unmute video */
687 i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE);
688 } else {
689 /* Mute video so that all data lanes go to LSP11 state.
690 * No data is output to CSI Tx block. */
691 i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE | MASK_VI_MUTE);
692 /* Set to non-continuous mode to enable clock lane LP11 state. */
693 i2c_wr32(sd, TXOPTIONCNTRL, 0);
694 }
695
696 mutex_lock(&state->confctl_mutex);
697 i2c_wr16_and_or(sd, CONFCTL, ~(MASK_VBUFEN | MASK_ABUFEN),
698 enable ? (MASK_VBUFEN | MASK_ABUFEN) : 0x0);
699 mutex_unlock(&state->confctl_mutex);
700 }
701
tc35874x_set_pll(struct v4l2_subdev * sd)702 static void tc35874x_set_pll(struct v4l2_subdev *sd)
703 {
704 struct tc35874x_state *state = to_state(sd);
705 struct tc35874x_platform_data *pdata = &state->pdata;
706 u16 pllctl0 = i2c_rd16(sd, PLLCTL0);
707 u16 pllctl1 = i2c_rd16(sd, PLLCTL1);
708 u16 pllctl0_new;
709 u32 hsck;
710 u16 pll_frs;
711
712 if (state->csi_lanes_in_use == 4) {
713 if ((state->timings.bt.interlaced) ||
714 (fps(&(state->timings.bt)) <= 33)) {
715 pdata->pll_prd = 2;
716 pdata->pll_fbd = 65;
717 pll_frs = 0x1;
718 } else {
719 pdata->pll_prd = 5;
720 pdata->pll_fbd = 138;
721 pll_frs = 0x0;
722 }
723 } else {
724 hsck = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd;
725
726 if (state->timings.bt.interlaced)
727 hsck /= 2;
728 if (hsck > 500000000)
729 pll_frs = 0x0;
730 else if (hsck > 250000000)
731 pll_frs = 0x1;
732 else if (hsck > 125000000)
733 pll_frs = 0x2;
734 else
735 pll_frs = 0x3;
736 }
737
738 pllctl0_new = SET_PLL_PRD(pdata->pll_prd) | SET_PLL_FBD(pdata->pll_fbd);
739
740 v4l2_dbg(1, debug, sd,
741 "%s: prd:%d, fbd:%d, frs:%d, interlaced:%d, fps:%d\n",
742 __func__, pdata->pll_prd, pdata->pll_fbd, pll_frs,
743 state->timings.bt.interlaced, fps(&(state->timings.bt)));
744
745 /* Only rewrite when needed (new value or disabled), since rewriting
746 * triggers another format change event. */
747 if (pllctl0 != pllctl0_new || (pllctl1 & MASK_PLL_EN) == 0 ||
748 SET_PLL_FRS(pll_frs) != (pllctl1 & MASK_PLL_FRS)) {
749
750 v4l2_dbg(1, debug, sd, "%s: updating PLL clock\n", __func__);
751 tc35874x_sleep_mode(sd, true);
752 i2c_wr16(sd, PLLCTL0, pllctl0_new);
753 i2c_wr16_and_or(sd, PLLCTL1,
754 ~(MASK_PLL_FRS | MASK_RESETB | MASK_PLL_EN),
755 (SET_PLL_FRS(pll_frs) | MASK_RESETB |
756 MASK_PLL_EN));
757 udelay(10); /* REF_02, Sheet "Source HDMI" */
758 i2c_wr16_and_or(sd, PLLCTL1, ~MASK_CKEN, MASK_CKEN);
759 tc35874x_sleep_mode(sd, false);
760 }
761 }
762
tc35874x_set_ref_clk(struct v4l2_subdev * sd)763 static void tc35874x_set_ref_clk(struct v4l2_subdev *sd)
764 {
765 struct tc35874x_state *state = to_state(sd);
766 struct tc35874x_platform_data *pdata = &state->pdata;
767 u32 sys_freq;
768 u32 lockdet_ref;
769 u16 fh_min;
770 u16 fh_max;
771
772 BUG_ON(!(pdata->refclk_hz == 26000000 ||
773 pdata->refclk_hz == 27000000 ||
774 pdata->refclk_hz == 42000000));
775
776 sys_freq = pdata->refclk_hz / 10000;
777 i2c_wr8(sd, SYS_FREQ0, sys_freq & 0x00ff);
778 i2c_wr8(sd, SYS_FREQ1, (sys_freq & 0xff00) >> 8);
779
780 i2c_wr8_and_or(sd, PHY_CTL0, ~MASK_PHY_SYSCLK_IND,
781 (pdata->refclk_hz == 42000000) ?
782 MASK_PHY_SYSCLK_IND : 0x0);
783
784 fh_min = pdata->refclk_hz / 100000;
785 i2c_wr8(sd, FH_MIN0, fh_min & 0x00ff);
786 i2c_wr8(sd, FH_MIN1, (fh_min & 0xff00) >> 8);
787
788 fh_max = (fh_min * 66) / 10;
789 i2c_wr8(sd, FH_MAX0, fh_max & 0x00ff);
790 i2c_wr8(sd, FH_MAX1, (fh_max & 0xff00) >> 8);
791
792 lockdet_ref = pdata->refclk_hz / 100;
793 i2c_wr8(sd, LOCKDET_REF0, lockdet_ref & 0x0000ff);
794 i2c_wr8(sd, LOCKDET_REF1, (lockdet_ref & 0x00ff00) >> 8);
795 i2c_wr8(sd, LOCKDET_REF2, (lockdet_ref & 0x0f0000) >> 16);
796
797 i2c_wr8_and_or(sd, NCO_F0_MOD, ~MASK_NCO_F0_MOD,
798 (pdata->refclk_hz == 27000000) ?
799 MASK_NCO_F0_MOD_27MHZ : 0x0);
800 }
801
tc35874x_set_csi_color_space(struct v4l2_subdev * sd)802 static void tc35874x_set_csi_color_space(struct v4l2_subdev *sd)
803 {
804 struct tc35874x_state *state = to_state(sd);
805
806 switch (state->mbus_fmt_code) {
807 case MEDIA_BUS_FMT_UYVY8_2X8:
808 v4l2_dbg(2, debug, sd, "%s: YCbCr 422 16-bit\n", __func__);
809 i2c_wr8_and_or(sd, VOUT_SET2,
810 ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff,
811 MASK_SEL422 | MASK_VOUT_422FIL_100);
812 i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff,
813 MASK_VOUT_COLOR_601_YCBCR_LIMITED);
814 mutex_lock(&state->confctl_mutex);
815 i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT,
816 MASK_YCBCRFMT_422_8_BIT);
817 mutex_unlock(&state->confctl_mutex);
818 break;
819 case MEDIA_BUS_FMT_RGB888_1X24:
820 v4l2_dbg(2, debug, sd, "%s: RGB 888 24-bit\n", __func__);
821 i2c_wr8_and_or(sd, VOUT_SET2,
822 ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff,
823 0x00);
824 i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff,
825 MASK_VOUT_COLOR_RGB_FULL);
826 mutex_lock(&state->confctl_mutex);
827 i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT, 0);
828 mutex_unlock(&state->confctl_mutex);
829 break;
830 default:
831 v4l2_dbg(2, debug, sd, "%s: Unsupported format code 0x%x\n",
832 __func__, state->mbus_fmt_code);
833 }
834 }
835
tc35874x_set_csi(struct v4l2_subdev * sd)836 static void tc35874x_set_csi(struct v4l2_subdev *sd)
837 {
838 struct tc35874x_state *state = to_state(sd);
839 struct tc35874x_platform_data *pdata = &state->pdata;
840 unsigned lanes = state->csi_lanes_in_use;
841
842 v4l2_dbg(3, debug, sd, "%s:\n", __func__);
843
844 tc35874x_reset(sd, MASK_CTXRST);
845
846 if (lanes < 1)
847 i2c_wr32(sd, CLW_CNTRL, MASK_CLW_LANEDISABLE);
848 if (lanes < 1)
849 i2c_wr32(sd, D0W_CNTRL, MASK_D0W_LANEDISABLE);
850 if (lanes < 2)
851 i2c_wr32(sd, D1W_CNTRL, MASK_D1W_LANEDISABLE);
852 if (lanes < 3)
853 i2c_wr32(sd, D2W_CNTRL, MASK_D2W_LANEDISABLE);
854 if (lanes < 4)
855 i2c_wr32(sd, D3W_CNTRL, MASK_D3W_LANEDISABLE);
856
857 v4l2_dbg(1, debug, sd, "%s: interlaced:%d, fps:%d\n", __func__,
858 state->timings.bt.interlaced, fps(&(state->timings.bt)));
859 if (state->csi_lanes_in_use == 4) {
860 if ((state->timings.bt.interlaced) ||
861 (fps(&(state->timings.bt)) <= 33)) {
862 state->pdata.lineinitcnt = 0x7d0;
863 state->pdata.lptxtimecnt = 0x002;
864 state->pdata.tclk_headercnt = 0x901;
865 state->pdata.tclk_trailcnt = 0x00;
866 state->pdata.ths_headercnt = 0x02;
867 state->pdata.twakeup = 0x32c8;
868 state->pdata.tclk_postcnt = 0x006;
869 state->pdata.ths_trailcnt = 0x0;
870 state->pdata.hstxvregcnt = 5;
871 } else {
872 state->pdata.lineinitcnt = 0x1770;
873 state->pdata.lptxtimecnt = 0x05;
874 state->pdata.tclk_headercnt = 0x1505;
875 state->pdata.tclk_trailcnt = 0x01;
876 state->pdata.ths_headercnt = 0x0105;
877 state->pdata.twakeup = 0x332c;
878 state->pdata.tclk_postcnt = 0x08;
879 state->pdata.ths_trailcnt = 0x02;
880 state->pdata.hstxvregcnt = 0x05;
881 }
882 }
883
884 i2c_wr32(sd, LINEINITCNT, pdata->lineinitcnt);
885 i2c_wr32(sd, LPTXTIMECNT, pdata->lptxtimecnt);
886 i2c_wr32(sd, TCLK_HEADERCNT, pdata->tclk_headercnt);
887 i2c_wr32(sd, TCLK_TRAILCNT, pdata->tclk_trailcnt);
888 i2c_wr32(sd, THS_HEADERCNT, pdata->ths_headercnt);
889 i2c_wr32(sd, TWAKEUP, pdata->twakeup);
890 i2c_wr32(sd, TCLK_POSTCNT, pdata->tclk_postcnt);
891 i2c_wr32(sd, THS_TRAILCNT, pdata->ths_trailcnt);
892 i2c_wr32(sd, HSTXVREGCNT, pdata->hstxvregcnt);
893
894 i2c_wr32(sd, HSTXVREGEN,
895 ((lanes > 0) ? MASK_CLM_HSTXVREGEN : 0x0) |
896 ((lanes > 0) ? MASK_D0M_HSTXVREGEN : 0x0) |
897 ((lanes > 1) ? MASK_D1M_HSTXVREGEN : 0x0) |
898 ((lanes > 2) ? MASK_D2M_HSTXVREGEN : 0x0) |
899 ((lanes > 3) ? MASK_D3M_HSTXVREGEN : 0x0));
900
901 i2c_wr32(sd, TXOPTIONCNTRL, (state->bus.flags &
902 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK) ? MASK_CONTCLKMODE : 0);
903 i2c_wr32(sd, STARTCNTRL, MASK_START);
904 i2c_wr32(sd, CSI_START, MASK_STRT);
905
906 i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
907 MASK_ADDRESS_CSI_CONTROL |
908 MASK_CSI_MODE |
909 MASK_TXHSMD |
910 ((lanes == 4) ? MASK_NOL_4 :
911 (lanes == 3) ? MASK_NOL_3 :
912 (lanes == 2) ? MASK_NOL_2 : MASK_NOL_1));
913
914 i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
915 MASK_ADDRESS_CSI_ERR_INTENA | MASK_TXBRK | MASK_QUNK |
916 MASK_WCER | MASK_INER);
917
918 i2c_wr32(sd, CSI_CONFW, MASK_MODE_CLEAR |
919 MASK_ADDRESS_CSI_ERR_HALT | MASK_TXBRK | MASK_QUNK);
920
921 i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
922 MASK_ADDRESS_CSI_INT_ENA | MASK_INTER);
923 }
924
tc35874x_set_hdmi_phy(struct v4l2_subdev * sd)925 static void tc35874x_set_hdmi_phy(struct v4l2_subdev *sd)
926 {
927 struct tc35874x_state *state = to_state(sd);
928 struct tc35874x_platform_data *pdata = &state->pdata;
929
930 /* Default settings from REF_02, sheet "Source HDMI"
931 * and custom settings as platform data */
932 i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, 0x0);
933 i2c_wr8(sd, PHY_CTL1, SET_PHY_AUTO_RST1_US(1600) |
934 SET_FREQ_RANGE_MODE_CYCLES(1));
935 i2c_wr8_and_or(sd, PHY_CTL2, ~MASK_PHY_AUTO_RSTn,
936 (pdata->hdmi_phy_auto_reset_tmds_detected ?
937 MASK_PHY_AUTO_RST2 : 0) |
938 (pdata->hdmi_phy_auto_reset_tmds_in_range ?
939 MASK_PHY_AUTO_RST3 : 0) |
940 (pdata->hdmi_phy_auto_reset_tmds_valid ?
941 MASK_PHY_AUTO_RST4 : 0));
942 i2c_wr8(sd, PHY_BIAS, 0x40);
943 i2c_wr8(sd, PHY_CSQ, SET_CSQ_CNT_LEVEL(0x0a));
944 i2c_wr8(sd, AVM_CTL, 45);
945 i2c_wr8_and_or(sd, HDMI_DET, ~MASK_HDMI_DET_V,
946 pdata->hdmi_detection_delay << 4);
947 i2c_wr8_and_or(sd, HV_RST, ~(MASK_H_PI_RST | MASK_V_PI_RST),
948 (pdata->hdmi_phy_auto_reset_hsync_out_of_range ?
949 MASK_H_PI_RST : 0) |
950 (pdata->hdmi_phy_auto_reset_vsync_out_of_range ?
951 MASK_V_PI_RST : 0));
952 i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, MASK_ENABLE_PHY);
953 }
954
tc35874x_set_hdmi_audio(struct v4l2_subdev * sd)955 static void tc35874x_set_hdmi_audio(struct v4l2_subdev *sd)
956 {
957 struct tc35874x_state *state = to_state(sd);
958
959 /* Default settings from REF_02, sheet "Source HDMI" */
960 i2c_wr8(sd, FORCE_MUTE, 0x00);
961 i2c_wr8(sd, AUTO_CMD0, MASK_AUTO_MUTE7 | MASK_AUTO_MUTE6 |
962 MASK_AUTO_MUTE5 | MASK_AUTO_MUTE4 |
963 MASK_AUTO_MUTE1 | MASK_AUTO_MUTE0);
964 i2c_wr8(sd, AUTO_CMD1, MASK_AUTO_MUTE9);
965 i2c_wr8(sd, AUTO_CMD2, MASK_AUTO_PLAY3 | MASK_AUTO_PLAY2);
966 i2c_wr8(sd, BUFINIT_START, SET_BUFINIT_START_MS(500));
967 i2c_wr8(sd, FS_MUTE, 0x00);
968 i2c_wr8(sd, FS_IMODE, MASK_NLPCM_SMODE | MASK_FS_SMODE);
969 i2c_wr8(sd, ACR_MODE, MASK_CTS_MODE);
970 i2c_wr8(sd, ACR_MDF0, MASK_ACR_L2MDF_1976_PPM | MASK_ACR_L1MDF_976_PPM);
971 i2c_wr8(sd, ACR_MDF1, MASK_ACR_L3MDF_3906_PPM);
972 i2c_wr8(sd, SDO_MODE1, MASK_SDO_FMT_I2S);
973 i2c_wr8(sd, DIV_MODE, SET_DIV_DLY_MS(100));
974
975 mutex_lock(&state->confctl_mutex);
976 i2c_wr16_and_or(sd, CONFCTL, 0xffff, MASK_AUDCHNUM_2 |
977 MASK_AUDOUTSEL_I2S | MASK_AUTOINDEX);
978 mutex_unlock(&state->confctl_mutex);
979 }
980
tc35874x_set_hdmi_info_frame_mode(struct v4l2_subdev * sd)981 static void tc35874x_set_hdmi_info_frame_mode(struct v4l2_subdev *sd)
982 {
983 /* Default settings from REF_02, sheet "Source HDMI" */
984 i2c_wr8(sd, PK_INT_MODE, MASK_ISRC2_INT_MODE | MASK_ISRC_INT_MODE |
985 MASK_ACP_INT_MODE | MASK_VS_INT_MODE |
986 MASK_SPD_INT_MODE | MASK_MS_INT_MODE |
987 MASK_AUD_INT_MODE | MASK_AVI_INT_MODE);
988 i2c_wr8(sd, NO_PKT_LIMIT, 0x2c);
989 i2c_wr8(sd, NO_PKT_CLR, 0x53);
990 i2c_wr8(sd, ERR_PK_LIMIT, 0x01);
991 i2c_wr8(sd, NO_PKT_LIMIT2, 0x30);
992 i2c_wr8(sd, NO_GDB_LIMIT, 0x10);
993 }
994
tc35874x_initial_setup(struct v4l2_subdev * sd)995 static void tc35874x_initial_setup(struct v4l2_subdev *sd)
996 {
997 struct tc35874x_state *state = to_state(sd);
998 struct tc35874x_platform_data *pdata = &state->pdata;
999
1000 /* CEC and IR are not supported by this driver */
1001 i2c_wr16_and_or(sd, SYSCTL, ~(MASK_CECRST | MASK_IRRST | MASK_I2SDIS),
1002 (MASK_CECRST | MASK_IRRST));
1003
1004 tc35874x_reset(sd, MASK_CTXRST | MASK_HDMIRST);
1005 tc35874x_sleep_mode(sd, false);
1006
1007 i2c_wr16(sd, FIFOCTL, pdata->fifo_level);
1008
1009 tc35874x_set_ref_clk(sd);
1010
1011 i2c_wr8_and_or(sd, DDC_CTL, ~MASK_DDC5V_MODE,
1012 pdata->ddc5v_delay & MASK_DDC5V_MODE);
1013 i2c_wr8_and_or(sd, EDID_MODE, ~MASK_EDID_MODE, MASK_EDID_MODE_E_DDC);
1014
1015 tc35874x_set_hdmi_phy(sd);
1016 tc35874x_set_hdmi_hdcp(sd, pdata->enable_hdcp);
1017 tc35874x_set_hdmi_audio(sd);
1018 tc35874x_set_hdmi_info_frame_mode(sd);
1019
1020 /* All CE and IT formats are detected as RGB full range in DVI mode */
1021 i2c_wr8_and_or(sd, VI_MODE, ~MASK_RGB_DVI, 0);
1022
1023 i2c_wr8_and_or(sd, VOUT_SET2, ~MASK_VOUTCOLORMODE,
1024 MASK_VOUTCOLORMODE_AUTO);
1025 i2c_wr8(sd, VOUT_SET3, MASK_VOUT_EXTCNT);
1026 }
1027
1028 /* --------------- IRQ --------------- */
1029
tc35874x_format_change(struct v4l2_subdev * sd)1030 static void tc35874x_format_change(struct v4l2_subdev *sd)
1031 {
1032 struct tc35874x_state *state = to_state(sd);
1033 struct v4l2_dv_timings timings;
1034 const struct v4l2_event tc35874x_ev_fmt = {
1035 .type = V4L2_EVENT_SOURCE_CHANGE,
1036 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
1037 };
1038
1039 if (tc35874x_get_detected_timings(sd, &timings)) {
1040 enable_stream(sd, false);
1041
1042 v4l2_dbg(1, debug, sd, "%s: No signal\n",
1043 __func__);
1044 } else {
1045 if (!v4l2_match_dv_timings(&state->timings, &timings, 0, false)) {
1046 enable_stream(sd, false);
1047 /* automaticly set timing rather than set by userspace */
1048 tc35874x_s_dv_timings(sd, &timings);
1049 }
1050
1051 v4l2_print_dv_timings(sd->name,
1052 "tc35874x_format_change: New format: ",
1053 &timings, false);
1054 }
1055
1056 if (sd->devnode)
1057 v4l2_subdev_notify_event(sd, &tc35874x_ev_fmt);
1058 }
1059
tc35874x_init_interrupts(struct v4l2_subdev * sd)1060 static void tc35874x_init_interrupts(struct v4l2_subdev *sd)
1061 {
1062 u16 i;
1063
1064 /* clear interrupt status registers */
1065 for (i = SYS_INT; i <= KEY_INT; i++)
1066 i2c_wr8(sd, i, 0xff);
1067
1068 i2c_wr16(sd, INTSTATUS, 0xffff);
1069 }
1070
tc35874x_enable_interrupts(struct v4l2_subdev * sd,bool cable_connected)1071 static void tc35874x_enable_interrupts(struct v4l2_subdev *sd,
1072 bool cable_connected)
1073 {
1074 v4l2_dbg(2, debug, sd, "%s: cable connected = %d\n", __func__,
1075 cable_connected);
1076
1077 if (cable_connected) {
1078 i2c_wr8(sd, SYS_INTM, ~(MASK_M_DDC | MASK_M_DVI_DET |
1079 MASK_M_HDMI_DET) & 0xff);
1080 i2c_wr8(sd, CLK_INTM, ~MASK_M_IN_DE_CHG);
1081 i2c_wr8(sd, CBIT_INTM, ~(MASK_M_CBIT_FS | MASK_M_AF_LOCK |
1082 MASK_M_AF_UNLOCK) & 0xff);
1083 i2c_wr8(sd, AUDIO_INTM, ~MASK_M_BUFINIT_END);
1084 i2c_wr8(sd, MISC_INTM, ~MASK_M_SYNC_CHG);
1085 } else {
1086 i2c_wr8(sd, SYS_INTM, ~MASK_M_DDC & 0xff);
1087 i2c_wr8(sd, CLK_INTM, 0xff);
1088 i2c_wr8(sd, CBIT_INTM, 0xff);
1089 i2c_wr8(sd, AUDIO_INTM, 0xff);
1090 i2c_wr8(sd, MISC_INTM, 0xff);
1091 }
1092 }
1093
tc35874x_hdmi_audio_int_handler(struct v4l2_subdev * sd,bool * handled)1094 static void tc35874x_hdmi_audio_int_handler(struct v4l2_subdev *sd,
1095 bool *handled)
1096 {
1097 u8 audio_int_mask = i2c_rd8(sd, AUDIO_INTM);
1098 u8 audio_int = i2c_rd8(sd, AUDIO_INT) & ~audio_int_mask;
1099
1100 i2c_wr8(sd, AUDIO_INT, audio_int);
1101
1102 v4l2_dbg(3, debug, sd, "%s: AUDIO_INT = 0x%02x\n", __func__, audio_int);
1103
1104 tc35874x_s_ctrl_audio_sampling_rate(sd);
1105 tc35874x_s_ctrl_audio_present(sd);
1106 }
1107
tc35874x_csi_err_int_handler(struct v4l2_subdev * sd,bool * handled)1108 static void tc35874x_csi_err_int_handler(struct v4l2_subdev *sd, bool *handled)
1109 {
1110 v4l2_err(sd, "%s: CSI_ERR = 0x%x\n", __func__, i2c_rd32(sd, CSI_ERR));
1111
1112 i2c_wr32(sd, CSI_INT_CLR, MASK_ICRER);
1113 }
1114
tc35874x_hdmi_misc_int_handler(struct v4l2_subdev * sd,bool * handled)1115 static void tc35874x_hdmi_misc_int_handler(struct v4l2_subdev *sd,
1116 bool *handled)
1117 {
1118 u8 misc_int_mask = i2c_rd8(sd, MISC_INTM);
1119 u8 misc_int = i2c_rd8(sd, MISC_INT) & ~misc_int_mask;
1120
1121 i2c_wr8(sd, MISC_INT, misc_int);
1122
1123 v4l2_dbg(3, debug, sd, "%s: MISC_INT = 0x%02x\n", __func__, misc_int);
1124
1125 if (misc_int & MASK_I_SYNC_CHG) {
1126 /* Reset the HDMI PHY to try to trigger proper lock on the
1127 * incoming video format. Erase BKSV to prevent that old keys
1128 * are used when a new source is connected. */
1129 if (no_sync(sd) || no_signal(sd)) {
1130 tc35874x_reset_phy(sd);
1131 tc35874x_erase_bksv(sd);
1132 }
1133
1134 tc35874x_format_change(sd);
1135
1136 misc_int &= ~MASK_I_SYNC_CHG;
1137 if (handled)
1138 *handled = true;
1139 }
1140
1141 if (misc_int) {
1142 v4l2_err(sd, "%s: Unhandled MISC_INT interrupts: 0x%02x\n",
1143 __func__, misc_int);
1144 }
1145 }
1146
tc35874x_hdmi_cbit_int_handler(struct v4l2_subdev * sd,bool * handled)1147 static void tc35874x_hdmi_cbit_int_handler(struct v4l2_subdev *sd,
1148 bool *handled)
1149 {
1150 u8 cbit_int_mask = i2c_rd8(sd, CBIT_INTM);
1151 u8 cbit_int = i2c_rd8(sd, CBIT_INT) & ~cbit_int_mask;
1152
1153 i2c_wr8(sd, CBIT_INT, cbit_int);
1154
1155 v4l2_dbg(3, debug, sd, "%s: CBIT_INT = 0x%02x\n", __func__, cbit_int);
1156
1157 if (cbit_int & MASK_I_CBIT_FS) {
1158
1159 v4l2_dbg(1, debug, sd, "%s: Audio sample rate changed\n",
1160 __func__);
1161 tc35874x_s_ctrl_audio_sampling_rate(sd);
1162
1163 cbit_int &= ~MASK_I_CBIT_FS;
1164 if (handled)
1165 *handled = true;
1166 }
1167
1168 if (cbit_int & (MASK_I_AF_LOCK | MASK_I_AF_UNLOCK)) {
1169
1170 v4l2_dbg(1, debug, sd, "%s: Audio present changed\n",
1171 __func__);
1172 tc35874x_s_ctrl_audio_present(sd);
1173
1174 cbit_int &= ~(MASK_I_AF_LOCK | MASK_I_AF_UNLOCK);
1175 if (handled)
1176 *handled = true;
1177 }
1178
1179 if (cbit_int) {
1180 v4l2_err(sd, "%s: Unhandled CBIT_INT interrupts: 0x%02x\n",
1181 __func__, cbit_int);
1182 }
1183 }
1184
tc35874x_hdmi_clk_int_handler(struct v4l2_subdev * sd,bool * handled)1185 static void tc35874x_hdmi_clk_int_handler(struct v4l2_subdev *sd, bool *handled)
1186 {
1187 u8 clk_int_mask = i2c_rd8(sd, CLK_INTM);
1188 u8 clk_int = i2c_rd8(sd, CLK_INT) & ~clk_int_mask;
1189
1190 /* Bit 7 and bit 6 are set even when they are masked */
1191 i2c_wr8(sd, CLK_INT, clk_int | 0x80 | MASK_I_OUT_H_CHG);
1192
1193 v4l2_dbg(3, debug, sd, "%s: CLK_INT = 0x%02x\n", __func__, clk_int);
1194
1195 if (clk_int & (MASK_I_IN_DE_CHG)) {
1196
1197 v4l2_dbg(1, debug, sd, "%s: DE size or position has changed\n",
1198 __func__);
1199
1200 /* If the source switch to a new resolution with the same pixel
1201 * frequency as the existing (e.g. 1080p25 -> 720p50), the
1202 * I_SYNC_CHG interrupt is not always triggered, while the
1203 * I_IN_DE_CHG interrupt seems to work fine. Format change
1204 * notifications are only sent when the signal is stable to
1205 * reduce the number of notifications. */
1206 if (!no_signal(sd) && !no_sync(sd))
1207 tc35874x_format_change(sd);
1208
1209 clk_int &= ~(MASK_I_IN_DE_CHG);
1210 if (handled)
1211 *handled = true;
1212 }
1213
1214 if (clk_int) {
1215 v4l2_err(sd, "%s: Unhandled CLK_INT interrupts: 0x%02x\n",
1216 __func__, clk_int);
1217 }
1218 }
1219
tc35874x_hdmi_sys_int_handler(struct v4l2_subdev * sd,bool * handled)1220 static void tc35874x_hdmi_sys_int_handler(struct v4l2_subdev *sd, bool *handled)
1221 {
1222 struct tc35874x_state *state = to_state(sd);
1223 u8 sys_int_mask = i2c_rd8(sd, SYS_INTM);
1224 u8 sys_int = i2c_rd8(sd, SYS_INT) & ~sys_int_mask;
1225
1226 i2c_wr8(sd, SYS_INT, sys_int);
1227
1228 v4l2_dbg(3, debug, sd, "%s: SYS_INT = 0x%02x\n", __func__, sys_int);
1229
1230 if (sys_int & MASK_I_DDC) {
1231 bool tx_5v = tx_5v_power_present(sd);
1232
1233 v4l2_dbg(1, debug, sd, "%s: Tx 5V power present: %s\n",
1234 __func__, tx_5v ? "yes" : "no");
1235
1236 if (tx_5v) {
1237 tc35874x_enable_edid(sd);
1238 } else {
1239 tc35874x_enable_interrupts(sd, false);
1240 tc35874x_disable_edid(sd);
1241 memset(&state->timings, 0, sizeof(state->timings));
1242 tc35874x_erase_bksv(sd);
1243 tc35874x_update_controls(sd);
1244 }
1245
1246 sys_int &= ~MASK_I_DDC;
1247 if (handled)
1248 *handled = true;
1249 }
1250
1251 if (sys_int & MASK_I_DVI) {
1252 v4l2_dbg(1, debug, sd, "%s: HDMI->DVI change detected\n",
1253 __func__);
1254
1255 /* Reset the HDMI PHY to try to trigger proper lock on the
1256 * incoming video format. Erase BKSV to prevent that old keys
1257 * are used when a new source is connected. */
1258 if (no_sync(sd) || no_signal(sd)) {
1259 tc35874x_reset_phy(sd);
1260 tc35874x_erase_bksv(sd);
1261 }
1262
1263 sys_int &= ~MASK_I_DVI;
1264 if (handled)
1265 *handled = true;
1266 }
1267
1268 if (sys_int & MASK_I_HDMI) {
1269 v4l2_dbg(1, debug, sd, "%s: DVI->HDMI change detected\n",
1270 __func__);
1271
1272 /* Register is reset in DVI mode (REF_01, c. 6.6.41) */
1273 i2c_wr8(sd, ANA_CTL, MASK_APPL_PCSX_NORMAL | MASK_ANALOG_ON);
1274
1275 sys_int &= ~MASK_I_HDMI;
1276 if (handled)
1277 *handled = true;
1278 }
1279
1280 if (sys_int) {
1281 v4l2_err(sd, "%s: Unhandled SYS_INT interrupts: 0x%02x\n",
1282 __func__, sys_int);
1283 }
1284 }
1285
1286 /* --------------- CTRL OPS --------------- */
1287
tc35874x_get_ctrl(struct v4l2_ctrl * ctrl)1288 static int tc35874x_get_ctrl(struct v4l2_ctrl *ctrl)
1289 {
1290 int ret = -1;
1291 struct tc35874x_state *state = container_of(ctrl->handler,
1292 struct tc35874x_state, hdl);
1293 struct v4l2_subdev *sd = &(state->sd);
1294
1295 if (ctrl->id == V4L2_CID_DV_RX_POWER_PRESENT) {
1296 ret = tx_5v_power_present(sd);
1297 *ctrl->p_new.p_s32 = ret;
1298 }
1299
1300 return ret;
1301 }
1302
1303 /* --------------- CORE OPS --------------- */
1304
tc35874x_log_status(struct v4l2_subdev * sd)1305 static int tc35874x_log_status(struct v4l2_subdev *sd)
1306 {
1307 struct tc35874x_state *state = to_state(sd);
1308 struct v4l2_dv_timings timings;
1309 uint8_t hdmi_sys_status = i2c_rd8(sd, SYS_STATUS);
1310 uint16_t sysctl = i2c_rd16(sd, SYSCTL);
1311 u8 vi_status3 = i2c_rd8(sd, VI_STATUS3);
1312 const int deep_color_mode[4] = { 8, 10, 12, 16 };
1313 static const char * const input_color_space[] = {
1314 "RGB", "YCbCr 601", "Adobe RGB", "YCbCr 709", "NA (4)",
1315 "xvYCC 601", "NA(6)", "xvYCC 709", "NA(8)", "sYCC601",
1316 "NA(10)", "NA(11)", "NA(12)", "Adobe YCC 601"};
1317
1318 v4l2_info(sd, "-----Chip status-----\n");
1319 v4l2_info(sd, "Chip ID: 0x%02x\n",
1320 (i2c_rd16(sd, CHIPID) & MASK_CHIPID) >> 8);
1321 v4l2_info(sd, "Chip revision: 0x%02x\n",
1322 i2c_rd16(sd, CHIPID) & MASK_REVID);
1323 v4l2_info(sd, "Reset: IR: %d, CEC: %d, CSI TX: %d, HDMI: %d\n",
1324 !!(sysctl & MASK_IRRST),
1325 !!(sysctl & MASK_CECRST),
1326 !!(sysctl & MASK_CTXRST),
1327 !!(sysctl & MASK_HDMIRST));
1328 v4l2_info(sd, "Sleep mode: %s\n", sysctl & MASK_SLEEP ? "on" : "off");
1329 v4l2_info(sd, "Cable detected (+5V power): %s\n",
1330 hdmi_sys_status & MASK_S_DDC5V ? "yes" : "no");
1331 v4l2_info(sd, "DDC lines enabled: %s\n",
1332 (i2c_rd8(sd, EDID_MODE) & MASK_EDID_MODE_E_DDC) ?
1333 "yes" : "no");
1334 v4l2_info(sd, "Hotplug enabled: %s\n",
1335 (i2c_rd8(sd, HPD_CTL) & MASK_HPD_OUT0) ?
1336 "yes" : "no");
1337 v4l2_info(sd, "CEC enabled: %s\n",
1338 (i2c_rd16(sd, CECEN) & MASK_CECEN) ? "yes" : "no");
1339 v4l2_info(sd, "-----Signal status-----\n");
1340 v4l2_info(sd, "TMDS signal detected: %s\n",
1341 hdmi_sys_status & MASK_S_TMDS ? "yes" : "no");
1342 v4l2_info(sd, "Stable sync signal: %s\n",
1343 hdmi_sys_status & MASK_S_SYNC ? "yes" : "no");
1344 v4l2_info(sd, "PHY PLL locked: %s\n",
1345 hdmi_sys_status & MASK_S_PHY_PLL ? "yes" : "no");
1346 v4l2_info(sd, "PHY DE detected: %s\n",
1347 hdmi_sys_status & MASK_S_PHY_SCDT ? "yes" : "no");
1348
1349 if (tc35874x_get_detected_timings(sd, &timings)) {
1350 v4l2_info(sd, "No video detected\n");
1351 } else {
1352 v4l2_print_dv_timings(sd->name, "Detected format: ", &timings,
1353 true);
1354 }
1355 v4l2_print_dv_timings(sd->name, "Configured format: ", &state->timings,
1356 true);
1357
1358 v4l2_info(sd, "-----CSI-TX status-----\n");
1359 v4l2_info(sd, "Lanes in use: %d\n",
1360 state->csi_lanes_in_use);
1361 v4l2_info(sd, "Waiting for particular sync signal: %s\n",
1362 (i2c_rd16(sd, CSI_STATUS) & MASK_S_WSYNC) ?
1363 "yes" : "no");
1364 v4l2_info(sd, "Transmit mode: %s\n",
1365 (i2c_rd16(sd, CSI_STATUS) & MASK_S_TXACT) ?
1366 "yes" : "no");
1367 v4l2_info(sd, "Receive mode: %s\n",
1368 (i2c_rd16(sd, CSI_STATUS) & MASK_S_RXACT) ?
1369 "yes" : "no");
1370 v4l2_info(sd, "Stopped: %s\n",
1371 (i2c_rd16(sd, CSI_STATUS) & MASK_S_HLT) ?
1372 "yes" : "no");
1373 v4l2_info(sd, "Color space: %s\n",
1374 state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_2X8 ?
1375 "YCbCr 422 16-bit" :
1376 state->mbus_fmt_code == MEDIA_BUS_FMT_RGB888_1X24 ?
1377 "RGB 888 24-bit" : "Unsupported");
1378
1379 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
1380 v4l2_info(sd, "HDCP encrypted content: %s\n",
1381 hdmi_sys_status & MASK_S_HDCP ? "yes" : "no");
1382 v4l2_info(sd, "Input color space: %s %s range\n",
1383 input_color_space[(vi_status3 & MASK_S_V_COLOR) >> 1],
1384 (vi_status3 & MASK_LIMITED) ? "limited" : "full");
1385 if (!is_hdmi(sd))
1386 return 0;
1387 v4l2_info(sd, "AV Mute: %s\n", hdmi_sys_status & MASK_S_AVMUTE ? "on" :
1388 "off");
1389 v4l2_info(sd, "Deep color mode: %d-bits per channel\n",
1390 deep_color_mode[(i2c_rd8(sd, VI_STATUS1) &
1391 MASK_S_DEEPCOLOR) >> 2]);
1392 print_avi_infoframe(sd);
1393
1394 return 0;
1395 }
1396
1397 #ifdef CONFIG_VIDEO_ADV_DEBUG
tc35874x_print_register_map(struct v4l2_subdev * sd)1398 static void tc35874x_print_register_map(struct v4l2_subdev *sd)
1399 {
1400 v4l2_info(sd, "0x0000-0x00FF: Global Control Register\n");
1401 v4l2_info(sd, "0x0100-0x01FF: CSI2-TX PHY Register\n");
1402 v4l2_info(sd, "0x0200-0x03FF: CSI2-TX PPI Register\n");
1403 v4l2_info(sd, "0x0400-0x05FF: Reserved\n");
1404 v4l2_info(sd, "0x0600-0x06FF: CEC Register\n");
1405 v4l2_info(sd, "0x0700-0x84FF: Reserved\n");
1406 v4l2_info(sd, "0x8500-0x85FF: HDMIRX System Control Register\n");
1407 v4l2_info(sd, "0x8600-0x86FF: HDMIRX Audio Control Register\n");
1408 v4l2_info(sd, "0x8700-0x87FF: HDMIRX InfoFrame packet data Register\n");
1409 v4l2_info(sd, "0x8800-0x88FF: HDMIRX HDCP Port Register\n");
1410 v4l2_info(sd, "0x8900-0x89FF: HDMIRX Video Output Port & 3D Register\n");
1411 v4l2_info(sd, "0x8A00-0x8BFF: Reserved\n");
1412 v4l2_info(sd, "0x8C00-0x8FFF: HDMIRX EDID-RAM (1024bytes)\n");
1413 v4l2_info(sd, "0x9000-0x90FF: HDMIRX GBD Extraction Control\n");
1414 v4l2_info(sd, "0x9100-0x92FF: HDMIRX GBD RAM read\n");
1415 v4l2_info(sd, "0x9300- : Reserved\n");
1416 }
1417
tc35874x_get_reg_size(u16 address)1418 static int tc35874x_get_reg_size(u16 address)
1419 {
1420 /* REF_01 p. 66-72 */
1421 if (address <= 0x00ff)
1422 return 2;
1423 else if ((address >= 0x0100) && (address <= 0x06FF))
1424 return 4;
1425 else if ((address >= 0x0700) && (address <= 0x84ff))
1426 return 2;
1427 else
1428 return 1;
1429 }
1430
tc35874x_g_register(struct v4l2_subdev * sd,struct v4l2_dbg_register * reg)1431 static int tc35874x_g_register(struct v4l2_subdev *sd,
1432 struct v4l2_dbg_register *reg)
1433 {
1434 if (reg->reg > 0xffff) {
1435 tc35874x_print_register_map(sd);
1436 return -EINVAL;
1437 }
1438
1439 reg->size = tc35874x_get_reg_size(reg->reg);
1440
1441 reg->val = i2c_rdreg(sd, reg->reg, reg->size);
1442
1443 return 0;
1444 }
1445
tc35874x_s_register(struct v4l2_subdev * sd,const struct v4l2_dbg_register * reg)1446 static int tc35874x_s_register(struct v4l2_subdev *sd,
1447 const struct v4l2_dbg_register *reg)
1448 {
1449 if (reg->reg > 0xffff) {
1450 tc35874x_print_register_map(sd);
1451 return -EINVAL;
1452 }
1453
1454 /* It should not be possible for the user to enable HDCP with a simple
1455 * v4l2-dbg command.
1456 *
1457 * DO NOT REMOVE THIS unless all other issues with HDCP have been
1458 * resolved.
1459 */
1460 if (reg->reg == HDCP_MODE ||
1461 reg->reg == HDCP_REG1 ||
1462 reg->reg == HDCP_REG2 ||
1463 reg->reg == HDCP_REG3 ||
1464 reg->reg == BCAPS)
1465 return 0;
1466
1467 i2c_wrreg(sd, (u16)reg->reg, reg->val,
1468 tc35874x_get_reg_size(reg->reg));
1469
1470 return 0;
1471 }
1472 #endif
1473
tc35874x_isr(struct v4l2_subdev * sd,u32 status,bool * handled)1474 static int tc35874x_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1475 {
1476 u16 intstatus = i2c_rd16(sd, INTSTATUS);
1477
1478 v4l2_dbg(1, debug, sd, "%s: IntStatus = 0x%04x\n", __func__, intstatus);
1479
1480 if (intstatus & MASK_HDMI_INT) {
1481 u8 hdmi_int0 = i2c_rd8(sd, HDMI_INT0);
1482 u8 hdmi_int1 = i2c_rd8(sd, HDMI_INT1);
1483
1484 if (hdmi_int0 & MASK_I_MISC)
1485 tc35874x_hdmi_misc_int_handler(sd, handled);
1486 if (hdmi_int1 & MASK_I_CBIT)
1487 tc35874x_hdmi_cbit_int_handler(sd, handled);
1488 if (hdmi_int1 & MASK_I_CLK)
1489 tc35874x_hdmi_clk_int_handler(sd, handled);
1490 if (hdmi_int1 & MASK_I_SYS)
1491 tc35874x_hdmi_sys_int_handler(sd, handled);
1492 if (hdmi_int1 & MASK_I_AUD)
1493 tc35874x_hdmi_audio_int_handler(sd, handled);
1494
1495 i2c_wr16(sd, INTSTATUS, MASK_HDMI_INT);
1496 intstatus &= ~MASK_HDMI_INT;
1497 }
1498
1499 if (intstatus & MASK_CSI_INT) {
1500 u32 csi_int = i2c_rd32(sd, CSI_INT);
1501
1502 if (csi_int & MASK_INTER)
1503 tc35874x_csi_err_int_handler(sd, handled);
1504
1505 i2c_wr16(sd, INTSTATUS, MASK_CSI_INT);
1506 }
1507
1508 intstatus = i2c_rd16(sd, INTSTATUS);
1509 if (intstatus) {
1510 v4l2_dbg(1, debug, sd,
1511 "%s: Unhandled IntStatus interrupts: 0x%02x\n",
1512 __func__, intstatus);
1513 }
1514
1515 return 0;
1516 }
1517
tc35874x_irq_handler(int irq,void * dev_id)1518 static irqreturn_t tc35874x_irq_handler(int irq, void *dev_id)
1519 {
1520 struct tc35874x_state *state = dev_id;
1521 bool handled = false;
1522
1523 tc35874x_isr(&state->sd, 0, &handled);
1524
1525 return handled ? IRQ_HANDLED : IRQ_NONE;
1526 }
1527
tc35874x_irq_poll_timer(struct timer_list * t)1528 static void tc35874x_irq_poll_timer(struct timer_list *t)
1529 {
1530 struct tc35874x_state *state = from_timer(state, t, timer);
1531 unsigned int msecs;
1532
1533 schedule_work(&state->work_i2c_poll);
1534
1535 /*
1536 * If CEC is present, then we need to poll more frequently,
1537 * otherwise we will miss CEC messages.
1538 */
1539 msecs = state->cec_adap ? POLL_INTERVAL_CEC_MS : POLL_INTERVAL_MS;
1540 mod_timer(&state->timer, jiffies + msecs_to_jiffies(msecs));
1541 }
1542
tc35874x_work_i2c_poll(struct work_struct * work)1543 static void tc35874x_work_i2c_poll(struct work_struct *work)
1544 {
1545 struct tc35874x_state *state = container_of(work,
1546 struct tc35874x_state, work_i2c_poll);
1547 bool handled;
1548
1549 tc35874x_isr(&state->sd, 0, &handled);
1550 }
1551
tc35874x_subscribe_event(struct v4l2_subdev * sd,struct v4l2_fh * fh,struct v4l2_event_subscription * sub)1552 static int tc35874x_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh,
1553 struct v4l2_event_subscription *sub)
1554 {
1555 switch (sub->type) {
1556 case V4L2_EVENT_SOURCE_CHANGE:
1557 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
1558 case V4L2_EVENT_CTRL:
1559 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
1560 default:
1561 return -EINVAL;
1562 }
1563 }
1564
1565 /* --------------- VIDEO OPS --------------- */
1566
tc35874x_g_input_status(struct v4l2_subdev * sd,u32 * status)1567 static int tc35874x_g_input_status(struct v4l2_subdev *sd, u32 *status)
1568 {
1569 *status = 0;
1570 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1571 *status |= no_sync(sd) ? V4L2_IN_ST_NO_SYNC : 0;
1572
1573 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1574
1575 return 0;
1576 }
1577
tc35874x_s_dv_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)1578 static int tc35874x_s_dv_timings(struct v4l2_subdev *sd,
1579 struct v4l2_dv_timings *timings)
1580 {
1581 struct tc35874x_state *state = to_state(sd);
1582
1583 if (!timings)
1584 return -EINVAL;
1585
1586 if (debug)
1587 v4l2_print_dv_timings(sd->name, "tc35874x_s_dv_timings: ",
1588 timings, false);
1589
1590 if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) {
1591 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1592 return 0;
1593 }
1594
1595 if (!v4l2_valid_dv_timings(timings,
1596 &tc35874x_timings_cap, NULL, NULL)) {
1597 v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
1598 return -ERANGE;
1599 }
1600
1601 state->timings = *timings;
1602
1603 enable_stream(sd, false);
1604 tc35874x_set_pll(sd);
1605 tc35874x_set_csi(sd);
1606
1607 return 0;
1608 }
1609
tc35874x_g_dv_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)1610 static int tc35874x_g_dv_timings(struct v4l2_subdev *sd,
1611 struct v4l2_dv_timings *timings)
1612 {
1613 struct tc35874x_state *state = to_state(sd);
1614
1615 *timings = state->timings;
1616
1617 return 0;
1618 }
1619
tc35874x_enum_dv_timings(struct v4l2_subdev * sd,struct v4l2_enum_dv_timings * timings)1620 static int tc35874x_enum_dv_timings(struct v4l2_subdev *sd,
1621 struct v4l2_enum_dv_timings *timings)
1622 {
1623 if (timings->pad != 0)
1624 return -EINVAL;
1625
1626 return v4l2_enum_dv_timings_cap(timings,
1627 &tc35874x_timings_cap, NULL, NULL);
1628 }
1629
tc35874x_query_dv_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)1630 static int tc35874x_query_dv_timings(struct v4l2_subdev *sd,
1631 struct v4l2_dv_timings *timings)
1632 {
1633 int ret;
1634
1635 ret = tc35874x_get_detected_timings(sd, timings);
1636 if (ret)
1637 return ret;
1638
1639 if (debug)
1640 v4l2_print_dv_timings(sd->name, "tc35874x_query_dv_timings: ",
1641 timings, false);
1642
1643 if (!v4l2_valid_dv_timings(timings,
1644 &tc35874x_timings_cap, NULL, NULL)) {
1645 v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
1646 return -ERANGE;
1647 }
1648
1649 return 0;
1650 }
1651
tc35874x_dv_timings_cap(struct v4l2_subdev * sd,struct v4l2_dv_timings_cap * cap)1652 static int tc35874x_dv_timings_cap(struct v4l2_subdev *sd,
1653 struct v4l2_dv_timings_cap *cap)
1654 {
1655 if (cap->pad != 0)
1656 return -EINVAL;
1657
1658 *cap = tc35874x_timings_cap;
1659
1660 return 0;
1661 }
1662
tc35874x_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad,struct v4l2_mbus_config * cfg)1663 static int tc35874x_g_mbus_config(struct v4l2_subdev *sd,
1664 unsigned int pad, struct v4l2_mbus_config *cfg)
1665 {
1666 struct tc35874x_state *state = to_state(sd);
1667
1668 cfg->type = V4L2_MBUS_CSI2_DPHY;
1669
1670 /* Support for non-continuous CSI-2 clock is missing in the driver */
1671 cfg->flags = V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1672
1673 switch (state->csi_lanes_in_use) {
1674 case 1:
1675 cfg->flags |= V4L2_MBUS_CSI2_1_LANE;
1676 break;
1677 case 2:
1678 cfg->flags |= V4L2_MBUS_CSI2_2_LANE;
1679 break;
1680 case 3:
1681 cfg->flags |= V4L2_MBUS_CSI2_3_LANE;
1682 break;
1683 case 4:
1684 cfg->flags |= V4L2_MBUS_CSI2_4_LANE;
1685 break;
1686 default:
1687 return -EINVAL;
1688 }
1689
1690 return 0;
1691 }
1692
tc35874x_s_stream(struct v4l2_subdev * sd,int enable)1693 static int tc35874x_s_stream(struct v4l2_subdev *sd, int enable)
1694 {
1695 enable_stream(sd, enable);
1696
1697 /* stop stream to reset csi*/
1698 if (!enable)
1699 tc35874x_set_csi(sd);
1700 return 0;
1701 }
1702
1703 /* --------------- PAD OPS --------------- */
1704
tc35874x_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)1705 static int tc35874x_enum_mbus_code(struct v4l2_subdev *sd,
1706 struct v4l2_subdev_pad_config *cfg,
1707 struct v4l2_subdev_mbus_code_enum *code)
1708 {
1709 switch (code->index) {
1710 case 0:
1711 code->code = MEDIA_BUS_FMT_UYVY8_2X8;
1712 break;
1713 /*
1714 case 1:
1715 code->code = MEDIA_BUS_FMT_RGB888_1X24;
1716 break;
1717 */
1718 default:
1719 return -EINVAL;
1720 }
1721 return 0;
1722 }
1723
tc35874x_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)1724 static int tc35874x_enum_frame_sizes(struct v4l2_subdev *sd,
1725 struct v4l2_subdev_pad_config *cfg,
1726 struct v4l2_subdev_frame_size_enum *fse)
1727 {
1728 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1729
1730 if (fse->index >= ARRAY_SIZE(supported_modes))
1731 return -EINVAL;
1732
1733 if (fse->code != MEDIA_BUS_FMT_UYVY8_2X8)
1734 return -EINVAL;
1735
1736 fse->min_width = supported_modes[fse->index].width;
1737 fse->max_width = supported_modes[fse->index].width;
1738 fse->max_height = supported_modes[fse->index].height;
1739 fse->min_height = supported_modes[fse->index].height;
1740
1741 return 0;
1742 }
1743
tc35874x_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1744 static int tc35874x_enum_frame_interval(struct v4l2_subdev *sd,
1745 struct v4l2_subdev_pad_config *cfg,
1746 struct v4l2_subdev_frame_interval_enum *fie)
1747 {
1748 if (fie->index >= ARRAY_SIZE(supported_modes))
1749 return -EINVAL;
1750
1751 if (fie->code != MEDIA_BUS_FMT_UYVY8_2X8)
1752 return -EINVAL;
1753
1754 fie->width = supported_modes[fie->index].width;
1755 fie->height = supported_modes[fie->index].height;
1756 fie->interval = supported_modes[fie->index].max_fps;
1757 return 0;
1758 }
1759
tc35874x_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * format)1760 static int tc35874x_get_fmt(struct v4l2_subdev *sd,
1761 struct v4l2_subdev_pad_config *cfg,
1762 struct v4l2_subdev_format *format)
1763 {
1764 struct tc35874x_state *state = to_state(sd);
1765 u8 vi_rep = i2c_rd8(sd, VI_REP);
1766
1767 format->format.code = state->mbus_fmt_code;
1768 format->format.width = state->timings.bt.width;
1769 format->format.height = state->timings.bt.height;
1770 format->format.field =
1771 state->timings.bt.interlaced ?
1772 V4L2_FIELD_INTERLACED : V4L2_FIELD_NONE;
1773
1774 switch (vi_rep & MASK_VOUT_COLOR_SEL) {
1775 case MASK_VOUT_COLOR_RGB_FULL:
1776 case MASK_VOUT_COLOR_RGB_LIMITED:
1777 format->format.colorspace = V4L2_COLORSPACE_SRGB;
1778 break;
1779 case MASK_VOUT_COLOR_601_YCBCR_LIMITED:
1780 case MASK_VOUT_COLOR_601_YCBCR_FULL:
1781 format->format.colorspace = V4L2_COLORSPACE_SMPTE170M;
1782 break;
1783 case MASK_VOUT_COLOR_709_YCBCR_FULL:
1784 case MASK_VOUT_COLOR_709_YCBCR_LIMITED:
1785 format->format.colorspace = V4L2_COLORSPACE_REC709;
1786 break;
1787 default:
1788 format->format.colorspace = 0;
1789 break;
1790 }
1791
1792 return 0;
1793 }
1794
tc35874x_get_reso_dist(const struct tc35874x_mode * mode,struct v4l2_mbus_framefmt * framefmt)1795 static int tc35874x_get_reso_dist(const struct tc35874x_mode *mode,
1796 struct v4l2_mbus_framefmt *framefmt)
1797 {
1798 return abs(mode->width - framefmt->width) +
1799 abs(mode->height - framefmt->height);
1800 }
1801
1802 static const struct tc35874x_mode *
tc35874x_find_best_fit(struct v4l2_subdev_format * fmt)1803 tc35874x_find_best_fit(struct v4l2_subdev_format *fmt)
1804 {
1805 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
1806 int dist;
1807 int cur_best_fit = 0;
1808 int cur_best_fit_dist = -1;
1809 unsigned int i;
1810
1811 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
1812 dist = tc35874x_get_reso_dist(&supported_modes[i], framefmt);
1813 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
1814 cur_best_fit_dist = dist;
1815 cur_best_fit = i;
1816 }
1817 }
1818
1819 return &supported_modes[cur_best_fit];
1820 }
1821
tc35874x_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * format)1822 static int tc35874x_set_fmt(struct v4l2_subdev *sd,
1823 struct v4l2_subdev_pad_config *cfg,
1824 struct v4l2_subdev_format *format)
1825 {
1826 struct tc35874x_state *state = to_state(sd);
1827 const struct tc35874x_mode *mode;
1828
1829 u32 code = format->format.code; /* is overwritten by get_fmt */
1830 int ret = tc35874x_get_fmt(sd, cfg, format);
1831
1832 format->format.code = code;
1833
1834 if (ret)
1835 return ret;
1836
1837 switch (code) {
1838 case MEDIA_BUS_FMT_RGB888_1X24:
1839 case MEDIA_BUS_FMT_UYVY8_2X8:
1840 break;
1841 default:
1842 return -EINVAL;
1843 }
1844
1845 if (format->which == V4L2_SUBDEV_FORMAT_TRY)
1846 return 0;
1847
1848 state->mbus_fmt_code = format->format.code;
1849
1850 enable_stream(sd, false);
1851 mode = tc35874x_find_best_fit(format);
1852 state->cur_mode = mode;
1853
1854 __v4l2_ctrl_s_ctrl(state->link_freq,
1855 link_freq_menu_items[0]);
1856 __v4l2_ctrl_s_ctrl_int64(state->pixel_rate,
1857 TC35874X_PIXEL_RATE_310M);
1858
1859 tc35874x_set_pll(sd);
1860 tc35874x_set_csi(sd);
1861 tc35874x_set_csi_color_space(sd);
1862
1863 return 0;
1864 }
1865
tc35874x_g_edid(struct v4l2_subdev * sd,struct v4l2_subdev_edid * edid)1866 static int tc35874x_g_edid(struct v4l2_subdev *sd,
1867 struct v4l2_subdev_edid *edid)
1868 {
1869 struct tc35874x_state *state = to_state(sd);
1870
1871 memset(edid->reserved, 0, sizeof(edid->reserved));
1872
1873 if (edid->pad != 0)
1874 return -EINVAL;
1875
1876 if (edid->start_block == 0 && edid->blocks == 0) {
1877 edid->blocks = state->edid_blocks_written;
1878 return 0;
1879 }
1880
1881 if (state->edid_blocks_written == 0)
1882 return -ENODATA;
1883
1884 if (edid->start_block >= state->edid_blocks_written ||
1885 edid->blocks == 0)
1886 return -EINVAL;
1887
1888 if (edid->start_block + edid->blocks > state->edid_blocks_written)
1889 edid->blocks = state->edid_blocks_written - edid->start_block;
1890
1891 i2c_rd(sd, EDID_RAM + (edid->start_block * EDID_BLOCK_SIZE), edid->edid,
1892 edid->blocks * EDID_BLOCK_SIZE);
1893
1894 return 0;
1895 }
1896
tc35874x_s_edid(struct v4l2_subdev * sd,struct v4l2_subdev_edid * edid)1897 static int tc35874x_s_edid(struct v4l2_subdev *sd,
1898 struct v4l2_subdev_edid *edid)
1899 {
1900 struct tc35874x_state *state = to_state(sd);
1901 u16 edid_len = edid->blocks * EDID_BLOCK_SIZE;
1902 int i;
1903
1904 v4l2_dbg(2, debug, sd, "%s, pad %d, start block %d, blocks %d\n",
1905 __func__, edid->pad, edid->start_block, edid->blocks);
1906
1907 memset(edid->reserved, 0, sizeof(edid->reserved));
1908
1909 if (edid->pad != 0)
1910 return -EINVAL;
1911
1912 if (edid->start_block != 0)
1913 return -EINVAL;
1914
1915 if (edid->blocks > EDID_NUM_BLOCKS_MAX) {
1916 edid->blocks = EDID_NUM_BLOCKS_MAX;
1917 return -E2BIG;
1918 }
1919
1920 tc35874x_disable_edid(sd);
1921
1922 i2c_wr8(sd, EDID_LEN1, edid_len & 0xff);
1923 i2c_wr8(sd, EDID_LEN2, edid_len >> 8);
1924
1925 if (edid->blocks == 0) {
1926 state->edid_blocks_written = 0;
1927 return 0;
1928 }
1929
1930 for (i = 0; i < edid_len; i += EDID_BLOCK_SIZE) {
1931 i2c_wr(sd, EDID_RAM + i, edid->edid + i, EDID_BLOCK_SIZE);
1932 i2c_wr(sd, EDID_EXT_RAM + i, EDID_extend + i, EDID_BLOCK_SIZE);
1933 }
1934
1935 state->edid_blocks_written = edid->blocks;
1936
1937 if (tx_5v_power_present(sd))
1938 tc35874x_enable_edid(sd);
1939
1940 return 0;
1941 }
1942
tc35874x_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)1943 static int tc35874x_g_frame_interval(struct v4l2_subdev *sd,
1944 struct v4l2_subdev_frame_interval *fi)
1945 {
1946 struct tc35874x_state *state = to_state(sd);
1947 const struct tc35874x_mode *mode = state->cur_mode;
1948
1949 mutex_lock(&state->confctl_mutex);
1950 fi->interval = mode->max_fps;
1951 mutex_unlock(&state->confctl_mutex);
1952
1953 return 0;
1954 }
1955
tc35874x_get_module_inf(struct tc35874x_state * tc35874x,struct rkmodule_inf * inf)1956 static void tc35874x_get_module_inf(struct tc35874x_state *tc35874x,
1957 struct rkmodule_inf *inf)
1958 {
1959 memset(inf, 0, sizeof(*inf));
1960 strlcpy(inf->base.sensor, TC35874X_NAME, sizeof(inf->base.sensor));
1961 strlcpy(inf->base.module, tc35874x->module_name,
1962 sizeof(inf->base.module));
1963 strlcpy(inf->base.lens, tc35874x->len_name, sizeof(inf->base.lens));
1964 }
1965
tc35874x_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)1966 static long tc35874x_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
1967 {
1968 struct tc35874x_state *tc35874x = to_state(sd);
1969 long ret = 0;
1970
1971 switch (cmd) {
1972 case RKMODULE_GET_MODULE_INFO:
1973 tc35874x_get_module_inf(tc35874x, (struct rkmodule_inf *)arg);
1974 break;
1975 default:
1976 ret = -ENOIOCTLCMD;
1977 break;
1978 }
1979
1980 return ret;
1981 }
1982
1983 #ifdef CONFIG_COMPAT
tc35874x_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)1984 static long tc35874x_compat_ioctl32(struct v4l2_subdev *sd,
1985 unsigned int cmd, unsigned long arg)
1986 {
1987 void __user *up = compat_ptr(arg);
1988 struct rkmodule_inf *inf;
1989 struct rkmodule_awb_cfg *cfg;
1990 long ret;
1991
1992 switch (cmd) {
1993 case RKMODULE_GET_MODULE_INFO:
1994 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
1995 if (!inf) {
1996 ret = -ENOMEM;
1997 return ret;
1998 }
1999
2000 ret = tc35874x_ioctl(sd, cmd, inf);
2001 if (!ret) {
2002 ret = copy_to_user(up, inf, sizeof(*inf));
2003 if (ret)
2004 ret = -EFAULT;
2005 }
2006 kfree(inf);
2007 break;
2008 case RKMODULE_AWB_CFG:
2009 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
2010 if (!cfg) {
2011 ret = -ENOMEM;
2012 return ret;
2013 }
2014
2015 ret = copy_from_user(cfg, up, sizeof(*cfg));
2016 if (!ret)
2017 ret = tc35874x_ioctl(sd, cmd, cfg);
2018 else
2019 ret = -EFAULT;
2020 kfree(cfg);
2021 break;
2022 default:
2023 ret = -ENOIOCTLCMD;
2024 break;
2025 }
2026
2027 return ret;
2028 }
2029 #endif
2030
2031 /* -------------------------------------------------------------------------- */
2032
2033 static const struct v4l2_ctrl_ops tc35874x_ctrl_ops = {
2034 .g_volatile_ctrl = tc35874x_get_ctrl,
2035 };
2036
2037 static const struct v4l2_subdev_core_ops tc35874x_core_ops = {
2038 .log_status = tc35874x_log_status,
2039 #ifdef CONFIG_VIDEO_ADV_DEBUG
2040 .g_register = tc35874x_g_register,
2041 .s_register = tc35874x_s_register,
2042 #endif
2043 .interrupt_service_routine = tc35874x_isr,
2044 .subscribe_event = tc35874x_subscribe_event,
2045 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
2046 .ioctl = tc35874x_ioctl,
2047 #ifdef CONFIG_COMPAT
2048 .compat_ioctl32 = tc35874x_compat_ioctl32,
2049 #endif
2050 };
2051
2052 static const struct v4l2_subdev_video_ops tc35874x_video_ops = {
2053 .g_input_status = tc35874x_g_input_status,
2054 .s_dv_timings = tc35874x_s_dv_timings,
2055 .g_dv_timings = tc35874x_g_dv_timings,
2056 .query_dv_timings = tc35874x_query_dv_timings,
2057 .s_stream = tc35874x_s_stream,
2058 .g_frame_interval = tc35874x_g_frame_interval,
2059 };
2060
2061 static const struct v4l2_subdev_pad_ops tc35874x_pad_ops = {
2062 .enum_mbus_code = tc35874x_enum_mbus_code,
2063 .enum_frame_size = tc35874x_enum_frame_sizes,
2064 .enum_frame_interval = tc35874x_enum_frame_interval,
2065 .set_fmt = tc35874x_set_fmt,
2066 .get_fmt = tc35874x_get_fmt,
2067 .get_edid = tc35874x_g_edid,
2068 .set_edid = tc35874x_s_edid,
2069 .enum_dv_timings = tc35874x_enum_dv_timings,
2070 .dv_timings_cap = tc35874x_dv_timings_cap,
2071 .get_mbus_config = tc35874x_g_mbus_config,
2072 };
2073
2074 static const struct v4l2_subdev_ops tc35874x_ops = {
2075 .core = &tc35874x_core_ops,
2076 .video = &tc35874x_video_ops,
2077 .pad = &tc35874x_pad_ops,
2078 };
2079
2080 /* --------------- CUSTOM CTRLS --------------- */
tc35874x_get_custom_ctrl(struct v4l2_ctrl * ctrl)2081 static int tc35874x_get_custom_ctrl(struct v4l2_ctrl *ctrl)
2082 {
2083 int ret = -EINVAL;
2084 struct tc35874x_state *state = container_of(ctrl->handler,
2085 struct tc35874x_state, hdl);
2086 struct v4l2_subdev *sd = &state->sd;
2087
2088 if (ctrl->id == TC35874X_CID_AUDIO_SAMPLING_RATE) {
2089 ret = get_audio_sampling_rate(sd);
2090 *ctrl->p_new.p_s32 = ret;
2091 }
2092
2093 return ret;
2094 }
2095
2096 static const struct v4l2_ctrl_ops tc35874x_custom_ctrl_ops = {
2097 .g_volatile_ctrl = tc35874x_get_custom_ctrl,
2098 };
2099
2100 static const struct v4l2_ctrl_config tc35874x_ctrl_audio_sampling_rate = {
2101 .ops = &tc35874x_custom_ctrl_ops,
2102 .id = TC35874X_CID_AUDIO_SAMPLING_RATE,
2103 .name = "Audio sampling rate",
2104 .type = V4L2_CTRL_TYPE_INTEGER,
2105 .min = 0,
2106 .max = 768000,
2107 .step = 1,
2108 .def = 0,
2109 .flags = V4L2_CTRL_FLAG_READ_ONLY,
2110 };
2111
2112 static const struct v4l2_ctrl_config tc35874x_ctrl_audio_present = {
2113 .id = TC35874X_CID_AUDIO_PRESENT,
2114 .name = "Audio present",
2115 .type = V4L2_CTRL_TYPE_BOOLEAN,
2116 .min = 0,
2117 .max = 1,
2118 .step = 1,
2119 .def = 0,
2120 .flags = V4L2_CTRL_FLAG_READ_ONLY,
2121 };
2122
2123 /* --------------- PROBE / REMOVE --------------- */
2124
2125 #ifdef CONFIG_OF
tc35874x_gpio_reset(struct tc35874x_state * state)2126 static void tc35874x_gpio_reset(struct tc35874x_state *state)
2127 {
2128 usleep_range(5000, 10000);
2129 gpiod_set_value(state->reset_gpio, 1);
2130 usleep_range(1000, 2000);
2131 gpiod_set_value(state->reset_gpio, 0);
2132 msleep(20);
2133 }
2134
tc35874x_probe_of(struct tc35874x_state * state)2135 static int tc35874x_probe_of(struct tc35874x_state *state)
2136 {
2137 struct device *dev = &state->i2c_client->dev;
2138 struct v4l2_fwnode_endpoint endpoint = { .bus_type = 0 };
2139 struct device_node *ep;
2140 struct clk *refclk;
2141 u32 bps_pr_lane;
2142 int ret = -EINVAL;
2143
2144 refclk = devm_clk_get(dev, "refclk");
2145 if (IS_ERR(refclk)) {
2146 if (PTR_ERR(refclk) != -EPROBE_DEFER)
2147 dev_err(dev, "failed to get refclk: %ld\n",
2148 PTR_ERR(refclk));
2149 return PTR_ERR(refclk);
2150 }
2151
2152 ep = of_graph_get_next_endpoint(dev->of_node, NULL);
2153 if (!ep) {
2154 dev_err(dev, "missing endpoint node\n");
2155 return -EINVAL;
2156 }
2157
2158 ret = v4l2_fwnode_endpoint_alloc_parse(of_fwnode_handle(ep), &endpoint);
2159 if (ret) {
2160 dev_err(dev, "failed to parse endpoint\n");
2161 goto put_node;
2162 }
2163
2164 if (endpoint.bus_type != V4L2_MBUS_CSI2_DPHY ||
2165 endpoint.bus.mipi_csi2.num_data_lanes == 0 ||
2166 endpoint.nr_of_link_frequencies == 0) {
2167 dev_err(dev, "missing CSI-2 properties in endpoint\n");
2168 goto free_endpoint;
2169 }
2170
2171 state->csi_lanes_in_use = endpoint.bus.mipi_csi2.num_data_lanes;
2172 state->bus = endpoint.bus.mipi_csi2;
2173
2174 ret = clk_prepare_enable(refclk);
2175 if (ret) {
2176 dev_err(dev, "Failed! to enable clock\n");
2177 goto free_endpoint;
2178 }
2179
2180 state->pdata.refclk_hz = clk_get_rate(refclk);
2181 state->pdata.ddc5v_delay = DDC5V_DELAY_100_MS;
2182 state->pdata.enable_hdcp = false;
2183 /* A FIFO level of 16 should be enough for 2-lane 720p60 at 594 MHz. */
2184 state->pdata.fifo_level = 16;
2185 /*
2186 * The PLL input clock is obtained by dividing refclk by pll_prd.
2187 * It must be between 6 MHz and 40 MHz, lower frequency is better.
2188 */
2189 switch (state->pdata.refclk_hz) {
2190 case 26000000:
2191 case 27000000:
2192 case 42000000:
2193 state->pdata.pll_prd = state->pdata.refclk_hz / 6000000;
2194 break;
2195 default:
2196 dev_err(dev, "unsupported refclk rate: %u Hz\n",
2197 state->pdata.refclk_hz);
2198 goto disable_clk;
2199 }
2200
2201 /*
2202 * The CSI bps per lane must be between 62.5 Mbps and 1 Gbps.
2203 * The default is 594 Mbps for 4-lane 1080p60 or 2-lane 720p60.
2204 */
2205 bps_pr_lane = 2 * endpoint.link_frequencies[0];
2206 if (bps_pr_lane < 62500000U || bps_pr_lane > 1000000000U) {
2207 dev_err(dev, "unsupported bps per lane: %u bps\n", bps_pr_lane);
2208 goto disable_clk;
2209 }
2210
2211 /* The CSI speed per lane is refclk / pll_prd * pll_fbd */
2212 state->pdata.pll_fbd = bps_pr_lane /
2213 state->pdata.refclk_hz * state->pdata.pll_prd;
2214
2215 /*
2216 * FIXME: These timings are from REF_02 for 594 Mbps per lane (297 MHz
2217 * link frequency). In principle it should be possible to calculate
2218 * them based on link frequency and resolution.
2219 */
2220 if (bps_pr_lane != 594000000U)
2221 dev_warn(dev, "untested bps per lane: %u bps\n", bps_pr_lane);
2222 state->pdata.lineinitcnt = 0xe80;
2223 state->pdata.lptxtimecnt = 0x003;
2224 /* tclk-preparecnt: 3, tclk-zerocnt: 20 */
2225 state->pdata.tclk_headercnt = 0x1403;
2226 state->pdata.tclk_trailcnt = 0x00;
2227 /* ths-preparecnt: 3, ths-zerocnt: 1 */
2228 state->pdata.ths_headercnt = 0x0103;
2229 state->pdata.twakeup = 0x4882;
2230 state->pdata.tclk_postcnt = 0x008;
2231 state->pdata.ths_trailcnt = 0x2;
2232 state->pdata.hstxvregcnt = 0;
2233
2234 state->reset_gpio = devm_gpiod_get_optional(dev, "reset",
2235 GPIOD_OUT_LOW);
2236 if (IS_ERR(state->reset_gpio)) {
2237 dev_err(dev, "failed to get reset gpio\n");
2238 ret = PTR_ERR(state->reset_gpio);
2239 goto disable_clk;
2240 }
2241
2242 if (state->reset_gpio)
2243 tc35874x_gpio_reset(state);
2244
2245 ret = 0;
2246 goto free_endpoint;
2247
2248 disable_clk:
2249 clk_disable_unprepare(refclk);
2250 free_endpoint:
2251 v4l2_fwnode_endpoint_free(&endpoint);
2252 put_node:
2253 of_node_put(ep);
2254 return ret;
2255 }
2256 #else
tc35874x_probe_of(struct tc35874x_state * state)2257 static inline int tc35874x_probe_of(struct tc35874x_state *state)
2258 {
2259 return -ENODEV;
2260 }
2261 #endif
2262
tc35874x_probe(struct i2c_client * client,const struct i2c_device_id * id)2263 static int tc35874x_probe(struct i2c_client *client,
2264 const struct i2c_device_id *id)
2265 {
2266 static struct v4l2_dv_timings default_timing =
2267 V4L2_DV_BT_CEA_640X480P59_94;
2268 struct tc35874x_state *state;
2269 struct tc35874x_platform_data *pdata = client->dev.platform_data;
2270 struct v4l2_subdev *sd;
2271 struct v4l2_subdev_edid def_edid;
2272 struct device *dev = &client->dev;
2273 struct device_node *node = dev->of_node;
2274 char facing[2];
2275 int err, data;
2276
2277 dev_info(dev, "driver version: %02x.%02x.%02x",
2278 DRIVER_VERSION >> 16,
2279 (DRIVER_VERSION & 0xff00) >> 8,
2280 DRIVER_VERSION & 0x00ff);
2281
2282 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
2283 return -EIO;
2284 v4l_dbg(1, debug, client, "chip found @ 0x%x (%s)\n",
2285 client->addr << 1, client->adapter->name);
2286
2287 state = devm_kzalloc(&client->dev, sizeof(struct tc35874x_state),
2288 GFP_KERNEL);
2289 if (!state)
2290 return -ENOMEM;
2291
2292 err = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
2293 &state->module_index);
2294 err |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
2295 &state->module_facing);
2296 err |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
2297 &state->module_name);
2298 err |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
2299 &state->len_name);
2300 if (err) {
2301 dev_err(dev, "could not get module information!\n");
2302 return -EINVAL;
2303 }
2304
2305 state->i2c_client = client;
2306 state->cur_mode = &supported_modes[0];
2307
2308 /* platform data */
2309 if (pdata) {
2310 state->pdata = *pdata;
2311 state->bus.flags = V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
2312 } else {
2313 err = tc35874x_probe_of(state);
2314 if (err == -ENODEV)
2315 v4l_err(client, "No platform data!\n");
2316 if (err)
2317 return err;
2318 }
2319
2320 sd = &state->sd;
2321 v4l2_i2c_subdev_init(sd, client, &tc35874x_ops);
2322 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
2323
2324 /* i2c access */
2325 data = i2c_rd16(sd, CHIPID) & MASK_CHIPID;
2326 switch (data) {
2327 case 0x0000:
2328 case 0x4700:
2329 break;
2330 default:
2331 v4l2_info(sd, "not a tc35874x on address 0x%x\n",
2332 client->addr << 1);
2333 return -ENODEV;
2334 }
2335
2336 /* control handlers */
2337 v4l2_ctrl_handler_init(&state->hdl, 4);
2338
2339 state->link_freq = v4l2_ctrl_new_int_menu(&state->hdl, NULL,
2340 V4L2_CID_LINK_FREQ, 0, 0, link_freq_menu_items);
2341
2342 state->pixel_rate = v4l2_ctrl_new_std(&state->hdl, NULL,
2343 V4L2_CID_PIXEL_RATE, 0, TC35874X_PIXEL_RATE_310M, 1,
2344 TC35874X_PIXEL_RATE_310M);
2345
2346 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(&state->hdl,
2347 &tc35874x_ctrl_ops, V4L2_CID_DV_RX_POWER_PRESENT,
2348 0, 1, 0, 0);
2349
2350 if (state->detect_tx_5v_ctrl)
2351 state->detect_tx_5v_ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;
2352
2353 /* custom controls */
2354 state->audio_sampling_rate_ctrl = v4l2_ctrl_new_custom(&state->hdl,
2355 &tc35874x_ctrl_audio_sampling_rate, NULL);
2356 if (state->audio_sampling_rate_ctrl)
2357 state->audio_sampling_rate_ctrl->flags |=
2358 V4L2_CTRL_FLAG_VOLATILE;
2359
2360 state->audio_present_ctrl = v4l2_ctrl_new_custom(&state->hdl,
2361 &tc35874x_ctrl_audio_present, NULL);
2362
2363 sd->ctrl_handler = &state->hdl;
2364 if (state->hdl.error) {
2365 err = state->hdl.error;
2366 goto err_hdl;
2367 }
2368
2369 if (tc35874x_update_controls(sd)) {
2370 err = -ENODEV;
2371 goto err_hdl;
2372 }
2373
2374 state->pad.flags = MEDIA_PAD_FL_SOURCE;
2375 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
2376 err = media_entity_pads_init(&sd->entity, 1, &state->pad);
2377 if (err < 0)
2378 goto err_hdl;
2379
2380 state->mbus_fmt_code = MEDIA_BUS_FMT_UYVY8_2X8;
2381
2382 sd->dev = &client->dev;
2383 memset(facing, 0, sizeof(facing));
2384 if (strcmp(state->module_facing, "back") == 0)
2385 facing[0] = 'b';
2386 else
2387 facing[0] = 'f';
2388
2389 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
2390 state->module_index, facing,
2391 TC35874X_NAME, dev_name(sd->dev));
2392 err = v4l2_async_register_subdev(sd);
2393 if (err < 0)
2394 goto err_hdl;
2395
2396 mutex_init(&state->confctl_mutex);
2397
2398 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
2399 tc35874x_delayed_work_enable_hotplug);
2400
2401 tc35874x_initial_setup(sd);
2402
2403 tc35874x_s_dv_timings(sd, &default_timing);
2404
2405 tc35874x_set_csi_color_space(sd);
2406
2407 def_edid.pad = 0;
2408 def_edid.start_block = 0;
2409 def_edid.blocks = 1;
2410 def_edid.edid = EDID_1920x1080_60;
2411
2412 tc35874x_s_edid(sd, &def_edid);
2413
2414 tc35874x_init_interrupts(sd);
2415
2416 if (state->i2c_client->irq) {
2417 err = devm_request_threaded_irq(&client->dev,
2418 state->i2c_client->irq,
2419 NULL, tc35874x_irq_handler,
2420 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
2421 "tc35874x", state);
2422 if (err)
2423 goto err_work_queues;
2424 } else {
2425 INIT_WORK(&state->work_i2c_poll,
2426 tc35874x_work_i2c_poll);
2427 timer_setup(&state->timer, tc35874x_irq_poll_timer, 0);
2428 state->timer.expires = jiffies +
2429 msecs_to_jiffies(POLL_INTERVAL_MS);
2430 add_timer(&state->timer);
2431 }
2432
2433 tc35874x_enable_interrupts(sd, tx_5v_power_present(sd));
2434 i2c_wr16(sd, INTMASK, ~(MASK_HDMI_MSK | MASK_CSI_MSK) & 0xffff);
2435
2436 err = v4l2_ctrl_handler_setup(sd->ctrl_handler);
2437 if (err)
2438 goto err_work_queues;
2439
2440 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
2441 client->addr << 1, client->adapter->name);
2442
2443 return 0;
2444
2445 err_work_queues:
2446 if (!state->i2c_client->irq)
2447 flush_work(&state->work_i2c_poll);
2448 cancel_delayed_work(&state->delayed_work_enable_hotplug);
2449 mutex_destroy(&state->confctl_mutex);
2450 err_hdl:
2451 media_entity_cleanup(&sd->entity);
2452 v4l2_ctrl_handler_free(&state->hdl);
2453 return err;
2454 }
2455
tc35874x_remove(struct i2c_client * client)2456 static int tc35874x_remove(struct i2c_client *client)
2457 {
2458 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2459 struct tc35874x_state *state = to_state(sd);
2460
2461 if (!state->i2c_client->irq) {
2462 del_timer_sync(&state->timer);
2463 flush_work(&state->work_i2c_poll);
2464 }
2465 cancel_delayed_work(&state->delayed_work_enable_hotplug);
2466 v4l2_async_unregister_subdev(sd);
2467 v4l2_device_unregister_subdev(sd);
2468 mutex_destroy(&state->confctl_mutex);
2469 media_entity_cleanup(&sd->entity);
2470 v4l2_ctrl_handler_free(&state->hdl);
2471
2472 return 0;
2473 }
2474
2475 static struct i2c_device_id tc35874x_id[] = {
2476 {"tc358743", 0},
2477 {"tc358749", 0},
2478 {}
2479 };
2480
2481 MODULE_DEVICE_TABLE(i2c, tc35874x_id);
2482
2483 #if IS_ENABLED(CONFIG_OF)
2484 static const struct of_device_id tc35874x_of_match[] = {
2485 { .compatible = "toshiba,tc358743" },
2486 { .compatible = "toshiba,tc358749" },
2487 {},
2488 };
2489 MODULE_DEVICE_TABLE(of, tc35874x_of_match);
2490 #endif
2491
2492 static struct i2c_driver tc35874x_driver = {
2493 .driver = {
2494 .name = TC35874X_NAME,
2495 .of_match_table = of_match_ptr(tc35874x_of_match),
2496 },
2497 .probe = tc35874x_probe,
2498 .remove = tc35874x_remove,
2499 .id_table = tc35874x_id,
2500 };
2501
tc35874x_driver_init(void)2502 static int __init tc35874x_driver_init(void)
2503 {
2504 return i2c_add_driver(&tc35874x_driver);
2505 }
2506
tc35874x_driver_exit(void)2507 static void __exit tc35874x_driver_exit(void)
2508 {
2509 i2c_del_driver(&tc35874x_driver);
2510 }
2511
2512 device_initcall_sync(tc35874x_driver_init);
2513 module_exit(tc35874x_driver_exit);
2514