1 /* 2 * tc35874x - Toshiba HDMI to CSI-2 bridge - register names and bit masks 3 * 4 * Copyright 2015 Cisco Systems, Inc. and/or its affiliates. All rights 5 * reserved. 6 * 7 * This program is free software; you may redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; version 2 of the License. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 12 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 13 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 14 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 15 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 16 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 17 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 18 * SOFTWARE. 19 * 20 */ 21 22 /* 23 * References (c = chapter, p = page): 24 * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60 25 * REF_02 - Toshiba, TC358749XBG (H2C+), Functional Specification, Rev 0.74 26 */ 27 28 /* Bit masks has prefix 'MASK_' and options after '_'. */ 29 30 #ifndef __TC35874X_REGS_H 31 #define __TC35874X_REGS_H 32 33 #define CHIPID 0x0000 34 #define MASK_CHIPID 0xff00 35 #define MASK_REVID 0x00ff 36 37 #define SYSCTL 0x0002 38 #define MASK_IRRST 0x0800 39 #define MASK_CECRST 0x0400 40 #define MASK_CTXRST 0x0200 41 #define MASK_HDMIRST 0x0100 42 #define MASK_I2SDIS 0x0080 43 #define MASK_SLEEP 0x0001 44 45 #define CONFCTL 0x0004 46 #define MASK_PWRISO 0x8000 47 #define MASK_ACLKOPT 0x1000 48 #define MASK_AUDCHNUM 0x0c00 49 #define MASK_AUDCHNUM_8 0x0000 50 #define MASK_AUDCHNUM_6 0x0400 51 #define MASK_AUDCHNUM_4 0x0800 52 #define MASK_AUDCHNUM_2 0x0c00 53 #define MASK_AUDCHSEL 0x0200 54 #define MASK_I2SDLYOPT 0x0100 55 #define MASK_YCBCRFMT 0x00c0 56 #define MASK_YCBCRFMT_444 0x0000 57 #define MASK_YCBCRFMT_422_12_BIT 0x0040 58 #define MASK_YCBCRFMT_COLORBAR 0x0080 59 #define MASK_YCBCRFMT_422_8_BIT 0x00c0 60 #define MASK_INFRMEN 0x0020 61 #define MASK_AUDOUTSEL 0x0018 62 #define MASK_AUDOUTSEL_CSI 0x0000 63 #define MASK_AUDOUTSEL_I2S 0x0010 64 #define MASK_AUDOUTSEL_TDM 0x0018 65 #define MASK_AUTOINDEX 0x0004 66 #define MASK_ABUFEN 0x0002 67 #define MASK_VBUFEN 0x0001 68 69 #define FIFOCTL 0x0006 70 71 #define PACKETID1 0x000C 72 73 #define FCCTL 0x0012 74 75 #define INTSTATUS 0x0014 76 #define MASK_AMUTE_INT 0x0400 77 #define MASK_HDMI_INT 0x0200 78 #define MASK_CSI_INT 0x0100 79 #define MASK_SYS_INT 0x0020 80 #define MASK_CEC_EINT 0x0010 81 #define MASK_CEC_TINT 0x0008 82 #define MASK_CEC_RINT 0x0004 83 #define MASK_IR_EINT 0x0002 84 #define MASK_IR_DINT 0x0001 85 86 #define INTMASK 0x0016 87 #define MASK_AMUTE_MSK 0x0400 88 #define MASK_HDMI_MSK 0x0200 89 #define MASK_CSI_MSK 0x0100 90 #define MASK_SYS_MSK 0x0020 91 #define MASK_CEC_EMSK 0x0010 92 #define MASK_CEC_TMSK 0x0008 93 #define MASK_CEC_RMSK 0x0004 94 #define MASK_IR_EMSK 0x0002 95 #define MASK_IR_DMSK 0x0001 96 97 #define INTFLAG 0x0018 98 #define INTSYSSTATUS 0x001A 99 100 #define PLLCTL0 0x0020 101 #define MASK_PLL_PRD 0xf000 102 #define SET_PLL_PRD(prd) ((((prd) - 1) << 12) &\ 103 MASK_PLL_PRD) 104 #define MASK_PLL_FBD 0x01ff 105 #define SET_PLL_FBD(fbd) (((fbd) - 1) & MASK_PLL_FBD) 106 107 #define PLLCTL1 0x0022 108 #define MASK_PLL_FRS 0x0c00 109 #define SET_PLL_FRS(frs) (((frs) << 10) & MASK_PLL_FRS) 110 #define MASK_PLL_LBWS 0x0300 111 #define MASK_LFBREN 0x0040 112 #define MASK_BYPCKEN 0x0020 113 #define MASK_CKEN 0x0010 114 #define MASK_RESETB 0x0002 115 #define MASK_PLL_EN 0x0001 116 117 #define CLW_CNTRL 0x0140 118 #define MASK_CLW_LANEDISABLE 0x0001 119 120 #define D0W_CNTRL 0x0144 121 #define MASK_D0W_LANEDISABLE 0x0001 122 123 #define D1W_CNTRL 0x0148 124 #define MASK_D1W_LANEDISABLE 0x0001 125 126 #define D2W_CNTRL 0x014C 127 #define MASK_D2W_LANEDISABLE 0x0001 128 129 #define D3W_CNTRL 0x0150 130 #define MASK_D3W_LANEDISABLE 0x0001 131 132 #define STARTCNTRL 0x0204 133 #define MASK_START 0x00000001 134 135 #define LINEINITCNT 0x0210 136 #define LPTXTIMECNT 0x0214 137 #define TCLK_HEADERCNT 0x0218 138 #define TCLK_TRAILCNT 0x021C 139 #define THS_HEADERCNT 0x0220 140 #define TWAKEUP 0x0224 141 #define TCLK_POSTCNT 0x0228 142 #define THS_TRAILCNT 0x022C 143 #define HSTXVREGCNT 0x0230 144 145 #define HSTXVREGEN 0x0234 146 #define MASK_D3M_HSTXVREGEN 0x0010 147 #define MASK_D2M_HSTXVREGEN 0x0008 148 #define MASK_D1M_HSTXVREGEN 0x0004 149 #define MASK_D0M_HSTXVREGEN 0x0002 150 #define MASK_CLM_HSTXVREGEN 0x0001 151 152 153 #define TXOPTIONCNTRL 0x0238 154 #define MASK_CONTCLKMODE 0x00000001 155 156 #define CSI_CONTROL 0x040C 157 #define MASK_CSI_MODE 0x8000 158 #define MASK_HTXTOEN 0x0400 159 #define MASK_TXHSMD 0x0080 160 #define MASK_HSCKMD 0x0020 161 #define MASK_NOL 0x0006 162 #define MASK_NOL_1 0x0000 163 #define MASK_NOL_2 0x0002 164 #define MASK_NOL_3 0x0004 165 #define MASK_NOL_4 0x0006 166 #define MASK_EOTDIS 0x0001 167 168 #define CSI_INT 0x0414 169 #define MASK_INTHLT 0x00000008 170 #define MASK_INTER 0x00000004 171 172 #define CSI_INT_ENA 0x0418 173 #define MASK_IENHLT 0x00000008 174 #define MASK_IENER 0x00000004 175 176 #define CSI_ERR 0x044C 177 #define MASK_INER 0x00000200 178 #define MASK_WCER 0x00000100 179 #define MASK_QUNK 0x00000010 180 #define MASK_TXBRK 0x00000002 181 182 #define CSI_ERR_INTENA 0x0450 183 #define CSI_ERR_HALT 0x0454 184 185 #define CSI_CONFW 0x0500 186 #define MASK_MODE 0xe0000000 187 #define MASK_MODE_SET 0xa0000000 188 #define MASK_MODE_CLEAR 0xc0000000 189 #define MASK_ADDRESS 0x1f000000 190 #define MASK_ADDRESS_CSI_CONTROL 0x03000000 191 #define MASK_ADDRESS_CSI_INT_ENA 0x06000000 192 #define MASK_ADDRESS_CSI_ERR_INTENA 0x14000000 193 #define MASK_ADDRESS_CSI_ERR_HALT 0x15000000 194 #define MASK_DATA 0x0000ffff 195 196 #define CSI_INT_CLR 0x050C 197 #define MASK_ICRER 0x00000004 198 199 #define CSI_START 0x0518 200 #define MASK_STRT 0x00000001 201 202 #define CECEN 0x0600 203 #define MASK_CECEN 0x0001 204 205 #define HDMI_INT0 0x8500 206 #define MASK_I_KEY 0x80 207 #define MASK_I_MISC 0x02 208 #define MASK_I_PHYERR 0x01 209 210 #define HDMI_INT1 0x8501 211 #define MASK_I_GBD 0x80 212 #define MASK_I_HDCP 0x40 213 #define MASK_I_ERR 0x20 214 #define MASK_I_AUD 0x10 215 #define MASK_I_CBIT 0x08 216 #define MASK_I_PACKET 0x04 217 #define MASK_I_CLK 0x02 218 #define MASK_I_SYS 0x01 219 220 #define SYS_INT 0x8502 221 #define MASK_I_ACR_CTS 0x80 222 #define MASK_I_ACRN 0x40 223 #define MASK_I_DVI 0x20 224 #define MASK_I_HDMI 0x10 225 #define MASK_I_NOPMBDET 0x08 226 #define MASK_I_DPMBDET 0x04 227 #define MASK_I_TMDS 0x02 228 #define MASK_I_DDC 0x01 229 230 #define CLK_INT 0x8503 231 #define MASK_I_OUT_H_CHG 0x40 232 #define MASK_I_IN_DE_CHG 0x20 233 #define MASK_I_IN_HV_CHG 0x10 234 #define MASK_I_DC_CHG 0x08 235 #define MASK_I_PXCLK_CHG 0x04 236 #define MASK_I_PHYCLK_CHG 0x02 237 #define MASK_I_TMDSCLK_CHG 0x01 238 239 #define CBIT_INT 0x8505 240 #define MASK_I_AF_LOCK 0x80 241 #define MASK_I_AF_UNLOCK 0x40 242 #define MASK_I_CBIT_FS 0x02 243 244 #define AUDIO_INT 0x8506 245 246 #define ERR_INT 0x8507 247 #define MASK_I_EESS_ERR 0x80 248 249 #define HDCP_INT 0x8508 250 #define MASK_I_AVM_SET 0x80 251 #define MASK_I_AVM_CLR 0x40 252 #define MASK_I_LINKERR 0x20 253 #define MASK_I_SHA_END 0x10 254 #define MASK_I_R0_END 0x08 255 #define MASK_I_KM_END 0x04 256 #define MASK_I_AKSV_END 0x02 257 #define MASK_I_AN_END 0x01 258 259 #define MISC_INT 0x850B 260 #define MASK_I_AS_LAYOUT 0x10 261 #define MASK_I_NO_SPD 0x08 262 #define MASK_I_NO_VS 0x03 263 #define MASK_I_SYNC_CHG 0x02 264 #define MASK_I_AUDIO_MUTE 0x01 265 266 #define KEY_INT 0x850F 267 268 #define SYS_INTM 0x8512 269 #define MASK_M_ACR_CTS 0x80 270 #define MASK_M_ACR_N 0x40 271 #define MASK_M_DVI_DET 0x20 272 #define MASK_M_HDMI_DET 0x10 273 #define MASK_M_NOPMBDET 0x08 274 #define MASK_M_BPMBDET 0x04 275 #define MASK_M_TMDS 0x02 276 #define MASK_M_DDC 0x01 277 278 #define CLK_INTM 0x8513 279 #define MASK_M_OUT_H_CHG 0x40 280 #define MASK_M_IN_DE_CHG 0x20 281 #define MASK_M_IN_HV_CHG 0x10 282 #define MASK_M_DC_CHG 0x08 283 #define MASK_M_PXCLK_CHG 0x04 284 #define MASK_M_PHYCLK_CHG 0x02 285 #define MASK_M_TMDS_CHG 0x01 286 287 #define PACKET_INTM 0x8514 288 289 #define CBIT_INTM 0x8515 290 #define MASK_M_AF_LOCK 0x80 291 #define MASK_M_AF_UNLOCK 0x40 292 #define MASK_M_CBIT_FS 0x02 293 294 #define AUDIO_INTM 0x8516 295 #define MASK_M_BUFINIT_END 0x01 296 297 #define ERR_INTM 0x8517 298 #define MASK_M_EESS_ERR 0x80 299 300 #define HDCP_INTM 0x8518 301 #define MASK_M_AVM_SET 0x80 302 #define MASK_M_AVM_CLR 0x40 303 #define MASK_M_LINKERR 0x20 304 #define MASK_M_SHA_END 0x10 305 #define MASK_M_R0_END 0x08 306 #define MASK_M_KM_END 0x04 307 #define MASK_M_AKSV_END 0x02 308 #define MASK_M_AN_END 0x01 309 310 #define MISC_INTM 0x851B 311 #define MASK_M_AS_LAYOUT 0x10 312 #define MASK_M_NO_SPD 0x08 313 #define MASK_M_NO_VS 0x03 314 #define MASK_M_SYNC_CHG 0x02 315 #define MASK_M_AUDIO_MUTE 0x01 316 317 #define KEY_INTM 0x851F 318 319 #define SYS_STATUS 0x8520 320 #define MASK_S_SYNC 0x80 321 #define MASK_S_AVMUTE 0x40 322 #define MASK_S_HDCP 0x20 323 #define MASK_S_HDMI 0x10 324 #define MASK_S_PHY_SCDT 0x08 325 #define MASK_S_PHY_PLL 0x04 326 #define MASK_S_TMDS 0x02 327 #define MASK_S_DDC5V 0x01 328 329 #define CSI_STATUS 0x0410 330 #define MASK_S_WSYNC 0x0400 331 #define MASK_S_TXACT 0x0200 332 #define MASK_S_RXACT 0x0100 333 #define MASK_S_HLT 0x0001 334 335 #define VI_STATUS1 0x8522 336 #define MASK_S_V_GBD 0x08 337 #define MASK_S_DEEPCOLOR 0x0c 338 #define MASK_S_V_422 0x02 339 #define MASK_S_V_INTERLACE 0x01 340 341 #define AU_STATUS0 0x8523 342 #define MASK_S_A_SAMPLE 0x01 343 344 #define VI_STATUS3 0x8528 345 #define MASK_S_V_COLOR 0x1e 346 #define MASK_LIMITED 0x01 347 348 #define PHY_CTL0 0x8531 349 #define MASK_PHY_SYSCLK_IND 0x02 350 #define MASK_PHY_CTL 0x01 351 352 353 #define PHY_CTL1 0x8532 /* Not in REF_01 */ 354 #define MASK_PHY_AUTO_RST1 0xf0 355 #define MASK_PHY_AUTO_RST1_OFF 0x00 356 #define SET_PHY_AUTO_RST1_US(us) ((((us) / 200) << 4) & \ 357 MASK_PHY_AUTO_RST1) 358 #define MASK_FREQ_RANGE_MODE 0x0f 359 #define SET_FREQ_RANGE_MODE_CYCLES(cycles) (((cycles) - 1) & \ 360 MASK_FREQ_RANGE_MODE) 361 362 #define PHY_CTL2 0x8533 /* Not in REF_01 */ 363 #define MASK_PHY_AUTO_RST4 0x04 364 #define MASK_PHY_AUTO_RST3 0x02 365 #define MASK_PHY_AUTO_RST2 0x01 366 #define MASK_PHY_AUTO_RSTn (MASK_PHY_AUTO_RST4 | \ 367 MASK_PHY_AUTO_RST3 | \ 368 MASK_PHY_AUTO_RST2) 369 370 #define PHY_EN 0x8534 371 #define MASK_ENABLE_PHY 0x01 372 373 #define PHY_RST 0x8535 374 #define MASK_RESET_CTRL 0x01 /* Reset active low */ 375 376 #define PHY_BIAS 0x8536 /* Not in REF_01 */ 377 378 #define PHY_CSQ 0x853F /* Not in REF_01 */ 379 #define MASK_CSQ_CNT 0x0f 380 #define SET_CSQ_CNT_LEVEL(n) (n & MASK_CSQ_CNT) 381 382 #define SYS_FREQ0 0x8540 383 #define SYS_FREQ1 0x8541 384 385 #define SYS_CLK 0x8542 /* Not in REF_01 */ 386 #define MASK_CLK_DIFF 0x0C 387 #define MASK_CLK_DIV 0x03 388 389 #define DDC_CTL 0x8543 390 #define MASK_DDC_ACK_POL 0x08 391 #define MASK_DDC_ACTION 0x04 392 #define MASK_DDC5V_MODE 0x03 393 #define MASK_DDC5V_MODE_0MS 0x00 394 #define MASK_DDC5V_MODE_50MS 0x01 395 #define MASK_DDC5V_MODE_100MS 0x02 396 #define MASK_DDC5V_MODE_200MS 0x03 397 398 #define HPD_CTL 0x8544 399 #define MASK_HPD_CTL0 0x10 400 #define MASK_HPD_OUT0 0x01 401 402 #define ANA_CTL 0x8545 403 #define MASK_APPL_PCSX 0x30 404 #define MASK_APPL_PCSX_HIZ 0x00 405 #define MASK_APPL_PCSX_L_FIX 0x10 406 #define MASK_APPL_PCSX_H_FIX 0x20 407 #define MASK_APPL_PCSX_NORMAL 0x30 408 #define MASK_ANALOG_ON 0x01 409 410 #define AVM_CTL 0x8546 411 412 #define INIT_END 0x854A 413 #define MASK_INIT_END 0x01 414 415 #define HDMI_DET 0x8552 /* Not in REF_01 */ 416 #define MASK_HDMI_DET_MOD1 0x80 417 #define MASK_HDMI_DET_MOD0 0x40 418 #define MASK_HDMI_DET_V 0x30 419 #define MASK_HDMI_DET_V_SYNC 0x00 420 #define MASK_HDMI_DET_V_ASYNC_25MS 0x10 421 #define MASK_HDMI_DET_V_ASYNC_50MS 0x20 422 #define MASK_HDMI_DET_V_ASYNC_100MS 0x30 423 #define MASK_HDMI_DET_NUM 0x0f 424 425 #define HDCP_MODE 0x8560 426 #define MASK_MODE_RST_TN 0x20 427 #define MASK_LINE_REKEY 0x10 428 #define MASK_AUTO_CLR 0x04 429 #define MASK_MANUAL_AUTHENTICATION 0x02 /* Not in REF_01 */ 430 431 #define HDCP_REG1 0x8563 /* Not in REF_01 */ 432 #define MASK_AUTH_UNAUTH_SEL 0x70 433 #define MASK_AUTH_UNAUTH_SEL_12_FRAMES 0x70 434 #define MASK_AUTH_UNAUTH_SEL_8_FRAMES 0x60 435 #define MASK_AUTH_UNAUTH_SEL_4_FRAMES 0x50 436 #define MASK_AUTH_UNAUTH_SEL_2_FRAMES 0x40 437 #define MASK_AUTH_UNAUTH_SEL_64_FRAMES 0x30 438 #define MASK_AUTH_UNAUTH_SEL_32_FRAMES 0x20 439 #define MASK_AUTH_UNAUTH_SEL_16_FRAMES 0x10 440 #define MASK_AUTH_UNAUTH_SEL_ONCE 0x00 441 #define MASK_AUTH_UNAUTH 0x01 442 #define MASK_AUTH_UNAUTH_AUTO 0x01 443 444 #define HDCP_REG2 0x8564 /* Not in REF_01 */ 445 #define MASK_AUTO_P3_RESET 0x0F 446 #define SET_AUTO_P3_RESET_FRAMES(n) (n & MASK_AUTO_P3_RESET) 447 #define MASK_AUTO_P3_RESET_OFF 0x00 448 449 #define VI_MODE 0x8570 450 #define MASK_RGB_DVI 0x08 /* Not in REF_01 */ 451 452 #define VOUT_SET2 0x8573 453 #define MASK_SEL422 0x80 454 #define MASK_VOUT_422FIL_100 0x40 455 #define MASK_VOUTCOLORMODE 0x03 456 #define MASK_VOUTCOLORMODE_THROUGH 0x00 457 #define MASK_VOUTCOLORMODE_AUTO 0x01 458 #define MASK_VOUTCOLORMODE_MANUAL 0x03 459 460 #define VOUT_SET3 0x8574 461 #define MASK_VOUT_EXTCNT 0x08 462 463 #define VI_REP 0x8576 464 #define MASK_VOUT_COLOR_SEL 0xe0 465 #define MASK_VOUT_COLOR_RGB_FULL 0x00 466 #define MASK_VOUT_COLOR_RGB_LIMITED 0x20 467 #define MASK_VOUT_COLOR_601_YCBCR_FULL 0x40 468 #define MASK_VOUT_COLOR_601_YCBCR_LIMITED 0x60 469 #define MASK_VOUT_COLOR_709_YCBCR_FULL 0x80 470 #define MASK_VOUT_COLOR_709_YCBCR_LIMITED 0xa0 471 #define MASK_VOUT_COLOR_FULL_TO_LIMITED 0xc0 472 #define MASK_VOUT_COLOR_LIMITED_TO_FULL 0xe0 473 #define MASK_IN_REP_HEN 0x10 474 #define MASK_IN_REP 0x0f 475 476 #define VI_MUTE 0x857F 477 #define MASK_AUTO_MUTE 0xc0 478 #define MASK_VI_MUTE 0x10 479 480 #define DE_WIDTH_H_LO 0x8582 /* Not in REF_01 */ 481 #define DE_WIDTH_H_HI 0x8583 /* Not in REF_01 */ 482 #define DE_WIDTH_V_LO 0x8588 /* Not in REF_01 */ 483 #define DE_WIDTH_V_HI 0x8589 /* Not in REF_01 */ 484 #define H_SIZE_LO 0x858A /* Not in REF_01 */ 485 #define H_SIZE_HI 0x858B /* Not in REF_01 */ 486 #define V_SIZE_LO 0x858C /* Not in REF_01 */ 487 #define V_SIZE_HI 0x858D /* Not in REF_01 */ 488 #define FV_CNT_LO 0x85A1 /* Not in REF_01 */ 489 #define FV_CNT_HI 0x85A2 /* Not in REF_01 */ 490 491 #define FH_MIN0 0x85AA /* Not in REF_01 */ 492 #define FH_MIN1 0x85AB /* Not in REF_01 */ 493 #define FH_MAX0 0x85AC /* Not in REF_01 */ 494 #define FH_MAX1 0x85AD /* Not in REF_01 */ 495 496 #define HV_RST 0x85AF /* Not in REF_01 */ 497 #define MASK_H_PI_RST 0x20 498 #define MASK_V_PI_RST 0x10 499 500 #define EDID_MODE 0x85C7 501 #define MASK_EDID_SPEED 0x40 502 #define MASK_EDID_MODE 0x03 503 #define MASK_EDID_MODE_DISABLE 0x00 504 #define MASK_EDID_MODE_DDC2B 0x01 505 #define MASK_EDID_MODE_E_DDC 0x02 506 507 #define EDID_LEN1 0x85CA 508 #define EDID_LEN2 0x85CB 509 510 #define HDCP_REG3 0x85D1 /* Not in REF_01 */ 511 #define KEY_RD_CMD 0x01 512 513 #define FORCE_MUTE 0x8600 514 #define MASK_FORCE_AMUTE 0x10 515 #define MASK_FORCE_DMUTE 0x01 516 517 #define CMD_AUD 0x8601 518 #define MASK_CMD_BUFINIT 0x04 519 #define MASK_CMD_LOCKDET 0x02 520 #define MASK_CMD_MUTE 0x01 521 522 #define AUTO_CMD0 0x8602 523 #define MASK_AUTO_MUTE7 0x80 524 #define MASK_AUTO_MUTE6 0x40 525 #define MASK_AUTO_MUTE5 0x20 526 #define MASK_AUTO_MUTE4 0x10 527 #define MASK_AUTO_MUTE3 0x08 528 #define MASK_AUTO_MUTE2 0x04 529 #define MASK_AUTO_MUTE1 0x02 530 #define MASK_AUTO_MUTE0 0x01 531 532 #define AUTO_CMD1 0x8603 533 #define MASK_AUTO_MUTE10 0x04 534 #define MASK_AUTO_MUTE9 0x02 535 #define MASK_AUTO_MUTE8 0x01 536 537 #define AUTO_CMD2 0x8604 538 #define MASK_AUTO_PLAY3 0x08 539 #define MASK_AUTO_PLAY2 0x04 540 541 #define BUFINIT_START 0x8606 542 #define SET_BUFINIT_START_MS(milliseconds) ((milliseconds) / 100) 543 544 #define FS_MUTE 0x8607 545 #define MASK_FS_ELSE_MUTE 0x80 546 #define MASK_FS22_MUTE 0x40 547 #define MASK_FS24_MUTE 0x20 548 #define MASK_FS88_MUTE 0x10 549 #define MASK_FS96_MUTE 0x08 550 #define MASK_FS176_MUTE 0x04 551 #define MASK_FS192_MUTE 0x02 552 #define MASK_FS_NO_MUTE 0x01 553 554 #define FS_IMODE 0x8620 555 #define MASK_NLPCM_HMODE 0x40 556 #define MASK_NLPCM_SMODE 0x20 557 #define MASK_NLPCM_IMODE 0x10 558 #define MASK_FS_HMODE 0x08 559 #define MASK_FS_AMODE 0x04 560 #define MASK_FS_SMODE 0x02 561 #define MASK_FS_IMODE 0x01 562 563 #define FS_SET 0x8621 564 #define MASK_FS 0x0f 565 566 #define LOCKDET_REF0 0x8630 567 #define LOCKDET_REF1 0x8631 568 #define LOCKDET_REF2 0x8632 569 570 #define ACR_MODE 0x8640 571 #define MASK_ACR_LOAD 0x10 572 #define MASK_N_MODE 0x04 573 #define MASK_CTS_MODE 0x01 574 575 #define ACR_MDF0 0x8641 576 #define MASK_ACR_L2MDF 0x70 577 #define MASK_ACR_L2MDF_0_PPM 0x00 578 #define MASK_ACR_L2MDF_61_PPM 0x10 579 #define MASK_ACR_L2MDF_122_PPM 0x20 580 #define MASK_ACR_L2MDF_244_PPM 0x30 581 #define MASK_ACR_L2MDF_488_PPM 0x40 582 #define MASK_ACR_L2MDF_976_PPM 0x50 583 #define MASK_ACR_L2MDF_1976_PPM 0x60 584 #define MASK_ACR_L2MDF_3906_PPM 0x70 585 #define MASK_ACR_L1MDF 0x07 586 #define MASK_ACR_L1MDF_0_PPM 0x00 587 #define MASK_ACR_L1MDF_61_PPM 0x01 588 #define MASK_ACR_L1MDF_122_PPM 0x02 589 #define MASK_ACR_L1MDF_244_PPM 0x03 590 #define MASK_ACR_L1MDF_488_PPM 0x04 591 #define MASK_ACR_L1MDF_976_PPM 0x05 592 #define MASK_ACR_L1MDF_1976_PPM 0x06 593 #define MASK_ACR_L1MDF_3906_PPM 0x07 594 595 #define ACR_MDF1 0x8642 596 #define MASK_ACR_L3MDF 0x07 597 #define MASK_ACR_L3MDF_0_PPM 0x00 598 #define MASK_ACR_L3MDF_61_PPM 0x01 599 #define MASK_ACR_L3MDF_122_PPM 0x02 600 #define MASK_ACR_L3MDF_244_PPM 0x03 601 #define MASK_ACR_L3MDF_488_PPM 0x04 602 #define MASK_ACR_L3MDF_976_PPM 0x05 603 #define MASK_ACR_L3MDF_1976_PPM 0x06 604 #define MASK_ACR_L3MDF_3906_PPM 0x07 605 606 #define SDO_MODE1 0x8652 607 #define MASK_SDO_BIT_LENG 0x70 608 #define MASK_SDO_FMT 0x03 609 #define MASK_SDO_FMT_RIGHT 0x00 610 #define MASK_SDO_FMT_LEFT 0x01 611 #define MASK_SDO_FMT_I2S 0x02 612 613 #define DIV_MODE 0x8665 /* Not in REF_01 */ 614 #define MASK_DIV_DLY 0xf0 615 #define SET_DIV_DLY_MS(milliseconds) ((((milliseconds) / 100) << 4) & \ 616 MASK_DIV_DLY) 617 #define MASK_DIV_MODE 0x01 618 619 #define NCO_F0_MOD 0x8670 620 #define MASK_NCO_F0_MOD 0x03 621 #define MASK_NCO_F0_MOD_42MHZ 0x00 622 #define MASK_NCO_F0_MOD_27MHZ 0x01 623 624 #define PK_INT_MODE 0x8709 625 #define MASK_ISRC2_INT_MODE 0x80 626 #define MASK_ISRC_INT_MODE 0x40 627 #define MASK_ACP_INT_MODE 0x20 628 #define MASK_VS_INT_MODE 0x10 629 #define MASK_SPD_INT_MODE 0x08 630 #define MASK_MS_INT_MODE 0x04 631 #define MASK_AUD_INT_MODE 0x02 632 #define MASK_AVI_INT_MODE 0x01 633 634 #define NO_PKT_LIMIT 0x870B 635 #define MASK_NO_ACP_LIMIT 0xf0 636 #define SET_NO_ACP_LIMIT_MS(milliseconds) ((((milliseconds) / 80) << 4) & \ 637 MASK_NO_ACP_LIMIT) 638 #define MASK_NO_AVI_LIMIT 0x0f 639 #define SET_NO_AVI_LIMIT_MS(milliseconds) (((milliseconds) / 80) & \ 640 MASK_NO_AVI_LIMIT) 641 642 #define NO_PKT_CLR 0x870C 643 #define MASK_NO_VS_CLR 0x40 644 #define MASK_NO_SPD_CLR 0x20 645 #define MASK_NO_ACP_CLR 0x10 646 #define MASK_NO_AVI_CLR1 0x02 647 #define MASK_NO_AVI_CLR0 0x01 648 649 #define ERR_PK_LIMIT 0x870D 650 #define NO_PKT_LIMIT2 0x870E 651 #define PK_AVI_0HEAD 0x8710 652 #define PK_AVI_1HEAD 0x8711 653 #define PK_AVI_2HEAD 0x8712 654 #define PK_AVI_0BYTE 0x8713 655 #define PK_AVI_1BYTE 0x8714 656 #define PK_AVI_2BYTE 0x8715 657 #define PK_AVI_3BYTE 0x8716 658 #define PK_AVI_4BYTE 0x8717 659 #define PK_AVI_5BYTE 0x8718 660 #define PK_AVI_6BYTE 0x8719 661 #define PK_AVI_7BYTE 0x871A 662 #define PK_AVI_8BYTE 0x871B 663 #define PK_AVI_9BYTE 0x871C 664 #define PK_AVI_10BYTE 0x871D 665 #define PK_AVI_11BYTE 0x871E 666 #define PK_AVI_12BYTE 0x871F 667 #define PK_AVI_13BYTE 0x8720 668 #define PK_AVI_14BYTE 0x8721 669 #define PK_AVI_15BYTE 0x8722 670 #define PK_AVI_16BYTE 0x8723 671 672 #define BKSV 0x8800 673 674 #define BCAPS 0x8840 675 #define MASK_HDMI_RSVD 0x80 676 #define MASK_REPEATER 0x40 677 #define MASK_READY 0x20 678 #define MASK_FASTI2C 0x10 679 #define MASK_1_1_FEA 0x02 680 #define MASK_FAST_REAU 0x01 681 682 #define BSTATUS1 0x8842 683 #define MASK_MAX_EXCED 0x08 684 685 #define EDID_RAM 0x8C00 686 #define EDID_EXT_RAM 0x8c80 687 #define NO_GDB_LIMIT 0x9007 688 689 #endif 690