1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2020 Rockchip Electronics Co., Ltd. */
3
4 #include <linux/delay.h>
5 #include <linux/pm_runtime.h>
6 #include <media/v4l2-common.h>
7 #include <media/v4l2-event.h>
8 #include <media/v4l2-fh.h>
9 #include <media/v4l2-ioctl.h>
10 #include <media/v4l2-subdev.h>
11 #include <media/videobuf2-dma-contig.h>
12 #include "dev.h"
13 #include "regs.h"
14
15 #define STREAM_MAX_MP_RSZ_OUTPUT_WIDTH 4416
16 #define STREAM_MAX_MP_RSZ_OUTPUT_HEIGHT 3312
17 #define STREAM_MAX_SP_RSZ_OUTPUT_WIDTH 1920
18 #define STREAM_MAX_SP_RSZ_OUTPUT_HEIGHT 1080
19 #define STREAM_MIN_RSZ_OUTPUT_WIDTH 32
20 #define STREAM_MIN_RSZ_OUTPUT_HEIGHT 16
21 #define STREAM_OUTPUT_STEP_WISE 8
22
23 #define STREAM_MIN_MP_SP_INPUT_WIDTH 32
24 #define STREAM_MIN_MP_SP_INPUT_HEIGHT 32
25
hdr_dma_frame(struct rkisp_device * dev)26 static int hdr_dma_frame(struct rkisp_device *dev)
27 {
28 int max_dma;
29
30 switch (dev->hdr.op_mode) {
31 case HDR_FRAMEX2_DDR:
32 case HDR_LINEX2_DDR:
33 case HDR_RDBK_FRAME1:
34 max_dma = 1;
35 break;
36 case HDR_FRAMEX3_DDR:
37 case HDR_LINEX3_DDR:
38 case HDR_RDBK_FRAME2:
39 max_dma = 2;
40 break;
41 case HDR_RDBK_FRAME3:
42 max_dma = HDR_DMA_MAX;
43 break;
44 case HDR_LINEX2_NO_DDR:
45 case HDR_NORMAL:
46 default:
47 max_dma = 0;
48 }
49 return max_dma;
50 }
51
rkisp_create_hdr_buf(struct rkisp_device * dev)52 static int rkisp_create_hdr_buf(struct rkisp_device *dev)
53 {
54 int i, j, max_dma, max_buf = 1;
55 struct rkisp_dummy_buffer *buf;
56 struct rkisp_stream *stream;
57 u32 size;
58
59 stream = &dev->cap_dev.stream[RKISP_STREAM_DMATX0];
60 size = stream->out_fmt.plane_fmt[0].sizeimage;
61 max_dma = hdr_dma_frame(dev);
62 /* hdr read back mode using base and shd address
63 * this support multi-buffer
64 */
65 if (IS_HDR_RDBK(dev->hdr.op_mode)) {
66 if (!dev->dmarx_dev.trigger)
67 max_buf = HDR_MAX_DUMMY_BUF;
68 else
69 max_buf = 0;
70 }
71 for (i = 0; i < max_dma; i++) {
72 for (j = 0; j < max_buf; j++) {
73 buf = &dev->hdr.dummy_buf[i][j];
74 buf->size = size;
75 if (rkisp_alloc_buffer(dev, buf) < 0) {
76 v4l2_err(&dev->v4l2_dev,
77 "Failed to allocate the memory for hdr buffer\n");
78 return -ENOMEM;
79 }
80 hdr_qbuf(&dev->hdr.q_tx[i], buf);
81 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
82 "hdr buf[%d][%d]:0x%x\n",
83 i, j, (u32)buf->dma_addr);
84 }
85 dev->hdr.index[i] = i;
86 }
87 /*
88 * normal: q_tx[0] to dma0
89 * q_tx[1] to dma1
90 * rdbk1: using dma2
91 q_tx[0] to dma2
92 * rdbk2: using dma0 (as M), dma2 (as S)
93 * q_tx[0] to dma0
94 * q_tx[1] to dma2
95 * rdbk3: using dma0 (as M), dam1 (as L), dma2 (as S)
96 * q_tx[0] to dma0
97 * q_tx[1] to dma1
98 * q_tx[2] to dma2
99 */
100 if (dev->hdr.op_mode == HDR_RDBK_FRAME1) {
101 dev->hdr.index[HDR_DMA2] = 0;
102 dev->hdr.index[HDR_DMA0] = 1;
103 dev->hdr.index[HDR_DMA1] = 2;
104 } else if (dev->hdr.op_mode == HDR_RDBK_FRAME2) {
105 dev->hdr.index[HDR_DMA0] = 0;
106 dev->hdr.index[HDR_DMA2] = 1;
107 dev->hdr.index[HDR_DMA1] = 2;
108 }
109
110 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
111 "hdr:%d buf index dma0:%d dma1:%d dma2:%d\n",
112 max_dma,
113 dev->hdr.index[HDR_DMA0],
114 dev->hdr.index[HDR_DMA1],
115 dev->hdr.index[HDR_DMA2]);
116 return 0;
117 }
118
hdr_destroy_buf(struct rkisp_device * dev)119 void hdr_destroy_buf(struct rkisp_device *dev)
120 {
121 int i, j;
122 struct rkisp_dummy_buffer *buf;
123
124 if (atomic_read(&dev->cap_dev.refcnt) > 1 ||
125 !dev->active_sensor ||
126 (dev->active_sensor &&
127 dev->active_sensor->mbus.type != V4L2_MBUS_CSI2_DPHY) ||
128 (dev->isp_inp & INP_CIF) ||
129 (dev->isp_ver != ISP_V20 && dev->isp_ver != ISP_V21))
130 return;
131
132 atomic_set(&dev->hdr.refcnt, 0);
133 for (i = 0; i < HDR_DMA_MAX; i++) {
134 buf = dev->hdr.rx_cur_buf[i];
135 if (buf) {
136 rkisp_free_buffer(dev, buf);
137 dev->hdr.rx_cur_buf[i] = NULL;
138 }
139
140 for (j = 0; j < HDR_MAX_DUMMY_BUF; j++) {
141 buf = hdr_dqbuf(&dev->hdr.q_tx[i]);
142 if (buf)
143 rkisp_free_buffer(dev, buf);
144 buf = hdr_dqbuf(&dev->hdr.q_rx[i]);
145 if (buf)
146 rkisp_free_buffer(dev, buf);
147 }
148 }
149 }
150
hdr_update_dmatx_buf(struct rkisp_device * dev)151 int hdr_update_dmatx_buf(struct rkisp_device *dev)
152 {
153 void __iomem *base = dev->base_addr;
154 struct rkisp_stream *dmatx;
155 struct rkisp_dummy_buffer *buf;
156 u8 i, index;
157
158 if (!dev->active_sensor ||
159 (dev->active_sensor &&
160 dev->active_sensor->mbus.type != V4L2_MBUS_CSI2_DPHY) ||
161 (dev->isp_inp & INP_CIF) ||
162 (dev->isp_ver != ISP_V20 && dev->isp_ver != ISP_V21))
163 return 0;
164
165 for (i = RKISP_STREAM_DMATX0; i <= RKISP_STREAM_DMATX2; i++) {
166 dmatx = &dev->cap_dev.stream[i];
167 if (dmatx->ops && dmatx->ops->frame_end)
168 dmatx->ops->frame_end(dmatx);
169 }
170
171 if (dev->dmarx_dev.trigger)
172 goto end;
173
174 /* for rawrd auto trigger mode, config first buf */
175 index = dev->hdr.index[HDR_DMA0];
176 buf = hdr_dqbuf(&dev->hdr.q_rx[index]);
177 if (buf) {
178 mi_raw0_rd_set_addr(base, buf->dma_addr);
179 dev->hdr.rx_cur_buf[index] = buf;
180 } else {
181 mi_raw0_rd_set_addr(base,
182 readl(base + MI_RAW0_WR_BASE_SHD));
183 }
184
185 index = dev->hdr.index[HDR_DMA1];
186 buf = hdr_dqbuf(&dev->hdr.q_rx[index]);
187 if (buf) {
188 mi_raw1_rd_set_addr(base, buf->dma_addr);
189 dev->hdr.rx_cur_buf[index] = buf;
190 } else {
191 mi_raw1_rd_set_addr(base,
192 readl(base + MI_RAW1_WR_BASE_SHD));
193 }
194
195 index = dev->hdr.index[HDR_DMA2];
196 buf = hdr_dqbuf(&dev->hdr.q_rx[index]);
197 if (buf) {
198 mi_raw2_rd_set_addr(base, buf->dma_addr);
199 dev->hdr.rx_cur_buf[index] = buf;
200 } else {
201 mi_raw2_rd_set_addr(base,
202 readl(base + MI_RAW2_WR_BASE_SHD));
203 }
204
205 end:
206 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
207 "CSI2RX CTRL0:0x%x CTRL1:0x%x\n"
208 "WR CTRL RAW0:0x%x RAW1:0x%x RAW2:0x%x\n"
209 "RD CTRL:0x%x\n",
210 readl(base + CSI2RX_CTRL0),
211 readl(base + CSI2RX_CTRL1),
212 readl(base + CSI2RX_RAW0_WR_CTRL),
213 readl(base + CSI2RX_RAW1_WR_CTRL),
214 readl(base + CSI2RX_RAW2_WR_CTRL),
215 readl(base + CSI2RX_RAW_RD_CTRL));
216 return 0;
217 }
218
hdr_config_dmatx(struct rkisp_device * dev)219 int hdr_config_dmatx(struct rkisp_device *dev)
220 {
221 struct rkisp_stream *stream;
222 struct v4l2_pix_format_mplane pixm;
223 u32 memory = 0;
224
225 if (atomic_inc_return(&dev->hdr.refcnt) > 1 ||
226 !dev->active_sensor ||
227 (dev->active_sensor &&
228 dev->active_sensor->mbus.type != V4L2_MBUS_CSI2_DPHY) ||
229 (dev->isp_inp & INP_CIF) ||
230 (dev->isp_ver != ISP_V20 && dev->isp_ver != ISP_V21))
231 return 0;
232
233 rkisp_create_hdr_buf(dev);
234 memset(&pixm, 0, sizeof(pixm));
235 if (dev->hdr.op_mode == HDR_FRAMEX2_DDR ||
236 dev->hdr.op_mode == HDR_LINEX2_DDR ||
237 dev->hdr.op_mode == HDR_FRAMEX3_DDR ||
238 dev->hdr.op_mode == HDR_LINEX3_DDR ||
239 dev->hdr.op_mode == HDR_RDBK_FRAME2 ||
240 dev->hdr.op_mode == HDR_RDBK_FRAME3) {
241 stream = &dev->cap_dev.stream[RKISP_STREAM_DMATX0];
242 if (stream->ops && stream->ops->config_mi)
243 stream->ops->config_mi(stream);
244
245 if (!dev->dmarx_dev.trigger) {
246 pixm = stream->out_fmt;
247 stream = &dev->dmarx_dev.stream[RKISP_STREAM_RAWRD0];
248 rkisp_dmarx_set_fmt(stream, pixm);
249 mi_raw_length(stream);
250 }
251 }
252 if (dev->hdr.op_mode == HDR_FRAMEX3_DDR ||
253 dev->hdr.op_mode == HDR_LINEX3_DDR ||
254 dev->hdr.op_mode == HDR_RDBK_FRAME3) {
255 stream = &dev->cap_dev.stream[RKISP_STREAM_DMATX1];
256 if (stream->ops && stream->ops->config_mi)
257 stream->ops->config_mi(stream);
258
259 if (!dev->dmarx_dev.trigger) {
260 pixm = stream->out_fmt;
261 stream = &dev->dmarx_dev.stream[RKISP_STREAM_RAWRD1];
262 rkisp_dmarx_set_fmt(stream, pixm);
263 mi_raw_length(stream);
264 }
265 }
266 if (dev->hdr.op_mode == HDR_RDBK_FRAME1 ||
267 dev->hdr.op_mode == HDR_RDBK_FRAME2 ||
268 dev->hdr.op_mode == HDR_RDBK_FRAME3) {
269 stream = &dev->cap_dev.stream[RKISP_STREAM_DMATX2];
270 if (stream->ops && stream->ops->config_mi)
271 stream->ops->config_mi(stream);
272
273 if (!dev->dmarx_dev.trigger) {
274 memory = stream->memory;
275 pixm = stream->out_fmt;
276 stream = &dev->dmarx_dev.stream[RKISP_STREAM_RAWRD2];
277 rkisp_dmarx_set_fmt(stream, pixm);
278 stream->ops->config_mi(stream);
279 }
280 }
281
282 if (dev->hdr.op_mode != HDR_NORMAL && !dev->dmarx_dev.trigger) {
283 raw_rd_ctrl(dev->base_addr, memory << 2);
284 if (pixm.width && pixm.height)
285 rkisp_rawrd_set_pic_size(dev, pixm.width, pixm.height);
286 }
287 return 0;
288 }
289
hdr_stop_dmatx(struct rkisp_device * dev)290 void hdr_stop_dmatx(struct rkisp_device *dev)
291 {
292 struct rkisp_stream *stream;
293
294 if (atomic_dec_return(&dev->hdr.refcnt) ||
295 !dev->active_sensor ||
296 (dev->active_sensor &&
297 dev->active_sensor->mbus.type != V4L2_MBUS_CSI2_DPHY) ||
298 (dev->isp_inp & INP_CIF) ||
299 (dev->isp_ver != ISP_V20 && dev->isp_ver != ISP_V21))
300 return;
301
302 if (dev->hdr.op_mode == HDR_FRAMEX2_DDR ||
303 dev->hdr.op_mode == HDR_LINEX2_DDR ||
304 dev->hdr.op_mode == HDR_FRAMEX3_DDR ||
305 dev->hdr.op_mode == HDR_LINEX3_DDR ||
306 dev->hdr.op_mode == HDR_RDBK_FRAME2 ||
307 dev->hdr.op_mode == HDR_RDBK_FRAME3) {
308 stream = &dev->cap_dev.stream[RKISP_STREAM_DMATX0];
309 stream->ops->stop_mi(stream);
310 }
311 if (dev->hdr.op_mode == HDR_FRAMEX3_DDR ||
312 dev->hdr.op_mode == HDR_LINEX3_DDR ||
313 dev->hdr.op_mode == HDR_RDBK_FRAME3) {
314 stream = &dev->cap_dev.stream[RKISP_STREAM_DMATX1];
315 stream->ops->stop_mi(stream);
316 }
317 if (dev->hdr.op_mode == HDR_RDBK_FRAME1 ||
318 dev->hdr.op_mode == HDR_RDBK_FRAME2 ||
319 dev->hdr.op_mode == HDR_RDBK_FRAME3) {
320 stream = &dev->cap_dev.stream[RKISP_STREAM_DMATX2];
321 stream->ops->stop_mi(stream);
322 }
323 }
324
hdr_dqbuf(struct list_head * q)325 struct rkisp_dummy_buffer *hdr_dqbuf(struct list_head *q)
326 {
327 struct rkisp_dummy_buffer *buf = NULL;
328
329 if (!list_empty(q)) {
330 buf = list_first_entry(q,
331 struct rkisp_dummy_buffer, queue);
332 list_del(&buf->queue);
333 }
334 return buf;
335 }
336
hdr_qbuf(struct list_head * q,struct rkisp_dummy_buffer * buf)337 void hdr_qbuf(struct list_head *q,
338 struct rkisp_dummy_buffer *buf)
339 {
340 if (buf)
341 list_add_tail(&buf->queue, q);
342 }
343
rkisp_config_dmatx_valid_buf(struct rkisp_device * dev)344 void rkisp_config_dmatx_valid_buf(struct rkisp_device *dev)
345 {
346 struct rkisp_hw_dev *hw = dev->hw_dev;
347 struct rkisp_stream *stream;
348 struct rkisp_device *isp;
349 u32 i, j;
350
351 if (!hw->dummy_buf.mem_priv ||
352 !dev->active_sensor ||
353 (dev->active_sensor &&
354 dev->active_sensor->mbus.type != V4L2_MBUS_CSI2_DPHY) ||
355 (dev->isp_inp & INP_CIF) ||
356 (dev->isp_ver != ISP_V20 && dev->isp_ver != ISP_V21))
357 return;
358 /* dmatx buf update by mi force or oneself frame end,
359 * for async dmatx enable need to update to valid buf first.
360 */
361 for (i = 0; i < hw->dev_num; i++) {
362 isp = hw->isp[i];
363 if (!(isp->isp_inp & INP_CSI))
364 continue;
365 for (j = RKISP_STREAM_DMATX0; j < RKISP_MAX_STREAM; j++) {
366 stream = &isp->cap_dev.stream[j];
367 if (!stream->linked || stream->u.dmatx.is_config)
368 continue;
369 mi_set_y_addr(stream, hw->dummy_buf.dma_addr);
370 }
371 }
372 }
373
374 /* Get xsubs and ysubs for fourcc formats
375 *
376 * @xsubs: horizontal color samples in a 4*4 matrix, for yuv
377 * @ysubs: vertical color samples in a 4*4 matrix, for yuv
378 */
rkisp_fcc_xysubs(u32 fcc,u32 * xsubs,u32 * ysubs)379 int rkisp_fcc_xysubs(u32 fcc, u32 *xsubs, u32 *ysubs)
380 {
381 switch (fcc) {
382 case V4L2_PIX_FMT_GREY:
383 case V4L2_PIX_FMT_YUV444M:
384 *xsubs = 1;
385 *ysubs = 1;
386 break;
387 case V4L2_PIX_FMT_YUYV:
388 case V4L2_PIX_FMT_YVYU:
389 case V4L2_PIX_FMT_VYUY:
390 case V4L2_PIX_FMT_UYVY:
391 case V4L2_PIX_FMT_YUV422P:
392 case V4L2_PIX_FMT_NV16:
393 case V4L2_PIX_FMT_NV61:
394 case V4L2_PIX_FMT_YVU422M:
395 case V4L2_PIX_FMT_FBC2:
396 *xsubs = 2;
397 *ysubs = 1;
398 break;
399 case V4L2_PIX_FMT_NV21:
400 case V4L2_PIX_FMT_NV12:
401 case V4L2_PIX_FMT_NV21M:
402 case V4L2_PIX_FMT_NV12M:
403 case V4L2_PIX_FMT_YUV420:
404 case V4L2_PIX_FMT_YVU420:
405 case V4L2_PIX_FMT_FBCG:
406 case V4L2_PIX_FMT_FBC0:
407 *xsubs = 2;
408 *ysubs = 2;
409 break;
410 default:
411 return -EINVAL;
412 }
413
414 return 0;
415 }
416
rkisp_mbus_code_xysubs(u32 code,u32 * xsubs,u32 * ysubs)417 int rkisp_mbus_code_xysubs(u32 code, u32 *xsubs, u32 *ysubs)
418 {
419 switch (code) {
420 case MEDIA_BUS_FMT_YUYV8_2X8:
421 case MEDIA_BUS_FMT_YUYV8_1X16:
422 case MEDIA_BUS_FMT_YVYU8_1X16:
423 case MEDIA_BUS_FMT_UYVY8_1X16:
424 case MEDIA_BUS_FMT_VYUY8_1X16:
425 *xsubs = 2;
426 *ysubs = 1;
427 break;
428 default:
429 return -EINVAL;
430 }
431
432 return 0;
433 }
434
435 static const struct capture_fmt mp_fmts[] = {
436 /* yuv422 */
437 {
438 .fourcc = V4L2_PIX_FMT_UYVY,
439 .fmt_type = FMT_YUV,
440 .bpp = { 16 },
441 .cplanes = 1,
442 .mplanes = 1,
443 .uv_swap = 0,
444 .write_format = MI_CTRL_MP_WRITE_YUVINT,
445 }, {
446 .fourcc = V4L2_PIX_FMT_YUV422P,
447 .fmt_type = FMT_YUV,
448 .bpp = { 8, 4, 4 },
449 .cplanes = 3,
450 .mplanes = 1,
451 .uv_swap = 0,
452 .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
453 }, {
454 .fourcc = V4L2_PIX_FMT_NV16,
455 .fmt_type = FMT_YUV,
456 .bpp = { 8, 16 },
457 .cplanes = 2,
458 .mplanes = 1,
459 .uv_swap = 0,
460 .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
461 }, {
462 .fourcc = V4L2_PIX_FMT_NV61,
463 .fmt_type = FMT_YUV,
464 .bpp = { 8, 16 },
465 .cplanes = 2,
466 .mplanes = 1,
467 .uv_swap = 1,
468 .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
469 }, {
470 .fourcc = V4L2_PIX_FMT_YUV422M,
471 .fmt_type = FMT_YUV,
472 .bpp = { 8, 8, 8 },
473 .cplanes = 3,
474 .mplanes = 3,
475 .uv_swap = 0,
476 .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
477 },
478 /* yuv420 */
479 {
480 .fourcc = V4L2_PIX_FMT_NV21,
481 .fmt_type = FMT_YUV,
482 .bpp = { 8, 16 },
483 .cplanes = 2,
484 .mplanes = 1,
485 .uv_swap = 1,
486 .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
487 }, {
488 .fourcc = V4L2_PIX_FMT_NV12,
489 .fmt_type = FMT_YUV,
490 .bpp = { 8, 16 },
491 .cplanes = 2,
492 .mplanes = 1,
493 .uv_swap = 0,
494 .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
495 }, {
496 .fourcc = V4L2_PIX_FMT_NV21M,
497 .fmt_type = FMT_YUV,
498 .bpp = { 8, 16 },
499 .cplanes = 2,
500 .mplanes = 2,
501 .uv_swap = 1,
502 .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
503 }, {
504 .fourcc = V4L2_PIX_FMT_NV12M,
505 .fmt_type = FMT_YUV,
506 .bpp = { 8, 16 },
507 .cplanes = 2,
508 .mplanes = 2,
509 .uv_swap = 0,
510 .write_format = MI_CTRL_MP_WRITE_YUV_SPLA,
511 }, {
512 .fourcc = V4L2_PIX_FMT_YUV420,
513 .fmt_type = FMT_YUV,
514 .bpp = { 8, 8, 8 },
515 .cplanes = 3,
516 .mplanes = 1,
517 .uv_swap = 0,
518 .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
519 },
520 /* yuv444 */
521 {
522 .fourcc = V4L2_PIX_FMT_YUV444M,
523 .fmt_type = FMT_YUV,
524 .bpp = { 8, 8, 8 },
525 .cplanes = 3,
526 .mplanes = 3,
527 .uv_swap = 0,
528 .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
529 },
530 /* raw */
531 {
532 .fourcc = V4L2_PIX_FMT_SRGGB8,
533 .fmt_type = FMT_BAYER,
534 .bpp = { 8 },
535 .mplanes = 1,
536 .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
537 }, {
538 .fourcc = V4L2_PIX_FMT_SGRBG8,
539 .fmt_type = FMT_BAYER,
540 .bpp = { 8 },
541 .mplanes = 1,
542 .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
543 }, {
544 .fourcc = V4L2_PIX_FMT_SGBRG8,
545 .fmt_type = FMT_BAYER,
546 .bpp = { 8 },
547 .mplanes = 1,
548 .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
549 }, {
550 .fourcc = V4L2_PIX_FMT_SBGGR8,
551 .fmt_type = FMT_BAYER,
552 .bpp = { 8 },
553 .mplanes = 1,
554 .write_format = MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
555 }, {
556 .fourcc = V4L2_PIX_FMT_SRGGB10,
557 .fmt_type = FMT_BAYER,
558 .bpp = { 10 },
559 .mplanes = 1,
560 .write_format = MI_CTRL_MP_WRITE_RAW12,
561 }, {
562 .fourcc = V4L2_PIX_FMT_SGRBG10,
563 .fmt_type = FMT_BAYER,
564 .bpp = { 10 },
565 .mplanes = 1,
566 .write_format = MI_CTRL_MP_WRITE_RAW12,
567 }, {
568 .fourcc = V4L2_PIX_FMT_SGBRG10,
569 .fmt_type = FMT_BAYER,
570 .bpp = { 10 },
571 .mplanes = 1,
572 .write_format = MI_CTRL_MP_WRITE_RAW12,
573 }, {
574 .fourcc = V4L2_PIX_FMT_SBGGR10,
575 .fmt_type = FMT_BAYER,
576 .bpp = { 10 },
577 .mplanes = 1,
578 .write_format = MI_CTRL_MP_WRITE_RAW12,
579 }, {
580 .fourcc = V4L2_PIX_FMT_SRGGB12,
581 .fmt_type = FMT_BAYER,
582 .bpp = { 12 },
583 .mplanes = 1,
584 .write_format = MI_CTRL_MP_WRITE_RAW12,
585 }, {
586 .fourcc = V4L2_PIX_FMT_SGRBG12,
587 .fmt_type = FMT_BAYER,
588 .bpp = { 12 },
589 .mplanes = 1,
590 .write_format = MI_CTRL_MP_WRITE_RAW12,
591 }, {
592 .fourcc = V4L2_PIX_FMT_SGBRG12,
593 .fmt_type = FMT_BAYER,
594 .bpp = { 12 },
595 .mplanes = 1,
596 .write_format = MI_CTRL_MP_WRITE_RAW12,
597 }, {
598 .fourcc = V4L2_PIX_FMT_SBGGR12,
599 .fmt_type = FMT_BAYER,
600 .bpp = { 12 },
601 .mplanes = 1,
602 .write_format = MI_CTRL_MP_WRITE_RAW12,
603 },
604 };
605
606 static const struct capture_fmt sp_fmts[] = {
607 /* yuv422 */
608 {
609 .fourcc = V4L2_PIX_FMT_UYVY,
610 .fmt_type = FMT_YUV,
611 .bpp = { 16 },
612 .cplanes = 1,
613 .mplanes = 1,
614 .uv_swap = 0,
615 .write_format = MI_CTRL_SP_WRITE_INT,
616 .output_format = MI_CTRL_SP_OUTPUT_YUV422,
617 }, {
618 .fourcc = V4L2_PIX_FMT_YUV422P,
619 .fmt_type = FMT_YUV,
620 .bpp = { 8, 8, 8 },
621 .cplanes = 3,
622 .mplanes = 1,
623 .uv_swap = 0,
624 .write_format = MI_CTRL_SP_WRITE_PLA,
625 .output_format = MI_CTRL_SP_OUTPUT_YUV422,
626 }, {
627 .fourcc = V4L2_PIX_FMT_NV16,
628 .fmt_type = FMT_YUV,
629 .bpp = { 8, 16 },
630 .cplanes = 2,
631 .mplanes = 1,
632 .uv_swap = 0,
633 .write_format = MI_CTRL_SP_WRITE_SPLA,
634 .output_format = MI_CTRL_SP_OUTPUT_YUV422,
635 }, {
636 .fourcc = V4L2_PIX_FMT_NV61,
637 .fmt_type = FMT_YUV,
638 .bpp = { 8, 16 },
639 .cplanes = 2,
640 .mplanes = 1,
641 .uv_swap = 1,
642 .write_format = MI_CTRL_SP_WRITE_SPLA,
643 .output_format = MI_CTRL_SP_OUTPUT_YUV422,
644 }, {
645 .fourcc = V4L2_PIX_FMT_YUV422M,
646 .fmt_type = FMT_YUV,
647 .bpp = { 8, 8, 8 },
648 .cplanes = 3,
649 .mplanes = 3,
650 .uv_swap = 0,
651 .write_format = MI_CTRL_SP_WRITE_PLA,
652 .output_format = MI_CTRL_SP_OUTPUT_YUV422,
653 },
654 /* yuv420 */
655 {
656 .fourcc = V4L2_PIX_FMT_NV21,
657 .fmt_type = FMT_YUV,
658 .bpp = { 8, 16 },
659 .cplanes = 2,
660 .mplanes = 1,
661 .uv_swap = 1,
662 .write_format = MI_CTRL_SP_WRITE_SPLA,
663 .output_format = MI_CTRL_SP_OUTPUT_YUV420,
664 }, {
665 .fourcc = V4L2_PIX_FMT_NV12,
666 .fmt_type = FMT_YUV,
667 .bpp = { 8, 16 },
668 .cplanes = 2,
669 .mplanes = 1,
670 .uv_swap = 0,
671 .write_format = MI_CTRL_SP_WRITE_SPLA,
672 .output_format = MI_CTRL_SP_OUTPUT_YUV420,
673 }, {
674 .fourcc = V4L2_PIX_FMT_NV21M,
675 .fmt_type = FMT_YUV,
676 .bpp = { 8, 16 },
677 .cplanes = 2,
678 .mplanes = 2,
679 .uv_swap = 1,
680 .write_format = MI_CTRL_SP_WRITE_SPLA,
681 .output_format = MI_CTRL_SP_OUTPUT_YUV420,
682 }, {
683 .fourcc = V4L2_PIX_FMT_NV12M,
684 .fmt_type = FMT_YUV,
685 .bpp = { 8, 16 },
686 .cplanes = 2,
687 .mplanes = 2,
688 .uv_swap = 0,
689 .write_format = MI_CTRL_SP_WRITE_SPLA,
690 .output_format = MI_CTRL_SP_OUTPUT_YUV420,
691 }, {
692 .fourcc = V4L2_PIX_FMT_YUV420,
693 .fmt_type = FMT_YUV,
694 .bpp = { 8, 8, 8 },
695 .cplanes = 3,
696 .mplanes = 1,
697 .uv_swap = 0,
698 .write_format = MI_CTRL_SP_WRITE_PLA,
699 .output_format = MI_CTRL_SP_OUTPUT_YUV420,
700 },
701 /* yuv444 */
702 {
703 .fourcc = V4L2_PIX_FMT_YUV444M,
704 .fmt_type = FMT_YUV,
705 .bpp = { 8, 8, 8 },
706 .cplanes = 3,
707 .mplanes = 3,
708 .uv_swap = 0,
709 .write_format = MI_CTRL_SP_WRITE_PLA,
710 .output_format = MI_CTRL_SP_OUTPUT_YUV444,
711 },
712 /* yuv400 */
713 {
714 .fourcc = V4L2_PIX_FMT_GREY,
715 .fmt_type = FMT_YUV,
716 .bpp = { 8 },
717 .cplanes = 1,
718 .mplanes = 1,
719 .uv_swap = 0,
720 .write_format = MI_CTRL_SP_WRITE_PLA,
721 .output_format = MI_CTRL_SP_OUTPUT_YUV400,
722 },
723 /* rgb */
724 {
725 .fourcc = V4L2_PIX_FMT_XBGR32,
726 .fmt_type = FMT_RGB,
727 .bpp = { 32 },
728 .mplanes = 1,
729 .write_format = MI_CTRL_SP_WRITE_PLA,
730 .output_format = MI_CTRL_SP_OUTPUT_RGB888,
731 }, {
732 .fourcc = V4L2_PIX_FMT_RGB565,
733 .fmt_type = FMT_RGB,
734 .bpp = { 16 },
735 .mplanes = 1,
736 .write_format = MI_CTRL_SP_WRITE_PLA,
737 .output_format = MI_CTRL_SP_OUTPUT_RGB565,
738 },
739 /* fbcg */
740 {
741 .fourcc = V4L2_PIX_FMT_FBCG,
742 .fmt_type = FMT_FBCGAIN,
743 .bpp = { 8, 16 },
744 .cplanes = 2,
745 .mplanes = 2,
746 .uv_swap = 0,
747 .write_format = MI_CTRL_SP_WRITE_SPLA,
748 .output_format = MI_CTRL_SP_OUTPUT_YUV420,
749 }
750 };
751
752 struct stream_config rkisp_mp_stream_config = {
753 .fmts = mp_fmts,
754 .fmt_size = ARRAY_SIZE(mp_fmts),
755 /* constraints */
756 .max_rsz_width = STREAM_MAX_MP_RSZ_OUTPUT_WIDTH,
757 .max_rsz_height = STREAM_MAX_MP_RSZ_OUTPUT_HEIGHT,
758 .min_rsz_width = STREAM_MIN_RSZ_OUTPUT_WIDTH,
759 .min_rsz_height = STREAM_MIN_RSZ_OUTPUT_HEIGHT,
760 .frame_end_id = CIF_MI_MP_FRAME,
761 /* registers */
762 .rsz = {
763 .ctrl = CIF_MRSZ_CTRL,
764 .scale_hy = CIF_MRSZ_SCALE_HY,
765 .scale_hcr = CIF_MRSZ_SCALE_HCR,
766 .scale_hcb = CIF_MRSZ_SCALE_HCB,
767 .scale_vy = CIF_MRSZ_SCALE_VY,
768 .scale_vc = CIF_MRSZ_SCALE_VC,
769 .scale_lut = CIF_MRSZ_SCALE_LUT,
770 .scale_lut_addr = CIF_MRSZ_SCALE_LUT_ADDR,
771 .scale_hy_shd = CIF_MRSZ_SCALE_HY_SHD,
772 .scale_hcr_shd = CIF_MRSZ_SCALE_HCR_SHD,
773 .scale_hcb_shd = CIF_MRSZ_SCALE_HCB_SHD,
774 .scale_vy_shd = CIF_MRSZ_SCALE_VY_SHD,
775 .scale_vc_shd = CIF_MRSZ_SCALE_VC_SHD,
776 .phase_hy = CIF_MRSZ_PHASE_HY,
777 .phase_hc = CIF_MRSZ_PHASE_HC,
778 .phase_vy = CIF_MRSZ_PHASE_VY,
779 .phase_vc = CIF_MRSZ_PHASE_VC,
780 .ctrl_shd = CIF_MRSZ_CTRL_SHD,
781 .phase_hy_shd = CIF_MRSZ_PHASE_HY_SHD,
782 .phase_hc_shd = CIF_MRSZ_PHASE_HC_SHD,
783 .phase_vy_shd = CIF_MRSZ_PHASE_VY_SHD,
784 .phase_vc_shd = CIF_MRSZ_PHASE_VC_SHD,
785 },
786 .dual_crop = {
787 .ctrl = CIF_DUAL_CROP_CTRL,
788 .yuvmode_mask = CIF_DUAL_CROP_MP_MODE_YUV,
789 .rawmode_mask = CIF_DUAL_CROP_MP_MODE_RAW,
790 .h_offset = CIF_DUAL_CROP_M_H_OFFS,
791 .v_offset = CIF_DUAL_CROP_M_V_OFFS,
792 .h_size = CIF_DUAL_CROP_M_H_SIZE,
793 .v_size = CIF_DUAL_CROP_M_V_SIZE,
794 },
795 .mi = {
796 .y_size_init = CIF_MI_MP_Y_SIZE_INIT,
797 .cb_size_init = CIF_MI_MP_CB_SIZE_INIT,
798 .cr_size_init = CIF_MI_MP_CR_SIZE_INIT,
799 .y_base_ad_init = CIF_MI_MP_Y_BASE_AD_INIT,
800 .cb_base_ad_init = CIF_MI_MP_CB_BASE_AD_INIT,
801 .cr_base_ad_init = CIF_MI_MP_CR_BASE_AD_INIT,
802 .y_offs_cnt_init = CIF_MI_MP_Y_OFFS_CNT_INIT,
803 .cb_offs_cnt_init = CIF_MI_MP_CB_OFFS_CNT_INIT,
804 .cr_offs_cnt_init = CIF_MI_MP_CR_OFFS_CNT_INIT,
805 .y_base_ad_shd = CIF_MI_MP_Y_BASE_AD_SHD,
806 },
807 };
808
809 struct stream_config rkisp_sp_stream_config = {
810 .fmts = sp_fmts,
811 .fmt_size = ARRAY_SIZE(sp_fmts),
812 /* constraints */
813 .max_rsz_width = STREAM_MAX_SP_RSZ_OUTPUT_WIDTH,
814 .max_rsz_height = STREAM_MAX_SP_RSZ_OUTPUT_HEIGHT,
815 .min_rsz_width = STREAM_MIN_RSZ_OUTPUT_WIDTH,
816 .min_rsz_height = STREAM_MIN_RSZ_OUTPUT_HEIGHT,
817 .frame_end_id = CIF_MI_SP_FRAME,
818 /* registers */
819 .rsz = {
820 .ctrl = CIF_SRSZ_CTRL,
821 .scale_hy = CIF_SRSZ_SCALE_HY,
822 .scale_hcr = CIF_SRSZ_SCALE_HCR,
823 .scale_hcb = CIF_SRSZ_SCALE_HCB,
824 .scale_vy = CIF_SRSZ_SCALE_VY,
825 .scale_vc = CIF_SRSZ_SCALE_VC,
826 .scale_lut = CIF_SRSZ_SCALE_LUT,
827 .scale_lut_addr = CIF_SRSZ_SCALE_LUT_ADDR,
828 .scale_hy_shd = CIF_SRSZ_SCALE_HY_SHD,
829 .scale_hcr_shd = CIF_SRSZ_SCALE_HCR_SHD,
830 .scale_hcb_shd = CIF_SRSZ_SCALE_HCB_SHD,
831 .scale_vy_shd = CIF_SRSZ_SCALE_VY_SHD,
832 .scale_vc_shd = CIF_SRSZ_SCALE_VC_SHD,
833 .phase_hy = CIF_SRSZ_PHASE_HY,
834 .phase_hc = CIF_SRSZ_PHASE_HC,
835 .phase_vy = CIF_SRSZ_PHASE_VY,
836 .phase_vc = CIF_SRSZ_PHASE_VC,
837 .ctrl_shd = CIF_SRSZ_CTRL_SHD,
838 .phase_hy_shd = CIF_SRSZ_PHASE_HY_SHD,
839 .phase_hc_shd = CIF_SRSZ_PHASE_HC_SHD,
840 .phase_vy_shd = CIF_SRSZ_PHASE_VY_SHD,
841 .phase_vc_shd = CIF_SRSZ_PHASE_VC_SHD,
842 },
843 .dual_crop = {
844 .ctrl = CIF_DUAL_CROP_CTRL,
845 .yuvmode_mask = CIF_DUAL_CROP_SP_MODE_YUV,
846 .rawmode_mask = CIF_DUAL_CROP_SP_MODE_RAW,
847 .h_offset = CIF_DUAL_CROP_S_H_OFFS,
848 .v_offset = CIF_DUAL_CROP_S_V_OFFS,
849 .h_size = CIF_DUAL_CROP_S_H_SIZE,
850 .v_size = CIF_DUAL_CROP_S_V_SIZE,
851 },
852 .mi = {
853 .y_size_init = CIF_MI_SP_Y_SIZE_INIT,
854 .cb_size_init = CIF_MI_SP_CB_SIZE_INIT,
855 .cr_size_init = CIF_MI_SP_CR_SIZE_INIT,
856 .y_base_ad_init = CIF_MI_SP_Y_BASE_AD_INIT,
857 .cb_base_ad_init = CIF_MI_SP_CB_BASE_AD_INIT,
858 .cr_base_ad_init = CIF_MI_SP_CR_BASE_AD_INIT,
859 .y_offs_cnt_init = CIF_MI_SP_Y_OFFS_CNT_INIT,
860 .cb_offs_cnt_init = CIF_MI_SP_CB_OFFS_CNT_INIT,
861 .cr_offs_cnt_init = CIF_MI_SP_CR_OFFS_CNT_INIT,
862 .y_base_ad_shd = CIF_MI_SP_Y_BASE_AD_SHD,
863 },
864 };
865
866 static const
find_fmt(struct rkisp_stream * stream,const u32 pixelfmt)867 struct capture_fmt *find_fmt(struct rkisp_stream *stream, const u32 pixelfmt)
868 {
869 const struct capture_fmt *fmt;
870 int i;
871
872 for (i = 0; i < stream->config->fmt_size; i++) {
873 fmt = &stream->config->fmts[i];
874 if (fmt->fourcc == pixelfmt)
875 return fmt;
876 }
877 return NULL;
878 }
879
880 /*
881 * Make sure max resize/output resolution is smaller than
882 * isp sub device output size. This assumes it's not
883 * recommended to use ISP scale-up function to get output size
884 * that exceeds sensor max resolution.
885 */
restrict_rsz_resolution(struct rkisp_device * dev,const struct stream_config * config,struct v4l2_rect * max_rsz)886 static void restrict_rsz_resolution(struct rkisp_device *dev,
887 const struct stream_config *config,
888 struct v4l2_rect *max_rsz)
889 {
890 struct v4l2_rect *input_win;
891
892 input_win = rkisp_get_isp_sd_win(&dev->isp_sdev);
893 max_rsz->width = min_t(int, input_win->width, config->max_rsz_width);
894 max_rsz->height = min_t(int, input_win->height, config->max_rsz_height);
895 }
896
rkisp_set_fmt(struct rkisp_stream * stream,struct v4l2_pix_format_mplane * pixm,bool try)897 static int rkisp_set_fmt(struct rkisp_stream *stream,
898 struct v4l2_pix_format_mplane *pixm,
899 bool try)
900 {
901 const struct capture_fmt *fmt;
902 const struct stream_config *config = stream->config;
903 struct rkisp_device *dev = stream->ispdev;
904 u32 planes, imagsize = 0;
905 u32 i = 0, xsubs = 1, ysubs = 1;
906
907 if (stream->id == RKISP_STREAM_VIR) {
908 for (i = RKISP_STREAM_MP; i < RKISP_STREAM_VIR; i++) {
909 struct rkisp_stream *t = &dev->cap_dev.stream[i];
910
911 if (t->out_isp_fmt.fmt_type != FMT_YUV || !t->streaming)
912 continue;
913 if (t->out_fmt.plane_fmt[0].sizeimage > imagsize) {
914 imagsize = t->out_fmt.plane_fmt[0].sizeimage;
915 *pixm = t->out_fmt;
916 stream->conn_id = t->id;
917 }
918 }
919 if (!imagsize) {
920 v4l2_err(&dev->v4l2_dev, "no output stream for iqtool\n");
921 return -EINVAL;
922 }
923 imagsize = 0;
924 }
925
926 fmt = find_fmt(stream, pixm->pixelformat);
927 if (!fmt) {
928 v4l2_err(&dev->v4l2_dev,
929 "nonsupport pixelformat:%c%c%c%c\n",
930 pixm->pixelformat,
931 pixm->pixelformat >> 8,
932 pixm->pixelformat >> 16,
933 pixm->pixelformat >> 24);
934 return -EINVAL;
935 }
936
937 if (stream->id == RKISP_STREAM_MP || stream->id == RKISP_STREAM_SP) {
938 struct v4l2_rect max_rsz;
939
940 /* do checks on resolution */
941 restrict_rsz_resolution(stream->ispdev, config, &max_rsz);
942 pixm->width = clamp_t(u32, pixm->width,
943 config->min_rsz_width, max_rsz.width);
944 pixm->height = clamp_t(u32, pixm->height,
945 config->min_rsz_height, max_rsz.height);
946 } else if (dev->isp_ver == ISP_V30) {
947 if (stream->id == RKISP_STREAM_BP &&
948 pixm->width != dev->isp_sdev.out_crop.width &&
949 pixm->height != dev->isp_sdev.out_crop.height) {
950 v4l2_warn(&dev->v4l2_dev,
951 "fullpath %dx%d no equal to isp output %dx%d\n",
952 pixm->width, pixm->height,
953 dev->isp_sdev.out_crop.width,
954 dev->isp_sdev.out_crop.height);
955 pixm->width = dev->isp_sdev.out_crop.width;
956 pixm->height = dev->isp_sdev.out_crop.height;
957 } else if (stream->id == RKISP_STREAM_FBC &&
958 pixm->width != stream->dcrop.width &&
959 pixm->height != stream->dcrop.height) {
960 v4l2_warn(&dev->v4l2_dev,
961 "fbcpatch no scale %dx%d should equal to crop %dx%d\n",
962 pixm->width, pixm->height,
963 stream->dcrop.width, stream->dcrop.height);
964 pixm->width = stream->dcrop.width;
965 pixm->height = stream->dcrop.height;
966 }
967 }
968
969 pixm->num_planes = fmt->mplanes;
970 pixm->field = V4L2_FIELD_NONE;
971 /* get quantization from ispsd */
972 pixm->quantization = stream->ispdev->isp_sdev.quantization;
973
974 /* calculate size */
975 rkisp_fcc_xysubs(fmt->fourcc, &xsubs, &ysubs);
976 planes = fmt->cplanes ? fmt->cplanes : fmt->mplanes;
977 for (i = 0; i < planes; i++) {
978 struct v4l2_plane_pix_format *plane_fmt;
979 unsigned int width, height, bytesperline, w, h;
980
981 plane_fmt = pixm->plane_fmt + i;
982
983 w = (fmt->fmt_type == FMT_FBC) ?
984 ALIGN(pixm->width, 16) : pixm->width;
985 h = (fmt->fmt_type == FMT_FBC) ?
986 ALIGN(pixm->height, 16) : pixm->height;
987 width = i ? w / xsubs : w;
988 height = i ? h / ysubs : h;
989
990 if (dev->isp_ver == ISP_V20 &&
991 fmt->fmt_type == FMT_BAYER &&
992 stream->id == RKISP_STREAM_DMATX2)
993 height += RKMODULE_EXTEND_LINE;
994
995 if ((dev->isp_ver == ISP_V20 ||
996 dev->isp_ver == ISP_V21) &&
997 !stream->memory &&
998 fmt->fmt_type == FMT_BAYER &&
999 stream->id != RKISP_STREAM_MP &&
1000 stream->id != RKISP_STREAM_SP)
1001 /* compact mode need bytesperline 4byte align */
1002 bytesperline = ALIGN(width * fmt->bpp[i] / 8, 256);
1003 else
1004 bytesperline = width * DIV_ROUND_UP(fmt->bpp[i], 8);
1005
1006 /* 128bit AXI, 16byte align for bytesperline */
1007 if ((dev->isp_ver == ISP_V20 && stream->id == RKISP_STREAM_SP) ||
1008 dev->isp_ver == ISP_V30)
1009 bytesperline = ALIGN(bytesperline, 16);
1010
1011 if (i != 0 || plane_fmt->bytesperline < bytesperline)
1012 plane_fmt->bytesperline = bytesperline;
1013
1014 plane_fmt->sizeimage = plane_fmt->bytesperline * height;
1015
1016 /* FMT_FBCGAIN: uv address is y size offset need 64 align
1017 * FMT_FBC: width and height need 16 align
1018 * header: width * height / 16, and 4096 align for mpp
1019 * payload: yuv420 or yuv422 size
1020 */
1021 if (fmt->fmt_type == FMT_FBCGAIN && i == 0)
1022 plane_fmt->sizeimage = ALIGN(plane_fmt->sizeimage, 64);
1023 else if (fmt->fmt_type == FMT_FBC && i == 0)
1024 plane_fmt->sizeimage = ALIGN(plane_fmt->sizeimage >> 4, RK_MPP_ALIGN);
1025 else if (fmt->fmt_type == FMT_FBC)
1026 plane_fmt->sizeimage += w * h;
1027 imagsize += plane_fmt->sizeimage;
1028 }
1029
1030 /* convert to non-MPLANE format.
1031 * it's important since we want to unify none-MPLANE
1032 * and MPLANE.
1033 */
1034 if (fmt->mplanes == 1 || fmt->fmt_type == FMT_FBCGAIN)
1035 pixm->plane_fmt[0].sizeimage = imagsize;
1036
1037 if (!try && !stream->start_stream && !stream->streaming) {
1038 stream->out_isp_fmt = *fmt;
1039 stream->out_fmt = *pixm;
1040
1041 if (stream->id == RKISP_STREAM_SP) {
1042 stream->u.sp.y_stride =
1043 pixm->plane_fmt[0].bytesperline /
1044 DIV_ROUND_UP(fmt->bpp[0], 8);
1045 } else if (stream->id == RKISP_STREAM_MP) {
1046 stream->u.mp.raw_enable = (fmt->fmt_type == FMT_BAYER);
1047 }
1048
1049 v4l2_dbg(1, rkisp_debug, &stream->ispdev->v4l2_dev,
1050 "%s: stream: %d req(%d, %d) out(%d, %d)\n", __func__,
1051 stream->id, pixm->width, pixm->height,
1052 stream->out_fmt.width, stream->out_fmt.height);
1053 }
1054
1055 return 0;
1056 }
1057
rkisp_fh_open(struct file * filp)1058 int rkisp_fh_open(struct file *filp)
1059 {
1060 struct rkisp_stream *stream = video_drvdata(filp);
1061 int ret;
1062
1063 ret = v4l2_fh_open(filp);
1064 if (!ret) {
1065 ret = v4l2_pipeline_pm_get(&stream->vnode.vdev.entity);
1066 if (ret < 0)
1067 vb2_fop_release(filp);
1068 }
1069
1070 return ret;
1071 }
1072
rkisp_fop_release(struct file * file)1073 int rkisp_fop_release(struct file *file)
1074 {
1075 struct rkisp_stream *stream = video_drvdata(file);
1076 int ret;
1077
1078 ret = vb2_fop_release(file);
1079 if (!ret)
1080 v4l2_pipeline_pm_put(&stream->vnode.vdev.entity);
1081 return ret;
1082 }
1083
rkisp_set_stream_def_fmt(struct rkisp_device * dev,u32 id,u32 width,u32 height,u32 pixelformat)1084 void rkisp_set_stream_def_fmt(struct rkisp_device *dev, u32 id,
1085 u32 width, u32 height, u32 pixelformat)
1086 {
1087 struct rkisp_stream *stream = &dev->cap_dev.stream[id];
1088 struct v4l2_pix_format_mplane pixm;
1089
1090 memset(&pixm, 0, sizeof(pixm));
1091 if (pixelformat)
1092 pixm.pixelformat = pixelformat;
1093 else
1094 pixm.pixelformat = stream->out_isp_fmt.fourcc;
1095 if (!pixm.pixelformat)
1096 return;
1097
1098 stream->dcrop.left = 0;
1099 stream->dcrop.top = 0;
1100 stream->dcrop.width = width;
1101 stream->dcrop.height = height;
1102
1103 pixm.width = width;
1104 pixm.height = height;
1105 rkisp_set_fmt(stream, &pixm, false);
1106 }
1107
1108 /************************* v4l2_file_operations***************************/
1109 static const struct v4l2_file_operations rkisp_fops = {
1110 .open = rkisp_fh_open,
1111 .release = rkisp_fop_release,
1112 .unlocked_ioctl = video_ioctl2,
1113 .poll = vb2_fop_poll,
1114 .mmap = vb2_fop_mmap,
1115 };
1116
1117 /*
1118 * mp and sp v4l2_ioctl_ops
1119 */
1120
rkisp_enum_input(struct file * file,void * priv,struct v4l2_input * input)1121 static int rkisp_enum_input(struct file *file, void *priv,
1122 struct v4l2_input *input)
1123 {
1124 if (input->index > 0)
1125 return -EINVAL;
1126
1127 input->type = V4L2_INPUT_TYPE_CAMERA;
1128 strlcpy(input->name, "Camera", sizeof(input->name));
1129
1130 return 0;
1131 }
1132
rkisp_try_fmt_vid_cap_mplane(struct file * file,void * fh,struct v4l2_format * f)1133 static int rkisp_try_fmt_vid_cap_mplane(struct file *file, void *fh,
1134 struct v4l2_format *f)
1135 {
1136 struct rkisp_stream *stream = video_drvdata(file);
1137
1138 return rkisp_set_fmt(stream, &f->fmt.pix_mp, true);
1139 }
1140
rkisp_enum_framesizes(struct file * file,void * prov,struct v4l2_frmsizeenum * fsize)1141 static int rkisp_enum_framesizes(struct file *file, void *prov,
1142 struct v4l2_frmsizeenum *fsize)
1143 {
1144 struct rkisp_stream *stream = video_drvdata(file);
1145 const struct stream_config *config = stream->config;
1146 struct v4l2_frmsize_stepwise *s = &fsize->stepwise;
1147 struct v4l2_frmsize_discrete *d = &fsize->discrete;
1148 const struct ispsd_out_fmt *input_isp_fmt;
1149 struct v4l2_rect max_rsz;
1150
1151 if (fsize->index != 0)
1152 return -EINVAL;
1153
1154 if (!find_fmt(stream, fsize->pixel_format))
1155 return -EINVAL;
1156
1157 restrict_rsz_resolution(stream->ispdev, config, &max_rsz);
1158
1159 input_isp_fmt = rkisp_get_ispsd_out_fmt(&stream->ispdev->isp_sdev);
1160 if (input_isp_fmt->fmt_type == FMT_BAYER) {
1161 fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
1162 d->width = max_rsz.width;
1163 d->height = max_rsz.height;
1164 } else {
1165 fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE;
1166 s->min_width = STREAM_MIN_RSZ_OUTPUT_WIDTH;
1167 s->min_height = STREAM_MIN_RSZ_OUTPUT_HEIGHT;
1168 s->max_width = max_rsz.width;
1169 s->max_height = max_rsz.height;
1170 s->step_width = STREAM_OUTPUT_STEP_WISE;
1171 s->step_height = STREAM_OUTPUT_STEP_WISE;
1172 }
1173
1174 return 0;
1175 }
1176
rkisp_get_cmsk(struct rkisp_stream * stream,struct rkisp_cmsk_cfg * cfg)1177 static int rkisp_get_cmsk(struct rkisp_stream *stream, struct rkisp_cmsk_cfg *cfg)
1178 {
1179 struct rkisp_device *dev = stream->ispdev;
1180 unsigned long lock_flags = 0;
1181 u32 i, win_en, mode;
1182
1183 if (dev->isp_ver != ISP_V30 || stream->id == RKISP_STREAM_FBC) {
1184 v4l2_err(&dev->v4l2_dev, "%s not support\n", __func__);
1185 return -EINVAL;
1186 }
1187
1188 spin_lock_irqsave(&dev->cmsk_lock, lock_flags);
1189 *cfg = dev->cmsk_cfg;
1190 spin_unlock_irqrestore(&dev->cmsk_lock, lock_flags);
1191
1192 switch (stream->id) {
1193 case RKISP_STREAM_MP:
1194 win_en = cfg->win[0].win_en;
1195 mode = cfg->win[0].mode;
1196 break;
1197 case RKISP_STREAM_SP:
1198 win_en = cfg->win[1].win_en;
1199 mode = cfg->win[1].mode;
1200 break;
1201 case RKISP_STREAM_BP:
1202 default:
1203 win_en = cfg->win[2].win_en;
1204 mode = cfg->win[2].mode;
1205 break;
1206 }
1207
1208 cfg->width_ro = dev->isp_sdev.out_crop.width;
1209 cfg->height_ro = dev->isp_sdev.out_crop.height;
1210 for (i = 0; i < RKISP_CMSK_WIN_MAX; i++) {
1211 cfg->win[i].win_en = !!(win_en & BIT(i));
1212 cfg->win[i].mode = !!(mode & BIT(i));
1213 }
1214
1215 return 0;
1216 }
1217
rkisp_set_cmsk(struct rkisp_stream * stream,struct rkisp_cmsk_cfg * cfg)1218 static int rkisp_set_cmsk(struct rkisp_stream *stream, struct rkisp_cmsk_cfg *cfg)
1219 {
1220 struct rkisp_device *dev = stream->ispdev;
1221 unsigned long lock_flags = 0;
1222 u8 i, win_en = 0, mode = 0;
1223 u16 h_offs, v_offs, h_size, v_size;
1224 u32 width = dev->isp_sdev.out_crop.width;
1225 u32 height = dev->isp_sdev.out_crop.height;
1226 bool warn = false;
1227
1228 if (dev->isp_ver != ISP_V30 || stream->id == RKISP_STREAM_FBC) {
1229 v4l2_err(&dev->v4l2_dev, "%s not support\n", __func__);
1230 return -EINVAL;
1231 }
1232
1233 spin_lock_irqsave(&dev->cmsk_lock, lock_flags);
1234 dev->is_cmsk_upd = true;
1235 for (i = 0; i < RKISP_CMSK_WIN_MAX; i++) {
1236 win_en |= cfg->win[i].win_en ? BIT(i) : 0;
1237 mode |= cfg->win[i].mode ? BIT(i) : 0;
1238
1239 if (cfg->win[i].win_en) {
1240 if (cfg->win[i].mode) {
1241 dev->cmsk_cfg.win[i].cover_color_y = cfg->win[i].cover_color_y;
1242 dev->cmsk_cfg.win[i].cover_color_u = cfg->win[i].cover_color_u;
1243 dev->cmsk_cfg.win[i].cover_color_v = cfg->win[i].cover_color_v;
1244 }
1245 h_offs = cfg->win[i].h_offs & ~0x1;
1246 v_offs = cfg->win[i].v_offs & ~0x1;
1247 h_size = cfg->win[i].h_size & ~0x7;
1248 v_size = cfg->win[i].v_size & ~0x7;
1249 if (h_offs != cfg->win[i].h_offs ||
1250 v_offs != cfg->win[i].v_offs ||
1251 h_size != cfg->win[i].h_size ||
1252 v_size != cfg->win[i].v_size)
1253 warn = true;
1254 if (h_offs + h_size > width) {
1255 h_size = (width - h_offs) & ~0x7;
1256 warn = true;
1257 }
1258 if (v_offs + v_size > height) {
1259 v_size = (height - v_offs) & ~0x7;
1260 warn = true;
1261 }
1262 if (warn) {
1263 warn = false;
1264 v4l2_warn(&dev->v4l2_dev,
1265 "%s cmsk offs 2 align, size 8 align and offs + size < resolution\n"
1266 "\t cmsk win%d result to offs:%d %d, size:%d %d\n",
1267 stream->vnode.vdev.name, i, h_offs, v_offs, h_size, v_size);
1268 }
1269 dev->cmsk_cfg.win[i].h_offs = h_offs;
1270 dev->cmsk_cfg.win[i].v_offs = v_offs;
1271 dev->cmsk_cfg.win[i].h_size = h_size;
1272 dev->cmsk_cfg.win[i].v_size = v_size;
1273 }
1274 }
1275
1276 switch (stream->id) {
1277 case RKISP_STREAM_MP:
1278 dev->cmsk_cfg.win[0].win_en = win_en;
1279 dev->cmsk_cfg.win[0].mode = mode;
1280 break;
1281 case RKISP_STREAM_SP:
1282 dev->cmsk_cfg.win[1].win_en = win_en;
1283 dev->cmsk_cfg.win[1].mode = mode;
1284 break;
1285 case RKISP_STREAM_BP:
1286 default:
1287 dev->cmsk_cfg.win[2].win_en = win_en;
1288 dev->cmsk_cfg.win[2].mode = mode;
1289 break;
1290 }
1291 spin_unlock_irqrestore(&dev->cmsk_lock, lock_flags);
1292 return 0;
1293
1294 }
1295
rkisp_ioctl_default(struct file * file,void * fh,bool valid_prio,unsigned int cmd,void * arg)1296 static long rkisp_ioctl_default(struct file *file, void *fh,
1297 bool valid_prio, unsigned int cmd, void *arg)
1298 {
1299 struct rkisp_stream *stream = video_drvdata(file);
1300 long ret = 0;
1301
1302 if (!arg)
1303 return -EINVAL;
1304
1305 switch (cmd) {
1306 case RKISP_CMD_GET_CSI_MEMORY_MODE:
1307 if (stream->id != RKISP_STREAM_DMATX0 &&
1308 stream->id != RKISP_STREAM_DMATX1 &&
1309 stream->id != RKISP_STREAM_DMATX2 &&
1310 stream->id != RKISP_STREAM_DMATX3)
1311 ret = -EINVAL;
1312 else if (stream->memory == 0)
1313 *(int *)arg = CSI_MEM_COMPACT;
1314 else if (stream->memory == SW_CSI_RAW_WR_SIMG_MODE)
1315 *(int *)arg = CSI_MEM_WORD_BIG_ALIGN;
1316 else
1317 *(int *)arg = CSI_MEM_WORD_LITTLE_ALIGN;
1318 break;
1319 case RKISP_CMD_SET_CSI_MEMORY_MODE:
1320 if (stream->id != RKISP_STREAM_DMATX0 &&
1321 stream->id != RKISP_STREAM_DMATX1 &&
1322 stream->id != RKISP_STREAM_DMATX2 &&
1323 stream->id != RKISP_STREAM_DMATX3)
1324 ret = -EINVAL;
1325 else if (*(int *)arg == CSI_MEM_COMPACT)
1326 stream->memory = 0;
1327 else if (*(int *)arg == CSI_MEM_WORD_BIG_ALIGN)
1328 stream->memory = SW_CSI_RAW_WR_SIMG_MODE;
1329 else
1330 stream->memory =
1331 SW_CSI_RWA_WR_SIMG_SWP | SW_CSI_RAW_WR_SIMG_MODE;
1332 break;
1333 case RKISP_CMD_GET_CMSK:
1334 ret = rkisp_get_cmsk(stream, arg);
1335 break;
1336 case RKISP_CMD_SET_CMSK:
1337 ret = rkisp_set_cmsk(stream, arg);
1338 break;
1339 default:
1340 ret = -EINVAL;
1341 }
1342
1343 return ret;
1344 }
1345
rkisp_enum_frameintervals(struct file * file,void * fh,struct v4l2_frmivalenum * fival)1346 static int rkisp_enum_frameintervals(struct file *file, void *fh,
1347 struct v4l2_frmivalenum *fival)
1348 {
1349 const struct rkisp_stream *stream = video_drvdata(file);
1350 struct rkisp_device *dev = stream->ispdev;
1351 struct rkisp_sensor_info *sensor = dev->active_sensor;
1352 struct v4l2_subdev_frame_interval fi;
1353 int ret;
1354
1355 if (fival->index != 0)
1356 return -EINVAL;
1357
1358 if (!sensor) {
1359 /* TODO: active_sensor is NULL if using DMARX path */
1360 v4l2_err(&dev->v4l2_dev, "%s Not active sensor\n", __func__);
1361 return -ENODEV;
1362 }
1363
1364 ret = v4l2_subdev_call(sensor->sd, video, g_frame_interval, &fi);
1365 if (ret && ret != -ENOIOCTLCMD) {
1366 return ret;
1367 } else if (ret == -ENOIOCTLCMD) {
1368 /* Set a default value for sensors not implements ioctl */
1369 fi.interval.numerator = 1;
1370 fi.interval.denominator = 30;
1371 }
1372
1373 fival->type = V4L2_FRMIVAL_TYPE_CONTINUOUS;
1374 fival->stepwise.step.numerator = 1;
1375 fival->stepwise.step.denominator = 1;
1376 fival->stepwise.max.numerator = 1;
1377 fival->stepwise.max.denominator = 1;
1378 fival->stepwise.min.numerator = fi.interval.numerator;
1379 fival->stepwise.min.denominator = fi.interval.denominator;
1380
1381 return 0;
1382 }
1383
rkisp_enum_fmt_vid_cap_mplane(struct file * file,void * priv,struct v4l2_fmtdesc * f)1384 static int rkisp_enum_fmt_vid_cap_mplane(struct file *file, void *priv,
1385 struct v4l2_fmtdesc *f)
1386 {
1387 struct rkisp_stream *stream = video_drvdata(file);
1388 const struct capture_fmt *fmt = NULL;
1389
1390 if (f->index >= stream->config->fmt_size)
1391 return -EINVAL;
1392
1393 fmt = &stream->config->fmts[f->index];
1394 f->pixelformat = fmt->fourcc;
1395 switch (f->pixelformat) {
1396 case V4L2_PIX_FMT_FBC2:
1397 strscpy(f->description,
1398 "Rockchip yuv422sp fbc encoder",
1399 sizeof(f->description));
1400 break;
1401 case V4L2_PIX_FMT_FBC0:
1402 strscpy(f->description,
1403 "Rockchip yuv420sp fbc encoder",
1404 sizeof(f->description));
1405 break;
1406 case V4L2_PIX_FMT_FBCG:
1407 strscpy(f->description,
1408 "Rockchip fbc gain",
1409 sizeof(f->description));
1410 break;
1411 case V4l2_PIX_FMT_EBD8:
1412 strscpy(f->description,
1413 "Embedded data 8-bit",
1414 sizeof(f->description));
1415 break;
1416 case V4l2_PIX_FMT_SPD16:
1417 strscpy(f->description,
1418 "Shield pix data 16-bit",
1419 sizeof(f->description));
1420 break;
1421 default:
1422 break;
1423 }
1424
1425 return 0;
1426 }
1427
rkisp_s_fmt_vid_cap_mplane(struct file * file,void * priv,struct v4l2_format * f)1428 static int rkisp_s_fmt_vid_cap_mplane(struct file *file,
1429 void *priv, struct v4l2_format *f)
1430 {
1431 struct rkisp_stream *stream = video_drvdata(file);
1432 struct video_device *vdev = &stream->vnode.vdev;
1433 struct rkisp_vdev_node *node = vdev_to_node(vdev);
1434 struct rkisp_device *dev = stream->ispdev;
1435
1436 if (vb2_is_streaming(&node->buf_queue)) {
1437 v4l2_err(&dev->v4l2_dev, "%s queue busy\n", __func__);
1438 return -EBUSY;
1439 }
1440
1441 return rkisp_set_fmt(stream, &f->fmt.pix_mp, false);
1442 }
1443
rkisp_g_fmt_vid_cap_mplane(struct file * file,void * fh,struct v4l2_format * f)1444 static int rkisp_g_fmt_vid_cap_mplane(struct file *file, void *fh,
1445 struct v4l2_format *f)
1446 {
1447 struct rkisp_stream *stream = video_drvdata(file);
1448
1449 f->fmt.pix_mp = stream->out_fmt;
1450
1451 return 0;
1452 }
1453
rkisp_g_selection(struct file * file,void * prv,struct v4l2_selection * sel)1454 static int rkisp_g_selection(struct file *file, void *prv,
1455 struct v4l2_selection *sel)
1456 {
1457 struct rkisp_stream *stream = video_drvdata(file);
1458 struct rkisp_device *dev = stream->ispdev;
1459 struct v4l2_rect *dcrop = &stream->dcrop;
1460 struct v4l2_rect *input_win;
1461
1462 input_win = rkisp_get_isp_sd_win(&dev->isp_sdev);
1463
1464 switch (sel->target) {
1465 case V4L2_SEL_TGT_CROP_BOUNDS:
1466 sel->r.width = input_win->width;
1467 sel->r.height = input_win->height;
1468 sel->r.left = 0;
1469 sel->r.top = 0;
1470 break;
1471 case V4L2_SEL_TGT_CROP:
1472 sel->r = *dcrop;
1473 break;
1474 default:
1475 return -EINVAL;
1476 }
1477
1478 return 0;
1479 }
1480
rkisp_update_crop(struct rkisp_stream * stream,struct v4l2_rect * sel,const struct v4l2_rect * in)1481 static struct v4l2_rect *rkisp_update_crop(struct rkisp_stream *stream,
1482 struct v4l2_rect *sel,
1483 const struct v4l2_rect *in)
1484 {
1485 struct rkisp_device *dev = stream->ispdev;
1486 bool is_unite = dev->hw_dev->is_unite;
1487 u32 align = is_unite ? 4 : 2;
1488
1489 /* Not crop for MP bayer raw data and dmatx path */
1490 if ((stream->id == RKISP_STREAM_MP &&
1491 stream->out_isp_fmt.fmt_type == FMT_BAYER) ||
1492 stream->id == RKISP_STREAM_DMATX0 ||
1493 stream->id == RKISP_STREAM_DMATX1 ||
1494 stream->id == RKISP_STREAM_DMATX2 ||
1495 stream->id == RKISP_STREAM_DMATX3) {
1496 sel->left = 0;
1497 sel->top = 0;
1498 sel->width = in->width;
1499 sel->height = in->height;
1500 return sel;
1501 }
1502
1503 sel->left = ALIGN(sel->left, 2);
1504 sel->width = ALIGN(sel->width, align);
1505 sel->left = clamp_t(u32, sel->left, 0,
1506 in->width - STREAM_MIN_MP_SP_INPUT_WIDTH);
1507 sel->top = clamp_t(u32, sel->top, 0,
1508 in->height - STREAM_MIN_MP_SP_INPUT_HEIGHT);
1509 sel->width = clamp_t(u32, sel->width, STREAM_MIN_MP_SP_INPUT_WIDTH,
1510 in->width - sel->left);
1511 sel->height = clamp_t(u32, sel->height, STREAM_MIN_MP_SP_INPUT_HEIGHT,
1512 in->height - sel->top);
1513 if (is_unite && (sel->width + 2 * sel->left) != in->width) {
1514 sel->left = ALIGN_DOWN((in->width - sel->width) / 2, 2);
1515 v4l2_warn(&dev->v4l2_dev,
1516 "try horizontal center crop(%d,%d)/%dx%d for dual isp\n",
1517 sel->left, sel->top, sel->width, sel->height);
1518 }
1519 return sel;
1520 }
1521
rkisp_s_selection(struct file * file,void * prv,struct v4l2_selection * sel)1522 static int rkisp_s_selection(struct file *file, void *prv,
1523 struct v4l2_selection *sel)
1524 {
1525 struct rkisp_stream *stream = video_drvdata(file);
1526 struct video_device *vdev = &stream->vnode.vdev;
1527 struct rkisp_vdev_node *node = vdev_to_node(vdev);
1528 struct rkisp_device *dev = stream->ispdev;
1529 struct v4l2_rect *dcrop = &stream->dcrop;
1530 const struct v4l2_rect *input_win;
1531
1532 if (vb2_is_busy(&node->buf_queue)) {
1533 v4l2_err(&dev->v4l2_dev, "%s queue busy\n", __func__);
1534 return -EBUSY;
1535 }
1536
1537 input_win = rkisp_get_isp_sd_win(&dev->isp_sdev);
1538
1539 if (sel->target != V4L2_SEL_TGT_CROP)
1540 return -EINVAL;
1541
1542 if (sel->flags != 0)
1543 return -EINVAL;
1544
1545 *dcrop = *rkisp_update_crop(stream, &sel->r, input_win);
1546 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
1547 "stream %d crop(%d,%d)/%dx%d\n", stream->id,
1548 dcrop->left, dcrop->top, dcrop->width, dcrop->height);
1549
1550 return 0;
1551 }
1552
rkisp_querycap(struct file * file,void * priv,struct v4l2_capability * cap)1553 static int rkisp_querycap(struct file *file, void *priv,
1554 struct v4l2_capability *cap)
1555 {
1556 struct rkisp_stream *stream = video_drvdata(file);
1557 struct device *dev = stream->ispdev->dev;
1558 struct video_device *vdev = video_devdata(file);
1559
1560 strlcpy(cap->card, vdev->name, sizeof(cap->card));
1561 snprintf(cap->driver, sizeof(cap->driver),
1562 "%s_v%d", dev->driver->name,
1563 stream->ispdev->isp_ver >> 4);
1564 snprintf(cap->bus_info, sizeof(cap->bus_info),
1565 "platform:%s", dev_name(dev));
1566
1567 return 0;
1568 }
1569
1570 static const struct v4l2_ioctl_ops rkisp_v4l2_ioctl_ops = {
1571 .vidioc_reqbufs = vb2_ioctl_reqbufs,
1572 .vidioc_querybuf = vb2_ioctl_querybuf,
1573 .vidioc_create_bufs = vb2_ioctl_create_bufs,
1574 .vidioc_qbuf = vb2_ioctl_qbuf,
1575 .vidioc_expbuf = vb2_ioctl_expbuf,
1576 .vidioc_dqbuf = vb2_ioctl_dqbuf,
1577 .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
1578 .vidioc_streamon = vb2_ioctl_streamon,
1579 .vidioc_streamoff = vb2_ioctl_streamoff,
1580 .vidioc_enum_input = rkisp_enum_input,
1581 .vidioc_try_fmt_vid_cap_mplane = rkisp_try_fmt_vid_cap_mplane,
1582 .vidioc_enum_fmt_vid_cap = rkisp_enum_fmt_vid_cap_mplane,
1583 .vidioc_s_fmt_vid_cap_mplane = rkisp_s_fmt_vid_cap_mplane,
1584 .vidioc_g_fmt_vid_cap_mplane = rkisp_g_fmt_vid_cap_mplane,
1585 .vidioc_s_selection = rkisp_s_selection,
1586 .vidioc_g_selection = rkisp_g_selection,
1587 .vidioc_querycap = rkisp_querycap,
1588 .vidioc_enum_frameintervals = rkisp_enum_frameintervals,
1589 .vidioc_enum_framesizes = rkisp_enum_framesizes,
1590 .vidioc_default = rkisp_ioctl_default,
1591 };
1592
rkisp_unregister_stream_vdev(struct rkisp_stream * stream)1593 void rkisp_unregister_stream_vdev(struct rkisp_stream *stream)
1594 {
1595 media_entity_cleanup(&stream->vnode.vdev.entity);
1596 video_unregister_device(&stream->vnode.vdev);
1597 }
1598
rkisp_register_stream_vdev(struct rkisp_stream * stream)1599 int rkisp_register_stream_vdev(struct rkisp_stream *stream)
1600 {
1601 struct rkisp_device *dev = stream->ispdev;
1602 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
1603 struct video_device *vdev = &stream->vnode.vdev;
1604 struct rkisp_vdev_node *node;
1605 struct media_entity *source, *sink;
1606 int ret = 0, pad;
1607
1608 mutex_init(&stream->apilock);
1609 node = vdev_to_node(vdev);
1610
1611 vdev->ioctl_ops = &rkisp_v4l2_ioctl_ops;
1612 vdev->release = video_device_release_empty;
1613 vdev->fops = &rkisp_fops;
1614 vdev->minor = -1;
1615 vdev->v4l2_dev = v4l2_dev;
1616 vdev->lock = &stream->apilock;
1617 vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE_MPLANE |
1618 V4L2_CAP_STREAMING;
1619 video_set_drvdata(vdev, stream);
1620 vdev->vfl_dir = VFL_DIR_RX;
1621 node->pad.flags = MEDIA_PAD_FL_SINK;
1622 vdev->queue = &node->buf_queue;
1623
1624 ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
1625 if (ret < 0) {
1626 v4l2_err(v4l2_dev,
1627 "video_register_device failed with error %d\n", ret);
1628 return ret;
1629 }
1630
1631 ret = media_entity_pads_init(&vdev->entity, 1, &node->pad);
1632 if (ret < 0)
1633 goto unreg;
1634
1635 source = &dev->csi_dev.sd.entity;
1636 switch (stream->id) {
1637 case RKISP_STREAM_DMATX0://CSI_SRC_CH1
1638 case RKISP_STREAM_DMATX1://CSI_SRC_CH2
1639 case RKISP_STREAM_DMATX2://CSI_SRC_CH3
1640 case RKISP_STREAM_DMATX3://CSI_SRC_CH4
1641 pad = stream->id;
1642 dev->csi_dev.sink[pad - 1].linked = true;
1643 dev->csi_dev.sink[pad - 1].index = BIT(pad - 1);
1644 break;
1645 default:
1646 source = &dev->isp_sdev.sd.entity;
1647 pad = RKISP_ISP_PAD_SOURCE_PATH;
1648 }
1649 sink = &vdev->entity;
1650 ret = media_create_pad_link(source, pad,
1651 sink, 0, stream->linked);
1652 if (ret < 0)
1653 goto unreg;
1654 return 0;
1655 unreg:
1656 video_unregister_device(vdev);
1657 return ret;
1658 }
1659
rkisp_register_stream_vdevs(struct rkisp_device * dev)1660 int rkisp_register_stream_vdevs(struct rkisp_device *dev)
1661 {
1662 struct rkisp_capture_device *cap_dev = &dev->cap_dev;
1663 struct stream_config *mp_cfg = &rkisp_mp_stream_config;
1664 int ret = 0;
1665
1666 memset(cap_dev, 0, sizeof(*cap_dev));
1667 cap_dev->ispdev = dev;
1668 atomic_set(&cap_dev->refcnt, 0);
1669
1670 if (dev->isp_ver <= ISP_V13) {
1671 if (dev->isp_ver == ISP_V12) {
1672 mp_cfg->max_rsz_width = CIF_ISP_INPUT_W_MAX_V12;
1673 mp_cfg->max_rsz_height = CIF_ISP_INPUT_H_MAX_V12;
1674 } else if (dev->isp_ver == ISP_V13) {
1675 mp_cfg->max_rsz_width = CIF_ISP_INPUT_W_MAX_V13;
1676 mp_cfg->max_rsz_height = CIF_ISP_INPUT_H_MAX_V13;
1677 }
1678 ret = rkisp_register_stream_v1x(dev);
1679 } else if (dev->isp_ver == ISP_V20) {
1680 ret = rkisp_register_stream_v20(dev);
1681 } else if (dev->isp_ver == ISP_V21) {
1682 mp_cfg->max_rsz_width = CIF_ISP_INPUT_W_MAX_V21;
1683 mp_cfg->max_rsz_height = CIF_ISP_INPUT_H_MAX_V21;
1684 ret = rkisp_register_stream_v21(dev);
1685 } else if (dev->isp_ver == ISP_V30) {
1686 mp_cfg->max_rsz_width = dev->hw_dev->is_unite ?
1687 CIF_ISP_INPUT_W_MAX_V30_UNITE : CIF_ISP_INPUT_W_MAX_V30;
1688 mp_cfg->max_rsz_height = dev->hw_dev->is_unite ?
1689 CIF_ISP_INPUT_H_MAX_V30_UNITE : CIF_ISP_INPUT_H_MAX_V30;
1690 ret = rkisp_register_stream_v30(dev);
1691 }
1692 return ret;
1693 }
1694
rkisp_unregister_stream_vdevs(struct rkisp_device * dev)1695 void rkisp_unregister_stream_vdevs(struct rkisp_device *dev)
1696 {
1697 if (dev->isp_ver <= ISP_V13)
1698 rkisp_unregister_stream_v1x(dev);
1699 else if (dev->isp_ver == ISP_V20)
1700 rkisp_unregister_stream_v20(dev);
1701 else if (dev->isp_ver == ISP_V21)
1702 rkisp_unregister_stream_v21(dev);
1703 else if (dev->isp_ver == ISP_V30)
1704 rkisp_unregister_stream_v30(dev);
1705 }
1706
rkisp_mi_isr(u32 mis_val,struct rkisp_device * dev)1707 void rkisp_mi_isr(u32 mis_val, struct rkisp_device *dev)
1708 {
1709 if (dev->isp_ver <= ISP_V13)
1710 rkisp_mi_v1x_isr(mis_val, dev);
1711 else if (dev->isp_ver == ISP_V20)
1712 rkisp_mi_v20_isr(mis_val, dev);
1713 else if (dev->isp_ver == ISP_V21)
1714 rkisp_mi_v21_isr(mis_val, dev);
1715 else if (dev->isp_ver == ISP_V30)
1716 rkisp_mi_v30_isr(mis_val, dev);
1717 }
1718