1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. */
3
4 #include <linux/delay.h>
5 #include <linux/pm_runtime.h>
6 #include <media/v4l2-common.h>
7 #include <media/v4l2-event.h>
8 #include <media/v4l2-fh.h>
9 #include <media/v4l2-ioctl.h>
10 #include <media/v4l2-subdev.h>
11 #include <media/videobuf2-dma-contig.h>
12 #include <media/videobuf2-dma-sg.h>
13 #include <linux/dma-iommu.h>
14 #include "dev.h"
15 #include "regs.h"
16
17 #define CIF_ISP_REQ_BUFS_MIN 0
18
19 static const struct capture_fmt dmarx_fmts[] = {
20 /* bayer raw */
21 {
22 .fourcc = V4L2_PIX_FMT_SRGGB8,
23 .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8,
24 .fmt_type = FMT_BAYER,
25 .bpp = { 8 },
26 .mplanes = 1,
27 .write_format = CIF_MI_DMA_CTRL_READ_FMT_PACKED,
28 .output_format = CIF_MI_DMA_CTRL_RGB_BAYER_8BIT,
29 }, {
30 .fourcc = V4L2_PIX_FMT_SGRBG8,
31 .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8,
32 .fmt_type = FMT_BAYER,
33 .bpp = { 8 },
34 .mplanes = 1,
35 .write_format = CIF_MI_DMA_CTRL_READ_FMT_PACKED,
36 .output_format = CIF_MI_DMA_CTRL_RGB_BAYER_8BIT,
37 }, {
38 .fourcc = V4L2_PIX_FMT_SGBRG8,
39 .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8,
40 .fmt_type = FMT_BAYER,
41 .bpp = { 8 },
42 .mplanes = 1,
43 .write_format = CIF_MI_DMA_CTRL_READ_FMT_PACKED,
44 .output_format = CIF_MI_DMA_CTRL_RGB_BAYER_8BIT,
45 }, {
46 .fourcc = V4L2_PIX_FMT_SBGGR8,
47 .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8,
48 .fmt_type = FMT_BAYER,
49 .bpp = { 8 },
50 .mplanes = 1,
51 .write_format = CIF_MI_DMA_CTRL_READ_FMT_PACKED,
52 .output_format = CIF_MI_DMA_CTRL_RGB_BAYER_8BIT,
53 }, { /* 12bit used, 4 lower bits of LSB unused */
54 .fourcc = V4L2_PIX_FMT_SBGGR16,
55 .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12,
56 .fmt_type = FMT_BAYER,
57 .bpp = { 16 },
58 .mplanes = 1,
59 .write_format = CIF_MI_DMA_CTRL_READ_FMT_PACKED,
60 .output_format = CIF_MI_DMA_CTRL_RGB_BAYER_16BIT,
61 }, {
62 .fourcc = V4L2_PIX_FMT_YUYV,
63 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
64 .fmt_type = FMT_YUV,
65 .bpp = { 16 },
66 .cplanes = 1,
67 .mplanes = 1,
68 .uv_swap = 0,
69 .write_format = CIF_MI_DMA_CTRL_READ_FMT_PACKED,
70 .output_format = CIF_MI_DMA_CTRL_FMT_YUV422,
71 }, {
72 .fourcc = V4L2_PIX_FMT_YVYU,
73 .mbus_code = MEDIA_BUS_FMT_YVYU8_2X8,
74 .fmt_type = FMT_YUV,
75 .bpp = { 16 },
76 .cplanes = 1,
77 .mplanes = 1,
78 .uv_swap = 0,
79 .write_format = CIF_MI_DMA_CTRL_READ_FMT_PACKED,
80 .output_format = CIF_MI_DMA_CTRL_FMT_YUV422,
81 }, {
82 .fourcc = V4L2_PIX_FMT_UYVY,
83 .mbus_code = MEDIA_BUS_FMT_UYVY8_2X8,
84 .fmt_type = FMT_YUV,
85 .bpp = { 16 },
86 .cplanes = 1,
87 .mplanes = 1,
88 .uv_swap = 0,
89 .write_format = CIF_MI_DMA_CTRL_READ_FMT_PACKED,
90 .output_format = CIF_MI_DMA_CTRL_FMT_YUV422,
91 }, {
92 .fourcc = V4L2_PIX_FMT_VYUY,
93 .mbus_code = MEDIA_BUS_FMT_VYUY8_2X8,
94 .fmt_type = FMT_YUV,
95 .bpp = { 16 },
96 .cplanes = 1,
97 .mplanes = 1,
98 .uv_swap = 0,
99 .write_format = CIF_MI_DMA_CTRL_READ_FMT_PACKED,
100 .output_format = CIF_MI_DMA_CTRL_FMT_YUV422,
101 }
102 };
103
104 static const struct capture_fmt rawrd_fmts[] = {
105 {
106 .fourcc = V4L2_PIX_FMT_SRGGB8,
107 .fmt_type = FMT_BAYER,
108 .bpp = { 8 },
109 .mplanes = 1,
110 }, {
111 .fourcc = V4L2_PIX_FMT_SGRBG8,
112 .fmt_type = FMT_BAYER,
113 .bpp = { 8 },
114 .mplanes = 1,
115 }, {
116 .fourcc = V4L2_PIX_FMT_SGBRG8,
117 .fmt_type = FMT_BAYER,
118 .bpp = { 8 },
119 .mplanes = 1,
120 }, {
121 .fourcc = V4L2_PIX_FMT_SBGGR8,
122 .fmt_type = FMT_BAYER,
123 .bpp = { 8 },
124 .mplanes = 1,
125 }, {
126 .fourcc = V4L2_PIX_FMT_GREY,
127 .fmt_type = FMT_BAYER,
128 .bpp = { 8 },
129 .mplanes = 1,
130 }, {
131 .fourcc = V4L2_PIX_FMT_SRGGB10,
132 .fmt_type = FMT_BAYER,
133 .bpp = { 10 },
134 .mplanes = 1,
135 }, {
136 .fourcc = V4L2_PIX_FMT_SGRBG10,
137 .fmt_type = FMT_BAYER,
138 .bpp = { 10 },
139 .mplanes = 1,
140 }, {
141 .fourcc = V4L2_PIX_FMT_SGBRG10,
142 .fmt_type = FMT_BAYER,
143 .bpp = { 10 },
144 .mplanes = 1,
145 }, {
146 .fourcc = V4L2_PIX_FMT_SBGGR10,
147 .fmt_type = FMT_BAYER,
148 .bpp = { 10 },
149 .mplanes = 1,
150 }, {
151 .fourcc = V4L2_PIX_FMT_Y10,
152 .fmt_type = FMT_BAYER,
153 .bpp = { 10 },
154 .mplanes = 1,
155 }, {
156 .fourcc = V4L2_PIX_FMT_SRGGB12,
157 .fmt_type = FMT_BAYER,
158 .bpp = { 12 },
159 .mplanes = 1,
160 }, {
161 .fourcc = V4L2_PIX_FMT_SGRBG12,
162 .fmt_type = FMT_BAYER,
163 .bpp = { 12 },
164 .mplanes = 1,
165 }, {
166 .fourcc = V4L2_PIX_FMT_SGBRG12,
167 .fmt_type = FMT_BAYER,
168 .bpp = { 12 },
169 .mplanes = 1,
170 }, {
171 .fourcc = V4L2_PIX_FMT_SBGGR12,
172 .fmt_type = FMT_BAYER,
173 .bpp = { 12 },
174 .mplanes = 1,
175 }, {
176 .fourcc = V4L2_PIX_FMT_Y12,
177 .fmt_type = FMT_BAYER,
178 .bpp = { 12 },
179 .mplanes = 1,
180 }, {
181 .fourcc = V4L2_PIX_FMT_YUYV,
182 .fmt_type = FMT_YUV,
183 .bpp = { 16 },
184 .mplanes = 1,
185 }, {
186 .fourcc = V4L2_PIX_FMT_YVYU,
187 .fmt_type = FMT_YUV,
188 .bpp = { 16 },
189 .mplanes = 1,
190 }, {
191 .fourcc = V4L2_PIX_FMT_UYVY,
192 .fmt_type = FMT_YUV,
193 .bpp = { 16 },
194 .mplanes = 1,
195 }, {
196 .fourcc = V4L2_PIX_FMT_VYUY,
197 .fmt_type = FMT_YUV,
198 .bpp = { 16 },
199 .mplanes = 1,
200 }
201 };
202
203 static struct stream_config rkisp_dmarx_stream_config = {
204 .fmts = dmarx_fmts,
205 .fmt_size = ARRAY_SIZE(dmarx_fmts),
206 .mi = {
207 .y_size_init = CIF_MI_DMA_Y_PIC_SIZE,
208 .y_base_ad_init = CIF_MI_DMA_Y_PIC_START_AD,
209 .cb_base_ad_init = CIF_MI_DMA_CB_PIC_START_AD,
210 .cr_base_ad_init = CIF_MI_DMA_CR_PIC_START_AD,
211 },
212 };
213
214 static struct stream_config rkisp2_dmarx0_stream_config = {
215 .fmts = rawrd_fmts,
216 .fmt_size = ARRAY_SIZE(rawrd_fmts),
217 .frame_end_id = RAW0_RD_FRAME,
218 .mi = {
219 .y_base_ad_init = MI_RAW0_RD_BASE,
220 .y_base_ad_shd = MI_RAW0_RD_BASE_SHD,
221 .length = MI_RAW0_RD_LENGTH,
222 },
223 };
224
225 static struct stream_config rkisp2_dmarx1_stream_config = {
226 .fmts = rawrd_fmts,
227 .fmt_size = ARRAY_SIZE(rawrd_fmts),
228 .frame_end_id = RAW1_RD_FRAME,
229 .mi = {
230 .y_base_ad_init = MI_RAW1_RD_BASE,
231 .y_base_ad_shd = MI_RAW1_RD_BASE_SHD,
232 .length = MI_RAW1_RD_LENGTH,
233 },
234 };
235
236 static struct stream_config rkisp2_dmarx2_stream_config = {
237 .fmts = rawrd_fmts,
238 .fmt_size = ARRAY_SIZE(rawrd_fmts),
239 .frame_end_id = RAW2_RD_FRAME,
240 .mi = {
241 .y_base_ad_init = MI_RAW2_RD_BASE,
242 .y_base_ad_shd = MI_RAW2_RD_BASE_SHD,
243 .length = MI_RAW2_RD_LENGTH,
244 },
245 };
246
247 static const
find_fmt(struct rkisp_stream * stream,const u32 pixelfmt)248 struct capture_fmt *find_fmt(struct rkisp_stream *stream,
249 const u32 pixelfmt)
250 {
251 const struct capture_fmt *fmt;
252 int i;
253
254 for (i = 0; i < stream->config->fmt_size; i++) {
255 fmt = &stream->config->fmts[i];
256 if (fmt->fourcc == pixelfmt)
257 return fmt;
258 }
259 return NULL;
260 }
261
dmarx_config_mi(struct rkisp_stream * stream)262 static int dmarx_config_mi(struct rkisp_stream *stream)
263 {
264 struct rkisp_device *dev = stream->ispdev;
265 void __iomem *base = dev->base_addr;
266 struct capture_fmt *dmarx_in_fmt = &stream->out_isp_fmt;
267
268 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
269 "%s %dx%d y_stride:%d\n", __func__,
270 stream->out_fmt.width,
271 stream->out_fmt.height,
272 stream->u.dmarx.y_stride);
273
274 mi_set_y_size(stream, stream->out_fmt.width *
275 stream->out_fmt.height);
276 dmarx_set_y_width(base, stream->out_fmt.width);
277 dmarx_set_y_line_length(base, stream->u.dmarx.y_stride);
278
279 mi_dmarx_ready_enable(stream);
280 if (dmarx_in_fmt->uv_swap)
281 dmarx_set_uv_swap(base);
282
283 dmarx_ctrl(base,
284 dmarx_in_fmt->write_format |
285 dmarx_in_fmt->output_format |
286 CIF_MI_DMA_CTRL_BURST_LEN_LUM_16 |
287 CIF_MI_DMA_CTRL_BURST_LEN_CHROM_16);
288 return 0;
289 }
290
update_dmarx(struct rkisp_stream * stream)291 static void update_dmarx(struct rkisp_stream *stream)
292 {
293 void __iomem *base = stream->ispdev->base_addr;
294
295 if (stream->curr_buf) {
296 mi_set_y_addr(stream,
297 stream->curr_buf->buff_addr[RKISP_PLANE_Y]);
298 mi_set_cb_addr(stream,
299 stream->curr_buf->buff_addr[RKISP_PLANE_CB]);
300 mi_set_cr_addr(stream,
301 stream->curr_buf->buff_addr[RKISP_PLANE_CR]);
302 mi_dmarx_start(base);
303 stream->frame_end = false;
304 }
305 }
306
dmarx_stop_mi(struct rkisp_stream * stream)307 static void dmarx_stop_mi(struct rkisp_stream *stream)
308 {
309 mi_dmarx_ready_disable(stream);
310 }
311
312 static struct streams_ops rkisp_dmarx_streams_ops = {
313 .config_mi = dmarx_config_mi,
314 .stop_mi = dmarx_stop_mi,
315 .update_mi = update_dmarx,
316 };
317
rawrd_config_mi(struct rkisp_stream * stream)318 static int rawrd_config_mi(struct rkisp_stream *stream)
319 {
320 struct rkisp_device *dev = stream->ispdev;
321 bool is_unite = dev->hw_dev->is_unite;
322 u32 val;
323
324 val = rkisp_read(dev, CSI2RX_DATA_IDS_1, true);
325 val &= ~SW_CSI_ID0(0xff);
326 switch (stream->out_isp_fmt.fourcc) {
327 case V4L2_PIX_FMT_SRGGB8:
328 case V4L2_PIX_FMT_SBGGR8:
329 case V4L2_PIX_FMT_SGRBG8:
330 case V4L2_PIX_FMT_SGBRG8:
331 case V4L2_PIX_FMT_GREY:
332 val |= CIF_CSI2_DT_RAW8;
333 break;
334 case V4L2_PIX_FMT_SRGGB10:
335 case V4L2_PIX_FMT_SBGGR10:
336 case V4L2_PIX_FMT_SGRBG10:
337 case V4L2_PIX_FMT_SGBRG10:
338 case V4L2_PIX_FMT_Y10:
339 val |= CIF_CSI2_DT_RAW10;
340 break;
341 case V4L2_PIX_FMT_YUYV:
342 case V4L2_PIX_FMT_YVYU:
343 case V4L2_PIX_FMT_UYVY:
344 case V4L2_PIX_FMT_VYUY:
345 val |= CIF_CSI2_DT_YUV422_8b;
346 break;
347 default:
348 val |= CIF_CSI2_DT_RAW12;
349 }
350 rkisp_unite_write(dev, CSI2RX_RAW_RD_CTRL,
351 stream->memory << 2, false, is_unite);
352 rkisp_unite_write(dev, CSI2RX_DATA_IDS_1, val, false, is_unite);
353 rkisp_rawrd_set_pic_size(dev, stream->out_fmt.width,
354 stream->out_fmt.height);
355 mi_raw_length(stream);
356 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev,
357 "%s id:%d 0x%x %dx%d\n", __func__,
358 stream->id, val,
359 stream->out_fmt.width,
360 stream->out_fmt.height);
361 return 0;
362 }
363
update_rawrd(struct rkisp_stream * stream)364 static void update_rawrd(struct rkisp_stream *stream)
365 {
366 struct rkisp_device *dev = stream->ispdev;
367 void __iomem *base = dev->base_addr;
368 struct capture_fmt *fmt = &stream->out_isp_fmt;
369 u32 val;
370
371 if (stream->curr_buf) {
372 val = stream->curr_buf->buff_addr[RKISP_PLANE_Y];
373 rkisp_write(dev, stream->config->mi.y_base_ad_init, val, false);
374 if (dev->hw_dev->is_unite) {
375 val += (stream->out_fmt.width / 2 - RKMOUDLE_UNITE_EXTEND_PIXEL) *
376 fmt->bpp[0] / 8;
377 rkisp_next_write(dev, stream->config->mi.y_base_ad_init, val, false);
378 }
379 stream->frame_end = false;
380 if (stream->id == RKISP_STREAM_RAWRD2 &&
381 stream->out_isp_fmt.fmt_type == FMT_YUV) {
382 struct vb2_v4l2_buffer *vbuf = &stream->curr_buf->vb;
383 struct isp2x_csi_trigger trigger = {
384 .frame_timestamp = vbuf->vb2_buf.timestamp,
385 .sof_timestamp = vbuf->vb2_buf.timestamp,
386 .frame_id = vbuf->sequence,
387 .mode = T_START_X1,
388 .times = 0,
389 };
390
391 if (!vbuf->sequence)
392 trigger.frame_id = atomic_inc_return(&dev->isp_sdev.frm_sync_seq);
393 rkisp_rdbk_trigger_event(dev, T_CMD_QUEUE, &trigger);
394 }
395 } else if (dev->dmarx_dev.trigger == T_AUTO) {
396 /* internal raw wr/rd buf rotate */
397 struct rkisp_dummy_buffer *buf;
398 u32 id, rawwr_addr, val;
399
400 switch (stream->id) {
401 case RKISP_STREAM_RAWRD2:
402 id = dev->hdr.index[HDR_DMA2];
403 rawwr_addr = MI_RAW2_WR_BASE_SHD;
404 break;
405 case RKISP_STREAM_RAWRD1:
406 id = dev->hdr.index[HDR_DMA1];
407 rawwr_addr = MI_RAW1_WR_BASE_SHD;
408 break;
409 case RKISP_STREAM_RAWRD0:
410 default:
411 id = dev->hdr.index[HDR_DMA0];
412 rawwr_addr = MI_RAW0_WR_BASE_SHD;
413 }
414 if (dev->hdr.rx_cur_buf[id]) {
415 hdr_qbuf(&dev->hdr.q_tx[id], dev->hdr.rx_cur_buf[id]);
416 dev->hdr.rx_cur_buf[id] = NULL;
417 }
418 buf = hdr_dqbuf(&dev->hdr.q_rx[id]);
419 if (buf) {
420 val = buf->dma_addr;
421 dev->hdr.rx_cur_buf[id] = buf;
422 } else {
423 val = readl(base + rawwr_addr);
424 }
425 mi_set_y_addr(stream, val);
426 }
427 }
428
429 static struct streams_ops rkisp2_dmarx_streams_ops = {
430 .config_mi = rawrd_config_mi,
431 .update_mi = update_rawrd,
432 };
433
dmarx_frame_end(struct rkisp_stream * stream)434 static int dmarx_frame_end(struct rkisp_stream *stream)
435 {
436 unsigned long lock_flags = 0;
437
438 spin_lock_irqsave(&stream->vbq_lock, lock_flags);
439 if (stream->curr_buf) {
440 vb2_buffer_done(&stream->curr_buf->vb.vb2_buf,
441 VB2_BUF_STATE_DONE);
442 stream->curr_buf = NULL;
443 }
444
445 if (!list_empty(&stream->buf_queue)) {
446 stream->curr_buf =
447 list_first_entry(&stream->buf_queue,
448 struct rkisp_buffer,
449 queue);
450 list_del(&stream->curr_buf->queue);
451 }
452
453 if (stream->streaming)
454 stream->ops->update_mi(stream);
455 spin_unlock_irqrestore(&stream->vbq_lock, lock_flags);
456 return 0;
457 }
458
459 /***************************** vb2 operations*******************************/
460
dmarx_stop(struct rkisp_stream * stream)461 static void dmarx_stop(struct rkisp_stream *stream)
462 {
463 struct rkisp_device *dev = stream->ispdev;
464 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
465 int ret = 0;
466
467 stream->stopping = true;
468 if ((dev->isp_state & ISP_START) && !stream->frame_end) {
469 ret = wait_event_timeout(stream->done,
470 !stream->streaming,
471 msecs_to_jiffies(100));
472 if (!ret)
473 v4l2_warn(v4l2_dev,
474 "dmarx:%d waiting on event return error %d\n",
475 stream->id, ret);
476 }
477 if (stream->ops->stop_mi)
478 stream->ops->stop_mi(stream);
479 stream->stopping = false;
480 stream->streaming = false;
481 stream->frame_end = false;
482 }
483
dmarx_start(struct rkisp_stream * stream)484 static int dmarx_start(struct rkisp_stream *stream)
485 {
486 int ret;
487
488 ret = stream->ops->config_mi(stream);
489 if (ret)
490 return ret;
491
492 stream->curr_buf = NULL;
493 stream->streaming = true;
494 dmarx_frame_end(stream);
495 return 0;
496 }
497
rkisp_queue_setup(struct vb2_queue * queue,unsigned int * num_buffers,unsigned int * num_planes,unsigned int sizes[],struct device * alloc_ctxs[])498 static int rkisp_queue_setup(struct vb2_queue *queue,
499 unsigned int *num_buffers,
500 unsigned int *num_planes,
501 unsigned int sizes[],
502 struct device *alloc_ctxs[])
503 {
504 struct rkisp_stream *stream = queue->drv_priv;
505 struct rkisp_device *dev = stream->ispdev;
506 const struct v4l2_pix_format_mplane *pixm = NULL;
507 const struct capture_fmt *isp_fmt = NULL;
508 u32 i;
509
510 pixm = &stream->out_fmt;
511 isp_fmt = &stream->out_isp_fmt;
512
513 *num_planes = isp_fmt->mplanes;
514
515 for (i = 0; i < isp_fmt->mplanes; i++) {
516 const struct v4l2_plane_pix_format *plane_fmt;
517
518 plane_fmt = &pixm->plane_fmt[i];
519 sizes[i] = plane_fmt->sizeimage;
520 }
521
522 rkisp_chk_tb_over(dev);
523 v4l2_dbg(1, rkisp_debug, &dev->v4l2_dev, "%s %s count %d, size %d\n",
524 stream->vnode.vdev.name, v4l2_type_names[queue->type], *num_buffers, sizes[0]);
525
526 return 0;
527 }
528
529 /*
530 * The vb2_buffer are stored in rkisp_buffer, in order to unify
531 * mplane buffer and none-mplane buffer.
532 */
rkisp_buf_queue(struct vb2_buffer * vb)533 static void rkisp_buf_queue(struct vb2_buffer *vb)
534 {
535 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
536 struct rkisp_buffer *ispbuf = to_rkisp_buffer(vbuf);
537 struct vb2_queue *queue = vb->vb2_queue;
538 struct rkisp_stream *stream = queue->drv_priv;
539 unsigned long lock_flags = 0;
540 struct v4l2_pix_format_mplane *pixm = &stream->out_fmt;
541 struct capture_fmt *isp_fmt = &stream->out_isp_fmt;
542 struct sg_table *sgt;
543 int i;
544
545 memset(ispbuf->buff_addr, 0, sizeof(ispbuf->buff_addr));
546 for (i = 0; i < isp_fmt->mplanes; i++) {
547 if (stream->ispdev->hw_dev->is_dma_sg_ops) {
548 sgt = vb2_dma_sg_plane_desc(vb, i);
549 ispbuf->buff_addr[i] = sg_dma_address(sgt->sgl);
550 } else {
551 ispbuf->buff_addr[i] = vb2_dma_contig_plane_dma_addr(vb, i);
552 }
553 }
554 /*
555 * NOTE: plane_fmt[0].sizeimage is total size of all planes for single
556 * memory plane formats, so calculate the size explicitly.
557 */
558 if (isp_fmt->mplanes == 1) {
559 for (i = 0; i < isp_fmt->cplanes - 1; i++) {
560 ispbuf->buff_addr[i + 1] = (i == 0) ?
561 ispbuf->buff_addr[i] +
562 pixm->plane_fmt[i].bytesperline *
563 pixm->height :
564 ispbuf->buff_addr[i] +
565 pixm->plane_fmt[i].sizeimage;
566 }
567 }
568
569 v4l2_dbg(2, rkisp_debug, &stream->ispdev->v4l2_dev,
570 "rx:%d queue buf:0x%x\n",
571 stream->id, ispbuf->buff_addr[0]);
572
573 spin_lock_irqsave(&stream->vbq_lock, lock_flags);
574 if (stream->streaming &&
575 list_empty(&stream->buf_queue) &&
576 !stream->curr_buf) {
577 stream->curr_buf = ispbuf;
578 stream->ops->update_mi(stream);
579 } else {
580 list_add_tail(&ispbuf->queue, &stream->buf_queue);
581 }
582 spin_unlock_irqrestore(&stream->vbq_lock, lock_flags);
583 }
584
destroy_buf_queue(struct rkisp_stream * stream,enum vb2_buffer_state state)585 static void destroy_buf_queue(struct rkisp_stream *stream,
586 enum vb2_buffer_state state)
587 {
588 struct rkisp_buffer *buf;
589 unsigned long lock_flags = 0;
590
591 spin_lock_irqsave(&stream->vbq_lock, lock_flags);
592 if (stream->curr_buf) {
593 list_add_tail(&stream->curr_buf->queue, &stream->buf_queue);
594 stream->curr_buf = NULL;
595 }
596 while (!list_empty(&stream->buf_queue)) {
597 buf = list_first_entry(&stream->buf_queue,
598 struct rkisp_buffer, queue);
599 list_del(&buf->queue);
600 vb2_buffer_done(&buf->vb.vb2_buf, state);
601 }
602 spin_unlock_irqrestore(&stream->vbq_lock, lock_flags);
603 }
604
dmarx_stop_streaming(struct vb2_queue * queue)605 static void dmarx_stop_streaming(struct vb2_queue *queue)
606 {
607 struct rkisp_stream *stream = queue->drv_priv;
608 struct v4l2_device *v4l2_dev = &stream->ispdev->v4l2_dev;
609
610 v4l2_dbg(1, rkisp_debug, v4l2_dev, "%s %s id:%d\n",
611 __func__, stream->vnode.vdev.name, stream->id);
612
613 if (!stream->streaming)
614 return;
615
616 dmarx_stop(stream);
617 destroy_buf_queue(stream, VB2_BUF_STATE_ERROR);
618
619 if (stream->id == RKISP_STREAM_RAWRD2 &&
620 (stream->ispdev->isp_ver == ISP_V20 || stream->ispdev->isp_ver == ISP_V21))
621 kfifo_reset(&stream->ispdev->rdbk_kfifo);
622 }
623
dmarx_start_streaming(struct vb2_queue * queue,unsigned int count)624 static int dmarx_start_streaming(struct vb2_queue *queue,
625 unsigned int count)
626 {
627 struct rkisp_stream *stream = queue->drv_priv;
628 struct rkisp_device *dev = stream->ispdev;
629 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
630 int ret = -1;
631
632 v4l2_dbg(1, rkisp_debug, v4l2_dev, "%s %s id:%d\n",
633 __func__, stream->vnode.vdev.name, stream->id);
634
635 if (WARN_ON(stream->streaming))
636 return -EBUSY;
637
638 if (!stream->linked) {
639 v4l2_err(v4l2_dev, "check %s link\n", stream->vnode.vdev.name);
640 goto free_buf_queue;
641 }
642
643 ret = dmarx_start(stream);
644 if (ret < 0) {
645 v4l2_err(v4l2_dev, "start %s failed\n", stream->vnode.vdev.name);
646 goto free_buf_queue;
647 }
648 return 0;
649 free_buf_queue:
650 destroy_buf_queue(stream, VB2_BUF_STATE_QUEUED);
651 return ret;
652 }
653
654 static struct vb2_ops dmarx_vb2_ops = {
655 .queue_setup = rkisp_queue_setup,
656 .buf_queue = rkisp_buf_queue,
657 .wait_prepare = vb2_ops_wait_prepare,
658 .wait_finish = vb2_ops_wait_finish,
659 .stop_streaming = dmarx_stop_streaming,
660 .start_streaming = dmarx_start_streaming,
661 };
662
rkisp_init_vb2_queue(struct vb2_queue * q,struct rkisp_stream * stream,enum v4l2_buf_type buf_type)663 static int rkisp_init_vb2_queue(struct vb2_queue *q,
664 struct rkisp_stream *stream,
665 enum v4l2_buf_type buf_type)
666 {
667 q->type = buf_type;
668 q->io_modes = VB2_MMAP | VB2_DMABUF | VB2_USERPTR;
669 q->drv_priv = stream;
670 q->ops = &dmarx_vb2_ops;
671 q->mem_ops = stream->ispdev->hw_dev->mem_ops;
672 q->buf_struct_size = sizeof(struct rkisp_buffer);
673 q->min_buffers_needed = CIF_ISP_REQ_BUFS_MIN;
674 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
675 q->lock = &stream->apilock;
676 q->dev = stream->ispdev->hw_dev->dev;
677 q->allow_cache_hints = 1;
678 q->bidirectional = 1;
679 q->gfp_flags = GFP_DMA32;
680 return vb2_queue_init(q);
681 }
682
rkisp_set_fmt(struct rkisp_stream * stream,struct v4l2_pix_format_mplane * pixm,bool try)683 static int rkisp_set_fmt(struct rkisp_stream *stream,
684 struct v4l2_pix_format_mplane *pixm,
685 bool try)
686 {
687 const struct capture_fmt *fmt;
688 unsigned int imagsize = 0;
689 unsigned int planes;
690 u32 xsubs = 1, ysubs = 1;
691 unsigned int i;
692
693 fmt = find_fmt(stream, pixm->pixelformat);
694 if (!fmt) {
695 v4l2_err(&stream->ispdev->v4l2_dev,
696 "nonsupport pixelformat:%c%c%c%c\n",
697 pixm->pixelformat,
698 pixm->pixelformat >> 8,
699 pixm->pixelformat >> 16,
700 pixm->pixelformat >> 24);
701 return -EINVAL;
702 }
703
704 pixm->num_planes = fmt->mplanes;
705 pixm->field = V4L2_FIELD_NONE;
706 if (!pixm->quantization)
707 pixm->quantization = V4L2_QUANTIZATION_FULL_RANGE;
708
709 /* calculate size */
710 rkisp_fcc_xysubs(fmt->fourcc, &xsubs, &ysubs);
711 planes = fmt->cplanes ? fmt->cplanes : fmt->mplanes;
712 for (i = 0; i < planes; i++) {
713 struct v4l2_plane_pix_format *plane_fmt;
714 unsigned int width, height, bytesperline;
715
716 plane_fmt = pixm->plane_fmt + i;
717
718 if (i == 0) {
719 width = pixm->width;
720 height = pixm->height;
721 } else {
722 width = pixm->width / xsubs;
723 height = pixm->height / ysubs;
724 }
725
726 if (stream->ispdev->isp_ver == ISP_V20 &&
727 stream->id == RKISP_STREAM_RAWRD2 &&
728 fmt->fmt_type == FMT_BAYER)
729 height += RKMODULE_EXTEND_LINE;
730
731 if ((stream->ispdev->isp_ver == ISP_V20 ||
732 stream->ispdev->isp_ver == ISP_V21 ||
733 stream->ispdev->isp_ver == ISP_V30) &&
734 fmt->fmt_type == FMT_BAYER &&
735 !stream->memory &&
736 stream->id != RKISP_STREAM_DMARX)
737 bytesperline = ALIGN(width * fmt->bpp[i] / 8, 256);
738 else
739 bytesperline = width * DIV_ROUND_UP(fmt->bpp[i], 8);
740 /* stride is only available for sp stream and y plane */
741 if (i != 0 ||
742 plane_fmt->bytesperline < bytesperline)
743 plane_fmt->bytesperline = bytesperline;
744
745 plane_fmt->sizeimage = plane_fmt->bytesperline * height;
746
747 imagsize += plane_fmt->sizeimage;
748 }
749
750 /* convert to non-MPLANE format.
751 * it's important since we want to unify none-MPLANE
752 * and MPLANE.
753 */
754 if (fmt->mplanes == 1)
755 pixm->plane_fmt[0].sizeimage = imagsize;
756
757 if (!try) {
758 stream->out_isp_fmt = *fmt;
759 stream->out_fmt = *pixm;
760
761 stream->u.dmarx.y_stride =
762 pixm->plane_fmt[0].bytesperline /
763 DIV_ROUND_UP(fmt->bpp[0], 8);
764
765 v4l2_dbg(1, rkisp_debug, &stream->ispdev->v4l2_dev,
766 "%s: rx:%d req(%d, %d) out(%d, %d)\n", __func__,
767 stream->id, pixm->width, pixm->height,
768 stream->out_fmt.width, stream->out_fmt.height);
769 }
770
771 return 0;
772 }
773
774 /************************* v4l2_file_operations***************************/
775
776 static const struct v4l2_file_operations rkisp_fops = {
777 .open = rkisp_fh_open,
778 .release = rkisp_fop_release,
779 .unlocked_ioctl = video_ioctl2,
780 .poll = vb2_fop_poll,
781 .mmap = vb2_fop_mmap,
782 };
783
rkisp_try_fmt_vid_out_mplane(struct file * file,void * fh,struct v4l2_format * f)784 static int rkisp_try_fmt_vid_out_mplane(struct file *file, void *fh,
785 struct v4l2_format *f)
786 {
787 struct rkisp_stream *stream = video_drvdata(file);
788
789 return rkisp_set_fmt(stream, &f->fmt.pix_mp, true);
790 }
791
rkisp_enum_fmt_vid_out_mplane(struct file * file,void * priv,struct v4l2_fmtdesc * f)792 static int rkisp_enum_fmt_vid_out_mplane(struct file *file, void *priv,
793 struct v4l2_fmtdesc *f)
794 {
795 struct rkisp_stream *stream = video_drvdata(file);
796 const struct capture_fmt *fmt = NULL;
797
798 if (f->index >= stream->config->fmt_size)
799 return -EINVAL;
800
801 fmt = &stream->config->fmts[f->index];
802 f->pixelformat = fmt->fourcc;
803
804 return 0;
805 }
806
rkisp_s_fmt_vid_out_mplane(struct file * file,void * priv,struct v4l2_format * f)807 static int rkisp_s_fmt_vid_out_mplane(struct file *file,
808 void *priv, struct v4l2_format *f)
809 {
810 struct rkisp_stream *stream = video_drvdata(file);
811 struct video_device *vdev = &stream->vnode.vdev;
812 struct rkisp_vdev_node *node = vdev_to_node(vdev);
813 struct rkisp_device *dev = stream->ispdev;
814
815 if (vb2_is_busy(&node->buf_queue)) {
816 v4l2_err(&dev->v4l2_dev, "%s rx:%d queue busy\n",
817 __func__, stream->id);
818 return -EBUSY;
819 }
820
821 return rkisp_set_fmt(stream, &f->fmt.pix_mp, false);
822 }
823
rkisp_g_fmt_vid_out_mplane(struct file * file,void * fh,struct v4l2_format * f)824 static int rkisp_g_fmt_vid_out_mplane(struct file *file, void *fh,
825 struct v4l2_format *f)
826 {
827 struct rkisp_stream *stream = video_drvdata(file);
828
829 f->fmt.pix_mp = stream->out_fmt;
830
831 return 0;
832 }
833
rkisp_querycap(struct file * file,void * priv,struct v4l2_capability * cap)834 static int rkisp_querycap(struct file *file, void *priv,
835 struct v4l2_capability *cap)
836 {
837 struct rkisp_stream *stream = video_drvdata(file);
838 struct device *dev = stream->ispdev->dev;
839 struct video_device *vdev = video_devdata(file);
840
841 strlcpy(cap->card, vdev->name, sizeof(cap->card));
842 snprintf(cap->driver, sizeof(cap->driver),
843 "%s_v%d", dev->driver->name,
844 stream->ispdev->isp_ver >> 4);
845 snprintf(cap->bus_info, sizeof(cap->bus_info),
846 "platform:%s", dev_name(dev));
847
848 return 0;
849 }
850
rkisp_ioctl_default(struct file * file,void * fh,bool valid_prio,unsigned int cmd,void * arg)851 static long rkisp_ioctl_default(struct file *file, void *fh,
852 bool valid_prio, unsigned int cmd, void *arg)
853 {
854 struct rkisp_stream *stream = video_drvdata(file);
855 long ret = 0;
856
857 switch (cmd) {
858 case RKISP_CMD_GET_CSI_MEMORY_MODE:
859 if (stream->id != RKISP_STREAM_RAWRD0 &&
860 stream->id != RKISP_STREAM_RAWRD1 &&
861 stream->id != RKISP_STREAM_RAWRD2)
862 ret = -EINVAL;
863 else if (stream->memory == 0)
864 *(int *)arg = CSI_MEM_COMPACT;
865 else if (stream->memory == SW_CSI_RAW_WR_SIMG_MODE)
866 *(int *)arg = CSI_MEM_WORD_BIG_ALIGN;
867 else
868 *(int *)arg = CSI_MEM_WORD_LITTLE_ALIGN;
869 break;
870 case RKISP_CMD_SET_CSI_MEMORY_MODE:
871 if (stream->id != RKISP_STREAM_RAWRD0 &&
872 stream->id != RKISP_STREAM_RAWRD1 &&
873 stream->id != RKISP_STREAM_RAWRD2)
874 ret = -EINVAL;
875 else if (*(int *)arg == CSI_MEM_COMPACT)
876 stream->memory = 0;
877 else if (*(int *)arg == CSI_MEM_WORD_BIG_ALIGN)
878 stream->memory = SW_CSI_RAW_WR_SIMG_MODE;
879 else
880 stream->memory =
881 SW_CSI_RWA_WR_SIMG_SWP | SW_CSI_RAW_WR_SIMG_MODE;
882 break;
883 default:
884 ret = -EINVAL;
885 }
886
887 return ret;
888 }
889
890 static const struct v4l2_ioctl_ops rkisp_dmarx_ioctl = {
891 .vidioc_reqbufs = vb2_ioctl_reqbufs,
892 .vidioc_querybuf = vb2_ioctl_querybuf,
893 .vidioc_create_bufs = vb2_ioctl_create_bufs,
894 .vidioc_qbuf = vb2_ioctl_qbuf,
895 .vidioc_expbuf = vb2_ioctl_expbuf,
896 .vidioc_dqbuf = vb2_ioctl_dqbuf,
897 .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
898 .vidioc_streamon = vb2_ioctl_streamon,
899 .vidioc_streamoff = vb2_ioctl_streamoff,
900 .vidioc_try_fmt_vid_out_mplane = rkisp_try_fmt_vid_out_mplane,
901 .vidioc_enum_fmt_vid_out = rkisp_enum_fmt_vid_out_mplane,
902 .vidioc_s_fmt_vid_out_mplane = rkisp_s_fmt_vid_out_mplane,
903 .vidioc_g_fmt_vid_out_mplane = rkisp_g_fmt_vid_out_mplane,
904 .vidioc_querycap = rkisp_querycap,
905 .vidioc_default = rkisp_ioctl_default,
906 };
907
rkisp_unregister_dmarx_video(struct rkisp_stream * stream)908 static void rkisp_unregister_dmarx_video(struct rkisp_stream *stream)
909 {
910 media_entity_cleanup(&stream->vnode.vdev.entity);
911 video_unregister_device(&stream->vnode.vdev);
912 }
913
rkisp_register_dmarx_video(struct rkisp_stream * stream)914 static int rkisp_register_dmarx_video(struct rkisp_stream *stream)
915 {
916 struct rkisp_device *dev = stream->ispdev;
917 struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
918 struct video_device *vdev = &stream->vnode.vdev;
919 struct rkisp_vdev_node *node;
920 int ret = 0;
921
922 mutex_init(&stream->apilock);
923 node = vdev_to_node(vdev);
924
925 vdev->release = video_device_release_empty;
926 vdev->fops = &rkisp_fops;
927 vdev->minor = -1;
928 vdev->v4l2_dev = v4l2_dev;
929 vdev->lock = &stream->apilock;
930 video_set_drvdata(vdev, stream);
931
932 vdev->ioctl_ops = &rkisp_dmarx_ioctl;
933 vdev->device_caps = V4L2_CAP_VIDEO_OUTPUT_MPLANE |
934 V4L2_CAP_STREAMING;
935 vdev->vfl_dir = VFL_DIR_TX;
936 node->pad.flags = MEDIA_PAD_FL_SOURCE;
937
938 rkisp_init_vb2_queue(&node->buf_queue, stream,
939 V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
940 vdev->queue = &node->buf_queue;
941
942 ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
943 if (ret < 0) {
944 v4l2_err(v4l2_dev,
945 "%s failed with error %d\n", __func__, ret);
946 return ret;
947 }
948
949 ret = media_entity_pads_init(&vdev->entity, 1, &node->pad);
950 if (ret < 0)
951 goto unreg;
952
953 return 0;
954 unreg:
955 video_unregister_device(vdev);
956 return ret;
957 }
958
959 /**************** Interrupter Handler ****************/
960
rkisp_dmarx_isr(u32 mis_val,struct rkisp_device * dev)961 void rkisp_dmarx_isr(u32 mis_val, struct rkisp_device *dev)
962 {
963 void __iomem *base = dev->base_addr;
964 struct rkisp_stream *stream;
965
966 if (mis_val & CIF_MI_DMA_READY) {
967 stream = &dev->dmarx_dev.stream[RKISP_STREAM_DMARX];
968 stream->frame_end = true;
969 writel(CIF_MI_DMA_READY, base + CIF_MI_ICR);
970
971 if (stream->stopping) {
972 stream->stopping = false;
973 stream->streaming = false;
974 wake_up(&stream->done);
975 } else {
976 dmarx_frame_end(stream);
977 }
978 }
979 }
980
rkisp2_rawrd_isr(u32 mis_val,struct rkisp_device * dev)981 void rkisp2_rawrd_isr(u32 mis_val, struct rkisp_device *dev)
982 {
983 struct rkisp_stream *stream;
984 int i;
985
986 for (i = RKISP_STREAM_RAWRD0; i < RKISP_MAX_DMARX_STREAM; i++) {
987 stream = &dev->dmarx_dev.stream[i];
988 if (!(mis_val & CIF_MI_FRAME(stream)))
989 continue;
990 stream->frame_end = true;
991 if (stream->stopping) {
992 stream->stopping = false;
993 stream->streaming = false;
994 wake_up(&stream->done);
995 } else {
996 dmarx_frame_end(stream);
997 }
998 }
999 }
1000
dmarx_init(struct rkisp_device * dev,u32 id)1001 static int dmarx_init(struct rkisp_device *dev, u32 id)
1002 {
1003 struct rkisp_dmarx_device *dmarx_dev = &dev->dmarx_dev;
1004 struct rkisp_stream *stream;
1005 struct video_device *vdev;
1006 struct media_entity *source, *sink;
1007 int ret = 0;
1008
1009 stream = &dmarx_dev->stream[id];
1010 INIT_LIST_HEAD(&stream->buf_queue);
1011 init_waitqueue_head(&stream->done);
1012 spin_lock_init(&stream->vbq_lock);
1013 stream->id = id;
1014 stream->ispdev = dev;
1015 vdev = &stream->vnode.vdev;
1016 stream->linked = false;
1017
1018 switch (id) {
1019 case RKISP_STREAM_DMARX:
1020 strlcpy(vdev->name, DMA_VDEV_NAME,
1021 sizeof(vdev->name));
1022 stream->ops = &rkisp_dmarx_streams_ops;
1023 stream->config = &rkisp_dmarx_stream_config;
1024 break;
1025 case RKISP_STREAM_RAWRD0:
1026 strlcpy(vdev->name, DMARX0_VDEV_NAME,
1027 sizeof(vdev->name));
1028 stream->ops = &rkisp2_dmarx_streams_ops;
1029 stream->config = &rkisp2_dmarx0_stream_config;
1030 break;
1031 case RKISP_STREAM_RAWRD1:
1032 strlcpy(vdev->name, DMARX1_VDEV_NAME,
1033 sizeof(vdev->name));
1034 stream->ops = &rkisp2_dmarx_streams_ops;
1035 stream->config = &rkisp2_dmarx1_stream_config;
1036 break;
1037 case RKISP_STREAM_RAWRD2:
1038 strlcpy(vdev->name, DMARX2_VDEV_NAME,
1039 sizeof(vdev->name));
1040 stream->ops = &rkisp2_dmarx_streams_ops;
1041 stream->config = &rkisp2_dmarx2_stream_config;
1042 break;
1043 default:
1044 v4l2_err(&dev->v4l2_dev, "Invalid dmarx\n");
1045 return -EINVAL;
1046 }
1047 ret = rkisp_register_dmarx_video(stream);
1048 if (ret < 0)
1049 return ret;
1050
1051 /* dmarx link -> isp subdev */
1052 source = &vdev->entity;
1053 sink = &dev->isp_sdev.sd.entity;
1054 return media_create_pad_link(source, 0, sink,
1055 RKISP_ISP_PAD_SINK, stream->linked);
1056 }
1057
rkisp_dmarx_set_fmt(struct rkisp_stream * stream,struct v4l2_pix_format_mplane pixm)1058 void rkisp_dmarx_set_fmt(struct rkisp_stream *stream,
1059 struct v4l2_pix_format_mplane pixm)
1060 {
1061 rkisp_set_fmt(stream, &pixm, false);
1062 }
1063
rkisp_rawrd_set_pic_size(struct rkisp_device * dev,u32 width,u32 height)1064 void rkisp_rawrd_set_pic_size(struct rkisp_device *dev,
1065 u32 width, u32 height)
1066 {
1067 struct rkisp_isp_subdev *sdev = &dev->isp_sdev;
1068 u8 mult = sdev->in_fmt.fmt_type == FMT_YUV ? 2 : 1;
1069 bool is_unite = dev->hw_dev->is_unite;
1070 u32 w = !is_unite ? width : width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
1071
1072 /* rx height should equal to isp height + offset for read back mode */
1073 height = sdev->in_crop.top + sdev->in_crop.height;
1074
1075 /* isp20 extend line for normal read back mode to fix internal bug */
1076 if (dev->isp_ver == ISP_V20 &&
1077 sdev->in_fmt.fmt_type == FMT_BAYER &&
1078 sdev->out_fmt.fmt_type != FMT_BAYER &&
1079 dev->rd_mode == HDR_RDBK_FRAME1)
1080 height += RKMODULE_EXTEND_LINE;
1081
1082 w *= mult;
1083 rkisp_unite_write(dev, CSI2RX_RAW_RD_PIC_SIZE, height << 16 | w, false, is_unite);
1084 }
1085
rkisp_dmarx_get_frame(struct rkisp_device * dev,u32 * id,u64 * sof_timestamp,u64 * timestamp,bool sync)1086 void rkisp_dmarx_get_frame(struct rkisp_device *dev, u32 *id,
1087 u64 *sof_timestamp, u64 *timestamp,
1088 bool sync)
1089 {
1090 unsigned long flag = 0;
1091 u64 sof_time = 0, frame_timestamp = 0;
1092 u32 frame_id = 0;
1093
1094 if (!dev->dmarx_dev.trigger && id) {
1095 *id = atomic_read(&dev->isp_sdev.frm_sync_seq) - 1;
1096 return;
1097 }
1098
1099 spin_lock_irqsave(&dev->rdbk_lock, flag);
1100 if (sync) {
1101 frame_id = dev->dmarx_dev.cur_frame.id;
1102 sof_time = dev->dmarx_dev.cur_frame.sof_timestamp;
1103 frame_timestamp = dev->dmarx_dev.cur_frame.timestamp;
1104 } else {
1105 frame_id = dev->dmarx_dev.pre_frame.id;
1106 sof_time = dev->dmarx_dev.pre_frame.sof_timestamp;
1107 frame_timestamp = dev->dmarx_dev.pre_frame.timestamp;
1108 }
1109 spin_unlock_irqrestore(&dev->rdbk_lock, flag);
1110 if (id)
1111 *id = frame_id;
1112 if (sof_timestamp)
1113 *sof_timestamp = sof_time;
1114 if (timestamp)
1115 *timestamp = frame_timestamp;
1116 }
1117
rkisp_register_dmarx_vdev(struct rkisp_device * dev)1118 int rkisp_register_dmarx_vdev(struct rkisp_device *dev)
1119 {
1120 struct rkisp_dmarx_device *dmarx_dev = &dev->dmarx_dev;
1121 int ret = 0;
1122
1123 memset(dmarx_dev, 0, sizeof(*dmarx_dev));
1124 dmarx_dev->ispdev = dev;
1125
1126 #ifdef RKISP_DMAREAD_EN
1127 ret = dmarx_init(dev, RKISP_STREAM_DMARX);
1128 if (ret < 0)
1129 goto err;
1130 #endif
1131 if (dev->isp_ver == ISP_V20 ||
1132 dev->isp_ver == ISP_V21 ||
1133 dev->isp_ver == ISP_V30) {
1134 ret = dmarx_init(dev, RKISP_STREAM_RAWRD0);
1135 if (ret < 0)
1136 goto err_free_dmarx;
1137 ret = dmarx_init(dev, RKISP_STREAM_RAWRD2);
1138 if (ret < 0)
1139 goto err_free_dmarx0;
1140 }
1141 if (dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V30) {
1142 ret = dmarx_init(dev, RKISP_STREAM_RAWRD1);
1143 if (ret < 0)
1144 goto err_free_dmarx2;
1145 }
1146
1147 return 0;
1148 err_free_dmarx2:
1149 rkisp_unregister_dmarx_video(&dmarx_dev->stream[RKISP_STREAM_RAWRD2]);
1150 err_free_dmarx0:
1151 rkisp_unregister_dmarx_video(&dmarx_dev->stream[RKISP_STREAM_RAWRD0]);
1152 err_free_dmarx:
1153 #ifdef RKISP_DMAREAD_EN
1154 rkisp_unregister_dmarx_video(&dmarx_dev->stream[RKISP_STREAM_DMARX]);
1155 err:
1156 #endif
1157 return ret;
1158 }
1159
rkisp_unregister_dmarx_vdev(struct rkisp_device * dev)1160 void rkisp_unregister_dmarx_vdev(struct rkisp_device *dev)
1161 {
1162 struct rkisp_dmarx_device *dmarx_dev = &dev->dmarx_dev;
1163 struct rkisp_stream *stream;
1164
1165 #ifdef RKISP_DMAREAD_EN
1166 stream = &dmarx_dev->stream[RKISP_STREAM_DMARX];
1167 rkisp_unregister_dmarx_video(stream);
1168 #endif
1169
1170 if (dev->isp_ver == ISP_V20 ||
1171 dev->isp_ver == ISP_V21 ||
1172 dev->isp_ver == ISP_V30) {
1173 stream = &dmarx_dev->stream[RKISP_STREAM_RAWRD0];
1174 rkisp_unregister_dmarx_video(stream);
1175
1176 stream = &dmarx_dev->stream[RKISP_STREAM_RAWRD2];
1177 rkisp_unregister_dmarx_video(stream);
1178 }
1179 if (dev->isp_ver == ISP_V20 || dev->isp_ver == ISP_V30) {
1180 stream = &dmarx_dev->stream[RKISP_STREAM_RAWRD1];
1181 rkisp_unregister_dmarx_video(stream);
1182 }
1183 }
1184