1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2020 Rockchip Electronics Co., Ltd. */
3
4 #include <media/v4l2-common.h>
5 #include <media/v4l2-ioctl.h>
6 #include <media/videobuf2-core.h>
7 #include <media/videobuf2-vmalloc.h> /* for ISP params */
8 #include <linux/rk-preisp.h>
9 #include <linux/slab.h>
10 #include "dev.h"
11 #include "regs.h"
12 #include "regs_v2x.h"
13 #include "isp_params_v21.h"
14
15 #define ISP2X_PACK_4BYTE(a, b, c, d) \
16 (((a) & 0xFF) << 0 | ((b) & 0xFF) << 8 | \
17 ((c) & 0xFF) << 16 | ((d) & 0xFF) << 24)
18
19 #define ISP2X_PACK_2SHORT(a, b) \
20 (((a) & 0xFFFF) << 0 | ((b) & 0xFFFF) << 16)
21
22 #define ISP2X_REG_WR_MASK BIT(31) //disable write protect
23 #define ISP2X_NOBIG_OVERFLOW_SIZE (2688 * 1536)
24 #define ISP2X_AUTO_BIGMODE_WIDTH 2688
25
26 static inline size_t
isp_param_get_insize(struct rkisp_isp_params_vdev * params_vdev)27 isp_param_get_insize(struct rkisp_isp_params_vdev *params_vdev)
28 {
29 struct rkisp_device *dev = params_vdev->dev;
30 struct rkisp_isp_subdev *isp_sdev = &dev->isp_sdev;
31
32 return isp_sdev->in_crop.width * isp_sdev->in_crop.height;
33 }
34
35 static void
isp_dpcc_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_dpcc_cfg * arg)36 isp_dpcc_config(struct rkisp_isp_params_vdev *params_vdev,
37 const struct isp2x_dpcc_cfg *arg)
38 {
39 u32 value;
40 int i;
41
42 value = rkisp_ioread32(params_vdev, ISP_DPCC0_MODE);
43 value &= ISP_DPCC_EN;
44
45 value |= (arg->stage1_enable & 0x01) << 2 |
46 (arg->grayscale_mode & 0x01) << 1;
47 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_MODE);
48 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_MODE);
49
50 value = (arg->sw_rk_out_sel & 0x03) << 5 |
51 (arg->sw_dpcc_output_sel & 0x01) << 4 |
52 (arg->stage1_rb_3x3 & 0x01) << 3 |
53 (arg->stage1_g_3x3 & 0x01) << 2 |
54 (arg->stage1_incl_rb_center & 0x01) << 1 |
55 (arg->stage1_incl_green_center & 0x01);
56 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_OUTPUT_MODE);
57 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_OUTPUT_MODE);
58
59 value = (arg->stage1_use_fix_set & 0x01) << 3 |
60 (arg->stage1_use_set_3 & 0x01) << 2 |
61 (arg->stage1_use_set_2 & 0x01) << 1 |
62 (arg->stage1_use_set_1 & 0x01);
63 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_SET_USE);
64 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_SET_USE);
65
66 value = (arg->sw_rk_red_blue1_en & 0x01) << 13 |
67 (arg->rg_red_blue1_enable & 0x01) << 12 |
68 (arg->rnd_red_blue1_enable & 0x01) << 11 |
69 (arg->ro_red_blue1_enable & 0x01) << 10 |
70 (arg->lc_red_blue1_enable & 0x01) << 9 |
71 (arg->pg_red_blue1_enable & 0x01) << 8 |
72 (arg->sw_rk_green1_en & 0x01) << 5 |
73 (arg->rg_green1_enable & 0x01) << 4 |
74 (arg->rnd_green1_enable & 0x01) << 3 |
75 (arg->ro_green1_enable & 0x01) << 2 |
76 (arg->lc_green1_enable & 0x01) << 1 |
77 (arg->pg_green1_enable & 0x01);
78 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_METHODS_SET_1);
79 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_METHODS_SET_1);
80
81 value = (arg->sw_rk_red_blue2_en & 0x01) << 13 |
82 (arg->rg_red_blue2_enable & 0x01) << 12 |
83 (arg->rnd_red_blue2_enable & 0x01) << 11 |
84 (arg->ro_red_blue2_enable & 0x01) << 10 |
85 (arg->lc_red_blue2_enable & 0x01) << 9 |
86 (arg->pg_red_blue2_enable & 0x01) << 8 |
87 (arg->sw_rk_green2_en & 0x01) << 5 |
88 (arg->rg_green2_enable & 0x01) << 4 |
89 (arg->rnd_green2_enable & 0x01) << 3 |
90 (arg->ro_green2_enable & 0x01) << 2 |
91 (arg->lc_green2_enable & 0x01) << 1 |
92 (arg->pg_green2_enable & 0x01);
93 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_METHODS_SET_2);
94 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_METHODS_SET_2);
95
96 value = (arg->sw_rk_red_blue3_en & 0x01) << 13 |
97 (arg->rg_red_blue3_enable & 0x01) << 12 |
98 (arg->rnd_red_blue3_enable & 0x01) << 11 |
99 (arg->ro_red_blue3_enable & 0x01) << 10 |
100 (arg->lc_red_blue3_enable & 0x01) << 9 |
101 (arg->pg_red_blue3_enable & 0x01) << 8 |
102 (arg->sw_rk_green3_en & 0x01) << 5 |
103 (arg->rg_green3_enable & 0x01) << 4 |
104 (arg->rnd_green3_enable & 0x01) << 3 |
105 (arg->ro_green3_enable & 0x01) << 2 |
106 (arg->lc_green3_enable & 0x01) << 1 |
107 (arg->pg_green3_enable & 0x01);
108 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_METHODS_SET_3);
109 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_METHODS_SET_3);
110
111 value = ISP2X_PACK_4BYTE(arg->line_thr_1_g, arg->line_thr_1_rb,
112 arg->sw_mindis1_g, arg->sw_mindis1_rb);
113 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_LINE_THRESH_1);
114 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_LINE_THRESH_1);
115
116 value = ISP2X_PACK_4BYTE(arg->line_mad_fac_1_g, arg->line_mad_fac_1_rb,
117 arg->sw_dis_scale_max1, arg->sw_dis_scale_min1);
118 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_LINE_MAD_FAC_1);
119 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_LINE_MAD_FAC_1);
120
121 value = ISP2X_PACK_4BYTE(arg->pg_fac_1_g, arg->pg_fac_1_rb, 0, 0);
122 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_PG_FAC_1);
123 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_PG_FAC_1);
124
125 value = ISP2X_PACK_4BYTE(arg->rnd_thr_1_g, arg->rnd_thr_1_rb, 0, 0);
126 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_RND_THRESH_1);
127 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_RND_THRESH_1);
128
129 value = ISP2X_PACK_4BYTE(arg->rg_fac_1_g, arg->rg_fac_1_rb, 0, 0);
130 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_RG_FAC_1);
131 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_RG_FAC_1);
132
133 value = ISP2X_PACK_4BYTE(arg->line_thr_2_g, arg->line_thr_2_rb,
134 arg->sw_mindis2_g, arg->sw_mindis2_rb);
135 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_LINE_THRESH_2);
136 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_LINE_THRESH_2);
137
138 value = ISP2X_PACK_4BYTE(arg->line_mad_fac_2_g, arg->line_mad_fac_2_rb,
139 arg->sw_dis_scale_max2, arg->sw_dis_scale_min2);
140 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_LINE_MAD_FAC_2);
141 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_LINE_MAD_FAC_2);
142
143 value = ISP2X_PACK_4BYTE(arg->pg_fac_2_g, arg->pg_fac_2_rb, 0, 0);
144 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_PG_FAC_2);
145 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_PG_FAC_2);
146
147 value = ISP2X_PACK_4BYTE(arg->rnd_thr_2_g, arg->rnd_thr_2_rb, 0, 0);
148 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_RND_THRESH_2);
149 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_RND_THRESH_2);
150
151 value = ISP2X_PACK_4BYTE(arg->rg_fac_2_g, arg->rg_fac_2_rb, 0, 0);
152 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_RG_FAC_2);
153 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_RG_FAC_2);
154
155 value = ISP2X_PACK_4BYTE(arg->line_thr_3_g, arg->line_thr_3_rb,
156 arg->sw_mindis3_g, arg->sw_mindis3_rb);
157 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_LINE_THRESH_3);
158 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_LINE_THRESH_3);
159
160 value = ISP2X_PACK_4BYTE(arg->line_mad_fac_3_g, arg->line_mad_fac_3_rb,
161 arg->sw_dis_scale_max3, arg->sw_dis_scale_min3);
162 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_LINE_MAD_FAC_3);
163 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_LINE_MAD_FAC_3);
164
165 value = ISP2X_PACK_4BYTE(arg->pg_fac_3_g, arg->pg_fac_3_rb, 0, 0);
166 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_PG_FAC_3);
167 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_PG_FAC_3);
168
169 value = ISP2X_PACK_4BYTE(arg->rnd_thr_3_g, arg->rnd_thr_3_rb, 0, 0);
170 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_RND_THRESH_3);
171 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_RND_THRESH_3);
172
173 value = ISP2X_PACK_4BYTE(arg->rg_fac_3_g, arg->rg_fac_3_rb, 0, 0);
174 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_RG_FAC_3);
175 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_RG_FAC_3);
176
177 value = (arg->ro_lim_3_rb & 0x03) << 10 |
178 (arg->ro_lim_3_g & 0x03) << 8 |
179 (arg->ro_lim_2_rb & 0x03) << 6 |
180 (arg->ro_lim_2_g & 0x03) << 4 |
181 (arg->ro_lim_1_rb & 0x03) << 2 |
182 (arg->ro_lim_1_g & 0x03);
183 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_RO_LIMITS);
184 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_RO_LIMITS);
185
186 value = (arg->rnd_offs_3_rb & 0x03) << 10 |
187 (arg->rnd_offs_3_g & 0x03) << 8 |
188 (arg->rnd_offs_2_rb & 0x03) << 6 |
189 (arg->rnd_offs_2_g & 0x03) << 4 |
190 (arg->rnd_offs_1_rb & 0x03) << 2 |
191 (arg->rnd_offs_1_g & 0x03);
192 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_RND_OFFS);
193 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_RND_OFFS);
194
195 value = (arg->bpt_rb_3x3 & 0x01) << 11 |
196 (arg->bpt_g_3x3 & 0x01) << 10 |
197 (arg->bpt_incl_rb_center & 0x01) << 9 |
198 (arg->bpt_incl_green_center & 0x01) << 8 |
199 (arg->bpt_use_fix_set & 0x01) << 7 |
200 (arg->bpt_use_set_3 & 0x01) << 6 |
201 (arg->bpt_use_set_2 & 0x01) << 5 |
202 (arg->bpt_use_set_1 & 0x01) << 4 |
203 (arg->bpt_cor_en & 0x01) << 1 |
204 (arg->bpt_det_en & 0x01);
205 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_BPT_CTRL);
206 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_BPT_CTRL);
207
208 rkisp_iowrite32(params_vdev, arg->bp_number, ISP_DPCC0_BPT_NUMBER);
209 rkisp_iowrite32(params_vdev, arg->bp_number, ISP_DPCC1_BPT_NUMBER);
210 rkisp_iowrite32(params_vdev, arg->bp_table_addr, ISP_DPCC0_BPT_ADDR);
211 rkisp_iowrite32(params_vdev, arg->bp_table_addr, ISP_DPCC1_BPT_ADDR);
212
213 value = ISP2X_PACK_2SHORT(arg->bpt_h_addr, arg->bpt_v_addr);
214 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_BPT_DATA);
215 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_BPT_DATA);
216
217 rkisp_iowrite32(params_vdev, arg->bp_cnt, ISP_DPCC0_BP_CNT);
218 rkisp_iowrite32(params_vdev, arg->bp_cnt, ISP_DPCC1_BP_CNT);
219
220 rkisp_iowrite32(params_vdev, arg->sw_pdaf_en, ISP_DPCC0_PDAF_EN);
221 rkisp_iowrite32(params_vdev, arg->sw_pdaf_en, ISP_DPCC1_PDAF_EN);
222
223 value = 0;
224 for (i = 0; i < ISP2X_DPCC_PDAF_POINT_NUM; i++)
225 value |= (arg->pdaf_point_en[i] & 0x01) << i;
226 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_PDAF_POINT_EN);
227 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_PDAF_POINT_EN);
228
229 value = ISP2X_PACK_2SHORT(arg->pdaf_offsetx, arg->pdaf_offsety);
230 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_PDAF_OFFSET);
231 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_PDAF_OFFSET);
232
233 value = ISP2X_PACK_2SHORT(arg->pdaf_wrapx, arg->pdaf_wrapy);
234 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_PDAF_WRAP);
235 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_PDAF_WRAP);
236
237 value = ISP2X_PACK_2SHORT(arg->pdaf_wrapx_num, arg->pdaf_wrapy_num);
238 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_PDAF_SCOPE);
239 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_PDAF_SCOPE);
240
241 for (i = 0; i < ISP2X_DPCC_PDAF_POINT_NUM / 2; i++) {
242 value = ISP2X_PACK_4BYTE(arg->point[2 * i].x, arg->point[2 * i].y,
243 arg->point[2 * i + 1].x, arg->point[2 * i + 1].y);
244 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_PDAF_POINT_0 + 4 * i);
245 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_PDAF_POINT_0 + 4 * i);
246 }
247
248 rkisp_iowrite32(params_vdev, arg->pdaf_forward_med, ISP_DPCC0_PDAF_FORWARD_MED);
249 rkisp_iowrite32(params_vdev, arg->pdaf_forward_med, ISP_DPCC1_PDAF_FORWARD_MED);
250 }
251
252 static void
isp_dpcc_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)253 isp_dpcc_enable(struct rkisp_isp_params_vdev *params_vdev,
254 bool en)
255 {
256 u32 value;
257
258 value = rkisp_ioread32(params_vdev, ISP_DPCC0_MODE);
259 value &= ~ISP_DPCC_EN;
260
261 if (en)
262 value |= ISP_DPCC_EN;
263 rkisp_iowrite32(params_vdev, value, ISP_DPCC0_MODE);
264 rkisp_iowrite32(params_vdev, value, ISP_DPCC1_MODE);
265 }
266
267 static void
isp_bls_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp21_bls_cfg * arg)268 isp_bls_config(struct rkisp_isp_params_vdev *params_vdev,
269 const struct isp21_bls_cfg *arg)
270 {
271 const struct isp2x_bls_fixed_val *pval;
272 u32 new_control, value;
273
274 new_control = rkisp_ioread32(params_vdev, ISP_BLS_CTRL);
275 new_control &= ISP_BLS_ENA;
276
277 pval = &arg->bls1_val;
278 if (arg->bls1_en) {
279 new_control |= ISP_BLS_BLS1_EN;
280
281 switch (params_vdev->raw_type) {
282 case RAW_BGGR:
283 rkisp_iowrite32(params_vdev,
284 pval->r, ISP_BLS1_D_FIXED);
285 rkisp_iowrite32(params_vdev,
286 pval->gr, ISP_BLS1_C_FIXED);
287 rkisp_iowrite32(params_vdev,
288 pval->gb, ISP_BLS1_B_FIXED);
289 rkisp_iowrite32(params_vdev,
290 pval->b, ISP_BLS1_A_FIXED);
291 break;
292 case RAW_GBRG:
293 rkisp_iowrite32(params_vdev,
294 pval->r, ISP_BLS1_C_FIXED);
295 rkisp_iowrite32(params_vdev,
296 pval->gr, ISP_BLS1_D_FIXED);
297 rkisp_iowrite32(params_vdev,
298 pval->gb, ISP_BLS1_A_FIXED);
299 rkisp_iowrite32(params_vdev,
300 pval->b, ISP_BLS1_B_FIXED);
301 break;
302 case RAW_GRBG:
303 rkisp_iowrite32(params_vdev,
304 pval->r, ISP_BLS1_B_FIXED);
305 rkisp_iowrite32(params_vdev,
306 pval->gr, ISP_BLS1_A_FIXED);
307 rkisp_iowrite32(params_vdev,
308 pval->gb, ISP_BLS1_D_FIXED);
309 rkisp_iowrite32(params_vdev,
310 pval->b, ISP_BLS1_C_FIXED);
311 break;
312 case RAW_RGGB:
313 rkisp_iowrite32(params_vdev,
314 pval->r, ISP_BLS1_A_FIXED);
315 rkisp_iowrite32(params_vdev,
316 pval->gr, ISP_BLS1_B_FIXED);
317 rkisp_iowrite32(params_vdev,
318 pval->gb, ISP_BLS1_C_FIXED);
319 rkisp_iowrite32(params_vdev,
320 pval->b, ISP_BLS1_D_FIXED);
321 break;
322 default:
323 break;
324 }
325 }
326
327 /* fixed subtraction values */
328 pval = &arg->fixed_val;
329 if (!arg->enable_auto) {
330 switch (params_vdev->raw_type) {
331 case RAW_BGGR:
332 rkisp_iowrite32(params_vdev,
333 pval->r, ISP_BLS_D_FIXED);
334 rkisp_iowrite32(params_vdev,
335 pval->gr, ISP_BLS_C_FIXED);
336 rkisp_iowrite32(params_vdev,
337 pval->gb, ISP_BLS_B_FIXED);
338 rkisp_iowrite32(params_vdev,
339 pval->b, ISP_BLS_A_FIXED);
340 break;
341 case RAW_GBRG:
342 rkisp_iowrite32(params_vdev,
343 pval->r, ISP_BLS_C_FIXED);
344 rkisp_iowrite32(params_vdev,
345 pval->gr, ISP_BLS_D_FIXED);
346 rkisp_iowrite32(params_vdev,
347 pval->gb, ISP_BLS_A_FIXED);
348 rkisp_iowrite32(params_vdev,
349 pval->b, ISP_BLS_B_FIXED);
350 break;
351 case RAW_GRBG:
352 rkisp_iowrite32(params_vdev,
353 pval->r, ISP_BLS_B_FIXED);
354 rkisp_iowrite32(params_vdev,
355 pval->gr, ISP_BLS_A_FIXED);
356 rkisp_iowrite32(params_vdev,
357 pval->gb, ISP_BLS_D_FIXED);
358 rkisp_iowrite32(params_vdev,
359 pval->b, ISP_BLS_C_FIXED);
360 break;
361 case RAW_RGGB:
362 rkisp_iowrite32(params_vdev,
363 pval->r, ISP_BLS_A_FIXED);
364 rkisp_iowrite32(params_vdev,
365 pval->gr, ISP_BLS_B_FIXED);
366 rkisp_iowrite32(params_vdev,
367 pval->gb, ISP_BLS_C_FIXED);
368 rkisp_iowrite32(params_vdev,
369 pval->b, ISP_BLS_D_FIXED);
370 break;
371 default:
372 break;
373 }
374 } else {
375 if (arg->en_windows & BIT(1)) {
376 rkisp_iowrite32(params_vdev, arg->bls_window2.h_offs,
377 ISP_BLS_H2_START);
378 value = arg->bls_window2.h_offs + arg->bls_window2.h_size;
379 rkisp_iowrite32(params_vdev, value, ISP_BLS_H2_STOP);
380 rkisp_iowrite32(params_vdev, arg->bls_window2.v_offs,
381 ISP_BLS_V2_START);
382 value = arg->bls_window2.v_offs + arg->bls_window2.v_size;
383 rkisp_iowrite32(params_vdev, value, ISP_BLS_V2_STOP);
384 new_control |= ISP_BLS_WINDOW_2;
385 }
386
387 if (arg->en_windows & BIT(0)) {
388 rkisp_iowrite32(params_vdev, arg->bls_window1.h_offs,
389 ISP_BLS_H1_START);
390 value = arg->bls_window1.h_offs + arg->bls_window1.h_size;
391 rkisp_iowrite32(params_vdev, value, ISP_BLS_H1_STOP);
392 rkisp_iowrite32(params_vdev, arg->bls_window1.v_offs,
393 ISP_BLS_V1_START);
394 value = arg->bls_window1.v_offs + arg->bls_window1.v_size;
395 rkisp_iowrite32(params_vdev, value, ISP_BLS_V1_STOP);
396 new_control |= ISP_BLS_WINDOW_1;
397 }
398
399 rkisp_iowrite32(params_vdev, arg->bls_samples,
400 ISP_BLS_SAMPLES);
401
402 new_control |= ISP_BLS_MODE_MEASURED;
403 }
404 rkisp_iowrite32(params_vdev, new_control, ISP_BLS_CTRL);
405 }
406
407 static void
isp_bls_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)408 isp_bls_enable(struct rkisp_isp_params_vdev *params_vdev,
409 bool en)
410 {
411 u32 new_control;
412
413 new_control = rkisp_ioread32(params_vdev, ISP_BLS_CTRL);
414 if (en)
415 new_control |= ISP_BLS_ENA;
416 else
417 new_control &= ~ISP_BLS_ENA;
418 rkisp_iowrite32(params_vdev, new_control, ISP_BLS_CTRL);
419 }
420
421 static void
isp_sdg_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_sdg_cfg * arg)422 isp_sdg_config(struct rkisp_isp_params_vdev *params_vdev,
423 const struct isp2x_sdg_cfg *arg)
424 {
425 int i;
426
427 rkisp_iowrite32(params_vdev,
428 arg->xa_pnts.gamma_dx0, ISP_GAMMA_DX_LO);
429 rkisp_iowrite32(params_vdev,
430 arg->xa_pnts.gamma_dx1, ISP_GAMMA_DX_HI);
431
432 for (i = 0; i < ISP2X_DEGAMMA_CURVE_SIZE; i++) {
433 rkisp_iowrite32(params_vdev, arg->curve_r.gamma_y[i],
434 ISP_GAMMA_R_Y_0 + i * 4);
435 rkisp_iowrite32(params_vdev, arg->curve_g.gamma_y[i],
436 ISP_GAMMA_G_Y_0 + i * 4);
437 rkisp_iowrite32(params_vdev, arg->curve_b.gamma_y[i],
438 ISP_GAMMA_B_Y_0 + i * 4);
439 }
440 }
441
442 static void
isp_sdg_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)443 isp_sdg_enable(struct rkisp_isp_params_vdev *params_vdev,
444 bool en)
445 {
446 if (en) {
447 isp_param_set_bits(params_vdev,
448 CIF_ISP_CTRL,
449 CIF_ISP_CTRL_ISP_GAMMA_IN_ENA);
450 } else {
451 isp_param_clear_bits(params_vdev,
452 CIF_ISP_CTRL,
453 CIF_ISP_CTRL_ISP_GAMMA_IN_ENA);
454 }
455 }
456
457 static void __maybe_unused
isp_lsc_matrix_cfg_sram(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_lsc_cfg * pconfig,bool is_check)458 isp_lsc_matrix_cfg_sram(struct rkisp_isp_params_vdev *params_vdev,
459 const struct isp2x_lsc_cfg *pconfig, bool is_check)
460 {
461 int i, j;
462 unsigned int sram_addr;
463 unsigned int data;
464
465 if (is_check &&
466 !(rkisp_ioread32(params_vdev, ISP_LSC_CTRL) & ISP_LSC_EN))
467 return;
468
469 /* CIF_ISP_LSC_TABLE_ADDRESS_153 = ( 17 * 18 ) >> 1 */
470 sram_addr = CIF_ISP_LSC_TABLE_ADDRESS_0;
471 rkisp_write(params_vdev->dev, ISP_LSC_R_TABLE_ADDR, sram_addr, true);
472 rkisp_write(params_vdev->dev, ISP_LSC_GR_TABLE_ADDR, sram_addr, true);
473 rkisp_write(params_vdev->dev, ISP_LSC_GB_TABLE_ADDR, sram_addr, true);
474 rkisp_write(params_vdev->dev, ISP_LSC_B_TABLE_ADDR, sram_addr, true);
475
476 /* program data tables (table size is 9 * 17 = 153) */
477 for (i = 0; i < CIF_ISP_LSC_SECTORS_MAX * CIF_ISP_LSC_SECTORS_MAX;
478 i += CIF_ISP_LSC_SECTORS_MAX) {
479 /*
480 * 17 sectors with 2 values in one DWORD = 9
481 * DWORDs (2nd value of last DWORD unused)
482 */
483 for (j = 0; j < CIF_ISP_LSC_SECTORS_MAX - 1; j += 2) {
484 data = ISP_ISP_LSC_TABLE_DATA(pconfig->r_data_tbl[i + j],
485 pconfig->r_data_tbl[i + j + 1]);
486 rkisp_write(params_vdev->dev, ISP_LSC_R_TABLE_DATA, data, true);
487
488 data = ISP_ISP_LSC_TABLE_DATA(pconfig->gr_data_tbl[i + j],
489 pconfig->gr_data_tbl[i + j + 1]);
490 rkisp_write(params_vdev->dev, ISP_LSC_GR_TABLE_DATA, data, true);
491
492 data = ISP_ISP_LSC_TABLE_DATA(pconfig->gb_data_tbl[i + j],
493 pconfig->gb_data_tbl[i + j + 1]);
494 rkisp_write(params_vdev->dev, ISP_LSC_GB_TABLE_DATA, data, true);
495
496 data = ISP_ISP_LSC_TABLE_DATA(pconfig->b_data_tbl[i + j],
497 pconfig->b_data_tbl[i + j + 1]);
498 rkisp_write(params_vdev->dev, ISP_LSC_B_TABLE_DATA, data, true);
499 }
500
501 data = ISP_ISP_LSC_TABLE_DATA(pconfig->r_data_tbl[i + j], 0);
502 rkisp_write(params_vdev->dev, ISP_LSC_R_TABLE_DATA, data, true);
503
504 data = ISP_ISP_LSC_TABLE_DATA(pconfig->gr_data_tbl[i + j], 0);
505 rkisp_write(params_vdev->dev, ISP_LSC_GR_TABLE_DATA, data, true);
506
507 data = ISP_ISP_LSC_TABLE_DATA(pconfig->gb_data_tbl[i + j], 0);
508 rkisp_write(params_vdev->dev, ISP_LSC_GB_TABLE_DATA, data, true);
509
510 data = ISP_ISP_LSC_TABLE_DATA(pconfig->b_data_tbl[i + j], 0);
511 rkisp_write(params_vdev->dev, ISP_LSC_B_TABLE_DATA, data, true);
512 }
513 }
514
515 static void __maybe_unused
isp_lsc_matrix_cfg_ddr(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_lsc_cfg * pconfig)516 isp_lsc_matrix_cfg_ddr(struct rkisp_isp_params_vdev *params_vdev,
517 const struct isp2x_lsc_cfg *pconfig)
518 {
519 struct rkisp_isp_params_val_v21 *priv_val;
520 u32 data, buf_idx, *vaddr[4], index[4];
521 void *buf_vaddr;
522 int i, j;
523
524 memset(&index[0], 0, sizeof(index));
525 priv_val = (struct rkisp_isp_params_val_v21 *)params_vdev->priv_val;
526 buf_idx = (priv_val->buf_lsclut_idx++) % RKISP_PARAM_LSC_LUT_BUF_NUM;
527 buf_vaddr = priv_val->buf_lsclut[buf_idx].vaddr;
528
529 vaddr[0] = buf_vaddr;
530 vaddr[1] = buf_vaddr + RKISP_PARAM_LSC_LUT_TBL_SIZE;
531 vaddr[2] = buf_vaddr + RKISP_PARAM_LSC_LUT_TBL_SIZE * 2;
532 vaddr[3] = buf_vaddr + RKISP_PARAM_LSC_LUT_TBL_SIZE * 3;
533
534 /* program data tables (table size is 9 * 17 = 153) */
535 for (i = 0; i < CIF_ISP_LSC_SECTORS_MAX * CIF_ISP_LSC_SECTORS_MAX;
536 i += CIF_ISP_LSC_SECTORS_MAX) {
537 /*
538 * 17 sectors with 2 values in one DWORD = 9
539 * DWORDs (2nd value of last DWORD unused)
540 */
541 for (j = 0; j < CIF_ISP_LSC_SECTORS_MAX - 1; j += 2) {
542 data = ISP_ISP_LSC_TABLE_DATA(
543 pconfig->r_data_tbl[i + j],
544 pconfig->r_data_tbl[i + j + 1]);
545 vaddr[0][index[0]++] = data;
546
547 data = ISP_ISP_LSC_TABLE_DATA(
548 pconfig->gr_data_tbl[i + j],
549 pconfig->gr_data_tbl[i + j + 1]);
550 vaddr[1][index[1]++] = data;
551
552 data = ISP_ISP_LSC_TABLE_DATA(
553 pconfig->b_data_tbl[i + j],
554 pconfig->b_data_tbl[i + j + 1]);
555 vaddr[2][index[2]++] = data;
556
557 data = ISP_ISP_LSC_TABLE_DATA(
558 pconfig->gb_data_tbl[i + j],
559 pconfig->gb_data_tbl[i + j + 1]);
560 vaddr[3][index[3]++] = data;
561 }
562
563 data = ISP_ISP_LSC_TABLE_DATA(
564 pconfig->r_data_tbl[i + j],
565 0);
566 vaddr[0][index[0]++] = data;
567
568 data = ISP_ISP_LSC_TABLE_DATA(
569 pconfig->gr_data_tbl[i + j],
570 0);
571 vaddr[1][index[1]++] = data;
572
573 data = ISP_ISP_LSC_TABLE_DATA(
574 pconfig->b_data_tbl[i + j],
575 0);
576 vaddr[2][index[2]++] = data;
577
578 data = ISP_ISP_LSC_TABLE_DATA(
579 pconfig->gb_data_tbl[i + j],
580 0);
581 vaddr[3][index[3]++] = data;
582 }
583 rkisp_prepare_buffer(params_vdev->dev, &priv_val->buf_lsclut[buf_idx]);
584 data = priv_val->buf_lsclut[buf_idx].dma_addr;
585 rkisp_iowrite32(params_vdev, data, MI_LUT_LSC_RD_BASE);
586 rkisp_iowrite32(params_vdev, RKISP_PARAM_LSC_LUT_BUF_SIZE, MI_LUT_LSC_RD_WSIZE);
587 }
588
589 static void
isp_lsc_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_lsc_cfg * arg)590 isp_lsc_config(struct rkisp_isp_params_vdev *params_vdev,
591 const struct isp2x_lsc_cfg *arg)
592 {
593 struct isp21_isp_params_cfg *params_rec = params_vdev->isp21_params;
594 struct rkisp_device *dev = params_vdev->dev;
595 unsigned int data;
596 u32 lsc_ctrl;
597 int i;
598
599 /* To config must be off , store the current status firstly */
600 lsc_ctrl = rkisp_ioread32(params_vdev, ISP_LSC_CTRL);
601 isp_param_clear_bits(params_vdev, ISP_LSC_CTRL, ISP_LSC_EN);
602 /* online mode lsc lut load from ddr quick for some sensor VB short
603 * readback mode lsc lut AHB config to sram, once for single device,
604 * need record to switch for multi-device.
605 */
606 if (!IS_HDR_RDBK(dev->rd_mode))
607 isp_lsc_matrix_cfg_ddr(params_vdev, arg);
608 else if (dev->hw_dev->is_single)
609 isp_lsc_matrix_cfg_sram(params_vdev, arg, false);
610 else
611 params_rec->others.lsc_cfg = *arg;
612
613 for (i = 0; i < 4; i++) {
614 /* program x size tables */
615 data = CIF_ISP_LSC_SECT_SIZE(arg->x_size_tbl[i * 2],
616 arg->x_size_tbl[i * 2 + 1]);
617 rkisp_iowrite32(params_vdev, data,
618 ISP_LSC_XSIZE_01 + i * 4);
619
620 /* program x grad tables */
621 data = CIF_ISP_LSC_SECT_SIZE(arg->x_grad_tbl[i * 2],
622 arg->x_grad_tbl[i * 2 + 1]);
623 rkisp_iowrite32(params_vdev, data,
624 ISP_LSC_XGRAD_01 + i * 4);
625
626 /* program y size tables */
627 data = CIF_ISP_LSC_SECT_SIZE(arg->y_size_tbl[i * 2],
628 arg->y_size_tbl[i * 2 + 1]);
629 rkisp_iowrite32(params_vdev, data,
630 ISP_LSC_YSIZE_01 + i * 4);
631
632 /* program y grad tables */
633 data = CIF_ISP_LSC_SECT_SIZE(arg->y_grad_tbl[i * 2],
634 arg->y_grad_tbl[i * 2 + 1]);
635 rkisp_iowrite32(params_vdev, data,
636 ISP_LSC_YGRAD_01 + i * 4);
637 }
638
639 /* restore the lsc ctrl status */
640 if (lsc_ctrl & ISP_LSC_EN) {
641 if (!IS_HDR_RDBK(dev->rd_mode))
642 lsc_ctrl |= ISP_LSC_LUT_EN;
643 isp_param_set_bits(params_vdev, ISP_LSC_CTRL, lsc_ctrl);
644 } else {
645 isp_param_clear_bits(params_vdev, ISP_LSC_CTRL, ISP_LSC_EN);
646 }
647 }
648
649 static void
isp_lsc_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)650 isp_lsc_enable(struct rkisp_isp_params_vdev *params_vdev,
651 bool en)
652 {
653 struct rkisp_device *dev = params_vdev->dev;
654 u32 val = ISP_LSC_EN;
655
656 if (!IS_HDR_RDBK(dev->rd_mode))
657 val |= ISP_LSC_LUT_EN;
658
659 if (en)
660 isp_param_set_bits(params_vdev, ISP_LSC_CTRL, val);
661 else
662 isp_param_clear_bits(params_vdev, ISP_LSC_CTRL, ISP_LSC_EN);
663 }
664
665 static void
isp_debayer_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_debayer_cfg * arg)666 isp_debayer_config(struct rkisp_isp_params_vdev *params_vdev,
667 const struct isp2x_debayer_cfg *arg)
668 {
669 u32 value;
670
671 value = rkisp_ioread32(params_vdev, ISP_DEBAYER_CONTROL);
672 value &= ISP_DEBAYER_EN;
673
674 value |= (arg->filter_c_en & 0x01) << 8 |
675 (arg->filter_g_en & 0x01) << 4;
676 rkisp_iowrite32(params_vdev, value, ISP_DEBAYER_CONTROL);
677
678 value = (arg->thed1 & 0x0F) << 12 |
679 (arg->thed0 & 0x0F) << 8 |
680 (arg->dist_scale & 0x0F) << 4 |
681 (arg->max_ratio & 0x07) << 1 |
682 (arg->clip_en & 0x01);
683 rkisp_iowrite32(params_vdev, value, ISP_DEBAYER_G_INTERP);
684
685 value = (arg->filter1_coe5 & 0x0F) << 16 |
686 (arg->filter1_coe4 & 0x0F) << 12 |
687 (arg->filter1_coe3 & 0x0F) << 8 |
688 (arg->filter1_coe2 & 0x0F) << 4 |
689 (arg->filter1_coe1 & 0x0F);
690 rkisp_iowrite32(params_vdev, value, ISP_DEBAYER_G_INTERP_FILTER1);
691
692 value = (arg->filter2_coe5 & 0x0F) << 16 |
693 (arg->filter2_coe4 & 0x0F) << 12 |
694 (arg->filter2_coe3 & 0x0F) << 8 |
695 (arg->filter2_coe2 & 0x0F) << 4 |
696 (arg->filter2_coe1 & 0x0F);
697 rkisp_iowrite32(params_vdev, value, ISP_DEBAYER_G_INTERP_FILTER2);
698
699 value = (arg->hf_offset & 0xFFFF) << 16 |
700 (arg->gain_offset & 0x0F) << 8 |
701 (arg->offset & 0x1F);
702 rkisp_iowrite32(params_vdev, value, ISP_DEBAYER_G_FILTER);
703
704 value = (arg->shift_num & 0x03) << 16 |
705 (arg->order_max & 0x1F) << 8 |
706 (arg->order_min & 0x1F);
707 rkisp_iowrite32(params_vdev, value, ISP_DEBAYER_C_FILTER);
708 }
709
710 static void
isp_debayer_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)711 isp_debayer_enable(struct rkisp_isp_params_vdev *params_vdev,
712 bool en)
713 {
714 if (en)
715 isp_param_set_bits(params_vdev,
716 ISP_DEBAYER_CONTROL,
717 ISP_DEBAYER_EN);
718 else
719 isp_param_clear_bits(params_vdev,
720 ISP_DEBAYER_CONTROL,
721 ISP_DEBAYER_EN);
722 }
723
724 static void
isp_awbgain_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp21_awb_gain_cfg * arg)725 isp_awbgain_config(struct rkisp_isp_params_vdev *params_vdev,
726 const struct isp21_awb_gain_cfg *arg)
727 {
728 struct rkisp_device *dev = params_vdev->dev;
729
730 if (!arg->gain0_red || !arg->gain0_blue ||
731 !arg->gain1_red || !arg->gain1_blue ||
732 !arg->gain2_red || !arg->gain2_blue ||
733 !arg->gain0_green_r || !arg->gain0_green_b ||
734 !arg->gain1_green_r || !arg->gain1_green_b ||
735 !arg->gain2_green_r || !arg->gain2_green_b) {
736 dev_err(dev->dev, "awb gain is zero!\n");
737 return;
738 }
739
740 rkisp_iowrite32(params_vdev,
741 ISP2X_PACK_2SHORT(arg->gain0_green_b, arg->gain0_green_r),
742 ISP21_AWB_GAIN0_G);
743
744 rkisp_iowrite32(params_vdev,
745 ISP2X_PACK_2SHORT(arg->gain0_blue, arg->gain0_red),
746 ISP21_AWB_GAIN0_RB);
747
748 rkisp_iowrite32(params_vdev,
749 ISP2X_PACK_2SHORT(arg->gain1_green_b, arg->gain1_green_r),
750 ISP21_AWB_GAIN1_G);
751
752 rkisp_iowrite32(params_vdev,
753 ISP2X_PACK_2SHORT(arg->gain1_blue, arg->gain1_red),
754 ISP21_AWB_GAIN1_RB);
755
756 rkisp_iowrite32(params_vdev,
757 ISP2X_PACK_2SHORT(arg->gain2_green_b, arg->gain2_green_r),
758 ISP21_AWB_GAIN2_G);
759
760 rkisp_iowrite32(params_vdev,
761 ISP2X_PACK_2SHORT(arg->gain2_blue, arg->gain2_red),
762 ISP21_AWB_GAIN2_RB);
763 }
764
765 static void
isp_awbgain_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)766 isp_awbgain_enable(struct rkisp_isp_params_vdev *params_vdev,
767 bool en)
768 {
769 if (en)
770 isp_param_set_bits(params_vdev, CIF_ISP_CTRL,
771 CIF_ISP_CTRL_ISP_AWB_ENA);
772 else
773 isp_param_clear_bits(params_vdev, CIF_ISP_CTRL,
774 CIF_ISP_CTRL_ISP_AWB_ENA);
775 }
776
777 static void
isp_ccm_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp21_ccm_cfg * arg)778 isp_ccm_config(struct rkisp_isp_params_vdev *params_vdev,
779 const struct isp21_ccm_cfg *arg)
780 {
781 u32 value;
782 u32 i;
783
784 value = rkisp_ioread32(params_vdev, ISP_CCM_CTRL);
785 value &= ISP_CCM_EN;
786
787 value |= (arg->highy_adjust_dis & 0x01) << 1;
788 rkisp_iowrite32(params_vdev, value, ISP_CCM_CTRL);
789
790 value = ISP2X_PACK_2SHORT(arg->coeff0_r, arg->coeff1_r);
791 rkisp_iowrite32(params_vdev, value, ISP_CCM_COEFF0_R);
792
793 value = ISP2X_PACK_2SHORT(arg->coeff2_r, arg->offset_r);
794 rkisp_iowrite32(params_vdev, value, ISP_CCM_COEFF1_R);
795
796 value = ISP2X_PACK_2SHORT(arg->coeff0_g, arg->coeff1_g);
797 rkisp_iowrite32(params_vdev, value, ISP_CCM_COEFF0_G);
798
799 value = ISP2X_PACK_2SHORT(arg->coeff2_g, arg->offset_g);
800 rkisp_iowrite32(params_vdev, value, ISP_CCM_COEFF1_G);
801
802 value = ISP2X_PACK_2SHORT(arg->coeff0_b, arg->coeff1_b);
803 rkisp_iowrite32(params_vdev, value, ISP_CCM_COEFF0_B);
804
805 value = ISP2X_PACK_2SHORT(arg->coeff2_b, arg->offset_b);
806 rkisp_iowrite32(params_vdev, value, ISP_CCM_COEFF1_B);
807
808 value = ISP2X_PACK_2SHORT(arg->coeff0_y, arg->coeff1_y);
809 rkisp_iowrite32(params_vdev, value, ISP_CCM_COEFF0_Y);
810
811 value = ISP2X_PACK_2SHORT(arg->coeff2_y, 0);
812 rkisp_iowrite32(params_vdev, value, ISP_CCM_COEFF1_Y);
813
814 for (i = 0; i < ISP2X_CCM_CURVE_NUM / 2; i++) {
815 value = ISP2X_PACK_2SHORT(arg->alp_y[2 * i], arg->alp_y[2 * i + 1]);
816 rkisp_iowrite32(params_vdev, value, ISP_CCM_ALP_Y0 + 4 * i);
817 }
818 value = ISP2X_PACK_2SHORT(arg->alp_y[2 * i], 0);
819 rkisp_iowrite32(params_vdev, value, ISP_CCM_ALP_Y0 + 4 * i);
820
821 value = arg->bound_bit & 0x0F;
822 rkisp_iowrite32(params_vdev, value, ISP_CCM_BOUND_BIT);
823 }
824
825 static void
isp_ccm_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)826 isp_ccm_enable(struct rkisp_isp_params_vdev *params_vdev,
827 bool en)
828 {
829 if (en)
830 isp_param_set_bits(params_vdev, ISP_CCM_CTRL, ISP_CCM_EN);
831 else
832 isp_param_clear_bits(params_vdev, ISP_CCM_CTRL, ISP_CCM_EN);
833 }
834
835 static void
isp_goc_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_gammaout_cfg * arg)836 isp_goc_config(struct rkisp_isp_params_vdev *params_vdev,
837 const struct isp2x_gammaout_cfg *arg)
838 {
839 int i;
840 u32 value;
841
842 if (arg->equ_segm)
843 isp_param_set_bits(params_vdev, ISP_GAMMA_OUT_CTRL, 0x02);
844 else
845 isp_param_clear_bits(params_vdev, ISP_GAMMA_OUT_CTRL, 0x02);
846
847 rkisp_iowrite32(params_vdev, arg->offset, ISP_GAMMA_OUT_OFFSET);
848 for (i = 0; i < ISP2X_GAMMA_OUT_MAX_SAMPLES / 2; i++) {
849 value = ISP2X_PACK_2SHORT(
850 arg->gamma_y[2 * i],
851 arg->gamma_y[2 * i + 1]);
852 rkisp_iowrite32(params_vdev, value, ISP_GAMMA_OUT_Y0 + i * 4);
853 }
854
855 rkisp_iowrite32(params_vdev, arg->gamma_y[2 * i], ISP_GAMMA_OUT_Y0 + i * 4);
856 }
857
858 static void
isp_goc_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)859 isp_goc_enable(struct rkisp_isp_params_vdev *params_vdev,
860 bool en)
861 {
862 if (en)
863 isp_param_set_bits(params_vdev, ISP_GAMMA_OUT_CTRL, 0x01);
864 else
865 isp_param_clear_bits(params_vdev, ISP_GAMMA_OUT_CTRL, 0x01);
866 }
867
868 static void
isp_cproc_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_cproc_cfg * arg)869 isp_cproc_config(struct rkisp_isp_params_vdev *params_vdev,
870 const struct isp2x_cproc_cfg *arg)
871 {
872 u32 quantization = params_vdev->quantization;
873
874 rkisp_iowrite32(params_vdev, arg->contrast, CPROC_CONTRAST);
875 rkisp_iowrite32(params_vdev, arg->hue, CPROC_HUE);
876 rkisp_iowrite32(params_vdev, arg->sat, CPROC_SATURATION);
877 rkisp_iowrite32(params_vdev, arg->brightness, CPROC_BRIGHTNESS);
878
879 if (quantization != V4L2_QUANTIZATION_FULL_RANGE) {
880 isp_param_clear_bits(params_vdev, CPROC_CTRL,
881 CIF_C_PROC_YOUT_FULL |
882 CIF_C_PROC_YIN_FULL |
883 CIF_C_PROC_COUT_FULL);
884 } else {
885 isp_param_set_bits(params_vdev, CPROC_CTRL,
886 CIF_C_PROC_YOUT_FULL |
887 CIF_C_PROC_YIN_FULL |
888 CIF_C_PROC_COUT_FULL);
889 }
890 }
891
892 static void
isp_cproc_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)893 isp_cproc_enable(struct rkisp_isp_params_vdev *params_vdev,
894 bool en)
895 {
896 if (en)
897 isp_param_set_bits(params_vdev,
898 CPROC_CTRL,
899 CIF_C_PROC_CTR_ENABLE);
900 else
901 isp_param_clear_bits(params_vdev,
902 CPROC_CTRL,
903 CIF_C_PROC_CTR_ENABLE);
904 }
905
906 static void
isp_ie_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_ie_cfg * arg)907 isp_ie_config(struct rkisp_isp_params_vdev *params_vdev,
908 const struct isp2x_ie_cfg *arg)
909 {
910 u32 eff_ctrl;
911
912 eff_ctrl = rkisp_ioread32(params_vdev, CIF_IMG_EFF_CTRL);
913 eff_ctrl &= ~CIF_IMG_EFF_CTRL_MODE_MASK;
914
915 if (params_vdev->quantization == V4L2_QUANTIZATION_FULL_RANGE)
916 eff_ctrl |= CIF_IMG_EFF_CTRL_YCBCR_FULL;
917
918 switch (arg->effect) {
919 case V4L2_COLORFX_SEPIA:
920 eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_SEPIA;
921 break;
922 case V4L2_COLORFX_SET_CBCR:
923 rkisp_iowrite32(params_vdev, arg->eff_tint, CIF_IMG_EFF_TINT);
924 eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_SEPIA;
925 break;
926 /*
927 * Color selection is similar to water color(AQUA):
928 * grayscale + selected color w threshold
929 */
930 case V4L2_COLORFX_AQUA:
931 eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_COLOR_SEL;
932 rkisp_iowrite32(params_vdev, arg->color_sel,
933 CIF_IMG_EFF_COLOR_SEL);
934 break;
935 case V4L2_COLORFX_EMBOSS:
936 eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_EMBOSS;
937 rkisp_iowrite32(params_vdev, arg->eff_mat_1,
938 CIF_IMG_EFF_MAT_1);
939 rkisp_iowrite32(params_vdev, arg->eff_mat_2,
940 CIF_IMG_EFF_MAT_2);
941 rkisp_iowrite32(params_vdev, arg->eff_mat_3,
942 CIF_IMG_EFF_MAT_3);
943 break;
944 case V4L2_COLORFX_SKETCH:
945 eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_SKETCH;
946 rkisp_iowrite32(params_vdev, arg->eff_mat_3,
947 CIF_IMG_EFF_MAT_3);
948 rkisp_iowrite32(params_vdev, arg->eff_mat_4,
949 CIF_IMG_EFF_MAT_4);
950 rkisp_iowrite32(params_vdev, arg->eff_mat_5,
951 CIF_IMG_EFF_MAT_5);
952 break;
953 case V4L2_COLORFX_BW:
954 eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_BLACKWHITE;
955 break;
956 case V4L2_COLORFX_NEGATIVE:
957 eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_NEGATIVE;
958 break;
959 default:
960 break;
961 }
962
963 rkisp_iowrite32(params_vdev, eff_ctrl, CIF_IMG_EFF_CTRL);
964 }
965
966 static void
isp_ie_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)967 isp_ie_enable(struct rkisp_isp_params_vdev *params_vdev,
968 bool en)
969 {
970 if (en) {
971 isp_param_set_bits(params_vdev, CIF_IMG_EFF_CTRL,
972 CIF_IMG_EFF_CTRL_ENABLE);
973 isp_param_set_bits(params_vdev, CIF_IMG_EFF_CTRL,
974 CIF_IMG_EFF_CTRL_CFG_UPD);
975 } else {
976 isp_param_clear_bits(params_vdev, CIF_IMG_EFF_CTRL,
977 CIF_IMG_EFF_CTRL_ENABLE);
978 }
979 }
980
981 static void
isp_rawaf_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawaf_meas_cfg * arg)982 isp_rawaf_config(struct rkisp_isp_params_vdev *params_vdev,
983 const struct isp2x_rawaf_meas_cfg *arg)
984 {
985 u32 i, var;
986 u16 h_size, v_size;
987 u16 h_offs, v_offs;
988 size_t num_of_win = min_t(size_t, ARRAY_SIZE(arg->win),
989 arg->num_afm_win);
990 u32 value = rkisp_ioread32(params_vdev, ISP_RAWAF_CTRL);
991
992 for (i = 0; i < num_of_win; i++) {
993 h_size = arg->win[i].h_size;
994 v_size = arg->win[i].v_size;
995 h_offs = arg->win[i].h_offs < 2 ? 2 : arg->win[i].h_offs;
996 v_offs = arg->win[i].v_offs < 1 ? 1 : arg->win[i].v_offs;
997
998 if (i == 0) {
999 h_size = h_size / 15 * 15;
1000 v_size = v_size / 15 * 15;
1001 }
1002
1003 // (horizontal left row), value must be greater or equal 2
1004 // (vertical top line), value must be greater or equal 1
1005 rkisp_iowrite32(params_vdev,
1006 ISP2X_PACK_2SHORT(v_offs, h_offs),
1007 ISP_RAWAF_LT_A + i * 8);
1008
1009 // value must be smaller than [width of picture -2]
1010 // value must be lower than (number of lines -2)
1011 rkisp_iowrite32(params_vdev,
1012 ISP2X_PACK_2SHORT(v_size, h_size),
1013 ISP_RAWAF_RB_A + i * 8);
1014 }
1015
1016 var = 0;
1017 for (i = 0; i < ISP2X_RAWAF_LINE_NUM; i++) {
1018 if (arg->line_en[i])
1019 var |= ISP2X_RAWAF_INT_LINE0_EN << i;
1020 var |= ISP2X_RAWAF_INT_LINE0_NUM(arg->line_num[i]) << 4 * i;
1021 }
1022 rkisp_iowrite32(params_vdev, var, ISP_RAWAF_INT_LINE);
1023
1024 rkisp_iowrite32(params_vdev,
1025 ISP2X_PACK_4BYTE(arg->gaus_coe_h0, arg->gaus_coe_h1, arg->gaus_coe_h2, 0),
1026 ISP_RAWAF_GAUS_COE);
1027
1028 var = rkisp_ioread32(params_vdev, ISP_RAWAF_THRES);
1029 var &= ~(ISP2X_RAWAF_THRES(0xFFFF));
1030 var |= arg->afm_thres;
1031 rkisp_iowrite32(params_vdev, var, ISP_RAWAF_THRES);
1032
1033 rkisp_iowrite32(params_vdev,
1034 ISP2X_RAWAF_SET_SHIFT_A(arg->lum_var_shift[0], arg->afm_var_shift[0]) |
1035 ISP2X_RAWAF_SET_SHIFT_B(arg->lum_var_shift[1], arg->afm_var_shift[1]),
1036 ISP_RAWAF_VAR_SHIFT);
1037
1038 for (i = 0; i < ISP2X_RAWAF_GAMMA_NUM / 2; i++)
1039 rkisp_iowrite32(params_vdev,
1040 ISP2X_PACK_2SHORT(arg->gamma_y[2 * i], arg->gamma_y[2 * i + 1]),
1041 ISP_RAWAF_GAMMA_Y0 + i * 4);
1042
1043 rkisp_iowrite32(params_vdev,
1044 ISP2X_PACK_2SHORT(arg->gamma_y[16], 0),
1045 ISP_RAWAF_GAMMA_Y8);
1046
1047 value &= ISP2X_RAWAF_ENA;
1048 if (arg->gamma_en)
1049 value |= ISP2X_RAWAF_GAMMA_ENA;
1050 else
1051 value &= ~ISP2X_RAWAF_GAMMA_ENA;
1052 if (arg->gaus_en)
1053 value |= ISP2X_RAWAF_GAUS_ENA;
1054 else
1055 value &= ~ISP2X_RAWAF_GAUS_ENA;
1056 value &= ~ISP2X_REG_WR_MASK;
1057 rkisp_iowrite32(params_vdev, value, ISP_RAWAF_CTRL);
1058
1059 value = rkisp_ioread32(params_vdev, CTRL_VI_ISP_PATH);
1060 value &= ~(ISP2X_ISPPATH_RAWAF_SEL_SET(3));
1061 value |= ISP2X_ISPPATH_RAWAF_SEL_SET(arg->rawaf_sel);
1062 rkisp_iowrite32(params_vdev, value, CTRL_VI_ISP_PATH);
1063 }
1064
1065 static void
isp_rawaf_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)1066 isp_rawaf_enable(struct rkisp_isp_params_vdev *params_vdev,
1067 bool en)
1068 {
1069 u32 afm_ctrl = rkisp_ioread32(params_vdev, ISP_RAWAF_CTRL);
1070
1071 afm_ctrl &= ~ISP2X_REG_WR_MASK;
1072 if (en)
1073 afm_ctrl |= ISP2X_RAWAF_ENA;
1074 else
1075 afm_ctrl &= ~ISP2X_RAWAF_ENA;
1076
1077 rkisp_iowrite32(params_vdev, afm_ctrl, ISP_RAWAF_CTRL);
1078 }
1079
1080 static void
isp_rawaelite_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawaelite_meas_cfg * arg)1081 isp_rawaelite_config(struct rkisp_isp_params_vdev *params_vdev,
1082 const struct isp2x_rawaelite_meas_cfg *arg)
1083 {
1084 struct rkisp_device *ispdev = params_vdev->dev;
1085 struct v4l2_rect *out_crop = &ispdev->isp_sdev.out_crop;
1086 u32 block_hsize, block_vsize, value;
1087 u32 wnd_num_idx = 0;
1088 const u32 ae_wnd_num[] = {
1089 1, 5
1090 };
1091
1092 value = rkisp_ioread32(params_vdev, ISP_RAWAE_LITE_CTRL);
1093 value &= ~(ISP2X_RAWAE_LITE_WNDNUM_SET(0x1));
1094 if (arg->wnd_num) {
1095 value |= ISP2X_RAWAE_LITE_WNDNUM_SET(0x1);
1096 wnd_num_idx = 1;
1097 }
1098 value &= ~ISP2X_REG_WR_MASK;
1099 rkisp_iowrite32(params_vdev, value, ISP_RAWAE_LITE_CTRL);
1100
1101 rkisp_iowrite32(params_vdev,
1102 ISP2X_RAWAE_LITE_V_OFFSET_SET(arg->win.v_offs) |
1103 ISP2X_RAWAE_LITE_H_OFFSET_SET(arg->win.h_offs),
1104 ISP_RAWAE_LITE_OFFSET);
1105
1106 block_hsize = arg->win.h_size / ae_wnd_num[wnd_num_idx];
1107 value = block_hsize * ae_wnd_num[wnd_num_idx] + arg->win.h_offs;
1108 if (value + 1 > out_crop->width)
1109 block_hsize -= 1;
1110 block_vsize = arg->win.v_size / ae_wnd_num[wnd_num_idx];
1111 value = block_vsize * ae_wnd_num[wnd_num_idx] + arg->win.v_offs;
1112 if (value + 2 > out_crop->height)
1113 block_vsize -= 1;
1114 if (block_vsize % 2)
1115 block_vsize -= 1;
1116 rkisp_iowrite32(params_vdev,
1117 ISP2X_RAWAE_LITE_V_SIZE_SET(block_vsize) |
1118 ISP2X_RAWAE_LITE_H_SIZE_SET(block_hsize),
1119 ISP_RAWAE_LITE_BLK_SIZ);
1120
1121 value = rkisp_ioread32(params_vdev, CTRL_VI_ISP_PATH);
1122 value &= ~(ISP2X_ISPPATH_RAWAE_SWAP_SET(3));
1123 value |= ISP2X_ISPPATH_RAWAE_SWAP_SET(arg->rawae_sel);
1124 rkisp_iowrite32(params_vdev, value, CTRL_VI_ISP_PATH);
1125 }
1126
1127 static void
isp_rawaelite_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)1128 isp_rawaelite_enable(struct rkisp_isp_params_vdev *params_vdev,
1129 bool en)
1130 {
1131 u32 exp_ctrl;
1132
1133 exp_ctrl = rkisp_ioread32(params_vdev, ISP_RAWAE_LITE_CTRL);
1134 exp_ctrl &= ~ISP2X_REG_WR_MASK;
1135 if (en)
1136 exp_ctrl |= ISP2X_RAWAE_LITE_ENA;
1137 else
1138 exp_ctrl &= ~ISP2X_RAWAE_LITE_ENA;
1139
1140 rkisp_iowrite32(params_vdev, exp_ctrl, ISP_RAWAE_LITE_CTRL);
1141 }
1142
1143 static void
isp_rawaebig_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawaebig_meas_cfg * arg,u32 blk_no)1144 isp_rawaebig_config(struct rkisp_isp_params_vdev *params_vdev,
1145 const struct isp2x_rawaebig_meas_cfg *arg, u32 blk_no)
1146 {
1147 struct rkisp_device *ispdev = params_vdev->dev;
1148 struct v4l2_rect *out_crop = &ispdev->isp_sdev.out_crop;
1149 u32 block_hsize, block_vsize;
1150 u32 addr, i, value, h_size, v_size;
1151 u32 wnd_num_idx = 0;
1152 const u32 ae_wnd_num[] = {
1153 1, 5, 15, 15
1154 };
1155
1156 switch (blk_no) {
1157 case 0:
1158 addr = RAWAE_BIG1_BASE;
1159 break;
1160 case 1:
1161 addr = RAWAE_BIG2_BASE;
1162 break;
1163 case 2:
1164 addr = RAWAE_BIG3_BASE;
1165 break;
1166 default:
1167 addr = RAWAE_BIG1_BASE;
1168 break;
1169 }
1170
1171 /* avoid to override the old enable value */
1172 value = rkisp_ioread32(params_vdev, addr + RAWAE_BIG_CTRL);
1173 value &= ~(ISP2X_RAWAEBIG_WNDNUM_SET(0x3) |
1174 ISP2X_RAWAEBIG_SUBWIN1_EN |
1175 ISP2X_RAWAEBIG_SUBWIN2_EN |
1176 ISP2X_RAWAEBIG_SUBWIN3_EN |
1177 ISP2X_RAWAEBIG_SUBWIN4_EN |
1178 ISP2X_REG_WR_MASK);
1179
1180 wnd_num_idx = arg->wnd_num;
1181 value |= ISP2X_RAWAEBIG_WNDNUM_SET(wnd_num_idx);
1182
1183 if (arg->subwin_en[0])
1184 value |= ISP2X_RAWAEBIG_SUBWIN1_EN;
1185 if (arg->subwin_en[1])
1186 value |= ISP2X_RAWAEBIG_SUBWIN2_EN;
1187 if (arg->subwin_en[2])
1188 value |= ISP2X_RAWAEBIG_SUBWIN3_EN;
1189 if (arg->subwin_en[3])
1190 value |= ISP2X_RAWAEBIG_SUBWIN4_EN;
1191
1192 rkisp_iowrite32(params_vdev, value, addr + RAWAE_BIG_CTRL);
1193
1194 rkisp_iowrite32(params_vdev,
1195 ISP2X_RAWAEBIG_V_OFFSET_SET(arg->win.v_offs) |
1196 ISP2X_RAWAEBIG_H_OFFSET_SET(arg->win.h_offs),
1197 addr + RAWAE_BIG_OFFSET);
1198
1199 block_hsize = arg->win.h_size / ae_wnd_num[wnd_num_idx];
1200 value = block_hsize * ae_wnd_num[wnd_num_idx] + arg->win.h_offs;
1201 if (value + 1 > out_crop->width)
1202 block_hsize -= 1;
1203 block_vsize = arg->win.v_size / ae_wnd_num[wnd_num_idx];
1204 value = block_vsize * ae_wnd_num[wnd_num_idx] + arg->win.v_offs;
1205 if (value + 2 > out_crop->height)
1206 block_vsize -= 1;
1207 if (block_vsize % 2)
1208 block_vsize -= 1;
1209 rkisp_iowrite32(params_vdev,
1210 ISP2X_RAWAEBIG_V_SIZE_SET(block_vsize) |
1211 ISP2X_RAWAEBIG_H_SIZE_SET(block_hsize),
1212 addr + RAWAE_BIG_BLK_SIZE);
1213
1214 for (i = 0; i < ISP2X_RAWAEBIG_SUBWIN_NUM; i++) {
1215 rkisp_iowrite32(params_vdev,
1216 ISP2X_RAWAEBIG_SUBWIN_V_OFFSET_SET(arg->subwin[i].v_offs) |
1217 ISP2X_RAWAEBIG_SUBWIN_H_OFFSET_SET(arg->subwin[i].h_offs),
1218 addr + RAWAE_BIG_WND1_OFFSET + 8 * i);
1219
1220 v_size = arg->subwin[i].v_size + arg->subwin[i].v_offs;
1221 h_size = arg->subwin[i].h_size + arg->subwin[i].h_offs;
1222 rkisp_iowrite32(params_vdev,
1223 ISP2X_RAWAEBIG_SUBWIN_V_SIZE_SET(v_size) |
1224 ISP2X_RAWAEBIG_SUBWIN_H_SIZE_SET(h_size),
1225 addr + RAWAE_BIG_WND1_SIZE + 8 * i);
1226 }
1227
1228 if (blk_no == 0) {
1229 value = rkisp_ioread32(params_vdev, CTRL_VI_ISP_PATH);
1230 value &= ~(ISP2X_ISPPATH_RAWAE_SEL_SET(3));
1231 value |= ISP2X_ISPPATH_RAWAE_SEL_SET(arg->rawae_sel);
1232 rkisp_iowrite32(params_vdev, value, CTRL_VI_ISP_PATH);
1233 } else {
1234 value = rkisp_ioread32(params_vdev, CTRL_VI_ISP_PATH);
1235 value &= ~(ISP2X_ISPPATH_RAWAE_SWAP_SET(3));
1236 value |= ISP2X_ISPPATH_RAWAE_SWAP_SET(arg->rawae_sel);
1237 rkisp_iowrite32(params_vdev, value, CTRL_VI_ISP_PATH);
1238 }
1239 }
1240
1241 static void
isp_rawaebig_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 blk_no)1242 isp_rawaebig_enable(struct rkisp_isp_params_vdev *params_vdev,
1243 bool en, u32 blk_no)
1244 {
1245 u32 exp_ctrl;
1246 u32 addr;
1247
1248 switch (blk_no) {
1249 case 0:
1250 addr = RAWAE_BIG1_BASE;
1251 break;
1252 case 1:
1253 addr = RAWAE_BIG2_BASE;
1254 break;
1255 case 2:
1256 addr = RAWAE_BIG3_BASE;
1257 break;
1258 default:
1259 addr = RAWAE_BIG1_BASE;
1260 break;
1261 }
1262
1263 exp_ctrl = rkisp_ioread32(params_vdev, addr + RAWAE_BIG_CTRL);
1264 exp_ctrl &= ~ISP2X_REG_WR_MASK;
1265 if (en)
1266 exp_ctrl |= ISP2X_RAWAEBIG_ENA;
1267 else
1268 exp_ctrl &= ~ISP2X_RAWAEBIG_ENA;
1269
1270 rkisp_iowrite32(params_vdev, exp_ctrl, addr + RAWAE_BIG_CTRL);
1271 }
1272
1273 static void
isp_rawae1_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawaebig_meas_cfg * arg)1274 isp_rawae1_config(struct rkisp_isp_params_vdev *params_vdev,
1275 const struct isp2x_rawaebig_meas_cfg *arg)
1276 {
1277 isp_rawaebig_config(params_vdev, arg, 1);
1278 }
1279
1280 static void
isp_rawae1_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)1281 isp_rawae1_enable(struct rkisp_isp_params_vdev *params_vdev,
1282 bool en)
1283 {
1284 isp_rawaebig_enable(params_vdev, en, 1);
1285 }
1286
1287 static void
isp_rawae2_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawaebig_meas_cfg * arg)1288 isp_rawae2_config(struct rkisp_isp_params_vdev *params_vdev,
1289 const struct isp2x_rawaebig_meas_cfg *arg)
1290 {
1291 isp_rawaebig_config(params_vdev, arg, 2);
1292 }
1293
1294 static void
isp_rawae2_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)1295 isp_rawae2_enable(struct rkisp_isp_params_vdev *params_vdev,
1296 bool en)
1297 {
1298 isp_rawaebig_enable(params_vdev, en, 2);
1299 }
1300
1301 static void
isp_rawae3_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawaebig_meas_cfg * arg)1302 isp_rawae3_config(struct rkisp_isp_params_vdev *params_vdev,
1303 const struct isp2x_rawaebig_meas_cfg *arg)
1304 {
1305 isp_rawaebig_config(params_vdev, arg, 0);
1306 }
1307
1308 static void
isp_rawae3_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)1309 isp_rawae3_enable(struct rkisp_isp_params_vdev *params_vdev,
1310 bool en)
1311 {
1312 isp_rawaebig_enable(params_vdev, en, 0);
1313 }
1314
1315 static void
isp_rawawb_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp21_rawawb_meas_cfg * arg)1316 isp_rawawb_config(struct rkisp_isp_params_vdev *params_vdev,
1317 const struct isp21_rawawb_meas_cfg *arg)
1318 {
1319 u32 i, value;
1320
1321 rkisp_iowrite32(params_vdev,
1322 (arg->sw_rawawb_blk_measure_enable & 0x1) |
1323 (arg->sw_rawawb_blk_measure_mode & 0x1) << 1 |
1324 (arg->sw_rawawb_blk_measure_xytype & 0x1) << 2 |
1325 (arg->sw_rawawb_blk_rtdw_measure_en & 0x1) << 3 |
1326 (arg->sw_rawawb_blk_measure_illu_idx & 0x7) << 4 |
1327 (arg->sw_rawawb_blk_with_luma_wei_en & 0x1) << 8,
1328 ISP21_RAWAWB_BLK_CTRL);
1329
1330 rkisp_iowrite32(params_vdev,
1331 ISP2X_PACK_2SHORT(arg->sw_rawawb_h_offs, arg->sw_rawawb_v_offs),
1332 ISP21_RAWAWB_WIN_OFFS);
1333
1334 rkisp_iowrite32(params_vdev,
1335 ISP2X_PACK_2SHORT(arg->sw_rawawb_h_size, arg->sw_rawawb_v_size),
1336 ISP21_RAWAWB_WIN_SIZE);
1337
1338 rkisp_iowrite32(params_vdev,
1339 ISP2X_PACK_2SHORT(arg->sw_rawawb_r_max, arg->sw_rawawb_g_max),
1340 ISP21_RAWAWB_LIMIT_RG_MAX);
1341
1342 rkisp_iowrite32(params_vdev,
1343 ISP2X_PACK_2SHORT(arg->sw_rawawb_b_max, arg->sw_rawawb_y_max),
1344 ISP21_RAWAWB_LIMIT_BY_MAX);
1345
1346 rkisp_iowrite32(params_vdev,
1347 ISP2X_PACK_2SHORT(arg->sw_rawawb_r_min, arg->sw_rawawb_g_min),
1348 ISP21_RAWAWB_LIMIT_RG_MIN);
1349
1350 rkisp_iowrite32(params_vdev,
1351 ISP2X_PACK_2SHORT(arg->sw_rawawb_b_min, arg->sw_rawawb_y_min),
1352 ISP21_RAWAWB_LIMIT_BY_MIN);
1353
1354 rkisp_iowrite32(params_vdev,
1355 (arg->sw_rawawb_wp_luma_wei_en0 & 0x1) |
1356 (arg->sw_rawawb_wp_luma_wei_en1 & 0x1) << 1 |
1357 (arg->sw_rawawb_wp_blk_wei_en0 & 0x1) << 2 |
1358 (arg->sw_rawawb_wp_blk_wei_en1 & 0x1) << 3 |
1359 (arg->sw_rawawb_wp_hist_xytype & 0x1) << 4,
1360 ISP21_RAWAWB_WEIGHT_CURVE_CTRL);
1361
1362 rkisp_iowrite32(params_vdev,
1363 ISP2X_PACK_4BYTE(arg->sw_rawawb_wp_luma_weicurve_y0,
1364 arg->sw_rawawb_wp_luma_weicurve_y1,
1365 arg->sw_rawawb_wp_luma_weicurve_y2,
1366 arg->sw_rawawb_wp_luma_weicurve_y3),
1367 ISP21_RAWAWB_YWEIGHT_CURVE_XCOOR03);
1368
1369 rkisp_iowrite32(params_vdev,
1370 ISP2X_PACK_4BYTE(arg->sw_rawawb_wp_luma_weicurve_y4,
1371 arg->sw_rawawb_wp_luma_weicurve_y5,
1372 arg->sw_rawawb_wp_luma_weicurve_y6,
1373 arg->sw_rawawb_wp_luma_weicurve_y7),
1374 ISP21_RAWAWB_YWEIGHT_CURVE_XCOOR47);
1375
1376 rkisp_iowrite32(params_vdev,
1377 arg->sw_rawawb_wp_luma_weicurve_y8,
1378 ISP21_RAWAWB_YWEIGHT_CURVE_XCOOR8);
1379
1380 rkisp_iowrite32(params_vdev,
1381 ISP2X_PACK_4BYTE(arg->sw_rawawb_wp_luma_weicurve_w0,
1382 arg->sw_rawawb_wp_luma_weicurve_w1,
1383 arg->sw_rawawb_wp_luma_weicurve_w2,
1384 arg->sw_rawawb_wp_luma_weicurve_w3),
1385 ISP21_RAWAWB_YWEIGHT_CURVE_YCOOR03);
1386
1387 rkisp_iowrite32(params_vdev,
1388 ISP2X_PACK_4BYTE(arg->sw_rawawb_wp_luma_weicurve_w4,
1389 arg->sw_rawawb_wp_luma_weicurve_w5,
1390 arg->sw_rawawb_wp_luma_weicurve_w6,
1391 arg->sw_rawawb_wp_luma_weicurve_w7),
1392 ISP21_RAWAWB_YWEIGHT_CURVE_YCOOR47);
1393
1394 rkisp_iowrite32(params_vdev,
1395 ISP2X_PACK_2SHORT(arg->sw_rawawb_wp_luma_weicurve_w8,
1396 arg->sw_rawawb_pre_wbgain_inv_r),
1397 ISP21_RAWAWB_YWEIGHT_CURVE_YCOOR8);
1398
1399 rkisp_iowrite32(params_vdev,
1400 ISP2X_PACK_2SHORT(arg->sw_rawawb_pre_wbgain_inv_g,
1401 arg->sw_rawawb_pre_wbgain_inv_b),
1402 ISP21_RAWAWB_PRE_WBGAIN_INV);
1403
1404 rkisp_iowrite32(params_vdev,
1405 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex0_u_0,
1406 arg->sw_rawawb_vertex0_v_0),
1407 ISP21_RAWAWB_UV_DETC_VERTEX0_0);
1408
1409 rkisp_iowrite32(params_vdev,
1410 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex1_u_0,
1411 arg->sw_rawawb_vertex1_v_0),
1412 ISP21_RAWAWB_UV_DETC_VERTEX1_0);
1413
1414 rkisp_iowrite32(params_vdev,
1415 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex2_u_0,
1416 arg->sw_rawawb_vertex2_v_0),
1417 ISP21_RAWAWB_UV_DETC_VERTEX2_0);
1418
1419 rkisp_iowrite32(params_vdev,
1420 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex3_u_0,
1421 arg->sw_rawawb_vertex3_v_0),
1422 ISP21_RAWAWB_UV_DETC_VERTEX3_0);
1423
1424 rkisp_iowrite32(params_vdev,
1425 arg->sw_rawawb_islope01_0,
1426 ISP21_RAWAWB_UV_DETC_ISLOPE01_0);
1427
1428 rkisp_iowrite32(params_vdev,
1429 arg->sw_rawawb_islope12_0,
1430 ISP21_RAWAWB_UV_DETC_ISLOPE12_0);
1431
1432 rkisp_iowrite32(params_vdev,
1433 arg->sw_rawawb_islope23_0,
1434 ISP21_RAWAWB_UV_DETC_ISLOPE23_0);
1435
1436 rkisp_iowrite32(params_vdev,
1437 arg->sw_rawawb_islope30_0,
1438 ISP21_RAWAWB_UV_DETC_ISLOPE30_0);
1439
1440 rkisp_iowrite32(params_vdev,
1441 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex0_u_1,
1442 arg->sw_rawawb_vertex0_v_1),
1443 ISP21_RAWAWB_UV_DETC_VERTEX0_1);
1444
1445 rkisp_iowrite32(params_vdev,
1446 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex1_u_1,
1447 arg->sw_rawawb_vertex1_v_1),
1448 ISP21_RAWAWB_UV_DETC_VERTEX1_1);
1449
1450 rkisp_iowrite32(params_vdev,
1451 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex2_u_1,
1452 arg->sw_rawawb_vertex2_v_1),
1453 ISP21_RAWAWB_UV_DETC_VERTEX2_1);
1454
1455 rkisp_iowrite32(params_vdev,
1456 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex3_u_1,
1457 arg->sw_rawawb_vertex3_v_1),
1458 ISP21_RAWAWB_UV_DETC_VERTEX3_1);
1459
1460 rkisp_iowrite32(params_vdev,
1461 arg->sw_rawawb_islope01_1,
1462 ISP21_RAWAWB_UV_DETC_ISLOPE01_1);
1463
1464 rkisp_iowrite32(params_vdev,
1465 arg->sw_rawawb_islope12_1,
1466 ISP21_RAWAWB_UV_DETC_ISLOPE12_1);
1467
1468 rkisp_iowrite32(params_vdev,
1469 arg->sw_rawawb_islope23_1,
1470 ISP21_RAWAWB_UV_DETC_ISLOPE23_1);
1471
1472 rkisp_iowrite32(params_vdev,
1473 arg->sw_rawawb_islope30_1,
1474 ISP21_RAWAWB_UV_DETC_ISLOPE30_1);
1475
1476 rkisp_iowrite32(params_vdev,
1477 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex0_u_2,
1478 arg->sw_rawawb_vertex0_v_2),
1479 ISP21_RAWAWB_UV_DETC_VERTEX0_2);
1480
1481 rkisp_iowrite32(params_vdev,
1482 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex1_u_2,
1483 arg->sw_rawawb_vertex1_v_2),
1484 ISP21_RAWAWB_UV_DETC_VERTEX1_2);
1485
1486 rkisp_iowrite32(params_vdev,
1487 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex2_u_2,
1488 arg->sw_rawawb_vertex2_v_2),
1489 ISP21_RAWAWB_UV_DETC_VERTEX2_2);
1490
1491 rkisp_iowrite32(params_vdev,
1492 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex3_u_2,
1493 arg->sw_rawawb_vertex3_v_2),
1494 ISP21_RAWAWB_UV_DETC_VERTEX3_2);
1495
1496 rkisp_iowrite32(params_vdev,
1497 arg->sw_rawawb_islope01_2,
1498 ISP21_RAWAWB_UV_DETC_ISLOPE01_2);
1499
1500 rkisp_iowrite32(params_vdev,
1501 arg->sw_rawawb_islope12_2,
1502 ISP21_RAWAWB_UV_DETC_ISLOPE12_2);
1503
1504 rkisp_iowrite32(params_vdev,
1505 arg->sw_rawawb_islope23_2,
1506 ISP21_RAWAWB_UV_DETC_ISLOPE23_2);
1507
1508 rkisp_iowrite32(params_vdev,
1509 arg->sw_rawawb_islope30_2,
1510 ISP21_RAWAWB_UV_DETC_ISLOPE30_2);
1511
1512 rkisp_iowrite32(params_vdev,
1513 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex0_u_3,
1514 arg->sw_rawawb_vertex0_v_3),
1515 ISP21_RAWAWB_UV_DETC_VERTEX0_3);
1516
1517 rkisp_iowrite32(params_vdev,
1518 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex1_u_3,
1519 arg->sw_rawawb_vertex1_v_3),
1520 ISP21_RAWAWB_UV_DETC_VERTEX1_3);
1521
1522 rkisp_iowrite32(params_vdev,
1523 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex2_u_3,
1524 arg->sw_rawawb_vertex2_v_3),
1525 ISP21_RAWAWB_UV_DETC_VERTEX2_3);
1526
1527 rkisp_iowrite32(params_vdev,
1528 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex3_u_3,
1529 arg->sw_rawawb_vertex3_v_3),
1530 ISP21_RAWAWB_UV_DETC_VERTEX3_3);
1531
1532 rkisp_iowrite32(params_vdev,
1533 arg->sw_rawawb_islope01_3,
1534 ISP21_RAWAWB_UV_DETC_ISLOPE01_3);
1535
1536 rkisp_iowrite32(params_vdev,
1537 arg->sw_rawawb_islope12_3,
1538 ISP21_RAWAWB_UV_DETC_ISLOPE12_3);
1539
1540 rkisp_iowrite32(params_vdev,
1541 arg->sw_rawawb_islope23_3,
1542 ISP21_RAWAWB_UV_DETC_ISLOPE23_3);
1543
1544 rkisp_iowrite32(params_vdev,
1545 arg->sw_rawawb_islope30_3,
1546 ISP21_RAWAWB_UV_DETC_ISLOPE30_3);
1547
1548 rkisp_iowrite32(params_vdev,
1549 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex0_u_4,
1550 arg->sw_rawawb_vertex0_v_4),
1551 ISP21_RAWAWB_UV_DETC_VERTEX0_4);
1552
1553 rkisp_iowrite32(params_vdev,
1554 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex1_u_4,
1555 arg->sw_rawawb_vertex1_v_4),
1556 ISP21_RAWAWB_UV_DETC_VERTEX1_4);
1557
1558 rkisp_iowrite32(params_vdev,
1559 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex2_u_4,
1560 arg->sw_rawawb_vertex2_v_4),
1561 ISP21_RAWAWB_UV_DETC_VERTEX2_4);
1562
1563 rkisp_iowrite32(params_vdev,
1564 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex3_u_4,
1565 arg->sw_rawawb_vertex3_v_4),
1566 ISP21_RAWAWB_UV_DETC_VERTEX3_4);
1567
1568 rkisp_iowrite32(params_vdev,
1569 arg->sw_rawawb_islope01_4,
1570 ISP21_RAWAWB_UV_DETC_ISLOPE01_4);
1571
1572 rkisp_iowrite32(params_vdev,
1573 arg->sw_rawawb_islope12_4,
1574 ISP21_RAWAWB_UV_DETC_ISLOPE12_4);
1575
1576 rkisp_iowrite32(params_vdev,
1577 arg->sw_rawawb_islope23_4,
1578 ISP21_RAWAWB_UV_DETC_ISLOPE23_4);
1579
1580 rkisp_iowrite32(params_vdev,
1581 arg->sw_rawawb_islope30_4,
1582 ISP21_RAWAWB_UV_DETC_ISLOPE30_4);
1583
1584 rkisp_iowrite32(params_vdev,
1585 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex0_u_5,
1586 arg->sw_rawawb_vertex0_v_5),
1587 ISP21_RAWAWB_UV_DETC_VERTEX0_5);
1588
1589 rkisp_iowrite32(params_vdev,
1590 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex1_u_5,
1591 arg->sw_rawawb_vertex1_v_5),
1592 ISP21_RAWAWB_UV_DETC_VERTEX1_5);
1593
1594 rkisp_iowrite32(params_vdev,
1595 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex2_u_5,
1596 arg->sw_rawawb_vertex2_v_5),
1597 ISP21_RAWAWB_UV_DETC_VERTEX2_5);
1598
1599 rkisp_iowrite32(params_vdev,
1600 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex3_u_5,
1601 arg->sw_rawawb_vertex3_v_5),
1602 ISP21_RAWAWB_UV_DETC_VERTEX3_5);
1603
1604 rkisp_iowrite32(params_vdev,
1605 arg->sw_rawawb_islope01_5,
1606 ISP21_RAWAWB_UV_DETC_ISLOPE01_5);
1607
1608 rkisp_iowrite32(params_vdev,
1609 arg->sw_rawawb_islope12_5,
1610 ISP21_RAWAWB_UV_DETC_ISLOPE10_5);
1611
1612 rkisp_iowrite32(params_vdev,
1613 arg->sw_rawawb_islope23_5,
1614 ISP21_RAWAWB_UV_DETC_ISLOPE23_5);
1615
1616 rkisp_iowrite32(params_vdev,
1617 arg->sw_rawawb_islope30_5,
1618 ISP21_RAWAWB_UV_DETC_ISLOPE30_5);
1619
1620 rkisp_iowrite32(params_vdev,
1621 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex0_u_6,
1622 arg->sw_rawawb_vertex0_v_6),
1623 ISP21_RAWAWB_UV_DETC_VERTEX0_6);
1624
1625 rkisp_iowrite32(params_vdev,
1626 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex1_u_6,
1627 arg->sw_rawawb_vertex1_v_6),
1628 ISP21_RAWAWB_UV_DETC_VERTEX1_6);
1629
1630 rkisp_iowrite32(params_vdev,
1631 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex2_u_6,
1632 arg->sw_rawawb_vertex2_v_6),
1633 ISP21_RAWAWB_UV_DETC_VERTEX2_6);
1634
1635 rkisp_iowrite32(params_vdev,
1636 ISP2X_PACK_2SHORT(arg->sw_rawawb_vertex3_u_6,
1637 arg->sw_rawawb_vertex3_v_6),
1638 ISP21_RAWAWB_UV_DETC_VERTEX3_6);
1639
1640 rkisp_iowrite32(params_vdev,
1641 arg->sw_rawawb_islope01_6,
1642 ISP21_RAWAWB_UV_DETC_ISLOPE01_6);
1643
1644 rkisp_iowrite32(params_vdev,
1645 arg->sw_rawawb_islope12_6,
1646 ISP21_RAWAWB_UV_DETC_ISLOPE10_6);
1647
1648 rkisp_iowrite32(params_vdev,
1649 arg->sw_rawawb_islope23_6,
1650 ISP21_RAWAWB_UV_DETC_ISLOPE23_6);
1651
1652 rkisp_iowrite32(params_vdev,
1653 arg->sw_rawawb_islope30_6,
1654 ISP21_RAWAWB_UV_DETC_ISLOPE30_6);
1655
1656
1657 rkisp_iowrite32(params_vdev,
1658 ISP2X_PACK_2SHORT(arg->sw_rawawb_rgb2ryuvmat0_y,
1659 arg->sw_rawawb_rgb2ryuvmat1_y),
1660 ISP21_RAWAWB_YUV_RGB2ROTY_0);
1661
1662 rkisp_iowrite32(params_vdev,
1663 ISP2X_PACK_2SHORT(arg->sw_rawawb_rgb2ryuvmat2_y,
1664 arg->sw_rawawb_rgb2ryuvofs_y),
1665 ISP21_RAWAWB_YUV_RGB2ROTY_1);
1666
1667
1668 rkisp_iowrite32(params_vdev,
1669 ISP2X_PACK_2SHORT(arg->sw_rawawb_rgb2ryuvmat0_u,
1670 arg->sw_rawawb_rgb2ryuvmat1_u),
1671 ISP21_RAWAWB_YUV_RGB2ROTU_0);
1672
1673 rkisp_iowrite32(params_vdev,
1674 ISP2X_PACK_2SHORT(arg->sw_rawawb_rgb2ryuvmat2_u,
1675 arg->sw_rawawb_rgb2ryuvofs_u),
1676 ISP21_RAWAWB_YUV_RGB2ROTU_1);
1677
1678 rkisp_iowrite32(params_vdev,
1679 ISP2X_PACK_2SHORT(arg->sw_rawawb_rgb2ryuvmat0_v,
1680 arg->sw_rawawb_rgb2ryuvmat1_v),
1681 ISP21_RAWAWB_YUV_RGB2ROTV_0);
1682
1683 rkisp_iowrite32(params_vdev,
1684 ISP2X_PACK_2SHORT(arg->sw_rawawb_rgb2ryuvmat2_v,
1685 arg->sw_rawawb_rgb2ryuvofs_v),
1686 ISP21_RAWAWB_YUV_RGB2ROTV_1);
1687
1688 rkisp_iowrite32(params_vdev,
1689 ISP2X_PACK_2SHORT(arg->sw_rawawb_coor_x1_ls0_y,
1690 arg->sw_rawawb_vec_x21_ls0_y),
1691 ISP21_RAWAWB_YUV_X_COOR_Y_0);
1692
1693 rkisp_iowrite32(params_vdev,
1694 ISP2X_PACK_2SHORT(arg->sw_rawawb_coor_x1_ls0_u,
1695 arg->sw_rawawb_vec_x21_ls0_u),
1696 ISP21_RAWAWB_YUV_X_COOR_U_0);
1697
1698 rkisp_iowrite32(params_vdev,
1699 ISP2X_PACK_2SHORT(arg->sw_rawawb_coor_x1_ls0_v,
1700 arg->sw_rawawb_vec_x21_ls0_v),
1701 ISP21_RAWAWB_YUV_X_COOR_V_0);
1702
1703 rkisp_iowrite32(params_vdev,
1704 ISP2X_PACK_4BYTE(arg->sw_rawawb_dis_x1x2_ls0,
1705 0,
1706 arg->sw_rawawb_rotu0_ls0,
1707 arg->sw_rawawb_rotu1_ls0),
1708 ISP21_RAWAWB_YUV_X1X2_DIS_0);
1709
1710 rkisp_iowrite32(params_vdev,
1711 ISP2X_PACK_4BYTE(arg->sw_rawawb_rotu2_ls0,
1712 arg->sw_rawawb_rotu3_ls0,
1713 arg->sw_rawawb_rotu4_ls0,
1714 arg->sw_rawawb_rotu5_ls0),
1715 ISP21_RAWAWB_YUV_INTERP_CURVE_UCOOR_0);
1716
1717 rkisp_iowrite32(params_vdev,
1718 ISP2X_PACK_2SHORT(arg->sw_rawawb_th0_ls0,
1719 arg->sw_rawawb_th1_ls0),
1720 ISP21_RAWAWB_YUV_INTERP_CURVE_TH0_0);
1721
1722 rkisp_iowrite32(params_vdev,
1723 ISP2X_PACK_2SHORT(arg->sw_rawawb_th2_ls0,
1724 arg->sw_rawawb_th3_ls0),
1725 ISP21_RAWAWB_YUV_INTERP_CURVE_TH1_0);
1726
1727 rkisp_iowrite32(params_vdev,
1728 ISP2X_PACK_2SHORT(arg->sw_rawawb_th4_ls0,
1729 arg->sw_rawawb_th5_ls0),
1730 ISP21_RAWAWB_YUV_INTERP_CURVE_TH2_0);
1731
1732 rkisp_iowrite32(params_vdev,
1733 ISP2X_PACK_2SHORT(arg->sw_rawawb_coor_x1_ls1_y,
1734 arg->sw_rawawb_vec_x21_ls1_y),
1735 ISP21_RAWAWB_YUV_X_COOR_Y_1);
1736
1737 rkisp_iowrite32(params_vdev,
1738 ISP2X_PACK_2SHORT(arg->sw_rawawb_coor_x1_ls1_u,
1739 arg->sw_rawawb_vec_x21_ls1_u),
1740 ISP21_RAWAWB_YUV_X_COOR_U_1);
1741
1742 rkisp_iowrite32(params_vdev,
1743 ISP2X_PACK_2SHORT(arg->sw_rawawb_coor_x1_ls1_v,
1744 arg->sw_rawawb_vec_x21_ls1_v),
1745 ISP21_RAWAWB_YUV_X_COOR_V_1);
1746
1747 rkisp_iowrite32(params_vdev,
1748 ISP2X_PACK_4BYTE(arg->sw_rawawb_dis_x1x2_ls1,
1749 0,
1750 arg->sw_rawawb_rotu0_ls1,
1751 arg->sw_rawawb_rotu1_ls1),
1752 ISP21_RAWAWB_YUV_X1X2_DIS_1);
1753
1754 rkisp_iowrite32(params_vdev,
1755 ISP2X_PACK_4BYTE(arg->sw_rawawb_rotu2_ls1,
1756 arg->sw_rawawb_rotu3_ls1,
1757 arg->sw_rawawb_rotu4_ls1,
1758 arg->sw_rawawb_rotu5_ls1),
1759 ISP21_RAWAWB_YUV_INTERP_CURVE_UCOOR_1);
1760
1761 rkisp_iowrite32(params_vdev,
1762 ISP2X_PACK_2SHORT(arg->sw_rawawb_th0_ls1,
1763 arg->sw_rawawb_th1_ls1),
1764 ISP21_RAWAWB_YUV_INTERP_CURVE_TH0_1);
1765
1766 rkisp_iowrite32(params_vdev,
1767 ISP2X_PACK_2SHORT(arg->sw_rawawb_th2_ls1,
1768 arg->sw_rawawb_th3_ls1),
1769 ISP21_RAWAWB_YUV_INTERP_CURVE_TH1_1);
1770
1771 rkisp_iowrite32(params_vdev,
1772 ISP2X_PACK_2SHORT(arg->sw_rawawb_th4_ls1,
1773 arg->sw_rawawb_th5_ls1),
1774 ISP21_RAWAWB_YUV_INTERP_CURVE_TH2_1);
1775
1776 rkisp_iowrite32(params_vdev,
1777 ISP2X_PACK_2SHORT(arg->sw_rawawb_coor_x1_ls2_y,
1778 arg->sw_rawawb_vec_x21_ls2_y),
1779 ISP21_RAWAWB_YUV_X_COOR_Y_2);
1780
1781 rkisp_iowrite32(params_vdev,
1782 ISP2X_PACK_2SHORT(arg->sw_rawawb_coor_x1_ls2_u,
1783 arg->sw_rawawb_vec_x21_ls2_u),
1784 ISP21_RAWAWB_YUV_X_COOR_U_2);
1785
1786 rkisp_iowrite32(params_vdev,
1787 ISP2X_PACK_2SHORT(arg->sw_rawawb_coor_x1_ls2_v,
1788 arg->sw_rawawb_vec_x21_ls2_v),
1789 ISP21_RAWAWB_YUV_X_COOR_V_2);
1790
1791 rkisp_iowrite32(params_vdev,
1792 ISP2X_PACK_4BYTE(arg->sw_rawawb_dis_x1x2_ls2,
1793 0,
1794 arg->sw_rawawb_rotu0_ls2,
1795 arg->sw_rawawb_rotu1_ls2),
1796 ISP21_RAWAWB_YUV_X1X2_DIS_2);
1797
1798 rkisp_iowrite32(params_vdev,
1799 ISP2X_PACK_4BYTE(arg->sw_rawawb_rotu2_ls2,
1800 arg->sw_rawawb_rotu3_ls2,
1801 arg->sw_rawawb_rotu4_ls2,
1802 arg->sw_rawawb_rotu5_ls2),
1803 ISP21_RAWAWB_YUV_INTERP_CURVE_UCOOR_2);
1804
1805 rkisp_iowrite32(params_vdev,
1806 ISP2X_PACK_2SHORT(arg->sw_rawawb_th0_ls2,
1807 arg->sw_rawawb_th1_ls2),
1808 ISP21_RAWAWB_YUV_INTERP_CURVE_TH0_2);
1809
1810 rkisp_iowrite32(params_vdev,
1811 ISP2X_PACK_2SHORT(arg->sw_rawawb_th2_ls2,
1812 arg->sw_rawawb_th3_ls2),
1813 ISP21_RAWAWB_YUV_INTERP_CURVE_TH1_2);
1814
1815 rkisp_iowrite32(params_vdev,
1816 ISP2X_PACK_2SHORT(arg->sw_rawawb_th4_ls2,
1817 arg->sw_rawawb_th5_ls2),
1818 ISP21_RAWAWB_YUV_INTERP_CURVE_TH2_2);
1819
1820 rkisp_iowrite32(params_vdev,
1821 ISP2X_PACK_2SHORT(arg->sw_rawawb_coor_x1_ls3_y,
1822 arg->sw_rawawb_vec_x21_ls3_y),
1823 ISP21_RAWAWB_YUV_X_COOR_Y_3);
1824
1825 rkisp_iowrite32(params_vdev,
1826 ISP2X_PACK_2SHORT(arg->sw_rawawb_coor_x1_ls3_u,
1827 arg->sw_rawawb_vec_x21_ls3_u),
1828 ISP21_RAWAWB_YUV_X_COOR_U_3);
1829
1830 rkisp_iowrite32(params_vdev,
1831 ISP2X_PACK_2SHORT(arg->sw_rawawb_coor_x1_ls3_v,
1832 arg->sw_rawawb_vec_x21_ls3_v),
1833 ISP21_RAWAWB_YUV_X_COOR_V_3);
1834
1835 rkisp_iowrite32(params_vdev,
1836 ISP2X_PACK_4BYTE(arg->sw_rawawb_dis_x1x2_ls3,
1837 0,
1838 arg->sw_rawawb_rotu0_ls3,
1839 arg->sw_rawawb_rotu1_ls3),
1840 ISP21_RAWAWB_YUV_X1X2_DIS_3);
1841
1842 rkisp_iowrite32(params_vdev,
1843 ISP2X_PACK_4BYTE(arg->sw_rawawb_rotu2_ls3,
1844 arg->sw_rawawb_rotu3_ls3,
1845 arg->sw_rawawb_rotu4_ls3,
1846 arg->sw_rawawb_rotu5_ls3),
1847 ISP21_RAWAWB_YUV_INTERP_CURVE_UCOOR_3);
1848
1849 rkisp_iowrite32(params_vdev,
1850 ISP2X_PACK_2SHORT(arg->sw_rawawb_th0_ls3,
1851 arg->sw_rawawb_th1_ls3),
1852 ISP21_RAWAWB_YUV_INTERP_CURVE_TH0_3);
1853
1854 rkisp_iowrite32(params_vdev,
1855 ISP2X_PACK_2SHORT(arg->sw_rawawb_th2_ls3,
1856 arg->sw_rawawb_th3_ls3),
1857 ISP21_RAWAWB_YUV_INTERP_CURVE_TH1_3);
1858
1859 rkisp_iowrite32(params_vdev,
1860 ISP2X_PACK_2SHORT(arg->sw_rawawb_th4_ls3,
1861 arg->sw_rawawb_th5_ls3),
1862 ISP21_RAWAWB_YUV_INTERP_CURVE_TH2_3);
1863
1864 rkisp_iowrite32(params_vdev,
1865 ISP2X_PACK_2SHORT(arg->sw_rawawb_wt0,
1866 arg->sw_rawawb_wt1),
1867 ISP21_RAWAWB_RGB2XY_WT01);
1868
1869 rkisp_iowrite32(params_vdev,
1870 arg->sw_rawawb_wt2,
1871 ISP21_RAWAWB_RGB2XY_WT2);
1872
1873 rkisp_iowrite32(params_vdev,
1874 ISP2X_PACK_2SHORT(arg->sw_rawawb_mat0_x,
1875 arg->sw_rawawb_mat0_y),
1876 ISP21_RAWAWB_RGB2XY_MAT0_XY);
1877
1878 rkisp_iowrite32(params_vdev,
1879 ISP2X_PACK_2SHORT(arg->sw_rawawb_mat1_x,
1880 arg->sw_rawawb_mat1_y),
1881 ISP21_RAWAWB_RGB2XY_MAT1_XY);
1882
1883 rkisp_iowrite32(params_vdev,
1884 ISP2X_PACK_2SHORT(arg->sw_rawawb_mat2_x,
1885 arg->sw_rawawb_mat2_y),
1886 ISP21_RAWAWB_RGB2XY_MAT2_XY);
1887
1888 rkisp_iowrite32(params_vdev,
1889 ISP2X_PACK_2SHORT(arg->sw_rawawb_nor_x0_0,
1890 arg->sw_rawawb_nor_x1_0),
1891 ISP21_RAWAWB_XY_DETC_NOR_X_0);
1892
1893 rkisp_iowrite32(params_vdev,
1894 ISP2X_PACK_2SHORT(arg->sw_rawawb_nor_y0_0,
1895 arg->sw_rawawb_nor_y1_0),
1896 ISP21_RAWAWB_XY_DETC_NOR_Y_0);
1897
1898 rkisp_iowrite32(params_vdev,
1899 ISP2X_PACK_2SHORT(arg->sw_rawawb_big_x0_0,
1900 arg->sw_rawawb_big_x1_0),
1901 ISP21_RAWAWB_XY_DETC_BIG_X_0);
1902
1903 rkisp_iowrite32(params_vdev,
1904 ISP2X_PACK_2SHORT(arg->sw_rawawb_big_y0_0,
1905 arg->sw_rawawb_big_y1_0),
1906 ISP21_RAWAWB_XY_DETC_BIG_Y_0);
1907
1908 rkisp_iowrite32(params_vdev,
1909 ISP2X_PACK_2SHORT(arg->sw_rawawb_nor_x0_1,
1910 arg->sw_rawawb_nor_x1_1),
1911 ISP21_RAWAWB_XY_DETC_NOR_X_1);
1912
1913 rkisp_iowrite32(params_vdev,
1914 ISP2X_PACK_2SHORT(arg->sw_rawawb_nor_y0_1,
1915 arg->sw_rawawb_nor_y1_1),
1916 ISP21_RAWAWB_XY_DETC_NOR_Y_1);
1917
1918 rkisp_iowrite32(params_vdev,
1919 ISP2X_PACK_2SHORT(arg->sw_rawawb_big_x0_1,
1920 arg->sw_rawawb_big_x1_1),
1921 ISP21_RAWAWB_XY_DETC_BIG_X_1);
1922
1923 rkisp_iowrite32(params_vdev,
1924 ISP2X_PACK_2SHORT(arg->sw_rawawb_big_y0_1,
1925 arg->sw_rawawb_big_y1_1),
1926 ISP21_RAWAWB_XY_DETC_BIG_Y_1);
1927
1928 rkisp_iowrite32(params_vdev,
1929 ISP2X_PACK_2SHORT(arg->sw_rawawb_nor_x0_2,
1930 arg->sw_rawawb_nor_x1_2),
1931 ISP21_RAWAWB_XY_DETC_NOR_X_2);
1932
1933 rkisp_iowrite32(params_vdev,
1934 ISP2X_PACK_2SHORT(arg->sw_rawawb_nor_y0_2,
1935 arg->sw_rawawb_nor_y1_2),
1936 ISP21_RAWAWB_XY_DETC_NOR_Y_2);
1937
1938 rkisp_iowrite32(params_vdev,
1939 ISP2X_PACK_2SHORT(arg->sw_rawawb_big_x0_2,
1940 arg->sw_rawawb_big_x1_2),
1941 ISP21_RAWAWB_XY_DETC_BIG_X_2);
1942
1943 rkisp_iowrite32(params_vdev,
1944 ISP2X_PACK_2SHORT(arg->sw_rawawb_big_y0_2,
1945 arg->sw_rawawb_big_y1_2),
1946 ISP21_RAWAWB_XY_DETC_BIG_Y_2);
1947
1948 rkisp_iowrite32(params_vdev,
1949 ISP2X_PACK_2SHORT(arg->sw_rawawb_nor_x0_3,
1950 arg->sw_rawawb_nor_x1_3),
1951 ISP21_RAWAWB_XY_DETC_NOR_X_3);
1952
1953 rkisp_iowrite32(params_vdev,
1954 ISP2X_PACK_2SHORT(arg->sw_rawawb_nor_y0_3,
1955 arg->sw_rawawb_nor_y1_3),
1956 ISP21_RAWAWB_XY_DETC_NOR_Y_3);
1957
1958 rkisp_iowrite32(params_vdev,
1959 ISP2X_PACK_2SHORT(arg->sw_rawawb_big_x0_3,
1960 arg->sw_rawawb_big_x1_3),
1961 ISP21_RAWAWB_XY_DETC_BIG_X_3);
1962
1963 rkisp_iowrite32(params_vdev,
1964 ISP2X_PACK_2SHORT(arg->sw_rawawb_big_y0_3,
1965 arg->sw_rawawb_big_y1_3),
1966 ISP21_RAWAWB_XY_DETC_BIG_Y_3);
1967
1968 rkisp_iowrite32(params_vdev,
1969 ISP2X_PACK_2SHORT(arg->sw_rawawb_nor_x0_4,
1970 arg->sw_rawawb_nor_x1_4),
1971 ISP21_RAWAWB_XY_DETC_NOR_X_4);
1972
1973 rkisp_iowrite32(params_vdev,
1974 ISP2X_PACK_2SHORT(arg->sw_rawawb_nor_y0_4,
1975 arg->sw_rawawb_nor_y1_4),
1976 ISP21_RAWAWB_XY_DETC_NOR_Y_4);
1977
1978 rkisp_iowrite32(params_vdev,
1979 ISP2X_PACK_2SHORT(arg->sw_rawawb_big_x0_4,
1980 arg->sw_rawawb_big_x1_4),
1981 ISP21_RAWAWB_XY_DETC_BIG_X_4);
1982
1983 rkisp_iowrite32(params_vdev,
1984 ISP2X_PACK_2SHORT(arg->sw_rawawb_big_y0_4,
1985 arg->sw_rawawb_big_y1_4),
1986 ISP21_RAWAWB_XY_DETC_BIG_Y_4);
1987
1988 rkisp_iowrite32(params_vdev,
1989 ISP2X_PACK_2SHORT(arg->sw_rawawb_nor_x0_5,
1990 arg->sw_rawawb_nor_x1_5),
1991 ISP21_RAWAWB_XY_DETC_NOR_X_5);
1992
1993 rkisp_iowrite32(params_vdev,
1994 ISP2X_PACK_2SHORT(arg->sw_rawawb_nor_y0_5,
1995 arg->sw_rawawb_nor_y1_5),
1996 ISP21_RAWAWB_XY_DETC_NOR_Y_5);
1997
1998 rkisp_iowrite32(params_vdev,
1999 ISP2X_PACK_2SHORT(arg->sw_rawawb_big_x0_5,
2000 arg->sw_rawawb_big_x1_5),
2001 ISP21_RAWAWB_XY_DETC_BIG_X_5);
2002
2003 rkisp_iowrite32(params_vdev,
2004 ISP2X_PACK_2SHORT(arg->sw_rawawb_big_y0_5,
2005 arg->sw_rawawb_big_y1_5),
2006 ISP21_RAWAWB_XY_DETC_BIG_Y_5);
2007
2008 rkisp_iowrite32(params_vdev,
2009 ISP2X_PACK_2SHORT(arg->sw_rawawb_nor_x0_6,
2010 arg->sw_rawawb_nor_x1_6),
2011 ISP21_RAWAWB_XY_DETC_NOR_X_6);
2012
2013 rkisp_iowrite32(params_vdev,
2014 ISP2X_PACK_2SHORT(arg->sw_rawawb_nor_y0_6,
2015 arg->sw_rawawb_nor_y1_6),
2016 ISP21_RAWAWB_XY_DETC_NOR_Y_6);
2017
2018 rkisp_iowrite32(params_vdev,
2019 ISP2X_PACK_2SHORT(arg->sw_rawawb_big_x0_6,
2020 arg->sw_rawawb_big_x1_6),
2021 ISP21_RAWAWB_XY_DETC_BIG_X_6);
2022
2023 rkisp_iowrite32(params_vdev,
2024 ISP2X_PACK_2SHORT(arg->sw_rawawb_big_y0_6,
2025 arg->sw_rawawb_big_y1_6),
2026 ISP21_RAWAWB_XY_DETC_BIG_Y_6);
2027
2028 rkisp_iowrite32(params_vdev,
2029 (arg->sw_rawawb_exc_wp_region0_excen0 & 0x1) << 0 |
2030 (arg->sw_rawawb_exc_wp_region0_excen1 & 0x1) << 1 |
2031 (arg->sw_rawawb_exc_wp_region0_domain & 0x1) << 3 |
2032 (arg->sw_rawawb_exc_wp_region1_excen0 & 0x1) << 4 |
2033 (arg->sw_rawawb_exc_wp_region1_excen1 & 0x1) << 5 |
2034 (arg->sw_rawawb_exc_wp_region1_domain & 0x1) << 7 |
2035 (arg->sw_rawawb_exc_wp_region2_excen0 & 0x1) << 8 |
2036 (arg->sw_rawawb_exc_wp_region2_excen1 & 0x1) << 9 |
2037 (arg->sw_rawawb_exc_wp_region2_domain & 0x1) << 11 |
2038 (arg->sw_rawawb_exc_wp_region3_excen0 & 0x1) << 12 |
2039 (arg->sw_rawawb_exc_wp_region3_excen1 & 0x1) << 13 |
2040 (arg->sw_rawawb_exc_wp_region3_domain & 0x1) << 15 |
2041 (arg->sw_rawawb_exc_wp_region4_excen0 & 0x1) << 16 |
2042 (arg->sw_rawawb_exc_wp_region4_excen1 & 0x1) << 17 |
2043 (arg->sw_rawawb_exc_wp_region4_domain & 0x1) << 19 |
2044 (arg->sw_rawawb_exc_wp_region5_excen0 & 0x1) << 20 |
2045 (arg->sw_rawawb_exc_wp_region5_excen1 & 0x1) << 21 |
2046 (arg->sw_rawawb_exc_wp_region5_domain & 0x1) << 23 |
2047 (arg->sw_rawawb_exc_wp_region6_excen0 & 0x1) << 24 |
2048 (arg->sw_rawawb_exc_wp_region6_excen1 & 0x1) << 25 |
2049 (arg->sw_rawawb_exc_wp_region6_domain & 0x1) << 27,
2050 ISP21_RAWAWB_MULTIWINDOW_EXC_CTRL);
2051
2052 rkisp_iowrite32(params_vdev,
2053 ISP2X_PACK_2SHORT(arg->sw_rawawb_exc_wp_region0_xu0,
2054 arg->sw_rawawb_exc_wp_region0_xu1),
2055 ISP21_RAWAWB_EXC_WP_REGION0_XU);
2056
2057 rkisp_iowrite32(params_vdev,
2058 ISP2X_PACK_2SHORT(arg->sw_rawawb_exc_wp_region0_yv0,
2059 arg->sw_rawawb_exc_wp_region0_yv1),
2060 ISP21_RAWAWB_EXC_WP_REGION0_YV);
2061
2062 rkisp_iowrite32(params_vdev,
2063 ISP2X_PACK_2SHORT(arg->sw_rawawb_exc_wp_region1_xu0,
2064 arg->sw_rawawb_exc_wp_region1_xu1),
2065 ISP21_RAWAWB_EXC_WP_REGION1_XU);
2066
2067 rkisp_iowrite32(params_vdev,
2068 ISP2X_PACK_2SHORT(arg->sw_rawawb_exc_wp_region1_yv0,
2069 arg->sw_rawawb_exc_wp_region1_yv1),
2070 ISP21_RAWAWB_EXC_WP_REGION1_YV);
2071
2072 rkisp_iowrite32(params_vdev,
2073 ISP2X_PACK_2SHORT(arg->sw_rawawb_exc_wp_region2_xu0,
2074 arg->sw_rawawb_exc_wp_region2_xu1),
2075 ISP21_RAWAWB_EXC_WP_REGION2_XU);
2076
2077 rkisp_iowrite32(params_vdev,
2078 ISP2X_PACK_2SHORT(arg->sw_rawawb_exc_wp_region2_yv0,
2079 arg->sw_rawawb_exc_wp_region2_yv1),
2080 ISP21_RAWAWB_EXC_WP_REGION2_YV);
2081
2082 rkisp_iowrite32(params_vdev,
2083 ISP2X_PACK_2SHORT(arg->sw_rawawb_exc_wp_region3_xu0,
2084 arg->sw_rawawb_exc_wp_region3_xu1),
2085 ISP21_RAWAWB_EXC_WP_REGION3_XU);
2086
2087 rkisp_iowrite32(params_vdev,
2088 ISP2X_PACK_2SHORT(arg->sw_rawawb_exc_wp_region3_yv0,
2089 arg->sw_rawawb_exc_wp_region3_yv1),
2090 ISP21_RAWAWB_EXC_WP_REGION3_YV);
2091
2092 rkisp_iowrite32(params_vdev,
2093 ISP2X_PACK_2SHORT(arg->sw_rawawb_exc_wp_region4_xu0,
2094 arg->sw_rawawb_exc_wp_region4_xu1),
2095 ISP21_RAWAWB_EXC_WP_REGION4_XU);
2096
2097 rkisp_iowrite32(params_vdev,
2098 ISP2X_PACK_2SHORT(arg->sw_rawawb_exc_wp_region4_yv0,
2099 arg->sw_rawawb_exc_wp_region4_yv1),
2100 ISP21_RAWAWB_EXC_WP_REGION4_YV);
2101
2102 rkisp_iowrite32(params_vdev,
2103 ISP2X_PACK_2SHORT(arg->sw_rawawb_exc_wp_region5_xu0,
2104 arg->sw_rawawb_exc_wp_region5_xu1),
2105 ISP21_RAWAWB_EXC_WP_REGION5_XU);
2106
2107 rkisp_iowrite32(params_vdev,
2108 ISP2X_PACK_2SHORT(arg->sw_rawawb_exc_wp_region5_yv0,
2109 arg->sw_rawawb_exc_wp_region5_yv1),
2110 ISP21_RAWAWB_EXC_WP_REGION5_YV);
2111
2112 rkisp_iowrite32(params_vdev,
2113 ISP2X_PACK_2SHORT(arg->sw_rawawb_exc_wp_region6_xu0,
2114 arg->sw_rawawb_exc_wp_region6_xu1),
2115 ISP21_RAWAWB_EXC_WP_REGION6_XU);
2116
2117 rkisp_iowrite32(params_vdev,
2118 ISP2X_PACK_2SHORT(arg->sw_rawawb_exc_wp_region6_yv0,
2119 arg->sw_rawawb_exc_wp_region6_yv1),
2120 ISP21_RAWAWB_EXC_WP_REGION6_YV);
2121
2122 for (i = 0; i < ISP21_RAWAWB_WEIGHT_NUM / 5; i++) {
2123 rkisp_iowrite32(params_vdev,
2124 (arg->sw_rawawb_wp_blk_wei_w[5 * i] & 0x3f) << 0 |
2125 (arg->sw_rawawb_wp_blk_wei_w[5 * i + 1] & 0x3f) << 6 |
2126 (arg->sw_rawawb_wp_blk_wei_w[5 * i + 2] & 0x3f) << 12 |
2127 (arg->sw_rawawb_wp_blk_wei_w[5 * i + 3] & 0x3f) << 18 |
2128 (arg->sw_rawawb_wp_blk_wei_w[5 * i + 4] & 0x3f) << 24,
2129 ISP21_RAWAWB_WRAM_DATA_BASE);
2130 }
2131
2132 /* avoid to override the old enable value */
2133 value = rkisp_ioread32(params_vdev, ISP21_RAWAWB_CTRL);
2134 value &= ISP2X_RAWAWB_ENA;
2135 value &= ~ISP2X_REG_WR_MASK;
2136 rkisp_iowrite32(params_vdev,
2137 value |
2138 (arg->sw_rawawb_uv_en0 & 0x1) << 1 |
2139 (arg->sw_rawawb_xy_en0 & 0x1) << 2 |
2140 (arg->sw_rawawb_3dyuv_en0 & 0x1) << 3 |
2141 (arg->sw_rawawb_3dyuv_ls_idx0 & 0x7) << 4 |
2142 (arg->sw_rawawb_3dyuv_ls_idx1 & 0x7) << 7 |
2143 (arg->sw_rawawb_3dyuv_ls_idx2 & 0x7) << 10 |
2144 (arg->sw_rawawb_3dyuv_ls_idx3 & 0x7) << 13 |
2145 (arg->sw_rawawb_wind_size & 0x1) << 18 |
2146 (arg->sw_rawlsc_bypass_en & 0x1) << 19 |
2147 (arg->sw_rawawb_light_num & 0x7) << 20 |
2148 (arg->sw_rawawb_uv_en1 & 0x1) << 24 |
2149 (arg->sw_rawawb_xy_en1 & 0x1) << 25 |
2150 (arg->sw_rawawb_3dyuv_en1 & 0x1) << 26,
2151 ISP21_RAWAWB_CTRL);
2152
2153 value = rkisp_ioread32(params_vdev, CTRL_VI_ISP_PATH);
2154 value &= ~(ISP2X_ISPPATH_RAWAWB_SEL_SET(3));
2155 value |= ISP2X_ISPPATH_RAWAWB_SEL_SET(arg->rawawb_sel);
2156 rkisp_iowrite32(params_vdev, value, CTRL_VI_ISP_PATH);
2157 }
2158
2159 static void
isp_rawawb_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)2160 isp_rawawb_enable(struct rkisp_isp_params_vdev *params_vdev,
2161 bool en)
2162 {
2163 u32 awb_ctrl;
2164
2165 awb_ctrl = rkisp_ioread32(params_vdev, ISP21_RAWAWB_CTRL);
2166 awb_ctrl &= ~ISP2X_REG_WR_MASK;
2167 if (en)
2168 awb_ctrl |= ISP2X_RAWAWB_ENA;
2169 else
2170 awb_ctrl &= ~ISP2X_RAWAWB_ENA;
2171
2172 rkisp_iowrite32(params_vdev, awb_ctrl, ISP21_RAWAWB_CTRL);
2173 }
2174
2175 static void
isp_rawhstlite_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawhistlite_cfg * arg)2176 isp_rawhstlite_config(struct rkisp_isp_params_vdev *params_vdev,
2177 const struct isp2x_rawhistlite_cfg *arg)
2178 {
2179 u32 i;
2180 u32 value;
2181 u32 hist_ctrl;
2182 u32 block_hsize, block_vsize;
2183
2184 /* avoid to override the old enable value */
2185 hist_ctrl = rkisp_ioread32(params_vdev,
2186 ISP_RAWHIST_LITE_CTRL);
2187 hist_ctrl &= ISP2X_RAWHSTLITE_CTRL_EN_MASK;
2188 hist_ctrl &= ~ISP2X_REG_WR_MASK;
2189 hist_ctrl = hist_ctrl |
2190 ISP2X_RAWHSTLITE_CTRL_MODE_SET(arg->mode) |
2191 ISP2X_RAWHSTLITE_CTRL_DATASEL_SET(arg->data_sel) |
2192 ISP2X_RAWHSTLITE_CTRL_WATERLINE_SET(arg->waterline) |
2193 ISP2X_RAWHSTLITE_CTRL_STEPSIZE_SET(arg->stepsize);
2194 rkisp_iowrite32(params_vdev, hist_ctrl,
2195 ISP_RAWHIST_LITE_CTRL);
2196
2197 rkisp_iowrite32(params_vdev,
2198 ISP2X_RAWHSTLITE_OFFS_SET(arg->win.h_offs & 0xFFFE,
2199 arg->win.v_offs & 0xFFFE),
2200 ISP_RAWHIST_LITE_OFFS);
2201
2202 block_hsize = arg->win.h_size / ISP2X_RAWHSTLITE_ROW_NUM - 1;
2203 block_vsize = arg->win.v_size / ISP2X_RAWHSTLITE_COLUMN_NUM - 1;
2204 block_hsize &= 0xFFFE;
2205 block_vsize &= 0xFFFE;
2206 rkisp_iowrite32(params_vdev,
2207 ISP2X_RAWHSTLITE_SIZE_SET(block_hsize, block_vsize),
2208 ISP_RAWHIST_LITE_SIZE);
2209
2210 rkisp_iowrite32(params_vdev,
2211 ISP2X_PACK_4BYTE(arg->rcc, arg->gcc, arg->bcc, arg->off),
2212 ISP_RAWHIST_LITE_RAW2Y_CC);
2213
2214 for (i = 0; i < (ISP2X_RAWHSTLITE_WEIGHT_REG_SIZE / 4); i++) {
2215 value = ISP2X_RAWHSTLITE_WEIGHT_SET(
2216 arg->weight[4 * i + 0],
2217 arg->weight[4 * i + 1],
2218 arg->weight[4 * i + 2],
2219 arg->weight[4 * i + 3]);
2220 rkisp_iowrite32(params_vdev, value,
2221 ISP_RAWHIST_LITE_WEIGHT + 4 * i);
2222 }
2223
2224 value = ISP2X_RAWHSTLITE_WEIGHT_SET(
2225 arg->weight[4 * i + 0], 0, 0, 0);
2226 rkisp_iowrite32(params_vdev, value,
2227 ISP_RAWHIST_LITE_WEIGHT + 4 * i);
2228 }
2229
2230 static void
isp_rawhstlite_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)2231 isp_rawhstlite_enable(struct rkisp_isp_params_vdev *params_vdev,
2232 bool en)
2233 {
2234 u32 hist_ctrl;
2235
2236 hist_ctrl = rkisp_ioread32(params_vdev,
2237 ISP_RAWHIST_LITE_CTRL);
2238 hist_ctrl &= ~(ISP2X_RAWHSTLITE_CTRL_EN_MASK | ISP2X_REG_WR_MASK);
2239
2240 if (en)
2241 hist_ctrl |= ISP2X_RAWHSTLITE_CTRL_EN_SET(0x1);
2242
2243 rkisp_iowrite32(params_vdev, hist_ctrl,
2244 ISP_RAWHIST_LITE_CTRL);
2245 }
2246
2247 static void
isp_rawhstbig_cfg_sram(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawhistbig_cfg * arg,u32 blk_no,bool is_check)2248 isp_rawhstbig_cfg_sram(struct rkisp_isp_params_vdev *params_vdev,
2249 const struct isp2x_rawhistbig_cfg *arg,
2250 u32 blk_no, bool is_check)
2251 {
2252 u32 i, j, wnd_num_idx, value;
2253 u8 weight15x15[ISP2X_RAWHSTBIG_WEIGHT_REG_SIZE];
2254 const u32 hist_wnd_num[] = { 5, 5, 15, 15 };
2255 u32 addr;
2256
2257 switch (blk_no) {
2258 case 1:
2259 addr = ISP_RAWHIST_BIG2_BASE;
2260 break;
2261 case 2:
2262 addr = ISP_RAWHIST_BIG3_BASE;
2263 break;
2264 case 0:
2265 default:
2266 addr = ISP_RAWHIST_BIG1_BASE;
2267 break;
2268 }
2269
2270 value = ISP2X_RAWHSTBIG_CTRL_EN_MASK;
2271 if (is_check &&
2272 !(rkisp_ioread32(params_vdev, addr + ISP_RAWHIST_BIG_CTRL) & value))
2273 return;
2274
2275 wnd_num_idx = arg->wnd_num;
2276 memset(weight15x15, 0, sizeof(weight15x15));
2277 for (i = 0; i < hist_wnd_num[wnd_num_idx]; i++) {
2278 for (j = 0; j < hist_wnd_num[wnd_num_idx]; j++) {
2279 weight15x15[i * ISP2X_RAWHSTBIG_ROW_NUM + j] =
2280 arg->weight[i * hist_wnd_num[wnd_num_idx] + j];
2281 }
2282 }
2283
2284 for (i = 0; i < (ISP2X_RAWHSTBIG_WEIGHT_REG_SIZE / 5); i++) {
2285 value = ISP2X_RAWHSTBIG_WEIGHT_SET(weight15x15[5 * i + 0],
2286 weight15x15[5 * i + 1],
2287 weight15x15[5 * i + 2],
2288 weight15x15[5 * i + 3],
2289 weight15x15[5 * i + 4]);
2290 rkisp_write(params_vdev->dev, addr + ISP_RAWHIST_BIG_WEIGHT_BASE,
2291 value, true);
2292 }
2293 }
2294
2295 static void
isp_rawhstbig_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawhistbig_cfg * arg,u32 blk_no)2296 isp_rawhstbig_config(struct rkisp_isp_params_vdev *params_vdev,
2297 const struct isp2x_rawhistbig_cfg *arg, u32 blk_no)
2298 {
2299 struct isp21_isp_params_cfg *params_rec = params_vdev->isp21_params;
2300 struct rkisp_device *dev = params_vdev->dev;
2301 struct isp2x_rawhistbig_cfg *arg_rec;
2302 u32 hist_ctrl, block_hsize, block_vsize, wnd_num_idx;
2303 const u32 hist_wnd_num[] = { 5, 5, 15, 15 };
2304 u32 addr;
2305
2306 switch (blk_no) {
2307 case 1:
2308 addr = ISP_RAWHIST_BIG2_BASE;
2309 arg_rec = ¶ms_rec->meas.rawhist1;
2310 break;
2311 case 2:
2312 addr = ISP_RAWHIST_BIG3_BASE;
2313 arg_rec = ¶ms_rec->meas.rawhist2;
2314 break;
2315 case 0:
2316 default:
2317 addr = ISP_RAWHIST_BIG1_BASE;
2318 arg_rec = ¶ms_rec->meas.rawhist3;
2319 break;
2320 }
2321
2322 wnd_num_idx = arg->wnd_num;
2323 /* avoid to override the old enable value */
2324 hist_ctrl = rkisp_ioread32(params_vdev, addr + ISP_RAWHIST_BIG_CTRL);
2325 hist_ctrl &= ISP2X_RAWHSTBIG_CTRL_EN_MASK;
2326 hist_ctrl &= ~ISP2X_REG_WR_MASK;
2327 hist_ctrl = hist_ctrl |
2328 ISP2X_RAWHSTBIG_CTRL_MODE_SET(arg->mode) |
2329 ISP2X_RAWHSTBIG_CTRL_DATASEL_SET(arg->data_sel) |
2330 ISP2X_RAWHSTBIG_CTRL_WATERLINE_SET(arg->waterline) |
2331 ISP2X_RAWHSTBIG_CTRL_WNDNUM_SET(arg->wnd_num) |
2332 ISP2X_RAWHSTBIG_CTRL_STEPSIZE_SET(arg->stepsize);
2333 rkisp_iowrite32(params_vdev, hist_ctrl, addr + ISP_RAWHIST_BIG_CTRL);
2334
2335 rkisp_iowrite32(params_vdev,
2336 ISP2X_RAWHSTBIG_OFFS_SET(arg->win.h_offs & 0xFFFE,
2337 arg->win.v_offs & 0xFFFE),
2338 addr + ISP_RAWHIST_BIG_OFFS);
2339
2340 block_hsize = arg->win.h_size / hist_wnd_num[wnd_num_idx] - 1;
2341 block_vsize = arg->win.v_size / hist_wnd_num[wnd_num_idx] - 1;
2342 block_hsize &= 0xFFFE;
2343 block_vsize &= 0xFFFE;
2344 rkisp_iowrite32(params_vdev,
2345 ISP2X_RAWHSTBIG_SIZE_SET(block_hsize, block_vsize),
2346 addr + ISP_RAWHIST_BIG_SIZE);
2347
2348 rkisp_iowrite32(params_vdev,
2349 ISP2X_PACK_4BYTE(arg->rcc, arg->gcc, arg->bcc, arg->off),
2350 addr + ISP_RAWHIST_BIG_RAW2Y_CC);
2351
2352 if (dev->hw_dev->is_single)
2353 isp_rawhstbig_cfg_sram(params_vdev, arg, blk_no, false);
2354 else
2355 *arg_rec = *arg;
2356 }
2357
2358 static void
isp_rawhstbig_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 blk_no)2359 isp_rawhstbig_enable(struct rkisp_isp_params_vdev *params_vdev,
2360 bool en, u32 blk_no)
2361 {
2362 u32 hist_ctrl;
2363 u32 addr;
2364
2365 switch (blk_no) {
2366 case 0:
2367 addr = ISP_RAWHIST_BIG1_BASE;
2368 break;
2369 case 1:
2370 addr = ISP_RAWHIST_BIG2_BASE;
2371 break;
2372 case 2:
2373 addr = ISP_RAWHIST_BIG3_BASE;
2374 break;
2375 default:
2376 addr = ISP_RAWHIST_BIG1_BASE;
2377 break;
2378 }
2379
2380 hist_ctrl = rkisp_ioread32(params_vdev, addr + ISP_RAWHIST_BIG_CTRL);
2381 hist_ctrl &= ~(ISP2X_RAWHSTBIG_CTRL_EN_MASK | ISP2X_REG_WR_MASK);
2382 if (en)
2383 hist_ctrl |= ISP2X_RAWHSTBIG_CTRL_EN_SET(0x1);
2384
2385 rkisp_iowrite32(params_vdev, hist_ctrl, addr + ISP_RAWHIST_BIG_CTRL);
2386 }
2387
2388 static void
isp_rawhst1_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawhistbig_cfg * arg)2389 isp_rawhst1_config(struct rkisp_isp_params_vdev *params_vdev,
2390 const struct isp2x_rawhistbig_cfg *arg)
2391 {
2392 isp_rawhstbig_config(params_vdev, arg, 1);
2393 }
2394
2395 static void
isp_rawhst1_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)2396 isp_rawhst1_enable(struct rkisp_isp_params_vdev *params_vdev,
2397 bool en)
2398 {
2399 isp_rawhstbig_enable(params_vdev, en, 1);
2400 }
2401
2402 static void
isp_rawhst2_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawhistbig_cfg * arg)2403 isp_rawhst2_config(struct rkisp_isp_params_vdev *params_vdev,
2404 const struct isp2x_rawhistbig_cfg *arg)
2405 {
2406 isp_rawhstbig_config(params_vdev, arg, 2);
2407 }
2408
2409 static void
isp_rawhst2_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)2410 isp_rawhst2_enable(struct rkisp_isp_params_vdev *params_vdev,
2411 bool en)
2412 {
2413 isp_rawhstbig_enable(params_vdev, en, 2);
2414 }
2415
2416 static void
isp_rawhst3_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawhistbig_cfg * arg)2417 isp_rawhst3_config(struct rkisp_isp_params_vdev *params_vdev,
2418 const struct isp2x_rawhistbig_cfg *arg)
2419 {
2420 isp_rawhstbig_config(params_vdev, arg, 0);
2421 }
2422
2423 static void
isp_rawhst3_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)2424 isp_rawhst3_enable(struct rkisp_isp_params_vdev *params_vdev,
2425 bool en)
2426 {
2427 isp_rawhstbig_enable(params_vdev, en, 0);
2428 }
2429
2430 static void
isp_hdrmge_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_hdrmge_cfg * arg,enum rkisp_params_type type)2431 isp_hdrmge_config(struct rkisp_isp_params_vdev *params_vdev,
2432 const struct isp2x_hdrmge_cfg *arg, enum rkisp_params_type type)
2433 {
2434 u32 value;
2435 int i;
2436
2437 if (type == RKISP_PARAMS_SHD || type == RKISP_PARAMS_ALL) {
2438 value = ISP2X_PACK_2SHORT(arg->gain0, arg->gain0_inv);
2439 rkisp_iowrite32(params_vdev, value, ISP_HDRMGE_GAIN0);
2440
2441 value = ISP2X_PACK_2SHORT(arg->gain1, arg->gain1_inv);
2442 rkisp_iowrite32(params_vdev, value, ISP_HDRMGE_GAIN1);
2443
2444 value = arg->gain2;
2445 rkisp_iowrite32(params_vdev, value, ISP_HDRMGE_GAIN2);
2446 }
2447
2448 if (type == RKISP_PARAMS_IMD || type == RKISP_PARAMS_ALL) {
2449 value = ISP2X_PACK_4BYTE(arg->ms_dif_0p8, arg->ms_diff_0p15,
2450 arg->lm_dif_0p9, arg->lm_dif_0p15);
2451 rkisp_iowrite32(params_vdev, value, ISP_HDRMGE_CONS_DIFF);
2452
2453 for (i = 0; i < ISP2X_HDRMGE_L_CURVE_NUM; i++) {
2454 value = ISP2X_PACK_2SHORT(arg->curve.curve_0[i], arg->curve.curve_1[i]);
2455 rkisp_iowrite32(params_vdev, value, ISP_HDRMGE_DIFF_Y0 + 4 * i);
2456 }
2457
2458 for (i = 0; i < ISP2X_HDRMGE_E_CURVE_NUM; i++) {
2459 value = arg->e_y[i];
2460 rkisp_iowrite32(params_vdev, value, ISP_HDRMGE_OVER_Y0 + 4 * i);
2461 }
2462 }
2463 }
2464
2465 static void
isp_hdrmge_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)2466 isp_hdrmge_enable(struct rkisp_isp_params_vdev *params_vdev,
2467 bool en)
2468 {
2469 }
2470
2471 static void
isp_hdrdrc_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp21_drc_cfg * arg,enum rkisp_params_type type)2472 isp_hdrdrc_config(struct rkisp_isp_params_vdev *params_vdev,
2473 const struct isp21_drc_cfg *arg, enum rkisp_params_type type)
2474 {
2475 u32 i, value;
2476
2477 if (type == RKISP_PARAMS_IMD)
2478 return;
2479
2480 value = (arg->sw_drc_offset_pow2 & 0x0F) << 28 |
2481 (arg->sw_drc_compres_scl & 0x1FFF) << 14 |
2482 (arg->sw_drc_position & 0x03FFF);
2483 rkisp_iowrite32(params_vdev, value, ISP21_DRC_CTRL1);
2484
2485 value = (arg->sw_drc_delta_scalein & 0xFF) << 24 |
2486 (arg->sw_drc_hpdetail_ratio & 0xFFF) << 12 |
2487 (arg->sw_drc_lpdetail_ratio & 0xFFF);
2488 rkisp_iowrite32(params_vdev, value, ISP21_DRC_LPRATIO);
2489
2490 value = ISP2X_PACK_4BYTE(0, 0, arg->sw_drc_weipre_frame, arg->sw_drc_weicur_pix);
2491 rkisp_iowrite32(params_vdev, value, ISP21_DRC_EXPLRATIO);
2492
2493 value = (arg->sw_drc_force_sgm_inv0 & 0xFFFF) << 16 |
2494 (arg->sw_drc_motion_scl & 0xFF) << 8 |
2495 (arg->sw_drc_edge_scl & 0xFF);
2496 rkisp_iowrite32(params_vdev, value, ISP21_DRC_SIGMA);
2497
2498 value = ISP2X_PACK_2SHORT(arg->sw_drc_space_sgm_inv0, arg->sw_drc_space_sgm_inv1);
2499 rkisp_iowrite32(params_vdev, value, ISP21_DRC_SPACESGM);
2500
2501 value = ISP2X_PACK_2SHORT(arg->sw_drc_range_sgm_inv0, arg->sw_drc_range_sgm_inv1);
2502 rkisp_iowrite32(params_vdev, value, ISP21_DRC_RANESGM);
2503
2504 value = ISP2X_PACK_4BYTE(arg->sw_drc_weig_bilat, arg->sw_drc_weig_maxl, 0, 0);
2505 rkisp_iowrite32(params_vdev, value, ISP21_DRC_BILAT);
2506
2507 for (i = 0; i < ISP21_DRC_Y_NUM / 2; i++) {
2508 value = ISP2X_PACK_2SHORT(arg->sw_drc_gain_y[2 * i],
2509 arg->sw_drc_gain_y[2 * i + 1]);
2510 rkisp_iowrite32(params_vdev, value, ISP21_DRC_GAIN_Y0 + 4 * i);
2511 }
2512
2513 value = ISP2X_PACK_2SHORT(arg->sw_drc_gain_y[2 * i], 0);
2514 rkisp_iowrite32(params_vdev, value, ISP21_DRC_GAIN_Y0 + 4 * i);
2515
2516 for (i = 0; i < ISP21_DRC_Y_NUM / 2; i++) {
2517 value = ISP2X_PACK_2SHORT(arg->sw_drc_compres_y[2 * i],
2518 arg->sw_drc_compres_y[2 * i + 1]);
2519 rkisp_iowrite32(params_vdev, value, ISP21_DRC_COMPRES_Y0 + 4 * i);
2520 }
2521
2522 value = ISP2X_PACK_2SHORT(arg->sw_drc_compres_y[2 * i], 0);
2523 rkisp_iowrite32(params_vdev, value, ISP21_DRC_COMPRES_Y0 + 4 * i);
2524
2525 for (i = 0; i < ISP21_DRC_Y_NUM / 2; i++) {
2526 value = ISP2X_PACK_2SHORT(arg->sw_drc_scale_y[2 * i],
2527 arg->sw_drc_scale_y[2 * i + 1]);
2528 rkisp_iowrite32(params_vdev, value, ISP21_DRC_SCALE_Y0 + 4 * i);
2529 }
2530
2531 value = ISP2X_PACK_2SHORT(arg->sw_drc_scale_y[2 * i], 0);
2532 rkisp_iowrite32(params_vdev, value, ISP21_DRC_SCALE_Y0 + 4 * i);
2533
2534 value = ISP2X_PACK_2SHORT(arg->sw_drc_min_ogain, arg->sw_drc_iir_weight);
2535 rkisp_iowrite32(params_vdev, value, ISP21_DRC_IIRWG_GAIN);
2536 }
2537
2538 static void
isp_hdrdrc_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)2539 isp_hdrdrc_enable(struct rkisp_isp_params_vdev *params_vdev,
2540 bool en)
2541 {
2542 u32 value;
2543 bool real_en;
2544
2545 value = rkisp_ioread32(params_vdev, ISP21_DRC_CTRL0);
2546 real_en = !!(value & ISP_DRC_EN);
2547 if ((en && real_en) || (!en && !real_en))
2548 return;
2549
2550 if (en) {
2551 value |= ISP_DRC_EN;
2552 rkisp_set_bits(params_vdev->dev, ISP_CTRL1,
2553 ISP2X_SYS_ADRC_FST, ISP2X_SYS_ADRC_FST, false);
2554 } else {
2555 value = 0;
2556 }
2557 rkisp_iowrite32(params_vdev, value, ISP21_DRC_CTRL0);
2558 }
2559
2560 static void
isp_gic_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp21_gic_cfg * arg)2561 isp_gic_config(struct rkisp_isp_params_vdev *params_vdev,
2562 const struct isp21_gic_cfg *arg)
2563 {
2564 u32 value;
2565 s32 i;
2566
2567 value = (arg->regmingradthrdark2 & 0x03FF) << 20 |
2568 (arg->regmingradthrdark1 & 0x03FF) << 10 |
2569 (arg->regminbusythre & 0x03FF);
2570 rkisp_iowrite32(params_vdev, value, ISP_GIC_DIFF_PARA1);
2571
2572 value = (arg->regdarkthre & 0x07FF) << 21 |
2573 (arg->regmaxcorvboth & 0x03FF) << 11 |
2574 (arg->regdarktthrehi & 0x07FF);
2575 rkisp_iowrite32(params_vdev, value, ISP_GIC_DIFF_PARA2);
2576
2577 value = (arg->regkgrad2dark & 0x0F) << 28 |
2578 (arg->regkgrad1dark & 0x0F) << 24 |
2579 (arg->regstrengthglobal_fix & 0xFF) << 16 |
2580 (arg->regdarkthrestep & 0x0F) << 12 |
2581 (arg->regkgrad2 & 0x0F) << 8 |
2582 (arg->regkgrad1 & 0x0F) << 4 |
2583 (arg->reggbthre & 0x0F);
2584 rkisp_iowrite32(params_vdev, value, ISP_GIC_DIFF_PARA3);
2585
2586 value = (arg->regmaxcorv & 0x03FF) << 20 |
2587 (arg->regmingradthr2 & 0x03FF) << 10 |
2588 (arg->regmingradthr1 & 0x03FF);
2589 rkisp_iowrite32(params_vdev, value, ISP_GIC_DIFF_PARA4);
2590
2591 value = (arg->gr_ratio & 0x03) << 28 |
2592 (arg->noise_scale & 0x7F) << 12 |
2593 (arg->noise_base & 0xFFF);
2594 rkisp_iowrite32(params_vdev, value, ISP_GIC_NOISE_PARA1);
2595
2596 rkisp_iowrite32(params_vdev, arg->diff_clip, ISP_GIC_NOISE_PARA2);
2597
2598 for (i = 0; i < ISP2X_GIC_SIGMA_Y_NUM / 2; i++) {
2599 value = ISP2X_PACK_2SHORT(arg->sigma_y[2 * i], arg->sigma_y[2 * i + 1]);
2600 rkisp_iowrite32(params_vdev, value, ISP_GIC_SIGMA_VALUE0 + 4 * i);
2601 }
2602 value = ISP2X_PACK_2SHORT(arg->sigma_y[2 * i], 0);
2603 rkisp_iowrite32(params_vdev, value, ISP_GIC_SIGMA_VALUE0 + 4 * i);
2604 }
2605
2606 static void
isp_gic_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)2607 isp_gic_enable(struct rkisp_isp_params_vdev *params_vdev,
2608 bool en)
2609 {
2610 u32 value = 0;
2611
2612 if (en)
2613 value |= ISP_GIC_ENA;
2614 rkisp_iowrite32(params_vdev, value, ISP_GIC_CONTROL);
2615 }
2616
2617 static void
isp_dhaz_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp21_dhaz_cfg * arg)2618 isp_dhaz_config(struct rkisp_isp_params_vdev *params_vdev,
2619 const struct isp21_dhaz_cfg *arg)
2620 {
2621 u32 i, value;
2622
2623 value = rkisp_ioread32(params_vdev, ISP21_DHAZ_CTRL);
2624 value &= ISP_DHAZ_ENMUX;
2625
2626 value |= (arg->enhance_en & 0x1) << 20 |
2627 (arg->air_lc_en & 0x1) << 16 |
2628 (arg->hpara_en & 0x1) << 12 |
2629 (arg->hist_en & 0x1) << 8 |
2630 (arg->dc_en & 0x1) << 4;
2631 rkisp_iowrite32(params_vdev, value, ISP21_DHAZ_CTRL);
2632
2633 value = ISP2X_PACK_4BYTE(arg->dc_min_th, arg->dc_max_th,
2634 arg->yhist_th, arg->yblk_th);
2635 rkisp_iowrite32(params_vdev, value, ISP21_DHAZ_ADP0);
2636
2637 value = ISP2X_PACK_4BYTE(arg->bright_min, arg->bright_max,
2638 arg->wt_max, 0);
2639 rkisp_iowrite32(params_vdev, value, ISP21_DHAZ_ADP1);
2640
2641 value = ISP2X_PACK_4BYTE(arg->air_min, arg->air_max,
2642 arg->dark_th, arg->tmax_base);
2643 rkisp_iowrite32(params_vdev, value, ISP21_DHAZ_ADP2);
2644
2645 value = ISP2X_PACK_2SHORT(arg->tmax_off, arg->tmax_max);
2646 rkisp_iowrite32(params_vdev, value, ISP21_DHAZ_ADP_TMAX);
2647
2648 value = (arg->hist_min & 0xFFFF) << 16 |
2649 (arg->hist_th_off & 0xFF) << 8 |
2650 (arg->hist_k & 0x1F);
2651 rkisp_iowrite32(params_vdev, value, ISP21_DHAZ_ADP_HIST0);
2652
2653 value = ISP2X_PACK_2SHORT(arg->hist_scale, arg->hist_gratio);
2654 rkisp_iowrite32(params_vdev, value, ISP21_DHAZ_ADP_HIST1);
2655
2656 value = ISP2X_PACK_2SHORT(arg->enhance_chroma, arg->enhance_value);
2657 rkisp_iowrite32(params_vdev, value, ISP21_DHAZ_ENHANCE);
2658
2659 value = (arg->iir_wt_sigma & 0x07FF) << 16 |
2660 (arg->iir_sigma & 0xFF) << 8 |
2661 (arg->stab_fnum & 0x1F);
2662 rkisp_iowrite32(params_vdev, value, ISP21_DHAZ_IIR0);
2663
2664 value = (arg->iir_pre_wet & 0x0F) << 24 |
2665 (arg->iir_tmax_sigma & 0x7FF) << 8 |
2666 (arg->iir_air_sigma & 0xFF);
2667 rkisp_iowrite32(params_vdev, value, ISP21_DHAZ_IIR1);
2668
2669 value = (arg->cfg_wt & 0x01FF) << 16 |
2670 (arg->cfg_air & 0xFF) << 8 |
2671 (arg->cfg_alpha & 0xFF);
2672 rkisp_iowrite32(params_vdev, value, ISP21_DHAZ_SOFT_CFG0);
2673
2674 value = ISP2X_PACK_2SHORT(arg->cfg_tmax, arg->cfg_gratio);
2675 rkisp_iowrite32(params_vdev, value, ISP21_DHAZ_SOFT_CFG1);
2676
2677 value = (arg->range_sima & 0x01FF) << 16 |
2678 (arg->space_sigma_pre & 0xFF) << 8 |
2679 (arg->space_sigma_cur & 0xFF);
2680 rkisp_iowrite32(params_vdev, value, ISP21_DHAZ_BF_SIGMA);
2681
2682 value = ISP2X_PACK_2SHORT(arg->bf_weight, arg->dc_weitcur);
2683 rkisp_iowrite32(params_vdev, value, ISP21_DHAZ_BF_WET);
2684
2685 for (i = 0; i < ISP21_DHAZ_ENH_CURVE_NUM / 2; i++) {
2686 value = ISP2X_PACK_2SHORT(arg->enh_curve[2 * i], arg->enh_curve[2 * i + 1]);
2687 rkisp_iowrite32(params_vdev, value, ISP21_DHAZ_ENH_CURVE0 + 4 * i);
2688 }
2689
2690 value = ISP2X_PACK_2SHORT(arg->enh_curve[2 * i], 0);
2691 rkisp_iowrite32(params_vdev, value, ISP21_DHAZ_ENH_CURVE0 + 4 * i);
2692
2693 value = ISP2X_PACK_4BYTE(arg->gaus_h0, arg->gaus_h1, arg->gaus_h2, 0);
2694 rkisp_iowrite32(params_vdev, value, ISP21_DHAZ_GAUS);
2695 }
2696
2697 static void
isp_dhaz_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)2698 isp_dhaz_enable(struct rkisp_isp_params_vdev *params_vdev,
2699 bool en)
2700 {
2701 u32 value;
2702 bool real_en;
2703
2704 value = rkisp_ioread32(params_vdev, ISP21_DHAZ_CTRL);
2705 real_en = !!(value & ISP_DHAZ_ENMUX);
2706 if ((en && real_en) || (!en && !real_en))
2707 return;
2708
2709 if (en) {
2710 value |= ISP21_SELF_FORCE_UPD | ISP_DHAZ_ENMUX;
2711 rkisp_set_bits(params_vdev->dev, ISP_CTRL1,
2712 ISP2X_SYS_DHAZ_FST, ISP2X_SYS_DHAZ_FST, false);
2713 } else {
2714 value &= ~ISP_DHAZ_ENMUX;
2715 }
2716
2717 rkisp_iowrite32(params_vdev, value, ISP21_DHAZ_CTRL);
2718 }
2719
2720 static void
isp_3dlut_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_3dlut_cfg * arg)2721 isp_3dlut_config(struct rkisp_isp_params_vdev *params_vdev,
2722 const struct isp2x_3dlut_cfg *arg)
2723 {
2724 struct rkisp_isp_params_val_v21 *priv_val;
2725 u32 value, buf_idx, i;
2726 u32 *data;
2727
2728 priv_val = (struct rkisp_isp_params_val_v21 *)params_vdev->priv_val;
2729 buf_idx = (priv_val->buf_3dlut_idx++) % RKISP_PARAM_3DLUT_BUF_NUM;
2730
2731 data = (u32 *)priv_val->buf_3dlut[buf_idx].vaddr;
2732 for (i = 0; i < arg->actual_size; i++)
2733 data[i] = (arg->lut_b[i] & 0x3FF) |
2734 (arg->lut_g[i] & 0xFFF) << 10 |
2735 (arg->lut_r[i] & 0x3FF) << 22;
2736 rkisp_prepare_buffer(params_vdev->dev, &priv_val->buf_3dlut[buf_idx]);
2737 value = priv_val->buf_3dlut[buf_idx].dma_addr;
2738 rkisp_iowrite32(params_vdev, value, MI_LUT_3D_RD_BASE);
2739 rkisp_iowrite32(params_vdev, arg->actual_size, MI_LUT_3D_RD_WSIZE);
2740
2741 value = rkisp_ioread32(params_vdev, ISP_3DLUT_CTRL);
2742 value &= ISP_3DLUT_EN;
2743
2744 if (value)
2745 isp_param_set_bits(params_vdev, ISP_3DLUT_UPDATE, 0x01);
2746
2747 if (arg->bypass_en)
2748 value |= ISP_3DLUT_BYPASS;
2749
2750 rkisp_iowrite32(params_vdev, value, ISP_3DLUT_CTRL);
2751 }
2752
2753 static void
isp_3dlut_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)2754 isp_3dlut_enable(struct rkisp_isp_params_vdev *params_vdev,
2755 bool en)
2756 {
2757 u32 value;
2758 bool en_state;
2759
2760 value = rkisp_ioread32(params_vdev, ISP_3DLUT_CTRL);
2761 en_state = (value & ISP_3DLUT_EN) ? true : false;
2762
2763 if (en == en_state)
2764 return;
2765
2766 if (en) {
2767 isp_param_set_bits(params_vdev, ISP_3DLUT_CTRL, 0x01);
2768 isp_param_set_bits(params_vdev, ISP_3DLUT_UPDATE, 0x01);
2769 } else {
2770 isp_param_clear_bits(params_vdev, ISP_3DLUT_CTRL, 0x01);
2771 isp_param_clear_bits(params_vdev, ISP_3DLUT_UPDATE, 0x01);
2772 }
2773 }
2774
2775 static void
isp_ldch_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_ldch_cfg * arg)2776 isp_ldch_config(struct rkisp_isp_params_vdev *params_vdev,
2777 const struct isp2x_ldch_cfg *arg)
2778 {
2779 struct rkisp_device *dev = params_vdev->dev;
2780 struct rkisp_isp_params_val_v21 *priv_val;
2781 struct isp2x_ldch_head *ldch_head;
2782 int buf_idx, i;
2783 u32 value;
2784
2785 priv_val = (struct rkisp_isp_params_val_v21 *)params_vdev->priv_val;
2786 for (i = 0; i < ISP2X_LDCH_BUF_NUM; i++) {
2787 if (arg->buf_fd == priv_val->buf_ldch[i].dma_fd)
2788 break;
2789 }
2790 if (i == ISP2X_LDCH_BUF_NUM) {
2791 dev_err(dev->dev, "cannot find ldch buf fd(%d)\n", arg->buf_fd);
2792 return;
2793 }
2794
2795 if (!priv_val->buf_ldch[i].vaddr) {
2796 dev_err(dev->dev, "no ldch buffer allocated\n");
2797 return;
2798 }
2799
2800 buf_idx = priv_val->buf_ldch_idx;
2801 ldch_head = (struct isp2x_ldch_head *)priv_val->buf_ldch[buf_idx].vaddr;
2802 ldch_head->stat = LDCH_BUF_INIT;
2803
2804 buf_idx = i;
2805 ldch_head = (struct isp2x_ldch_head *)priv_val->buf_ldch[buf_idx].vaddr;
2806 ldch_head->stat = LDCH_BUF_CHIPINUSE;
2807 priv_val->buf_ldch_idx = buf_idx;
2808 rkisp_prepare_buffer(dev, &priv_val->buf_ldch[buf_idx]);
2809 value = priv_val->buf_ldch[buf_idx].dma_addr + ldch_head->data_oft;
2810 rkisp_iowrite32(params_vdev, value, MI_LUT_LDCH_RD_BASE);
2811 rkisp_iowrite32(params_vdev, arg->hsize, MI_LUT_LDCH_RD_H_WSIZE);
2812 rkisp_iowrite32(params_vdev, arg->vsize, MI_LUT_LDCH_RD_V_SIZE);
2813 }
2814
2815 static void
isp_ldch_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)2816 isp_ldch_enable(struct rkisp_isp_params_vdev *params_vdev,
2817 bool en)
2818 {
2819 struct rkisp_device *dev = params_vdev->dev;
2820 struct rkisp_isp_params_val_v21 *priv_val;
2821 u32 buf_idx;
2822
2823 priv_val = (struct rkisp_isp_params_val_v21 *)params_vdev->priv_val;
2824 if (en) {
2825 buf_idx = priv_val->buf_ldch_idx;
2826 if (!priv_val->buf_ldch[buf_idx].vaddr) {
2827 dev_err(dev->dev, "no ldch buffer allocated\n");
2828 return;
2829 }
2830 isp_param_set_bits(params_vdev, ISP_LDCH_STS, 0x01);
2831 } else {
2832 isp_param_clear_bits(params_vdev, ISP_LDCH_STS, 0x01);
2833 }
2834 }
2835
2836 static void
isp_ynr_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp21_ynr_cfg * arg)2837 isp_ynr_config(struct rkisp_isp_params_vdev *params_vdev,
2838 const struct isp21_ynr_cfg *arg)
2839 {
2840 u32 i, value;
2841
2842 value = rkisp_ioread32(params_vdev, ISP21_YNR_GLOBAL_CTRL);
2843 value &= ISP21_YNR_EN;
2844
2845 value |= (arg->sw_ynr_thumb_mix_cur_en & 0x1) << 24 |
2846 (arg->sw_ynr_global_gain_alpha & 0xF) << 20 |
2847 (arg->sw_ynr_global_gain & 0x3FF) << 8 |
2848 (arg->sw_ynr_flt1x1_bypass_sel & 0x3) << 6 |
2849 (arg->sw_ynr_sft5x5_bypass & 0x1) << 5 |
2850 (arg->sw_ynr_flt1x1_bypass & 0x1) << 4 |
2851 (arg->sw_ynr_lgft3x3_bypass & 0x1) << 3 |
2852 (arg->sw_ynr_lbft5x5_bypass & 0x1) << 2 |
2853 (arg->sw_ynr_bft3x3_bypass & 0x1) << 1;
2854 rkisp_iowrite32(params_vdev, value, ISP21_YNR_GLOBAL_CTRL);
2855
2856 rkisp_iowrite32(params_vdev, arg->sw_ynr_rnr_max_r, ISP21_YNR_RNR_MAX_R);
2857
2858 value = ISP2X_PACK_2SHORT(arg->sw_ynr_low_bf_inv0, arg->sw_ynr_low_bf_inv1);
2859 rkisp_iowrite32(params_vdev, value, ISP21_YNR_LOWNR_CTRL0);
2860
2861 value = ISP2X_PACK_2SHORT(arg->sw_ynr_low_thred_adj, arg->sw_ynr_low_peak_supress);
2862 rkisp_iowrite32(params_vdev, value, ISP21_YNR_LOWNR_CTRL1);
2863
2864 value = ISP2X_PACK_2SHORT(arg->sw_ynr_low_edge_adj_thresh, arg->sw_ynr_low_dist_adj);
2865 rkisp_iowrite32(params_vdev, value, ISP21_YNR_LOWNR_CTRL2);
2866
2867 value = (arg->sw_ynr_low_bi_weight & 0xFF) << 24 |
2868 (arg->sw_ynr_low_weight & 0xFF) << 16 |
2869 (arg->sw_ynr_low_center_weight & 0xFFFF);
2870 rkisp_iowrite32(params_vdev, value, ISP21_YNR_LOWNR_CTRL3);
2871
2872 value = ISP2X_PACK_2SHORT(arg->sw_ynr_high_thred_adj, arg->sw_ynr_hi_min_adj);
2873 rkisp_iowrite32(params_vdev, value, ISP21_YNR_HIGHNR_CTRL0);
2874
2875 value = ISP2X_PACK_2SHORT(arg->sw_ynr_hi_edge_thed, arg->sw_ynr_high_retain_weight);
2876 rkisp_iowrite32(params_vdev, value, ISP21_YNR_HIGHNR_CTRL1);
2877
2878 value = ISP2X_PACK_4BYTE(arg->sw_ynr_base_filter_weight0,
2879 arg->sw_ynr_base_filter_weight1,
2880 arg->sw_ynr_base_filter_weight2,
2881 0);
2882 rkisp_iowrite32(params_vdev, value, ISP21_YNR_HIGHNR_BASE_FILTER_WEIGHT);
2883
2884 value = (arg->sw_ynr_low_gauss1_coeff2 & 0xFFFF) << 16 |
2885 (arg->sw_ynr_low_gauss1_coeff1 & 0xFF) << 8 |
2886 (arg->sw_ynr_low_gauss1_coeff0 & 0xFF);
2887 rkisp_iowrite32(params_vdev, value, ISP21_YNR_GAUSS1_COEFF);
2888
2889 value = (arg->sw_ynr_low_gauss2_coeff2 & 0xFFFF) << 16 |
2890 (arg->sw_ynr_low_gauss2_coeff1 & 0xFF) << 8 |
2891 (arg->sw_ynr_low_gauss2_coeff0 & 0xFF);
2892 rkisp_iowrite32(params_vdev, value, ISP21_YNR_GAUSS2_COEFF);
2893
2894 value = ISP2X_PACK_4BYTE(arg->sw_ynr_direction_weight0,
2895 arg->sw_ynr_direction_weight1,
2896 arg->sw_ynr_direction_weight2,
2897 arg->sw_ynr_direction_weight3);
2898 rkisp_iowrite32(params_vdev, value, ISP21_YNR_DIRECTION_W_0_3);
2899
2900 value = ISP2X_PACK_4BYTE(arg->sw_ynr_direction_weight4,
2901 arg->sw_ynr_direction_weight5,
2902 arg->sw_ynr_direction_weight6,
2903 arg->sw_ynr_direction_weight7);
2904 rkisp_iowrite32(params_vdev, value, ISP21_YNR_DIRECTION_W_4_7);
2905
2906 for (i = 0; i < ISP21_YNR_XY_NUM / 2; i++) {
2907 value = ISP2X_PACK_2SHORT(arg->sw_ynr_luma_points_x[2 * i],
2908 arg->sw_ynr_luma_points_x[2 * i + 1]);
2909 rkisp_iowrite32(params_vdev, value, ISP21_YNR_SGM_DX_0_1 + 4 * i);
2910 }
2911
2912 value = ISP2X_PACK_2SHORT(arg->sw_ynr_luma_points_x[2 * i], 0);
2913 rkisp_iowrite32(params_vdev, value, ISP21_YNR_SGM_DX_0_1 + 4 * i);
2914
2915 for (i = 0; i < ISP21_YNR_XY_NUM / 2; i++) {
2916 value = ISP2X_PACK_2SHORT(arg->sw_ynr_lsgm_y[2 * i],
2917 arg->sw_ynr_lsgm_y[2 * i + 1]);
2918 rkisp_iowrite32(params_vdev, value, ISP21_YNR_LSGM_Y_0_1 + 4 * i);
2919 }
2920
2921 value = ISP2X_PACK_2SHORT(arg->sw_ynr_lsgm_y[2 * i], 0);
2922 rkisp_iowrite32(params_vdev, value, ISP21_YNR_LSGM_Y_0_1 + 4 * i);
2923
2924 for (i = 0; i < ISP21_YNR_XY_NUM / 2; i++) {
2925 value = ISP2X_PACK_2SHORT(arg->sw_ynr_hsgm_y[2 * i],
2926 arg->sw_ynr_hsgm_y[2 * i + 1]);
2927 rkisp_iowrite32(params_vdev, value, ISP21_YNR_HSGM_Y_0_1 + 4 * i);
2928 }
2929
2930 value = ISP2X_PACK_2SHORT(arg->sw_ynr_hsgm_y[2 * i], 0);
2931 rkisp_iowrite32(params_vdev, value, ISP21_YNR_HSGM_Y_0_1 + 4 * i);
2932
2933 for (i = 0; i < ISP21_YNR_XY_NUM / 4; i++) {
2934 value = ISP2X_PACK_4BYTE(arg->sw_ynr_rnr_strength3[4 * i],
2935 arg->sw_ynr_rnr_strength3[4 * i + 1],
2936 arg->sw_ynr_rnr_strength3[4 * i + 2],
2937 arg->sw_ynr_rnr_strength3[4 * i + 3]);
2938 rkisp_iowrite32(params_vdev, value, ISP21_YNR_RNR_STRENGTH03 + 4 * i);
2939 }
2940
2941 value = ISP2X_PACK_4BYTE(arg->sw_ynr_rnr_strength3[4 * i], 0, 0, 0);
2942 rkisp_iowrite32(params_vdev, value, ISP21_YNR_RNR_STRENGTH03 + 4 * i);
2943 }
2944
2945 static void
isp_ynr_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,const struct isp21_ynr_cfg * arg)2946 isp_ynr_enable(struct rkisp_isp_params_vdev *params_vdev,
2947 bool en, const struct isp21_ynr_cfg *arg)
2948 {
2949 u32 ynr_ctrl, value = 0;
2950 bool real_en;
2951
2952 if (arg) {
2953 value = (arg->sw_ynr_thumb_mix_cur_en & 0x1) << 24 |
2954 (arg->sw_ynr_global_gain_alpha & 0xF) << 20 |
2955 (arg->sw_ynr_global_gain & 0x3FF) << 8 |
2956 (arg->sw_ynr_flt1x1_bypass_sel & 0x3) << 6 |
2957 (arg->sw_ynr_sft5x5_bypass & 0x1) << 5 |
2958 (arg->sw_ynr_flt1x1_bypass & 0x1) << 4 |
2959 (arg->sw_ynr_lgft3x3_bypass & 0x1) << 3 |
2960 (arg->sw_ynr_lbft5x5_bypass & 0x1) << 2 |
2961 (arg->sw_ynr_bft3x3_bypass & 0x1) << 1;
2962 }
2963
2964 ynr_ctrl = rkisp_ioread32(params_vdev, ISP21_YNR_GLOBAL_CTRL);
2965 real_en = !!(ynr_ctrl & ISP21_YNR_EN);
2966 if ((en && real_en) || (!en && !real_en))
2967 return;
2968
2969 if (en) {
2970 value |= ISP21_YNR_EN;
2971 rkisp_set_bits(params_vdev->dev, ISP_CTRL1,
2972 ISP2X_SYS_YNR_FST, ISP2X_SYS_YNR_FST, false);
2973 }
2974
2975 rkisp_iowrite32(params_vdev, value, ISP21_YNR_GLOBAL_CTRL);
2976 }
2977
2978 static void
isp_cnr_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp21_cnr_cfg * arg)2979 isp_cnr_config(struct rkisp_isp_params_vdev *params_vdev,
2980 const struct isp21_cnr_cfg *arg)
2981 {
2982 u32 value;
2983
2984 value = rkisp_ioread32(params_vdev, ISP21_CNR_CTRL);
2985 value &= ISP21_CNR_EN;
2986
2987 value |= (arg->sw_cnr_thumb_mix_cur_en & 0x1) << 4 |
2988 (arg->sw_cnr_lq_bila_bypass & 0x1) << 3 |
2989 (arg->sw_cnr_hq_bila_bypass & 0x1) << 2 |
2990 (arg->sw_cnr_exgain_bypass & 0x1) << 1;
2991 rkisp_iowrite32(params_vdev, value, ISP21_CNR_CTRL);
2992
2993 rkisp_iowrite32(params_vdev, arg->sw_cnr_exgain_mux, ISP21_CNR_EXGAIN);
2994
2995 value = ISP2X_PACK_4BYTE(arg->sw_cnr_gain_1sigma, arg->sw_cnr_gain_offset,
2996 arg->sw_cnr_gain_iso, 0);
2997 rkisp_iowrite32(params_vdev, value, ISP21_CNR_GAIN_PARA);
2998
2999 value = ISP2X_PACK_4BYTE(arg->sw_cnr_gain_uvgain0, arg->sw_cnr_gain_uvgain1, 0, 0);
3000 rkisp_iowrite32(params_vdev, value, ISP21_CNR_GAIN_UV_PARA);
3001
3002 rkisp_iowrite32(params_vdev, arg->sw_cnr_lmed3_alpha, ISP21_CNR_LMED3);
3003
3004 value = ISP2X_PACK_4BYTE(arg->sw_cnr_lbf5_gain_c, arg->sw_cnr_lbf5_gain_y, 0, 0);
3005 rkisp_iowrite32(params_vdev, value, ISP21_CNR_LBF5_GAIN);
3006
3007 value = ISP2X_PACK_4BYTE(arg->sw_cnr_lbf5_weit_d0, arg->sw_cnr_lbf5_weit_d1,
3008 arg->sw_cnr_lbf5_weit_d2, arg->sw_cnr_lbf5_weit_d3);
3009 rkisp_iowrite32(params_vdev, value, ISP21_CNR_LBF5_WEITD0_3);
3010
3011 rkisp_iowrite32(params_vdev, arg->sw_cnr_lbf5_weit_d4, ISP21_CNR_LBF5_WEITD4);
3012
3013 rkisp_iowrite32(params_vdev, arg->sw_cnr_hmed3_alpha, ISP21_CNR_HMED3);
3014
3015 value = (arg->sw_cnr_hbf5_weit_src & 0xFF) << 24 |
3016 (arg->sw_cnr_hbf5_min_wgt & 0xFF) << 16 |
3017 (arg->sw_cnr_hbf5_sigma & 0xFFFF);
3018 rkisp_iowrite32(params_vdev, value, ISP21_CNR_HBF5);
3019
3020 value = ISP2X_PACK_2SHORT(arg->sw_cnr_lbf3_sigma, arg->sw_cnr_lbf5_weit_src);
3021 rkisp_iowrite32(params_vdev, value, ISP21_CNR_LBF3);
3022 }
3023
3024 static void
isp_cnr_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,const struct isp21_cnr_cfg * arg)3025 isp_cnr_enable(struct rkisp_isp_params_vdev *params_vdev,
3026 bool en, const struct isp21_cnr_cfg *arg)
3027 {
3028 u32 cnr_ctrl, value = 0;
3029 bool real_en;
3030
3031 if (arg) {
3032 value = (arg->sw_cnr_thumb_mix_cur_en & 0x1) << 4 |
3033 (arg->sw_cnr_lq_bila_bypass & 0x1) << 3 |
3034 (arg->sw_cnr_hq_bila_bypass & 0x1) << 2 |
3035 (arg->sw_cnr_exgain_bypass & 0x1) << 1;
3036 }
3037
3038 cnr_ctrl = rkisp_ioread32(params_vdev, ISP21_CNR_CTRL);
3039 real_en = !!(cnr_ctrl & ISP21_CNR_EN);
3040 if ((en && real_en) || (!en && !real_en))
3041 return;
3042
3043 if (en) {
3044 value |= ISP21_CNR_EN;
3045 rkisp_set_bits(params_vdev->dev, ISP_CTRL1,
3046 ISP2X_SYS_CNR_FST, ISP2X_SYS_CNR_FST, false);
3047 }
3048
3049 rkisp_iowrite32(params_vdev, value, ISP21_CNR_CTRL);
3050 }
3051
3052 static void
isp_sharp_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp21_sharp_cfg * arg)3053 isp_sharp_config(struct rkisp_isp_params_vdev *params_vdev,
3054 const struct isp21_sharp_cfg *arg)
3055 {
3056 u32 value;
3057
3058 value = rkisp_ioread32(params_vdev, ISP21_SHARP_SHARP_EN);
3059 value &= ISP21_SHARP_EN;
3060
3061 value |= (arg->sw_sharp_bypass & 0x1) << 1;
3062 rkisp_iowrite32(params_vdev, value, ISP21_SHARP_SHARP_EN);
3063
3064 value = ISP2X_PACK_4BYTE(arg->sw_sharp_pbf_ratio, arg->sw_sharp_gaus_ratio,
3065 arg->sw_sharp_bf_ratio, arg->sw_sharp_sharp_ratio);
3066 rkisp_iowrite32(params_vdev, value, ISP21_SHARP_SHARP_RATIO);
3067
3068 value = (arg->sw_sharp_luma_dx[6] & 0x0F) << 24 |
3069 (arg->sw_sharp_luma_dx[5] & 0x0F) << 20 |
3070 (arg->sw_sharp_luma_dx[4] & 0x0F) << 16 |
3071 (arg->sw_sharp_luma_dx[3] & 0x0F) << 12 |
3072 (arg->sw_sharp_luma_dx[2] & 0x0F) << 8 |
3073 (arg->sw_sharp_luma_dx[1] & 0x0F) << 4 |
3074 (arg->sw_sharp_luma_dx[0] & 0x0F);
3075 rkisp_iowrite32(params_vdev, value, ISP21_SHARP_SHARP_LUMA_DX);
3076
3077 value = (arg->sw_sharp_pbf_sigma_inv[2] & 0x3FF) << 20 |
3078 (arg->sw_sharp_pbf_sigma_inv[1] & 0x3FF) << 10 |
3079 (arg->sw_sharp_pbf_sigma_inv[0] & 0x3FF);
3080 rkisp_iowrite32(params_vdev, value, ISP21_SHARP_SHARP_PBF_SIGMA_INV_0);
3081
3082 value = (arg->sw_sharp_pbf_sigma_inv[5] & 0x3FF) << 20 |
3083 (arg->sw_sharp_pbf_sigma_inv[4] & 0x3FF) << 10 |
3084 (arg->sw_sharp_pbf_sigma_inv[3] & 0x3FF);
3085 rkisp_iowrite32(params_vdev, value, ISP21_SHARP_SHARP_PBF_SIGMA_INV_1);
3086
3087 value = (arg->sw_sharp_pbf_sigma_inv[7] & 0x3FF) << 10 |
3088 (arg->sw_sharp_pbf_sigma_inv[6] & 0x3FF);
3089 rkisp_iowrite32(params_vdev, value, ISP21_SHARP_SHARP_PBF_SIGMA_INV_2);
3090
3091 value = (arg->sw_sharp_bf_sigma_inv[2] & 0x3FF) << 20 |
3092 (arg->sw_sharp_bf_sigma_inv[1] & 0x3FF) << 10 |
3093 (arg->sw_sharp_bf_sigma_inv[0] & 0x3FF);
3094 rkisp_iowrite32(params_vdev, value, ISP21_SHARP_SHARP_BF_SIGMA_INV_0);
3095
3096 value = (arg->sw_sharp_bf_sigma_inv[5] & 0x3FF) << 20 |
3097 (arg->sw_sharp_bf_sigma_inv[4] & 0x3FF) << 10 |
3098 (arg->sw_sharp_bf_sigma_inv[3] & 0x3FF);
3099 rkisp_iowrite32(params_vdev, value, ISP21_SHARP_SHARP_BF_SIGMA_INV_1);
3100
3101 value = (arg->sw_sharp_bf_sigma_inv[7] & 0x3FF) << 10 |
3102 (arg->sw_sharp_bf_sigma_inv[6] & 0x3FF);
3103 rkisp_iowrite32(params_vdev, value, ISP21_SHARP_SHARP_BF_SIGMA_INV_2);
3104
3105 value = (arg->sw_sharp_bf_sigma_shift & 0x0F) << 4 |
3106 (arg->sw_sharp_pbf_sigma_shift & 0x0F);
3107 rkisp_iowrite32(params_vdev, value, ISP21_SHARP_SHARP_SIGMA_SHIFT);
3108
3109 value = (arg->sw_sharp_ehf_th[2] & 0x3FF) << 20 |
3110 (arg->sw_sharp_ehf_th[1] & 0x3FF) << 10 |
3111 (arg->sw_sharp_ehf_th[0] & 0x3FF);
3112 rkisp_iowrite32(params_vdev, value, ISP21_SHARP_SHARP_EHF_TH_0);
3113
3114 value = (arg->sw_sharp_ehf_th[5] & 0x3FF) << 20 |
3115 (arg->sw_sharp_ehf_th[4] & 0x3FF) << 10 |
3116 (arg->sw_sharp_ehf_th[3] & 0x3FF);
3117 rkisp_iowrite32(params_vdev, value, ISP21_SHARP_SHARP_EHF_TH_1);
3118
3119 value = (arg->sw_sharp_ehf_th[7] & 0x3FF) << 10 |
3120 (arg->sw_sharp_ehf_th[6] & 0x3FF);
3121 rkisp_iowrite32(params_vdev, value, ISP21_SHARP_SHARP_EHF_TH_2);
3122
3123 value = (arg->sw_sharp_clip_hf[2] & 0x3FF) << 20 |
3124 (arg->sw_sharp_clip_hf[1] & 0x3FF) << 10 |
3125 (arg->sw_sharp_clip_hf[0] & 0x3FF);
3126 rkisp_iowrite32(params_vdev, value, ISP21_SHARP_SHARP_CLIP_HF_0);
3127
3128 value = (arg->sw_sharp_clip_hf[5] & 0x3FF) << 20 |
3129 (arg->sw_sharp_clip_hf[4] & 0x3FF) << 10 |
3130 (arg->sw_sharp_clip_hf[3] & 0x3FF);
3131 rkisp_iowrite32(params_vdev, value, ISP21_SHARP_SHARP_CLIP_HF_1);
3132
3133 value = (arg->sw_sharp_clip_hf[7] & 0x3FF) << 10 |
3134 (arg->sw_sharp_clip_hf[6] & 0x3FF);
3135 rkisp_iowrite32(params_vdev, value, ISP21_SHARP_SHARP_CLIP_HF_2);
3136
3137 value = ISP2X_PACK_4BYTE(arg->sw_sharp_pbf_coef_0, arg->sw_sharp_pbf_coef_1,
3138 arg->sw_sharp_pbf_coef_2, 0);
3139 rkisp_iowrite32(params_vdev, value, ISP21_SHARP_SHARP_PBF_COEF);
3140
3141 value = ISP2X_PACK_4BYTE(arg->sw_sharp_bf_coef_0, arg->sw_sharp_bf_coef_1,
3142 arg->sw_sharp_bf_coef_2, 0);
3143 rkisp_iowrite32(params_vdev, value, ISP21_SHARP_SHARP_BF_COEF);
3144
3145 value = ISP2X_PACK_4BYTE(arg->sw_sharp_gaus_coef_0, arg->sw_sharp_gaus_coef_1,
3146 arg->sw_sharp_gaus_coef_2, 0);
3147 rkisp_iowrite32(params_vdev, value, ISP21_SHARP_SHARP_GAUS_COEF);
3148 }
3149
3150 static void
isp_sharp_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)3151 isp_sharp_enable(struct rkisp_isp_params_vdev *params_vdev,
3152 bool en)
3153 {
3154 u32 value;
3155
3156 value = rkisp_ioread32(params_vdev, ISP21_SHARP_SHARP_EN);
3157 value &= ~ISP21_SHARP_EN;
3158
3159 if (en)
3160 value |= ISP21_SHARP_EN;
3161
3162 rkisp_iowrite32(params_vdev, value, ISP21_SHARP_SHARP_EN);
3163 }
3164
3165 static void
isp_baynr_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp21_baynr_cfg * arg)3166 isp_baynr_config(struct rkisp_isp_params_vdev *params_vdev,
3167 const struct isp21_baynr_cfg *arg)
3168 {
3169 u32 i, value;
3170
3171 value = rkisp_ioread32(params_vdev, ISP21_BAYNR_CTRL);
3172 value &= ISP21_BAYNR_EN;
3173
3174 value |= (arg->sw_baynr_gauss_en & 0x1) << 8 |
3175 (arg->sw_baynr_log_bypass & 0x1) << 4;
3176 rkisp_iowrite32(params_vdev, value, ISP21_BAYNR_CTRL);
3177
3178 value = ISP2X_PACK_2SHORT(arg->sw_baynr_dgain0, arg->sw_baynr_dgain1);
3179 rkisp_iowrite32(params_vdev, value, ISP21_BAYNR_DGAIN0);
3180
3181 rkisp_iowrite32(params_vdev, arg->sw_baynr_dgain2, ISP21_BAYNR_DGAIN1);
3182 rkisp_iowrite32(params_vdev, arg->sw_baynr_pix_diff, ISP21_BAYNR_PIXDIFF);
3183
3184 value = ISP2X_PACK_2SHORT(arg->sw_baynr_softthld, arg->sw_baynr_diff_thld);
3185 rkisp_iowrite32(params_vdev, value, ISP21_BAYNR_THLD);
3186
3187 value = ISP2X_PACK_2SHORT(arg->sw_baynr_reg_w1, arg->sw_bltflt_streng);
3188 rkisp_iowrite32(params_vdev, value, ISP21_BAYNR_W1_STRENG);
3189
3190 for (i = 0; i < ISP21_BAYNR_XY_NUM / 2; i++) {
3191 value = ISP2X_PACK_2SHORT(arg->sw_sigma_x[2 * i], arg->sw_sigma_x[2 * i + 1]);
3192 rkisp_iowrite32(params_vdev, value, ISP21_BAYNR_SIGMAX01 + 4 * i);
3193 }
3194
3195 for (i = 0; i < ISP21_BAYNR_XY_NUM / 2; i++) {
3196 value = ISP2X_PACK_2SHORT(arg->sw_sigma_y[2 * i], arg->sw_sigma_y[2 * i + 1]);
3197 rkisp_iowrite32(params_vdev, value, ISP21_BAYNR_SIGMAY01 + 4 * i);
3198 }
3199
3200 value = (arg->weit_d2 & 0x3FF) << 20 |
3201 (arg->weit_d1 & 0x3FF) << 10 |
3202 (arg->weit_d0 & 0x3FF);
3203 rkisp_iowrite32(params_vdev, value, ISP21_BAYNR_WRIT_D);
3204 }
3205
3206 static void
isp_baynr_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)3207 isp_baynr_enable(struct rkisp_isp_params_vdev *params_vdev,
3208 bool en)
3209 {
3210 u32 value;
3211
3212 value = rkisp_ioread32(params_vdev, ISP21_BAYNR_CTRL);
3213 value &= ~ISP21_BAYNR_EN;
3214
3215 if (en)
3216 value |= ISP21_BAYNR_EN;
3217
3218 rkisp_iowrite32(params_vdev, value, ISP21_BAYNR_CTRL);
3219 }
3220
3221 static void
isp_bay3d_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp21_bay3d_cfg * arg)3222 isp_bay3d_config(struct rkisp_isp_params_vdev *params_vdev,
3223 const struct isp21_bay3d_cfg *arg)
3224 {
3225 u32 i, value;
3226
3227 value = rkisp_ioread32(params_vdev, ISP21_BAY3D_CTRL);
3228 value &= ISP21_BAY3D_EN;
3229
3230 value |= (arg->sw_bay3d_exp_sel & 0x1) << 16 |
3231 (arg->sw_bay3d_bypass_en & 0x1) << 12 |
3232 (arg->sw_bay3d_pk_en & 0x1) << 4;
3233 rkisp_iowrite32(params_vdev, value, ISP21_BAY3D_CTRL);
3234
3235 value = ISP2X_PACK_2SHORT(arg->sw_bay3d_sigratio, arg->sw_bay3d_softwgt);
3236 rkisp_iowrite32(params_vdev, value, ISP21_BAY3D_KALRATIO);
3237
3238 rkisp_iowrite32(params_vdev, arg->sw_bay3d_glbpk2, ISP21_BAY3D_GLBPK2);
3239
3240 value = ISP2X_PACK_2SHORT(arg->sw_bay3d_str, arg->sw_bay3d_exp_str);
3241 rkisp_iowrite32(params_vdev, value, ISP21_BAY3D_KALSTR);
3242
3243 value = ISP2X_PACK_2SHORT(arg->sw_bay3d_wgtlmt_l, arg->sw_bay3d_wgtlmt_h);
3244 rkisp_iowrite32(params_vdev, value, ISP21_BAY3D_WGTLMT);
3245
3246 for (i = 0; i < ISP21_BAY3D_XY_NUM / 2; i++) {
3247 value = ISP2X_PACK_2SHORT(arg->sw_bay3d_sig_x[2 * i],
3248 arg->sw_bay3d_sig_x[2 * i + 1]);
3249 rkisp_iowrite32(params_vdev, value, ISP21_BAY3D_SIG_X0 + 4 * i);
3250 }
3251
3252 for (i = 0; i < ISP21_BAY3D_XY_NUM / 2; i++) {
3253 value = ISP2X_PACK_2SHORT(arg->sw_bay3d_sig_y[2 * i],
3254 arg->sw_bay3d_sig_y[2 * i + 1]);
3255 rkisp_iowrite32(params_vdev, value, ISP21_BAY3D_SIG_Y0 + 4 * i);
3256 }
3257 }
3258
3259 static void
isp_bay3d_enable(struct rkisp_isp_params_vdev * params_vdev,bool en)3260 isp_bay3d_enable(struct rkisp_isp_params_vdev *params_vdev,
3261 bool en)
3262 {
3263 struct rkisp_device *ispdev = params_vdev->dev;
3264 struct rkisp_isp_params_val_v21 *priv_val;
3265 u32 value, bay3d_ctrl;
3266
3267 priv_val = (struct rkisp_isp_params_val_v21 *)params_vdev->priv_val;
3268 bay3d_ctrl = rkisp_ioread32(params_vdev, ISP21_BAY3D_CTRL);
3269 if ((en && (bay3d_ctrl & ISP21_BAY3D_EN)) ||
3270 (!en && !(bay3d_ctrl & ISP21_BAY3D_EN)))
3271 return;
3272
3273 if (en) {
3274 if (!priv_val->buf_3dnr.size) {
3275 dev_err(ispdev->dev, "no bay3d buffer available\n");
3276 return;
3277 }
3278
3279 value = priv_val->buf_3dnr.size;
3280 rkisp_iowrite32(params_vdev, value, ISP21_MI_BAY3D_WR_SIZE);
3281 value = priv_val->buf_3dnr.dma_addr;
3282 rkisp_iowrite32(params_vdev, value, ISP21_MI_BAY3D_WR_BASE);
3283 rkisp_iowrite32(params_vdev, value, ISP21_MI_BAY3D_RD_BASE);
3284
3285 rkisp_set_bits(params_vdev->dev, MI_RD_CTRL2,
3286 BAY3D_RW_ONEADDR_EN, BAY3D_RW_ONEADDR_EN, false);
3287 rkisp_set_bits(params_vdev->dev, MI_WR_CTRL2,
3288 SW_BAY3D_WR_AUTOUPD | SW_BAY3D_FORCEUPD,
3289 SW_BAY3D_WR_AUTOUPD | SW_BAY3D_FORCEUPD, false);
3290
3291 rkisp_set_bits(params_vdev->dev, ISP_CTRL1,
3292 ISP2X_SYS_BAY3D_FST, ISP2X_SYS_BAY3D_FST, false);
3293
3294 bay3d_ctrl |= ISP21_BAY3D_EN;
3295 } else {
3296 bay3d_ctrl &= ~ISP21_BAY3D_EN;
3297 }
3298
3299 rkisp_iowrite32(params_vdev, bay3d_ctrl, ISP21_BAY3D_CTRL);
3300 }
3301
3302 static void
isp_csm_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp21_csm_cfg * arg)3303 isp_csm_config(struct rkisp_isp_params_vdev *params_vdev,
3304 const struct isp21_csm_cfg *arg)
3305 {
3306 u32 i, val, eff_ctrl, cproc_ctrl;
3307
3308 for (i = 0; i < ISP21_CSM_COEFF_NUM; i++) {
3309 if (i == 0)
3310 val = (arg->csm_y_offset & 0x3f) << 24 |
3311 (arg->csm_c_offset & 0xff) << 16 |
3312 (arg->csm_coeff[i] & 0x1ff);
3313 else
3314 val = arg->csm_coeff[i] & 0x1ff;
3315 rkisp_iowrite32(params_vdev, val, ISP_CC_COEFF_0 + i * 4);
3316 }
3317
3318 val = CIF_ISP_CTRL_ISP_CSM_Y_FULL_ENA | CIF_ISP_CTRL_ISP_CSM_C_FULL_ENA;
3319 if (arg->csm_full_range) {
3320 params_vdev->quantization = V4L2_QUANTIZATION_FULL_RANGE;
3321 isp_param_set_bits(params_vdev, ISP_CTRL, val);
3322 } else {
3323 params_vdev->quantization = V4L2_QUANTIZATION_LIM_RANGE;
3324 isp_param_clear_bits(params_vdev, ISP_CTRL, val);
3325 }
3326
3327 eff_ctrl = rkisp_ioread32(params_vdev, CIF_IMG_EFF_CTRL);
3328 if (eff_ctrl & CIF_IMG_EFF_CTRL_ENABLE) {
3329 if (arg->csm_full_range)
3330 eff_ctrl |= CIF_IMG_EFF_CTRL_YCBCR_FULL;
3331 else
3332 eff_ctrl &= ~CIF_IMG_EFF_CTRL_YCBCR_FULL;
3333 rkisp_iowrite32(params_vdev, eff_ctrl, CIF_IMG_EFF_CTRL);
3334 }
3335
3336 cproc_ctrl = rkisp_ioread32(params_vdev, CPROC_CTRL);
3337 if (cproc_ctrl & CIF_C_PROC_CTR_ENABLE) {
3338 val = CIF_C_PROC_YOUT_FULL | CIF_C_PROC_YIN_FULL | CIF_C_PROC_COUT_FULL;
3339 if (eff_ctrl & CIF_IMG_EFF_CTRL_ENABLE || !arg->csm_full_range)
3340 cproc_ctrl &= ~val;
3341 else
3342 cproc_ctrl |= val;
3343 rkisp_iowrite32(params_vdev, cproc_ctrl, CPROC_CTRL);
3344 }
3345 }
3346
3347 struct rkisp_isp_params_v21_ops rkisp_v21_isp_params_ops = {
3348 .dpcc_config = isp_dpcc_config,
3349 .dpcc_enable = isp_dpcc_enable,
3350 .bls_config = isp_bls_config,
3351 .bls_enable = isp_bls_enable,
3352 .sdg_config = isp_sdg_config,
3353 .sdg_enable = isp_sdg_enable,
3354 .lsc_config = isp_lsc_config,
3355 .lsc_enable = isp_lsc_enable,
3356 .awbgain_config = isp_awbgain_config,
3357 .awbgain_enable = isp_awbgain_enable,
3358 .debayer_config = isp_debayer_config,
3359 .debayer_enable = isp_debayer_enable,
3360 .ccm_config = isp_ccm_config,
3361 .ccm_enable = isp_ccm_enable,
3362 .goc_config = isp_goc_config,
3363 .goc_enable = isp_goc_enable,
3364 .cproc_config = isp_cproc_config,
3365 .cproc_enable = isp_cproc_enable,
3366 .ie_config = isp_ie_config,
3367 .ie_enable = isp_ie_enable,
3368 .rawaf_config = isp_rawaf_config,
3369 .rawaf_enable = isp_rawaf_enable,
3370 .rawae0_config = isp_rawaelite_config,
3371 .rawae0_enable = isp_rawaelite_enable,
3372 .rawae1_config = isp_rawae1_config,
3373 .rawae1_enable = isp_rawae1_enable,
3374 .rawae2_config = isp_rawae2_config,
3375 .rawae2_enable = isp_rawae2_enable,
3376 .rawae3_config = isp_rawae3_config,
3377 .rawae3_enable = isp_rawae3_enable,
3378 .rawawb_config = isp_rawawb_config,
3379 .rawawb_enable = isp_rawawb_enable,
3380 .rawhst0_config = isp_rawhstlite_config,
3381 .rawhst0_enable = isp_rawhstlite_enable,
3382 .rawhst1_config = isp_rawhst1_config,
3383 .rawhst1_enable = isp_rawhst1_enable,
3384 .rawhst2_config = isp_rawhst2_config,
3385 .rawhst2_enable = isp_rawhst2_enable,
3386 .rawhst3_config = isp_rawhst3_config,
3387 .rawhst3_enable = isp_rawhst3_enable,
3388 .hdrmge_config = isp_hdrmge_config,
3389 .hdrmge_enable = isp_hdrmge_enable,
3390 .hdrdrc_config = isp_hdrdrc_config,
3391 .hdrdrc_enable = isp_hdrdrc_enable,
3392 .gic_config = isp_gic_config,
3393 .gic_enable = isp_gic_enable,
3394 .dhaz_config = isp_dhaz_config,
3395 .dhaz_enable = isp_dhaz_enable,
3396 .isp3dlut_config = isp_3dlut_config,
3397 .isp3dlut_enable = isp_3dlut_enable,
3398 .ldch_config = isp_ldch_config,
3399 .ldch_enable = isp_ldch_enable,
3400 .ynr_config = isp_ynr_config,
3401 .ynr_enable = isp_ynr_enable,
3402 .cnr_config = isp_cnr_config,
3403 .cnr_enable = isp_cnr_enable,
3404 .sharp_config = isp_sharp_config,
3405 .sharp_enable = isp_sharp_enable,
3406 .baynr_config = isp_baynr_config,
3407 .baynr_enable = isp_baynr_enable,
3408 .bay3d_config = isp_bay3d_config,
3409 .bay3d_enable = isp_bay3d_enable,
3410 .csm_config = isp_csm_config,
3411 };
3412
3413 static __maybe_unused
__isp_isr_other_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp21_isp_params_cfg * new_params,enum rkisp_params_type type)3414 void __isp_isr_other_config(struct rkisp_isp_params_vdev *params_vdev,
3415 const struct isp21_isp_params_cfg *new_params,
3416 enum rkisp_params_type type)
3417 {
3418 struct rkisp_isp_params_v21_ops *ops =
3419 (struct rkisp_isp_params_v21_ops *)params_vdev->priv_ops;
3420 u64 module_cfg_update = new_params->module_cfg_update;
3421
3422 if (type == RKISP_PARAMS_SHD) {
3423 if ((module_cfg_update & ISP2X_MODULE_HDRMGE))
3424 ops->hdrmge_config(params_vdev, &new_params->others.hdrmge_cfg, type);
3425
3426 if ((module_cfg_update & ISP2X_MODULE_DRC))
3427 ops->hdrdrc_config(params_vdev, &new_params->others.drc_cfg, type);
3428 return;
3429 }
3430
3431 if ((module_cfg_update & ISP2X_MODULE_DPCC))
3432 ops->dpcc_config(params_vdev, &new_params->others.dpcc_cfg);
3433
3434 if ((module_cfg_update & ISP2X_MODULE_BLS))
3435 ops->bls_config(params_vdev, &new_params->others.bls_cfg);
3436
3437 if ((module_cfg_update & ISP2X_MODULE_SDG))
3438 ops->sdg_config(params_vdev, &new_params->others.sdg_cfg);
3439
3440 if ((module_cfg_update & ISP2X_MODULE_LSC))
3441 ops->lsc_config(params_vdev, &new_params->others.lsc_cfg);
3442
3443 if ((module_cfg_update & ISP2X_MODULE_AWB_GAIN))
3444 ops->awbgain_config(params_vdev, &new_params->others.awb_gain_cfg);
3445
3446 if ((module_cfg_update & ISP2X_MODULE_DEBAYER))
3447 ops->debayer_config(params_vdev, &new_params->others.debayer_cfg);
3448
3449 if ((module_cfg_update & ISP2X_MODULE_CCM))
3450 ops->ccm_config(params_vdev, &new_params->others.ccm_cfg);
3451
3452 if ((module_cfg_update & ISP2X_MODULE_GOC))
3453 ops->goc_config(params_vdev, &new_params->others.gammaout_cfg);
3454
3455 if ((module_cfg_update & ISP2X_MODULE_CSM))
3456 ops->csm_config(params_vdev, &new_params->others.csm_cfg);
3457
3458 if ((module_cfg_update & ISP2X_MODULE_CPROC))
3459 ops->cproc_config(params_vdev, &new_params->others.cproc_cfg);
3460
3461 if ((module_cfg_update & ISP2X_MODULE_IE))
3462 ops->ie_config(params_vdev, &new_params->others.ie_cfg);
3463
3464 if ((module_cfg_update & ISP2X_MODULE_HDRMGE))
3465 ops->hdrmge_config(params_vdev, &new_params->others.hdrmge_cfg, type);
3466
3467 if ((module_cfg_update & ISP2X_MODULE_DRC))
3468 ops->hdrdrc_config(params_vdev, &new_params->others.drc_cfg, type);
3469
3470 if ((module_cfg_update & ISP2X_MODULE_GIC))
3471 ops->gic_config(params_vdev, &new_params->others.gic_cfg);
3472
3473 if ((module_cfg_update & ISP2X_MODULE_DHAZ))
3474 ops->dhaz_config(params_vdev, &new_params->others.dhaz_cfg);
3475
3476 if ((module_cfg_update & ISP2X_MODULE_3DLUT))
3477 ops->isp3dlut_config(params_vdev, &new_params->others.isp3dlut_cfg);
3478
3479 if ((module_cfg_update & ISP2X_MODULE_LDCH))
3480 ops->ldch_config(params_vdev, &new_params->others.ldch_cfg);
3481
3482 if ((module_cfg_update & ISP2X_MODULE_YNR))
3483 ops->ynr_config(params_vdev, &new_params->others.ynr_cfg);
3484
3485 if ((module_cfg_update & ISP2X_MODULE_CNR))
3486 ops->cnr_config(params_vdev, &new_params->others.cnr_cfg);
3487
3488 if ((module_cfg_update & ISP2X_MODULE_SHARP))
3489 ops->sharp_config(params_vdev, &new_params->others.sharp_cfg);
3490
3491 if ((module_cfg_update & ISP2X_MODULE_BAYNR))
3492 ops->baynr_config(params_vdev, &new_params->others.baynr_cfg);
3493
3494 if ((module_cfg_update & ISP2X_MODULE_BAY3D))
3495 ops->bay3d_config(params_vdev, &new_params->others.bay3d_cfg);
3496 }
3497
3498 static __maybe_unused
__isp_isr_other_en(struct rkisp_isp_params_vdev * params_vdev,const struct isp21_isp_params_cfg * new_params,enum rkisp_params_type type)3499 void __isp_isr_other_en(struct rkisp_isp_params_vdev *params_vdev,
3500 const struct isp21_isp_params_cfg *new_params,
3501 enum rkisp_params_type type)
3502 {
3503 struct rkisp_isp_params_v21_ops *ops =
3504 (struct rkisp_isp_params_v21_ops *)params_vdev->priv_ops;
3505 struct rkisp_isp_params_val_v21 *priv_val =
3506 (struct rkisp_isp_params_val_v21 *)params_vdev->priv_val;
3507 struct rkisp_device *ispdev = params_vdev->dev;
3508 bool is_feature_on = ispdev->hw_dev->is_feature_on;
3509 u64 iq_feature = ispdev->hw_dev->iq_feature;
3510 u64 module_en_update = new_params->module_en_update;
3511 u64 module_ens = new_params->module_ens;
3512
3513 if (type == RKISP_PARAMS_SHD)
3514 return;
3515
3516 if (is_feature_on) {
3517 module_en_update &= ~ISP2X_MODULE_HDRMGE;
3518 if (module_en_update & ~iq_feature) {
3519 dev_err(ispdev->dev,
3520 "some iq features(0x%llx, 0x%llx) are not supported\n",
3521 module_en_update, iq_feature);
3522 module_en_update &= iq_feature;
3523 }
3524 }
3525
3526 if (module_en_update & ISP2X_MODULE_HDRMGE) {
3527 ops->hdrmge_enable(params_vdev, !!(module_ens & ISP2X_MODULE_HDRMGE));
3528 priv_val->mge_en = !!(module_ens & ISP2X_MODULE_HDRMGE);
3529 }
3530
3531 if (module_en_update & ISP2X_MODULE_DRC)
3532 ops->hdrdrc_enable(params_vdev, !!(module_ens & ISP2X_MODULE_DRC));
3533
3534 if (module_en_update & ISP2X_MODULE_DPCC)
3535 ops->dpcc_enable(params_vdev, !!(module_ens & ISP2X_MODULE_DPCC));
3536
3537 if (module_en_update & ISP2X_MODULE_BLS)
3538 ops->bls_enable(params_vdev, !!(module_ens & ISP2X_MODULE_BLS));
3539
3540 if (module_en_update & ISP2X_MODULE_SDG)
3541 ops->sdg_enable(params_vdev, !!(module_ens & ISP2X_MODULE_SDG));
3542
3543 if (module_en_update & ISP2X_MODULE_LSC) {
3544 ops->lsc_enable(params_vdev, !!(module_ens & ISP2X_MODULE_LSC));
3545 priv_val->lsc_en = !!(module_ens & ISP2X_MODULE_LSC);
3546 }
3547
3548 if (module_en_update & ISP2X_MODULE_AWB_GAIN)
3549 ops->awbgain_enable(params_vdev, !!(module_ens & ISP2X_MODULE_AWB_GAIN));
3550
3551 if (module_en_update & ISP2X_MODULE_DEBAYER)
3552 ops->debayer_enable(params_vdev, !!(module_ens & ISP2X_MODULE_DEBAYER));
3553
3554 if (module_en_update & ISP2X_MODULE_CCM)
3555 ops->ccm_enable(params_vdev, !!(module_ens & ISP2X_MODULE_CCM));
3556
3557 if (module_en_update & ISP2X_MODULE_GOC)
3558 ops->goc_enable(params_vdev, !!(module_ens & ISP2X_MODULE_GOC));
3559
3560 if (module_en_update & ISP2X_MODULE_CPROC)
3561 ops->cproc_enable(params_vdev, !!(module_ens & ISP2X_MODULE_CPROC));
3562
3563 if (module_en_update & ISP2X_MODULE_IE)
3564 ops->ie_enable(params_vdev, !!(module_ens & ISP2X_MODULE_IE));
3565
3566 if (module_en_update & ISP2X_MODULE_HDRMGE) {
3567 ops->hdrmge_enable(params_vdev, !!(module_ens & ISP2X_MODULE_HDRMGE));
3568 priv_val->mge_en = !!(module_ens & ISP2X_MODULE_HDRMGE);
3569 }
3570
3571 if (module_en_update & ISP2X_MODULE_DRC)
3572 ops->hdrdrc_enable(params_vdev, !!(module_ens & ISP2X_MODULE_DRC));
3573
3574 if (module_en_update & ISP2X_MODULE_GIC)
3575 ops->gic_enable(params_vdev, !!(module_ens & ISP2X_MODULE_GIC));
3576
3577 if (module_en_update & ISP2X_MODULE_DHAZ) {
3578 ops->dhaz_enable(params_vdev, !!(module_ens & ISP2X_MODULE_DHAZ));
3579 priv_val->dhaz_en = !!(module_ens & ISP2X_MODULE_DHAZ);
3580 }
3581
3582 if (module_en_update & ISP2X_MODULE_3DLUT)
3583 ops->isp3dlut_enable(params_vdev, !!(module_ens & ISP2X_MODULE_3DLUT));
3584
3585 if (module_en_update & ISP2X_MODULE_LDCH)
3586 ops->ldch_enable(params_vdev, !!(module_ens & ISP2X_MODULE_LDCH));
3587
3588 if (module_en_update & ISP2X_MODULE_YNR)
3589 ops->ynr_enable(params_vdev, !!(module_ens & ISP2X_MODULE_YNR), &new_params->others.ynr_cfg);
3590
3591 if (module_en_update & ISP2X_MODULE_CNR)
3592 ops->cnr_enable(params_vdev, !!(module_ens & ISP2X_MODULE_CNR), &new_params->others.cnr_cfg);
3593
3594 if (module_en_update & ISP2X_MODULE_SHARP)
3595 ops->sharp_enable(params_vdev, !!(module_ens & ISP2X_MODULE_SHARP));
3596
3597 if (module_en_update & ISP2X_MODULE_BAYNR)
3598 ops->baynr_enable(params_vdev, !!(module_ens & ISP2X_MODULE_BAYNR));
3599
3600 if (module_en_update & ISP2X_MODULE_BAY3D)
3601 ops->bay3d_enable(params_vdev, !!(module_ens & ISP2X_MODULE_BAY3D));
3602 }
3603
3604 static __maybe_unused
__isp_isr_meas_config(struct rkisp_isp_params_vdev * params_vdev,struct isp21_isp_params_cfg * new_params,enum rkisp_params_type type)3605 void __isp_isr_meas_config(struct rkisp_isp_params_vdev *params_vdev,
3606 struct isp21_isp_params_cfg *new_params,
3607 enum rkisp_params_type type)
3608 {
3609 struct rkisp_isp_params_v21_ops *ops =
3610 (struct rkisp_isp_params_v21_ops *)params_vdev->priv_ops;
3611 u64 module_cfg_update = new_params->module_cfg_update;
3612
3613 if (type == RKISP_PARAMS_SHD)
3614 return;
3615
3616 if ((module_cfg_update & ISP2X_MODULE_RAWAE0))
3617 ops->rawae0_config(params_vdev, &new_params->meas.rawae0);
3618
3619 if ((module_cfg_update & ISP2X_MODULE_RAWAE1))
3620 ops->rawae1_config(params_vdev, &new_params->meas.rawae1);
3621
3622 if ((module_cfg_update & ISP2X_MODULE_RAWAE2))
3623 ops->rawae2_config(params_vdev, &new_params->meas.rawae2);
3624
3625 if ((module_cfg_update & ISP2X_MODULE_RAWAE3))
3626 ops->rawae3_config(params_vdev, &new_params->meas.rawae3);
3627
3628 if ((module_cfg_update & ISP2X_MODULE_RAWHIST0))
3629 ops->rawhst0_config(params_vdev, &new_params->meas.rawhist0);
3630
3631 if ((module_cfg_update & ISP2X_MODULE_RAWHIST1))
3632 ops->rawhst1_config(params_vdev, &new_params->meas.rawhist1);
3633
3634 if ((module_cfg_update & ISP2X_MODULE_RAWHIST2))
3635 ops->rawhst2_config(params_vdev, &new_params->meas.rawhist2);
3636
3637 if ((module_cfg_update & ISP2X_MODULE_RAWHIST3))
3638 ops->rawhst3_config(params_vdev, &new_params->meas.rawhist3);
3639
3640 if ((module_cfg_update & ISP2X_MODULE_RAWAWB))
3641 ops->rawawb_config(params_vdev, &new_params->meas.rawawb);
3642
3643 if ((module_cfg_update & ISP2X_MODULE_RAWAF))
3644 ops->rawaf_config(params_vdev, &new_params->meas.rawaf);
3645 }
3646
3647 static __maybe_unused
__isp_isr_meas_en(struct rkisp_isp_params_vdev * params_vdev,struct isp21_isp_params_cfg * new_params,enum rkisp_params_type type)3648 void __isp_isr_meas_en(struct rkisp_isp_params_vdev *params_vdev,
3649 struct isp21_isp_params_cfg *new_params,
3650 enum rkisp_params_type type)
3651 {
3652 struct rkisp_isp_params_v21_ops *ops =
3653 (struct rkisp_isp_params_v21_ops *)params_vdev->priv_ops;
3654 struct rkisp_device *ispdev = params_vdev->dev;
3655 bool is_feature_on = ispdev->hw_dev->is_feature_on;
3656 u64 iq_feature = ispdev->hw_dev->iq_feature;
3657 u64 module_en_update = new_params->module_en_update;
3658 u64 module_ens = new_params->module_ens;
3659
3660 if (type == RKISP_PARAMS_SHD)
3661 return;
3662
3663 if (is_feature_on) {
3664 module_en_update &= ~ISP2X_MODULE_HDRMGE;
3665 if (module_en_update & ~iq_feature) {
3666 dev_err(ispdev->dev,
3667 "some iq features(0x%llx, 0x%llx) are not supported\n",
3668 module_en_update, iq_feature);
3669 module_en_update &= iq_feature;
3670 }
3671 }
3672
3673 if (module_en_update & ISP2X_MODULE_RAWAE0)
3674 ops->rawae0_enable(params_vdev, !!(module_ens & ISP2X_MODULE_RAWAE0));
3675
3676 if (module_en_update & ISP2X_MODULE_RAWAE1)
3677 ops->rawae1_enable(params_vdev, !!(module_ens & ISP2X_MODULE_RAWAE1));
3678
3679 if (module_en_update & ISP2X_MODULE_RAWAE2)
3680 ops->rawae2_enable(params_vdev, !!(module_ens & ISP2X_MODULE_RAWAE2));
3681
3682 if (module_en_update & ISP2X_MODULE_RAWAE3)
3683 ops->rawae3_enable(params_vdev, !!(module_ens & ISP2X_MODULE_RAWAE3));
3684
3685 if (module_en_update & ISP2X_MODULE_RAWHIST0)
3686 ops->rawhst0_enable(params_vdev, !!(module_ens & ISP2X_MODULE_RAWHIST0));
3687
3688 if (module_en_update & ISP2X_MODULE_RAWHIST1)
3689 ops->rawhst1_enable(params_vdev, !!(module_ens & ISP2X_MODULE_RAWHIST1));
3690
3691 if (module_en_update & ISP2X_MODULE_RAWHIST2)
3692 ops->rawhst2_enable(params_vdev, !!(module_ens & ISP2X_MODULE_RAWHIST2));
3693
3694 if (module_en_update & ISP2X_MODULE_RAWHIST3)
3695 ops->rawhst3_enable(params_vdev, !!(module_ens & ISP2X_MODULE_RAWHIST3));
3696
3697 if (module_en_update & ISP2X_MODULE_RAWAWB)
3698 ops->rawawb_enable(params_vdev, !!(module_ens & ISP2X_MODULE_RAWAWB));
3699
3700 if (module_en_update & ISP2X_MODULE_RAWAF)
3701 ops->rawaf_enable(params_vdev, !!(module_ens & ISP2X_MODULE_RAWAF));
3702 }
3703
3704 static __maybe_unused
__isp_config_hdrshd(struct rkisp_isp_params_vdev * params_vdev)3705 void __isp_config_hdrshd(struct rkisp_isp_params_vdev *params_vdev)
3706 {
3707 struct rkisp_isp_params_v21_ops *ops =
3708 (struct rkisp_isp_params_v21_ops *)params_vdev->priv_ops;
3709 struct rkisp_isp_params_val_v21 *priv_val =
3710 (struct rkisp_isp_params_val_v21 *)params_vdev->priv_val;
3711
3712 ops->hdrmge_config(params_vdev, &priv_val->last_hdrmge, RKISP_PARAMS_SHD);
3713
3714 ops->hdrdrc_config(params_vdev, &priv_val->last_hdrdrc, RKISP_PARAMS_SHD);
3715 }
3716
3717 static
rkisp_params_cfgsram_v21(struct rkisp_isp_params_vdev * params_vdev)3718 void rkisp_params_cfgsram_v21(struct rkisp_isp_params_vdev *params_vdev)
3719 {
3720 struct isp21_isp_params_cfg *params = params_vdev->isp21_params;
3721
3722 isp_lsc_matrix_cfg_sram(params_vdev, ¶ms->others.lsc_cfg, true);
3723 isp_rawhstbig_cfg_sram(params_vdev, ¶ms->meas.rawhist1, 1, true);
3724 isp_rawhstbig_cfg_sram(params_vdev, ¶ms->meas.rawhist2, 2, true);
3725 isp_rawhstbig_cfg_sram(params_vdev, ¶ms->meas.rawhist3, 0, true);
3726 }
3727
3728 static void
rkisp_alloc_bay3d_buf(struct rkisp_isp_params_vdev * params_vdev,const struct isp21_isp_params_cfg * new_params)3729 rkisp_alloc_bay3d_buf(struct rkisp_isp_params_vdev *params_vdev,
3730 const struct isp21_isp_params_cfg *new_params)
3731 {
3732 struct rkisp_device *ispdev = params_vdev->dev;
3733 struct rkisp_isp_subdev *isp_sdev = &ispdev->isp_sdev;
3734 struct rkisp_isp_params_val_v21 *priv_val;
3735 u64 module_en_update, module_ens;
3736 u32 w, h, size;
3737 int ret;
3738
3739 module_en_update = new_params->module_en_update;
3740 module_ens = new_params->module_ens;
3741
3742 if ((module_en_update & ISP2X_MODULE_BAY3D) &&
3743 (module_ens & ISP2X_MODULE_BAY3D)) {
3744 w = isp_sdev->in_crop.width;
3745 h = isp_sdev->in_crop.height;
3746 size = 2 * ALIGN((ALIGN(w, 16) + (w + 15) / 8) * h, 16);
3747 priv_val = (struct rkisp_isp_params_val_v21 *)params_vdev->priv_val;
3748 rkisp_free_buffer(ispdev, &priv_val->buf_3dnr);
3749
3750 priv_val->buf_3dnr.size = size;
3751 ret = rkisp_alloc_buffer(ispdev, &priv_val->buf_3dnr);
3752 if (ret)
3753 dev_err(ispdev->dev, "can not alloc bay3d buffer\n");
3754 }
3755 }
3756
3757 /* Not called when the camera active, thus not isr protection. */
3758 static void
rkisp_params_first_cfg_v2x(struct rkisp_isp_params_vdev * params_vdev)3759 rkisp_params_first_cfg_v2x(struct rkisp_isp_params_vdev *params_vdev)
3760 {
3761 struct device *dev = params_vdev->dev->dev;
3762 struct rkisp_isp_params_val_v21 *priv_val =
3763 (struct rkisp_isp_params_val_v21 *)params_vdev->priv_val;
3764 struct rkisp_hw_dev *hw = params_vdev->dev->hw_dev;
3765 struct v4l2_rect *out_crop = ¶ms_vdev->dev->isp_sdev.out_crop;
3766 u32 width = hw->max_in.w ? hw->max_in.w : out_crop->width;
3767 u32 size = hw->max_in.w ? hw->max_in.w * hw->max_in.h : isp_param_get_insize(params_vdev);
3768
3769 rkisp_alloc_bay3d_buf(params_vdev, params_vdev->isp21_params);
3770 spin_lock(¶ms_vdev->config_lock);
3771 /* override the default things */
3772 if (!params_vdev->isp21_params->module_cfg_update &&
3773 !params_vdev->isp21_params->module_en_update)
3774 dev_warn(dev, "can not get first iq setting in stream on\n");
3775
3776 priv_val->dhaz_en = 0;
3777 priv_val->wdr_en = 0;
3778 priv_val->tmo_en = 0;
3779 priv_val->lsc_en = 0;
3780 priv_val->mge_en = 0;
3781 __isp_isr_other_config(params_vdev, params_vdev->isp21_params, RKISP_PARAMS_ALL);
3782 __isp_isr_other_en(params_vdev, params_vdev->isp21_params, RKISP_PARAMS_ALL);
3783 __isp_isr_meas_config(params_vdev, params_vdev->isp21_params, RKISP_PARAMS_ALL);
3784 __isp_isr_meas_en(params_vdev, params_vdev->isp21_params, RKISP_PARAMS_ALL);
3785 if (width <= ISP2X_AUTO_BIGMODE_WIDTH && size > ISP2X_NOBIG_OVERFLOW_SIZE) {
3786 rkisp_set_bits(params_vdev->dev, ISP_CTRL1,
3787 ISP2X_SYS_BIGMODE_MANUAL | ISP2X_SYS_BIGMODE_FORCEEN,
3788 ISP2X_SYS_BIGMODE_MANUAL | ISP2X_SYS_BIGMODE_FORCEEN, false);
3789 }
3790
3791 priv_val->cur_hdrmge = params_vdev->isp21_params->others.hdrmge_cfg;
3792 priv_val->cur_hdrdrc = params_vdev->isp21_params->others.drc_cfg;
3793 priv_val->last_hdrmge = priv_val->cur_hdrmge;
3794 priv_val->last_hdrdrc = priv_val->cur_hdrdrc;
3795 spin_unlock(¶ms_vdev->config_lock);
3796 }
3797
rkisp_save_first_param_v2x(struct rkisp_isp_params_vdev * params_vdev,void * param)3798 static void rkisp_save_first_param_v2x(struct rkisp_isp_params_vdev *params_vdev, void *param)
3799 {
3800 struct isp21_isp_params_cfg *new_params;
3801
3802 new_params = (struct isp21_isp_params_cfg *)param;
3803 *params_vdev->isp21_params = *new_params;
3804 }
3805
rkisp_clear_first_param_v2x(struct rkisp_isp_params_vdev * params_vdev)3806 static void rkisp_clear_first_param_v2x(struct rkisp_isp_params_vdev *params_vdev)
3807 {
3808 params_vdev->isp21_params->module_cfg_update = 0;
3809 params_vdev->isp21_params->module_en_update = 0;
3810 }
3811
rkisp_get_ldch_meshsize(struct rkisp_isp_params_vdev * params_vdev,struct rkisp_ldchbuf_size * ldchsize)3812 static u32 rkisp_get_ldch_meshsize(struct rkisp_isp_params_vdev *params_vdev,
3813 struct rkisp_ldchbuf_size *ldchsize)
3814 {
3815 int mesh_w, mesh_h, map_align;
3816
3817 mesh_w = ((ldchsize->meas_width + (1 << 4) - 1) >> 4) + 1;
3818 mesh_h = ((ldchsize->meas_height + (1 << 3) - 1) >> 3) + 1;
3819
3820 map_align = ((mesh_w + 1) >> 1) << 1;
3821 return map_align * mesh_h;
3822 }
3823
rkisp_deinit_ldch_buf(struct rkisp_isp_params_vdev * params_vdev)3824 static void rkisp_deinit_ldch_buf(struct rkisp_isp_params_vdev *params_vdev)
3825 {
3826 struct rkisp_isp_params_val_v21 *priv_val;
3827 int i;
3828
3829 priv_val = params_vdev->priv_val;
3830 if (!priv_val)
3831 return;
3832
3833 for (i = 0; i < ISP2X_LDCH_BUF_NUM; i++)
3834 rkisp_free_buffer(params_vdev->dev, &priv_val->buf_ldch[i]);
3835 }
3836
rkisp_init_ldch_buf(struct rkisp_isp_params_vdev * params_vdev,struct rkisp_ldchbuf_size * ldchsize)3837 static int rkisp_init_ldch_buf(struct rkisp_isp_params_vdev *params_vdev,
3838 struct rkisp_ldchbuf_size *ldchsize)
3839 {
3840 struct device *dev = params_vdev->dev->dev;
3841 struct rkisp_isp_params_val_v21 *priv_val;
3842 struct isp2x_ldch_head *ldch_head;
3843 u32 mesh_size, buf_size;
3844 int i, ret;
3845
3846 priv_val = params_vdev->priv_val;
3847 if (!priv_val) {
3848 dev_err(dev, "priv_val is NULL\n");
3849 return -EINVAL;
3850 }
3851
3852 priv_val->buf_ldch_idx = 0;
3853 mesh_size = rkisp_get_ldch_meshsize(params_vdev, ldchsize);
3854 buf_size = PAGE_ALIGN(mesh_size * sizeof(u16) + ALIGN(sizeof(struct isp2x_ldch_head), 16));
3855 for (i = 0; i < ISP2X_LDCH_BUF_NUM; i++) {
3856 priv_val->buf_ldch[i].is_need_vaddr = true;
3857 priv_val->buf_ldch[i].is_need_dbuf = true;
3858 priv_val->buf_ldch[i].is_need_dmafd = true;
3859 priv_val->buf_ldch[i].size = buf_size;
3860 ret = rkisp_alloc_buffer(params_vdev->dev, &priv_val->buf_ldch[i]);
3861 if (ret) {
3862 dev_err(dev, "can not alloc buffer\n");
3863 goto err;
3864 }
3865
3866 ldch_head = (struct isp2x_ldch_head *)priv_val->buf_ldch[i].vaddr;
3867 ldch_head->stat = LDCH_BUF_INIT;
3868 ldch_head->data_oft = ALIGN(sizeof(struct isp2x_ldch_head), 16);
3869 }
3870
3871 return 0;
3872
3873 err:
3874 rkisp_deinit_ldch_buf(params_vdev);
3875
3876 return -ENOMEM;
3877
3878 }
3879
3880 static void
rkisp_get_param_size_v2x(struct rkisp_isp_params_vdev * params_vdev,unsigned int sizes[])3881 rkisp_get_param_size_v2x(struct rkisp_isp_params_vdev *params_vdev,
3882 unsigned int sizes[])
3883 {
3884 sizes[0] = sizeof(struct isp2x_isp_params_cfg);
3885 }
3886
3887 static void
rkisp_params_get_ldchbuf_inf_v2x(struct rkisp_isp_params_vdev * params_vdev,void * buf)3888 rkisp_params_get_ldchbuf_inf_v2x(struct rkisp_isp_params_vdev *params_vdev,
3889 void *buf)
3890 {
3891 struct rkisp_isp_params_val_v21 *priv_val;
3892 struct rkisp_ldchbuf_info *ldchbuf = buf;
3893 int i;
3894
3895 priv_val = params_vdev->priv_val;
3896 for (i = 0; i < ISP2X_LDCH_BUF_NUM; i++) {
3897 ldchbuf->buf_fd[i] = priv_val->buf_ldch[i].dma_fd;
3898 ldchbuf->buf_size[i] = priv_val->buf_ldch[i].size;
3899 }
3900 }
3901
3902 static void
rkisp_params_set_ldchbuf_size_v2x(struct rkisp_isp_params_vdev * params_vdev,void * size)3903 rkisp_params_set_ldchbuf_size_v2x(struct rkisp_isp_params_vdev *params_vdev,
3904 void *size)
3905 {
3906 struct rkisp_ldchbuf_size *ldchsize = size;
3907
3908 rkisp_deinit_ldch_buf(params_vdev);
3909 rkisp_init_ldch_buf(params_vdev, ldchsize);
3910 }
3911
3912 static void
rkisp_params_stream_stop_v2x(struct rkisp_isp_params_vdev * params_vdev)3913 rkisp_params_stream_stop_v2x(struct rkisp_isp_params_vdev *params_vdev)
3914 {
3915 struct rkisp_device *ispdev = params_vdev->dev;
3916 struct rkisp_isp_params_val_v21 *priv_val;
3917
3918 priv_val = (struct rkisp_isp_params_val_v21 *)params_vdev->priv_val;
3919 rkisp_free_buffer(ispdev, &priv_val->buf_3dnr);
3920 }
3921
3922 static void
rkisp_params_fop_release_v2x(struct rkisp_isp_params_vdev * params_vdev)3923 rkisp_params_fop_release_v2x(struct rkisp_isp_params_vdev *params_vdev)
3924 {
3925 rkisp_deinit_ldch_buf(params_vdev);
3926 }
3927
3928 /* Not called when the camera active, thus not isr protection. */
3929 static void
rkisp_params_disable_isp_v2x(struct rkisp_isp_params_vdev * params_vdev)3930 rkisp_params_disable_isp_v2x(struct rkisp_isp_params_vdev *params_vdev)
3931 {
3932 struct rkisp_isp_params_v21_ops *ops =
3933 (struct rkisp_isp_params_v21_ops *)params_vdev->priv_ops;
3934
3935 ops->dpcc_enable(params_vdev, false);
3936 ops->bls_enable(params_vdev, false);
3937 ops->sdg_enable(params_vdev, false);
3938 ops->lsc_enable(params_vdev, false);
3939 ops->awbgain_enable(params_vdev, false);
3940 ops->debayer_enable(params_vdev, false);
3941 ops->ccm_enable(params_vdev, false);
3942 ops->goc_enable(params_vdev, false);
3943 ops->cproc_enable(params_vdev, false);
3944 ops->ie_enable(params_vdev, false);
3945 ops->rawaf_enable(params_vdev, false);
3946 ops->rawae0_enable(params_vdev, false);
3947 ops->rawae1_enable(params_vdev, false);
3948 ops->rawae2_enable(params_vdev, false);
3949 ops->rawae3_enable(params_vdev, false);
3950 ops->rawawb_enable(params_vdev, false);
3951 ops->rawhst0_enable(params_vdev, false);
3952 ops->rawhst1_enable(params_vdev, false);
3953 ops->rawhst2_enable(params_vdev, false);
3954 ops->rawhst3_enable(params_vdev, false);
3955 ops->hdrmge_enable(params_vdev, false);
3956 ops->hdrdrc_enable(params_vdev, false);
3957 ops->gic_enable(params_vdev, false);
3958 ops->dhaz_enable(params_vdev, false);
3959 ops->isp3dlut_enable(params_vdev, false);
3960 ops->ldch_enable(params_vdev, false);
3961 ops->ynr_enable(params_vdev, false, NULL);
3962 ops->cnr_enable(params_vdev, false, NULL);
3963 ops->sharp_enable(params_vdev, false);
3964 ops->baynr_enable(params_vdev, false);
3965 ops->bay3d_enable(params_vdev, false);
3966 }
3967
3968 static void
ldch_data_abandon(struct rkisp_isp_params_vdev * params_vdev,struct isp21_isp_params_cfg * params)3969 ldch_data_abandon(struct rkisp_isp_params_vdev *params_vdev,
3970 struct isp21_isp_params_cfg *params)
3971 {
3972 const struct isp2x_ldch_cfg *arg = ¶ms->others.ldch_cfg;
3973 struct rkisp_isp_params_val_v21 *priv_val;
3974 struct isp2x_ldch_head *ldch_head;
3975 int i;
3976
3977 priv_val = (struct rkisp_isp_params_val_v21 *)params_vdev->priv_val;
3978 for (i = 0; i < ISP2X_LDCH_BUF_NUM; i++) {
3979 if (arg->buf_fd == priv_val->buf_ldch[i].dma_fd &&
3980 priv_val->buf_ldch[i].vaddr) {
3981 ldch_head = (struct isp2x_ldch_head *)priv_val->buf_ldch[i].vaddr;
3982 ldch_head->stat = LDCH_BUF_CHIPINUSE;
3983 break;
3984 }
3985 }
3986 }
3987
3988 static void
rkisp_params_cfg_v2x(struct rkisp_isp_params_vdev * params_vdev,u32 frame_id,enum rkisp_params_type type)3989 rkisp_params_cfg_v2x(struct rkisp_isp_params_vdev *params_vdev,
3990 u32 frame_id, enum rkisp_params_type type)
3991 {
3992 struct isp21_isp_params_cfg *new_params = NULL;
3993 struct rkisp_buffer *cur_buf = params_vdev->cur_buf;
3994 struct rkisp_device *dev = params_vdev->dev;
3995 struct rkisp_hw_dev *hw_dev = dev->hw_dev;
3996
3997 spin_lock(¶ms_vdev->config_lock);
3998 if (!params_vdev->streamon)
3999 goto unlock;
4000
4001 /* get buffer by frame_id */
4002 while (!list_empty(¶ms_vdev->params) && !cur_buf) {
4003 cur_buf = list_first_entry(¶ms_vdev->params,
4004 struct rkisp_buffer, queue);
4005
4006 new_params = (struct isp21_isp_params_cfg *)(cur_buf->vaddr[0]);
4007 if (new_params->frame_id < frame_id) {
4008 list_del(&cur_buf->queue);
4009 if (list_empty(¶ms_vdev->params))
4010 break;
4011 else if (new_params->module_en_update) {
4012 /* update en immediately */
4013 __isp_isr_other_en(params_vdev, new_params, type);
4014 __isp_isr_meas_en(params_vdev, new_params, type);
4015 }
4016 if (new_params->module_cfg_update & ISP2X_MODULE_LDCH)
4017 ldch_data_abandon(params_vdev, new_params);
4018 vb2_buffer_done(&cur_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
4019 cur_buf = NULL;
4020 continue;
4021 } else if (new_params->frame_id == frame_id) {
4022 list_del(&cur_buf->queue);
4023 } else {
4024 cur_buf = NULL;
4025 }
4026 break;
4027 }
4028
4029 if (!cur_buf)
4030 goto unlock;
4031
4032 new_params = (struct isp21_isp_params_cfg *)(cur_buf->vaddr[0]);
4033 __isp_isr_other_config(params_vdev, new_params, type);
4034 __isp_isr_other_en(params_vdev, new_params, type);
4035 __isp_isr_meas_config(params_vdev, new_params, type);
4036 __isp_isr_meas_en(params_vdev, new_params, type);
4037 if (!hw_dev->is_single && type != RKISP_PARAMS_SHD)
4038 __isp_config_hdrshd(params_vdev);
4039
4040 if (type != RKISP_PARAMS_IMD) {
4041 struct rkisp_isp_params_val_v21 *priv_val =
4042 (struct rkisp_isp_params_val_v21 *)params_vdev->priv_val;
4043
4044 priv_val->last_hdrmge = priv_val->cur_hdrmge;
4045 priv_val->last_hdrdrc = priv_val->cur_hdrdrc;
4046 priv_val->cur_hdrmge = new_params->others.hdrmge_cfg;
4047 priv_val->cur_hdrdrc = new_params->others.drc_cfg;
4048 vb2_buffer_done(&cur_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
4049 cur_buf = NULL;
4050 }
4051
4052 unlock:
4053 params_vdev->cur_buf = cur_buf;
4054 spin_unlock(¶ms_vdev->config_lock);
4055 }
4056
4057 static void
rkisp_params_clear_fstflg(struct rkisp_isp_params_vdev * params_vdev)4058 rkisp_params_clear_fstflg(struct rkisp_isp_params_vdev *params_vdev)
4059 {
4060 u32 value;
4061
4062 value = rkisp_ioread32(params_vdev, ISP_CTRL1);
4063 if (value & ISP2X_SYS_YNR_FST)
4064 rkisp_clear_bits(params_vdev->dev, ISP_CTRL1,
4065 ISP2X_SYS_YNR_FST, false);
4066 if (value & ISP2X_SYS_ADRC_FST)
4067 rkisp_clear_bits(params_vdev->dev, ISP_CTRL1,
4068 ISP2X_SYS_ADRC_FST, false);
4069 if (value & ISP2X_SYS_DHAZ_FST)
4070 rkisp_clear_bits(params_vdev->dev, ISP_CTRL1,
4071 ISP2X_SYS_DHAZ_FST, false);
4072 if (value & ISP2X_SYS_CNR_FST)
4073 rkisp_clear_bits(params_vdev->dev, ISP_CTRL1,
4074 ISP2X_SYS_CNR_FST, false);
4075 if (value & ISP2X_SYS_BAY3D_FST)
4076 rkisp_clear_bits(params_vdev->dev, ISP_CTRL1,
4077 ISP2X_SYS_BAY3D_FST, false);
4078 }
4079
4080 static void
rkisp_params_isr_v2x(struct rkisp_isp_params_vdev * params_vdev,u32 isp_mis)4081 rkisp_params_isr_v2x(struct rkisp_isp_params_vdev *params_vdev,
4082 u32 isp_mis)
4083 {
4084 struct rkisp_device *dev = params_vdev->dev;
4085 u32 cur_frame_id;
4086
4087 rkisp_dmarx_get_frame(dev, &cur_frame_id, NULL, NULL, true);
4088 if (isp_mis & CIF_ISP_V_START) {
4089 if (params_vdev->rdbk_times)
4090 params_vdev->rdbk_times--;
4091 if (!params_vdev->cur_buf)
4092 return;
4093
4094 if (IS_HDR_RDBK(dev->rd_mode) && !params_vdev->rdbk_times) {
4095 rkisp_params_cfg_v2x(params_vdev, cur_frame_id, RKISP_PARAMS_SHD);
4096 return;
4097 }
4098 }
4099
4100 if (isp_mis & CIF_ISP_FRAME)
4101 rkisp_params_clear_fstflg(params_vdev);
4102
4103 if ((isp_mis & CIF_ISP_FRAME) && !IS_HDR_RDBK(dev->rd_mode))
4104 rkisp_params_cfg_v2x(params_vdev, cur_frame_id + 1, RKISP_PARAMS_ALL);
4105 }
4106
4107 static struct rkisp_isp_params_ops rkisp_isp_params_ops_tbl = {
4108 .save_first_param = rkisp_save_first_param_v2x,
4109 .clear_first_param = rkisp_clear_first_param_v2x,
4110 .get_param_size = rkisp_get_param_size_v2x,
4111 .first_cfg = rkisp_params_first_cfg_v2x,
4112 .disable_isp = rkisp_params_disable_isp_v2x,
4113 .isr_hdl = rkisp_params_isr_v2x,
4114 .param_cfg = rkisp_params_cfg_v2x,
4115 .param_cfgsram = rkisp_params_cfgsram_v21,
4116 .get_meshbuf_inf = rkisp_params_get_ldchbuf_inf_v2x,
4117 .set_meshbuf_size = rkisp_params_set_ldchbuf_size_v2x,
4118 .stream_stop = rkisp_params_stream_stop_v2x,
4119 .fop_release = rkisp_params_fop_release_v2x,
4120 };
4121
rkisp_init_params_vdev_v21(struct rkisp_isp_params_vdev * params_vdev)4122 int rkisp_init_params_vdev_v21(struct rkisp_isp_params_vdev *params_vdev)
4123 {
4124 struct device *dev = params_vdev->dev->dev;
4125 struct rkisp_isp_params_val_v21 *priv_val;
4126 int i, ret;
4127
4128 priv_val = kzalloc(sizeof(*priv_val), GFP_KERNEL);
4129 if (!priv_val)
4130 return -ENOMEM;
4131
4132 params_vdev->isp21_params = vmalloc(sizeof(*params_vdev->isp21_params));
4133 if (!params_vdev->isp21_params) {
4134 kfree(priv_val);
4135 return -ENOMEM;
4136 }
4137 priv_val->buf_3dlut_idx = 0;
4138 for (i = 0; i < RKISP_PARAM_3DLUT_BUF_NUM; i++) {
4139 priv_val->buf_3dlut[i].is_need_vaddr = true;
4140 priv_val->buf_3dlut[i].size = RKISP_PARAM_3DLUT_BUF_SIZE;
4141 ret = rkisp_alloc_buffer(params_vdev->dev, &priv_val->buf_3dlut[i]);
4142 if (ret) {
4143 dev_err(dev, "can not alloc buffer\n");
4144 goto err;
4145 }
4146 }
4147
4148 priv_val->buf_lsclut_idx = 0;
4149 for (i = 0; i < RKISP_PARAM_LSC_LUT_BUF_NUM; i++) {
4150 priv_val->buf_lsclut[i].is_need_vaddr = true;
4151 priv_val->buf_lsclut[i].size = RKISP_PARAM_LSC_LUT_BUF_SIZE;
4152 ret = rkisp_alloc_buffer(params_vdev->dev, &priv_val->buf_lsclut[i]);
4153 if (ret) {
4154 dev_err(dev, "can not alloc buffer\n");
4155 goto err;
4156 }
4157 }
4158
4159 params_vdev->priv_val = (void *)priv_val;
4160 params_vdev->ops = &rkisp_isp_params_ops_tbl;
4161 params_vdev->priv_ops = &rkisp_v21_isp_params_ops;
4162 rkisp_clear_first_param_v2x(params_vdev);
4163 return 0;
4164
4165 err:
4166 for (i = 0; i < RKISP_PARAM_3DLUT_BUF_NUM; i++)
4167 rkisp_free_buffer(params_vdev->dev, &priv_val->buf_3dlut[i]);
4168
4169 for (i = 0; i < RKISP_PARAM_LSC_LUT_BUF_NUM; i++)
4170 rkisp_free_buffer(params_vdev->dev, &priv_val->buf_lsclut[i]);
4171 vfree(params_vdev->isp21_params);
4172
4173 return ret;
4174 }
4175
rkisp_uninit_params_vdev_v21(struct rkisp_isp_params_vdev * params_vdev)4176 void rkisp_uninit_params_vdev_v21(struct rkisp_isp_params_vdev *params_vdev)
4177 {
4178 struct rkisp_isp_params_val_v21 *priv_val;
4179 int i;
4180
4181 priv_val = params_vdev->priv_val;
4182 if (!priv_val)
4183 return;
4184
4185 rkisp_deinit_ldch_buf(params_vdev);
4186 for (i = 0; i < RKISP_PARAM_3DLUT_BUF_NUM; i++)
4187 rkisp_free_buffer(params_vdev->dev, &priv_val->buf_3dlut[i]);
4188
4189 for (i = 0; i < RKISP_PARAM_LSC_LUT_BUF_NUM; i++)
4190 rkisp_free_buffer(params_vdev->dev, &priv_val->buf_lsclut[i]);
4191 vfree(params_vdev->isp21_params);
4192 kfree(priv_val);
4193
4194 params_vdev->priv_val = NULL;
4195 }
4196