1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2021 Rockchip Electronics Co., Ltd. */
3
4 #include <media/v4l2-common.h>
5 #include <media/v4l2-ioctl.h>
6 #include <media/videobuf2-core.h>
7 #include <media/videobuf2-vmalloc.h> /* for ISP params */
8 #include "dev.h"
9 #include "regs.h"
10 #include "isp_params_v3x.h"
11
12 #define ISP3X_MODULE_EN BIT(0)
13 #define ISP3X_SELF_FORCE_UPD BIT(31)
14 #define ISP3X_REG_WR_MASK BIT(31) //disable write protect
15 #define ISP3X_NOBIG_OVERFLOW_SIZE (2688 * 1536)
16 #define ISP3X_AUTO_BIGMODE_WIDTH 2688
17 #define ISP3X_VIR2_NOBIG_OVERFLOW_SIZE (1920 * 1080)
18 #define ISP3X_VIR2_AUTO_BIGMODE_WIDTH 1920
19 #define ISP3X_VIR4_NOBIG_OVERFLOW_SIZE (1280 * 800)
20 #define ISP3X_VIR4_AUTO_BIGMODE_WIDTH 1280
21
22 #define ISP3X_VIR2_MAX_WIDTH 3840
23 #define ISP3X_VIR2_MAX_SIZE (3840 * 2160)
24 #define ISP3X_VIR4_MAX_WIDTH 2560
25 #define ISP3X_VIR4_MAX_SIZE (2560 * 1536)
26
27 static inline void
isp3_param_write_direct(struct rkisp_isp_params_vdev * params_vdev,u32 value,u32 addr,u32 id)28 isp3_param_write_direct(struct rkisp_isp_params_vdev *params_vdev,
29 u32 value, u32 addr, u32 id)
30 {
31 if (id == ISP3_LEFT)
32 rkisp_write(params_vdev->dev, addr, value, true);
33 else
34 rkisp_next_write(params_vdev->dev, addr, value, true);
35 }
36
37 static inline void
isp3_param_write(struct rkisp_isp_params_vdev * params_vdev,u32 value,u32 addr,u32 id)38 isp3_param_write(struct rkisp_isp_params_vdev *params_vdev,
39 u32 value, u32 addr, u32 id)
40 {
41 if (id == ISP3_LEFT)
42 rkisp_write(params_vdev->dev, addr, value, false);
43 else
44 rkisp_next_write(params_vdev->dev, addr, value, false);
45 }
46
47 static inline u32
isp3_param_read_direct(struct rkisp_isp_params_vdev * params_vdev,u32 addr,u32 id)48 isp3_param_read_direct(struct rkisp_isp_params_vdev *params_vdev,
49 u32 addr, u32 id)
50 {
51 u32 val;
52
53 if (id == ISP3_LEFT)
54 val = rkisp_read(params_vdev->dev, addr, true);
55 else
56 val = rkisp_next_read(params_vdev->dev, addr, true);
57 return val;
58 }
59
60 static inline u32
isp3_param_read(struct rkisp_isp_params_vdev * params_vdev,u32 addr,u32 id)61 isp3_param_read(struct rkisp_isp_params_vdev *params_vdev,
62 u32 addr, u32 id)
63 {
64 u32 val;
65
66 if (id == ISP3_LEFT)
67 val = rkisp_read(params_vdev->dev, addr, false);
68 else
69 val = rkisp_next_read(params_vdev->dev, addr, false);
70 return val;
71 }
72
73 static inline u32
isp3_param_read_cache(struct rkisp_isp_params_vdev * params_vdev,u32 addr,u32 id)74 isp3_param_read_cache(struct rkisp_isp_params_vdev *params_vdev,
75 u32 addr, u32 id)
76 {
77 u32 val;
78
79 if (id == ISP3_LEFT)
80 val = rkisp_read_reg_cache(params_vdev->dev, addr);
81 else
82 val = rkisp_next_read_reg_cache(params_vdev->dev, addr);
83 return val;
84 }
85
86 static inline void
isp3_param_set_bits(struct rkisp_isp_params_vdev * params_vdev,u32 reg,u32 bit_mask,u32 id)87 isp3_param_set_bits(struct rkisp_isp_params_vdev *params_vdev,
88 u32 reg, u32 bit_mask, u32 id)
89 {
90 if (id == ISP3_LEFT)
91 rkisp_set_bits(params_vdev->dev, reg, 0, bit_mask, false);
92 else
93 rkisp_next_set_bits(params_vdev->dev, reg, 0, bit_mask, false);
94 }
95
96 static inline void
isp3_param_clear_bits(struct rkisp_isp_params_vdev * params_vdev,u32 reg,u32 bit_mask,u32 id)97 isp3_param_clear_bits(struct rkisp_isp_params_vdev *params_vdev,
98 u32 reg, u32 bit_mask, u32 id)
99 {
100 if (id == ISP3_LEFT)
101 rkisp_clear_bits(params_vdev->dev, reg, bit_mask, false);
102 else
103 rkisp_next_clear_bits(params_vdev->dev, reg, bit_mask, false);
104 }
105
106 static void
isp_dpcc_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_dpcc_cfg * arg,u32 id)107 isp_dpcc_config(struct rkisp_isp_params_vdev *params_vdev,
108 const struct isp2x_dpcc_cfg *arg, u32 id)
109 {
110 u32 value;
111 int i;
112
113 value = isp3_param_read(params_vdev, ISP3X_DPCC0_MODE, id);
114 value &= ISP_DPCC_EN;
115
116 value |= (arg->stage1_enable & 0x01) << 2 |
117 (arg->grayscale_mode & 0x01) << 1;
118 isp3_param_write(params_vdev, value, ISP3X_DPCC0_MODE, id);
119 isp3_param_write(params_vdev, value, ISP3X_DPCC1_MODE, id);
120 isp3_param_write(params_vdev, value, ISP3X_DPCC2_MODE, id);
121
122 value = (arg->sw_rk_out_sel & 0x03) << 5 |
123 (arg->sw_dpcc_output_sel & 0x01) << 4 |
124 (arg->stage1_rb_3x3 & 0x01) << 3 |
125 (arg->stage1_g_3x3 & 0x01) << 2 |
126 (arg->stage1_incl_rb_center & 0x01) << 1 |
127 (arg->stage1_incl_green_center & 0x01);
128 isp3_param_write(params_vdev, value, ISP3X_DPCC0_OUTPUT_MODE, id);
129 isp3_param_write(params_vdev, value, ISP3X_DPCC1_OUTPUT_MODE, id);
130 isp3_param_write(params_vdev, value, ISP3X_DPCC2_OUTPUT_MODE, id);
131
132 value = (arg->stage1_use_fix_set & 0x01) << 3 |
133 (arg->stage1_use_set_3 & 0x01) << 2 |
134 (arg->stage1_use_set_2 & 0x01) << 1 |
135 (arg->stage1_use_set_1 & 0x01);
136 isp3_param_write(params_vdev, value, ISP3X_DPCC0_SET_USE, id);
137 isp3_param_write(params_vdev, value, ISP3X_DPCC1_SET_USE, id);
138 isp3_param_write(params_vdev, value, ISP3X_DPCC2_SET_USE, id);
139
140 value = (arg->sw_rk_red_blue1_en & 0x01) << 13 |
141 (arg->rg_red_blue1_enable & 0x01) << 12 |
142 (arg->rnd_red_blue1_enable & 0x01) << 11 |
143 (arg->ro_red_blue1_enable & 0x01) << 10 |
144 (arg->lc_red_blue1_enable & 0x01) << 9 |
145 (arg->pg_red_blue1_enable & 0x01) << 8 |
146 (arg->sw_rk_green1_en & 0x01) << 5 |
147 (arg->rg_green1_enable & 0x01) << 4 |
148 (arg->rnd_green1_enable & 0x01) << 3 |
149 (arg->ro_green1_enable & 0x01) << 2 |
150 (arg->lc_green1_enable & 0x01) << 1 |
151 (arg->pg_green1_enable & 0x01);
152 isp3_param_write(params_vdev, value, ISP3X_DPCC0_METHODS_SET_1, id);
153 isp3_param_write(params_vdev, value, ISP3X_DPCC1_METHODS_SET_1, id);
154 isp3_param_write(params_vdev, value, ISP3X_DPCC2_METHODS_SET_1, id);
155
156 value = (arg->sw_rk_red_blue2_en & 0x01) << 13 |
157 (arg->rg_red_blue2_enable & 0x01) << 12 |
158 (arg->rnd_red_blue2_enable & 0x01) << 11 |
159 (arg->ro_red_blue2_enable & 0x01) << 10 |
160 (arg->lc_red_blue2_enable & 0x01) << 9 |
161 (arg->pg_red_blue2_enable & 0x01) << 8 |
162 (arg->sw_rk_green2_en & 0x01) << 5 |
163 (arg->rg_green2_enable & 0x01) << 4 |
164 (arg->rnd_green2_enable & 0x01) << 3 |
165 (arg->ro_green2_enable & 0x01) << 2 |
166 (arg->lc_green2_enable & 0x01) << 1 |
167 (arg->pg_green2_enable & 0x01);
168 isp3_param_write(params_vdev, value, ISP3X_DPCC0_METHODS_SET_2, id);
169 isp3_param_write(params_vdev, value, ISP3X_DPCC1_METHODS_SET_2, id);
170 isp3_param_write(params_vdev, value, ISP3X_DPCC2_METHODS_SET_2, id);
171
172 value = (arg->sw_rk_red_blue3_en & 0x01) << 13 |
173 (arg->rg_red_blue3_enable & 0x01) << 12 |
174 (arg->rnd_red_blue3_enable & 0x01) << 11 |
175 (arg->ro_red_blue3_enable & 0x01) << 10 |
176 (arg->lc_red_blue3_enable & 0x01) << 9 |
177 (arg->pg_red_blue3_enable & 0x01) << 8 |
178 (arg->sw_rk_green3_en & 0x01) << 5 |
179 (arg->rg_green3_enable & 0x01) << 4 |
180 (arg->rnd_green3_enable & 0x01) << 3 |
181 (arg->ro_green3_enable & 0x01) << 2 |
182 (arg->lc_green3_enable & 0x01) << 1 |
183 (arg->pg_green3_enable & 0x01);
184 isp3_param_write(params_vdev, value, ISP3X_DPCC0_METHODS_SET_3, id);
185 isp3_param_write(params_vdev, value, ISP3X_DPCC1_METHODS_SET_3, id);
186 isp3_param_write(params_vdev, value, ISP3X_DPCC2_METHODS_SET_3, id);
187
188 value = ISP_PACK_4BYTE(arg->line_thr_1_g, arg->line_thr_1_rb,
189 arg->sw_mindis1_g, arg->sw_mindis1_rb);
190 isp3_param_write(params_vdev, value, ISP3X_DPCC0_LINE_THRESH_1, id);
191 isp3_param_write(params_vdev, value, ISP3X_DPCC1_LINE_THRESH_1, id);
192 isp3_param_write(params_vdev, value, ISP3X_DPCC2_LINE_THRESH_1, id);
193
194 value = ISP_PACK_4BYTE(arg->line_mad_fac_1_g, arg->line_mad_fac_1_rb,
195 arg->sw_dis_scale_max1, arg->sw_dis_scale_min1);
196 isp3_param_write(params_vdev, value, ISP3X_DPCC0_LINE_MAD_FAC_1, id);
197 isp3_param_write(params_vdev, value, ISP3X_DPCC1_LINE_MAD_FAC_1, id);
198 isp3_param_write(params_vdev, value, ISP3X_DPCC2_LINE_MAD_FAC_1, id);
199
200 value = ISP_PACK_4BYTE(arg->pg_fac_1_g, arg->pg_fac_1_rb, 0, 0);
201 isp3_param_write(params_vdev, value, ISP3X_DPCC0_PG_FAC_1, id);
202 isp3_param_write(params_vdev, value, ISP3X_DPCC1_PG_FAC_1, id);
203 isp3_param_write(params_vdev, value, ISP3X_DPCC2_PG_FAC_1, id);
204
205 value = ISP_PACK_4BYTE(arg->rnd_thr_1_g, arg->rnd_thr_1_rb, 0, 0);
206 isp3_param_write(params_vdev, value, ISP3X_DPCC0_RND_THRESH_1, id);
207 isp3_param_write(params_vdev, value, ISP3X_DPCC1_RND_THRESH_1, id);
208 isp3_param_write(params_vdev, value, ISP3X_DPCC2_RND_THRESH_1, id);
209
210 value = ISP_PACK_4BYTE(arg->rg_fac_1_g, arg->rg_fac_1_rb, 0, 0);
211 isp3_param_write(params_vdev, value, ISP3X_DPCC0_RG_FAC_1, id);
212 isp3_param_write(params_vdev, value, ISP3X_DPCC1_RG_FAC_1, id);
213 isp3_param_write(params_vdev, value, ISP3X_DPCC2_RG_FAC_1, id);
214
215 value = ISP_PACK_4BYTE(arg->line_thr_2_g, arg->line_thr_2_rb,
216 arg->sw_mindis2_g, arg->sw_mindis2_rb);
217 isp3_param_write(params_vdev, value, ISP3X_DPCC0_LINE_THRESH_2, id);
218 isp3_param_write(params_vdev, value, ISP3X_DPCC1_LINE_THRESH_2, id);
219
220 value = ISP_PACK_4BYTE(arg->line_mad_fac_2_g, arg->line_mad_fac_2_rb,
221 arg->sw_dis_scale_max2, arg->sw_dis_scale_min2);
222 isp3_param_write(params_vdev, value, ISP3X_DPCC0_LINE_MAD_FAC_2, id);
223 isp3_param_write(params_vdev, value, ISP3X_DPCC1_LINE_MAD_FAC_2, id);
224 isp3_param_write(params_vdev, value, ISP3X_DPCC2_LINE_MAD_FAC_2, id);
225
226 value = ISP_PACK_4BYTE(arg->pg_fac_2_g, arg->pg_fac_2_rb, 0, 0);
227 isp3_param_write(params_vdev, value, ISP3X_DPCC0_PG_FAC_2, id);
228 isp3_param_write(params_vdev, value, ISP3X_DPCC1_PG_FAC_2, id);
229 isp3_param_write(params_vdev, value, ISP3X_DPCC2_PG_FAC_2, id);
230
231 value = ISP_PACK_4BYTE(arg->rnd_thr_2_g, arg->rnd_thr_2_rb, 0, 0);
232 isp3_param_write(params_vdev, value, ISP3X_DPCC0_RND_THRESH_2, id);
233 isp3_param_write(params_vdev, value, ISP3X_DPCC1_RND_THRESH_2, id);
234 isp3_param_write(params_vdev, value, ISP3X_DPCC2_RND_THRESH_2, id);
235
236 value = ISP_PACK_4BYTE(arg->rg_fac_2_g, arg->rg_fac_2_rb, 0, 0);
237 isp3_param_write(params_vdev, value, ISP3X_DPCC0_RG_FAC_2, id);
238 isp3_param_write(params_vdev, value, ISP3X_DPCC1_RG_FAC_2, id);
239 isp3_param_write(params_vdev, value, ISP3X_DPCC2_RG_FAC_2, id);
240
241 value = ISP_PACK_4BYTE(arg->line_thr_3_g, arg->line_thr_3_rb,
242 arg->sw_mindis3_g, arg->sw_mindis3_rb);
243 isp3_param_write(params_vdev, value, ISP3X_DPCC0_LINE_THRESH_3, id);
244 isp3_param_write(params_vdev, value, ISP3X_DPCC1_LINE_THRESH_3, id);
245 isp3_param_write(params_vdev, value, ISP3X_DPCC2_LINE_THRESH_3, id);
246
247 value = ISP_PACK_4BYTE(arg->line_mad_fac_3_g, arg->line_mad_fac_3_rb,
248 arg->sw_dis_scale_max3, arg->sw_dis_scale_min3);
249 isp3_param_write(params_vdev, value, ISP3X_DPCC0_LINE_MAD_FAC_3, id);
250 isp3_param_write(params_vdev, value, ISP3X_DPCC1_LINE_MAD_FAC_3, id);
251 isp3_param_write(params_vdev, value, ISP3X_DPCC2_LINE_MAD_FAC_3, id);
252
253 value = ISP_PACK_4BYTE(arg->pg_fac_3_g, arg->pg_fac_3_rb, 0, 0);
254 isp3_param_write(params_vdev, value, ISP3X_DPCC0_PG_FAC_3, id);
255 isp3_param_write(params_vdev, value, ISP3X_DPCC1_PG_FAC_3, id);
256 isp3_param_write(params_vdev, value, ISP3X_DPCC2_PG_FAC_3, id);
257
258 value = ISP_PACK_4BYTE(arg->rnd_thr_3_g, arg->rnd_thr_3_rb, 0, 0);
259 isp3_param_write(params_vdev, value, ISP3X_DPCC0_RND_THRESH_3, id);
260 isp3_param_write(params_vdev, value, ISP3X_DPCC1_RND_THRESH_3, id);
261 isp3_param_write(params_vdev, value, ISP3X_DPCC2_RND_THRESH_3, id);
262
263 value = ISP_PACK_4BYTE(arg->rg_fac_3_g, arg->rg_fac_3_rb, 0, 0);
264 isp3_param_write(params_vdev, value, ISP3X_DPCC0_RG_FAC_3, id);
265 isp3_param_write(params_vdev, value, ISP3X_DPCC1_RG_FAC_3, id);
266 isp3_param_write(params_vdev, value, ISP3X_DPCC2_RG_FAC_3, id);
267
268 value = (arg->ro_lim_3_rb & 0x03) << 10 |
269 (arg->ro_lim_3_g & 0x03) << 8 |
270 (arg->ro_lim_2_rb & 0x03) << 6 |
271 (arg->ro_lim_2_g & 0x03) << 4 |
272 (arg->ro_lim_1_rb & 0x03) << 2 |
273 (arg->ro_lim_1_g & 0x03);
274 isp3_param_write(params_vdev, value, ISP3X_DPCC0_RO_LIMITS, id);
275 isp3_param_write(params_vdev, value, ISP3X_DPCC1_RO_LIMITS, id);
276 isp3_param_write(params_vdev, value, ISP3X_DPCC2_RO_LIMITS, id);
277
278 value = (arg->rnd_offs_3_rb & 0x03) << 10 |
279 (arg->rnd_offs_3_g & 0x03) << 8 |
280 (arg->rnd_offs_2_rb & 0x03) << 6 |
281 (arg->rnd_offs_2_g & 0x03) << 4 |
282 (arg->rnd_offs_1_rb & 0x03) << 2 |
283 (arg->rnd_offs_1_g & 0x03);
284 isp3_param_write(params_vdev, value, ISP3X_DPCC0_RND_OFFS, id);
285 isp3_param_write(params_vdev, value, ISP3X_DPCC1_RND_OFFS, id);
286 isp3_param_write(params_vdev, value, ISP3X_DPCC2_RND_OFFS, id);
287
288 value = (arg->bpt_rb_3x3 & 0x01) << 11 |
289 (arg->bpt_g_3x3 & 0x01) << 10 |
290 (arg->bpt_incl_rb_center & 0x01) << 9 |
291 (arg->bpt_incl_green_center & 0x01) << 8 |
292 (arg->bpt_use_fix_set & 0x01) << 7 |
293 (arg->bpt_use_set_3 & 0x01) << 6 |
294 (arg->bpt_use_set_2 & 0x01) << 5 |
295 (arg->bpt_use_set_1 & 0x01) << 4 |
296 (arg->bpt_cor_en & 0x01) << 1 |
297 (arg->bpt_det_en & 0x01);
298 isp3_param_write(params_vdev, value, ISP3X_DPCC0_BPT_CTRL, id);
299 isp3_param_write(params_vdev, value, ISP3X_DPCC1_BPT_CTRL, id);
300 isp3_param_write(params_vdev, value, ISP3X_DPCC2_BPT_CTRL, id);
301
302 isp3_param_write(params_vdev, arg->bp_number, ISP3X_DPCC0_BPT_NUMBER, id);
303 isp3_param_write(params_vdev, arg->bp_number, ISP3X_DPCC1_BPT_NUMBER, id);
304 isp3_param_write(params_vdev, arg->bp_number, ISP3X_DPCC2_BPT_NUMBER, id);
305 isp3_param_write(params_vdev, arg->bp_table_addr, ISP3X_DPCC0_BPT_ADDR, id);
306 isp3_param_write(params_vdev, arg->bp_table_addr, ISP3X_DPCC1_BPT_ADDR, id);
307 isp3_param_write(params_vdev, arg->bp_table_addr, ISP3X_DPCC2_BPT_ADDR, id);
308
309 value = ISP_PACK_2SHORT(arg->bpt_h_addr, arg->bpt_v_addr);
310 isp3_param_write(params_vdev, value, ISP3X_DPCC0_BPT_DATA, id);
311 isp3_param_write(params_vdev, value, ISP3X_DPCC1_BPT_DATA, id);
312 isp3_param_write(params_vdev, value, ISP3X_DPCC2_BPT_DATA, id);
313
314 isp3_param_write(params_vdev, arg->bp_cnt, ISP3X_DPCC0_BP_CNT, id);
315 isp3_param_write(params_vdev, arg->bp_cnt, ISP3X_DPCC1_BP_CNT, id);
316 isp3_param_write(params_vdev, arg->bp_cnt, ISP3X_DPCC2_BP_CNT, id);
317
318 isp3_param_write(params_vdev, arg->sw_pdaf_en, ISP3X_DPCC0_PDAF_EN, id);
319 isp3_param_write(params_vdev, arg->sw_pdaf_en, ISP3X_DPCC1_PDAF_EN, id);
320 isp3_param_write(params_vdev, arg->sw_pdaf_en, ISP3X_DPCC2_PDAF_EN, id);
321
322 value = 0;
323 for (i = 0; i < ISP3X_DPCC_PDAF_POINT_NUM; i++)
324 value |= (arg->pdaf_point_en[i] & 0x01) << i;
325 isp3_param_write(params_vdev, value, ISP3X_DPCC0_PDAF_POINT_EN, id);
326 isp3_param_write(params_vdev, value, ISP3X_DPCC1_PDAF_POINT_EN, id);
327 isp3_param_write(params_vdev, value, ISP3X_DPCC2_PDAF_POINT_EN, id);
328
329 value = ISP_PACK_2SHORT(arg->pdaf_offsetx, arg->pdaf_offsety);
330 isp3_param_write(params_vdev, value, ISP3X_DPCC0_PDAF_OFFSET, id);
331 isp3_param_write(params_vdev, value, ISP3X_DPCC1_PDAF_OFFSET, id);
332 isp3_param_write(params_vdev, value, ISP3X_DPCC2_PDAF_OFFSET, id);
333
334 value = ISP_PACK_2SHORT(arg->pdaf_wrapx, arg->pdaf_wrapy);
335 isp3_param_write(params_vdev, value, ISP3X_DPCC0_PDAF_WRAP, id);
336 isp3_param_write(params_vdev, value, ISP3X_DPCC1_PDAF_WRAP, id);
337 isp3_param_write(params_vdev, value, ISP3X_DPCC2_PDAF_WRAP, id);
338
339 value = ISP_PACK_2SHORT(arg->pdaf_wrapx_num, arg->pdaf_wrapy_num);
340 isp3_param_write(params_vdev, value, ISP_DPCC0_PDAF_SCOPE, id);
341 isp3_param_write(params_vdev, value, ISP_DPCC1_PDAF_SCOPE, id);
342 isp3_param_write(params_vdev, value, ISP_DPCC2_PDAF_SCOPE, id);
343
344 for (i = 0; i < ISP3X_DPCC_PDAF_POINT_NUM / 2; i++) {
345 value = ISP_PACK_4BYTE(arg->point[2 * i].x, arg->point[2 * i].y,
346 arg->point[2 * i + 1].x, arg->point[2 * i + 1].y);
347 isp3_param_write(params_vdev, value, ISP3X_DPCC0_PDAF_POINT_0 + 4 * i, id);
348 isp3_param_write(params_vdev, value, ISP3X_DPCC1_PDAF_POINT_0 + 4 * i, id);
349 isp3_param_write(params_vdev, value, ISP3X_DPCC2_PDAF_POINT_0 + 4 * i, id);
350 }
351
352 isp3_param_write(params_vdev, arg->pdaf_forward_med, ISP3X_DPCC0_PDAF_FORWARD_MED, id);
353 isp3_param_write(params_vdev, arg->pdaf_forward_med, ISP3X_DPCC1_PDAF_FORWARD_MED, id);
354 isp3_param_write(params_vdev, arg->pdaf_forward_med, ISP3X_DPCC2_PDAF_FORWARD_MED, id);
355 }
356
357 static void
isp_dpcc_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)358 isp_dpcc_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
359 {
360 u32 value;
361
362 value = isp3_param_read(params_vdev, ISP3X_DPCC0_MODE, id);
363 value &= ~ISP_DPCC_EN;
364
365 if (en)
366 value |= ISP_DPCC_EN;
367 isp3_param_write(params_vdev, value, ISP3X_DPCC0_MODE, id);
368 isp3_param_write(params_vdev, value, ISP3X_DPCC1_MODE, id);
369 isp3_param_write(params_vdev, value, ISP3X_DPCC2_MODE, id);
370 }
371
372 static void
isp_bls_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp21_bls_cfg * arg,u32 id)373 isp_bls_config(struct rkisp_isp_params_vdev *params_vdev,
374 const struct isp21_bls_cfg *arg, u32 id)
375 {
376 const struct isp2x_bls_fixed_val *pval;
377 u32 new_control, value;
378
379 new_control = isp3_param_read(params_vdev, ISP3X_BLS_CTRL, id);
380 new_control &= ISP_BLS_ENA;
381
382 pval = &arg->bls1_val;
383 if (arg->bls1_en) {
384 new_control |= ISP_BLS_BLS1_EN;
385
386 switch (params_vdev->raw_type) {
387 case RAW_BGGR:
388 isp3_param_write(params_vdev, pval->r, ISP_BLS1_D_FIXED, id);
389 isp3_param_write(params_vdev, pval->gr, ISP_BLS1_C_FIXED, id);
390 isp3_param_write(params_vdev, pval->gb, ISP_BLS1_B_FIXED, id);
391 isp3_param_write(params_vdev, pval->b, ISP_BLS1_A_FIXED, id);
392 break;
393 case RAW_GBRG:
394 isp3_param_write(params_vdev, pval->r, ISP_BLS1_C_FIXED, id);
395 isp3_param_write(params_vdev, pval->gr, ISP_BLS1_D_FIXED, id);
396 isp3_param_write(params_vdev, pval->gb, ISP_BLS1_A_FIXED, id);
397 isp3_param_write(params_vdev, pval->b, ISP_BLS1_B_FIXED, id);
398 break;
399 case RAW_GRBG:
400 isp3_param_write(params_vdev, pval->r, ISP_BLS1_B_FIXED, id);
401 isp3_param_write(params_vdev, pval->gr, ISP_BLS1_A_FIXED, id);
402 isp3_param_write(params_vdev, pval->gb, ISP_BLS1_D_FIXED, id);
403 isp3_param_write(params_vdev, pval->b, ISP_BLS1_C_FIXED, id);
404 break;
405 case RAW_RGGB:
406 default:
407 isp3_param_write(params_vdev, pval->r, ISP_BLS1_A_FIXED, id);
408 isp3_param_write(params_vdev, pval->gr, ISP_BLS1_B_FIXED, id);
409 isp3_param_write(params_vdev, pval->gb, ISP_BLS1_C_FIXED, id);
410 isp3_param_write(params_vdev, pval->b, ISP_BLS1_D_FIXED, id);
411 break;
412 }
413 }
414
415 /* fixed subtraction values */
416 pval = &arg->fixed_val;
417 if (!arg->enable_auto) {
418 switch (params_vdev->raw_type) {
419 case RAW_BGGR:
420 isp3_param_write(params_vdev, pval->r, ISP_BLS_D_FIXED, id);
421 isp3_param_write(params_vdev, pval->gr, ISP_BLS_C_FIXED, id);
422 isp3_param_write(params_vdev, pval->gb, ISP_BLS_B_FIXED, id);
423 isp3_param_write(params_vdev, pval->b, ISP_BLS_A_FIXED, id);
424 break;
425 case RAW_GBRG:
426 isp3_param_write(params_vdev, pval->r, ISP_BLS_C_FIXED, id);
427 isp3_param_write(params_vdev, pval->gr, ISP_BLS_D_FIXED, id);
428 isp3_param_write(params_vdev, pval->gb, ISP_BLS_A_FIXED, id);
429 isp3_param_write(params_vdev, pval->b, ISP_BLS_B_FIXED, id);
430 break;
431 case RAW_GRBG:
432 isp3_param_write(params_vdev, pval->r, ISP_BLS_B_FIXED, id);
433 isp3_param_write(params_vdev, pval->gr, ISP_BLS_A_FIXED, id);
434 isp3_param_write(params_vdev, pval->gb, ISP_BLS_D_FIXED, id);
435 isp3_param_write(params_vdev, pval->b, ISP_BLS_C_FIXED, id);
436 break;
437 case RAW_RGGB:
438 default:
439 isp3_param_write(params_vdev, pval->r, ISP_BLS_A_FIXED, id);
440 isp3_param_write(params_vdev, pval->gr, ISP_BLS_B_FIXED, id);
441 isp3_param_write(params_vdev, pval->gb, ISP_BLS_C_FIXED, id);
442 isp3_param_write(params_vdev, pval->b, ISP_BLS_D_FIXED, id);
443 break;
444 }
445 } else {
446 if (arg->en_windows & BIT(1)) {
447 isp3_param_write(params_vdev, arg->bls_window2.h_offs, ISP3X_BLS_H2_START, id);
448 value = arg->bls_window2.h_offs + arg->bls_window2.h_size;
449 isp3_param_write(params_vdev, value, ISP3X_BLS_H2_STOP, id);
450 isp3_param_write(params_vdev, arg->bls_window2.v_offs, ISP3X_BLS_V2_START, id);
451 value = arg->bls_window2.v_offs + arg->bls_window2.v_size;
452 isp3_param_write(params_vdev, value, ISP3X_BLS_V2_STOP, id);
453 new_control |= ISP_BLS_WINDOW_2;
454 }
455
456 if (arg->en_windows & BIT(0)) {
457 isp3_param_write(params_vdev, arg->bls_window1.h_offs, ISP3X_BLS_H1_START, id);
458 value = arg->bls_window1.h_offs + arg->bls_window1.h_size;
459 isp3_param_write(params_vdev, value, ISP3X_BLS_H1_STOP, id);
460 isp3_param_write(params_vdev, arg->bls_window1.v_offs, ISP3X_BLS_V1_START, id);
461 value = arg->bls_window1.v_offs + arg->bls_window1.v_size;
462 isp3_param_write(params_vdev, value, ISP3X_BLS_V1_STOP, id);
463 new_control |= ISP_BLS_WINDOW_1;
464 }
465
466 isp3_param_write(params_vdev, arg->bls_samples, ISP3X_BLS_SAMPLES, id);
467
468 new_control |= ISP_BLS_MODE_MEASURED;
469 }
470 isp3_param_write(params_vdev, new_control, ISP3X_BLS_CTRL, id);
471 }
472
473 static void
isp_bls_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)474 isp_bls_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
475 {
476 u32 new_control;
477
478 new_control = isp3_param_read(params_vdev, ISP3X_BLS_CTRL, id);
479 if (en)
480 new_control |= ISP_BLS_ENA;
481 else
482 new_control &= ~ISP_BLS_ENA;
483 isp3_param_write(params_vdev, new_control, ISP3X_BLS_CTRL, id);
484 }
485
486 static void
isp_sdg_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_sdg_cfg * arg,u32 id)487 isp_sdg_config(struct rkisp_isp_params_vdev *params_vdev,
488 const struct isp2x_sdg_cfg *arg, u32 id)
489 {
490 int i;
491
492 isp3_param_write(params_vdev, arg->xa_pnts.gamma_dx0, ISP3X_ISP_GAMMA_DX_LO, id);
493 isp3_param_write(params_vdev, arg->xa_pnts.gamma_dx1, ISP3X_ISP_GAMMA_DX_HI, id);
494
495 for (i = 0; i < ISP3X_DEGAMMA_CURVE_SIZE; i++) {
496 isp3_param_write(params_vdev, arg->curve_r.gamma_y[i],
497 ISP3X_ISP_GAMMA_R_Y_0 + i * 4, id);
498 isp3_param_write(params_vdev, arg->curve_g.gamma_y[i],
499 ISP3X_ISP_GAMMA_G_Y_0 + i * 4, id);
500 isp3_param_write(params_vdev, arg->curve_b.gamma_y[i],
501 ISP3X_ISP_GAMMA_B_Y_0 + i * 4, id);
502 }
503 }
504
505 static void
isp_sdg_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)506 isp_sdg_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
507 {
508 if (en) {
509 isp3_param_set_bits(params_vdev,
510 ISP3X_ISP_CTRL0,
511 CIF_ISP_CTRL_ISP_GAMMA_IN_ENA, id);
512 } else {
513 isp3_param_clear_bits(params_vdev,
514 ISP3X_ISP_CTRL0,
515 CIF_ISP_CTRL_ISP_GAMMA_IN_ENA, id);
516 }
517 }
518
519 static void
isp_lsc_matrix_cfg_sram(struct rkisp_isp_params_vdev * params_vdev,const struct isp3x_lsc_cfg * pconfig,bool is_check,u32 id)520 isp_lsc_matrix_cfg_sram(struct rkisp_isp_params_vdev *params_vdev,
521 const struct isp3x_lsc_cfg *pconfig,
522 bool is_check, u32 id)
523 {
524 struct rkisp_device *dev = params_vdev->dev;
525 u32 sram_addr, data, table;
526 int i, j;
527
528 if (is_check &&
529 !(isp3_param_read(params_vdev, ISP3X_LSC_CTRL, id) & ISP_LSC_EN))
530 return;
531
532 table = isp3_param_read_direct(params_vdev, ISP3X_LSC_STATUS, id);
533 table &= ISP3X_LSC_ACTIVE_TABLE;
534 /* default table 0 for multi device */
535 if (!dev->hw_dev->is_single)
536 table = ISP3X_LSC_ACTIVE_TABLE;
537
538 /* CIF_ISP_LSC_TABLE_ADDRESS_153 = ( 17 * 18 ) >> 1 */
539 sram_addr = table ? ISP3X_LSC_TABLE_ADDRESS_0 : CIF_ISP_LSC_TABLE_ADDRESS_153;
540 isp3_param_write_direct(params_vdev, sram_addr, ISP3X_LSC_R_TABLE_ADDR, id);
541 isp3_param_write_direct(params_vdev, sram_addr, ISP3X_LSC_GR_TABLE_ADDR, id);
542 isp3_param_write_direct(params_vdev, sram_addr, ISP3X_LSC_GB_TABLE_ADDR, id);
543 isp3_param_write_direct(params_vdev, sram_addr, ISP3X_LSC_B_TABLE_ADDR, id);
544
545 /* program data tables (table size is 9 * 17 = 153) */
546 for (i = 0; i < CIF_ISP_LSC_SECTORS_MAX * CIF_ISP_LSC_SECTORS_MAX;
547 i += CIF_ISP_LSC_SECTORS_MAX) {
548 /*
549 * 17 sectors with 2 values in one DWORD = 9
550 * DWORDs (2nd value of last DWORD unused)
551 */
552 for (j = 0; j < CIF_ISP_LSC_SECTORS_MAX - 1; j += 2) {
553 data = ISP_ISP_LSC_TABLE_DATA(pconfig->r_data_tbl[i + j],
554 pconfig->r_data_tbl[i + j + 1]);
555 isp3_param_write_direct(params_vdev, data, ISP3X_LSC_R_TABLE_DATA, id);
556
557 data = ISP_ISP_LSC_TABLE_DATA(pconfig->gr_data_tbl[i + j],
558 pconfig->gr_data_tbl[i + j + 1]);
559 isp3_param_write_direct(params_vdev, data, ISP3X_LSC_GR_TABLE_DATA, id);
560
561 data = ISP_ISP_LSC_TABLE_DATA(pconfig->gb_data_tbl[i + j],
562 pconfig->gb_data_tbl[i + j + 1]);
563 isp3_param_write_direct(params_vdev, data, ISP3X_LSC_GB_TABLE_DATA, id);
564
565 data = ISP_ISP_LSC_TABLE_DATA(pconfig->b_data_tbl[i + j],
566 pconfig->b_data_tbl[i + j + 1]);
567 isp3_param_write_direct(params_vdev, data, ISP3X_LSC_B_TABLE_DATA, id);
568 }
569
570 data = ISP_ISP_LSC_TABLE_DATA(pconfig->r_data_tbl[i + j], 0);
571 isp3_param_write_direct(params_vdev, data, ISP3X_LSC_R_TABLE_DATA, id);
572
573 data = ISP_ISP_LSC_TABLE_DATA(pconfig->gr_data_tbl[i + j], 0);
574 isp3_param_write_direct(params_vdev, data, ISP3X_LSC_GR_TABLE_DATA, id);
575
576 data = ISP_ISP_LSC_TABLE_DATA(pconfig->gb_data_tbl[i + j], 0);
577 isp3_param_write_direct(params_vdev, data, ISP3X_LSC_GB_TABLE_DATA, id);
578
579 data = ISP_ISP_LSC_TABLE_DATA(pconfig->b_data_tbl[i + j], 0);
580 isp3_param_write_direct(params_vdev, data, ISP3X_LSC_B_TABLE_DATA, id);
581 }
582 isp3_param_write_direct(params_vdev, !table, ISP3X_LSC_TABLE_SEL, id);
583 }
584
585 static void
isp_lsc_cfg_sram_task(unsigned long data)586 isp_lsc_cfg_sram_task(unsigned long data)
587 {
588 struct rkisp_isp_params_vdev *params_vdev =
589 (struct rkisp_isp_params_vdev *)data;
590 struct isp3x_isp_params_cfg *params = params_vdev->isp3x_params;
591
592 isp_lsc_matrix_cfg_sram(params_vdev, ¶ms->others.lsc_cfg, true, 0);
593 if (params_vdev->dev->hw_dev->is_unite) {
594 params++;
595 isp_lsc_matrix_cfg_sram(params_vdev, ¶ms->others.lsc_cfg, true, 1);
596 }
597 }
598
599 static void
isp_lsc_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp3x_lsc_cfg * arg,u32 id)600 isp_lsc_config(struct rkisp_isp_params_vdev *params_vdev,
601 const struct isp3x_lsc_cfg *arg, u32 id)
602 {
603 struct rkisp_isp_params_val_v3x *priv_val =
604 (struct rkisp_isp_params_val_v3x *)params_vdev->priv_val;
605 struct isp3x_isp_params_cfg *params_rec = params_vdev->isp3x_params + id;
606 struct rkisp_device *dev = params_vdev->dev;
607 unsigned int data;
608 u32 lsc_ctrl;
609 int i;
610
611 /* To config must be off , store the current status firstly */
612 lsc_ctrl = isp3_param_read(params_vdev, ISP3X_LSC_CTRL, id);
613 isp3_param_clear_bits(params_vdev, ISP3X_LSC_CTRL, ISP_LSC_EN | BIT(2), id);
614 params_rec->others.lsc_cfg = *arg;
615 if (dev->hw_dev->is_single) {
616 if (lsc_ctrl & ISP_LSC_EN) {
617 /* latest config for ISP3_LEFT, unite isp or single isp */
618 if (id == ISP3_LEFT)
619 tasklet_schedule(&priv_val->lsc_tasklet);
620 } else {
621 isp_lsc_matrix_cfg_sram(params_vdev, arg, false, id);
622 }
623 }
624
625 for (i = 0; i < ISP3X_LSC_SIZE_TBL_SIZE / 4; i++) {
626 /* program x size tables */
627 data = CIF_ISP_LSC_SECT_SIZE(arg->x_size_tbl[i * 2],
628 arg->x_size_tbl[i * 2 + 1]);
629 isp3_param_write(params_vdev, data, ISP3X_LSC_XSIZE_01 + i * 4, id);
630 data = CIF_ISP_LSC_SECT_SIZE(arg->x_size_tbl[i * 2 + 8],
631 arg->x_size_tbl[i * 2 + 9]);
632 isp3_param_write(params_vdev, data, ISP3X_LSC_XSIZE_89 + i * 4, id);
633
634 /* program x grad tables */
635 data = CIF_ISP_LSC_SECT_SIZE(arg->x_grad_tbl[i * 2],
636 arg->x_grad_tbl[i * 2 + 1]);
637 isp3_param_write(params_vdev, data, ISP3X_LSC_XGRAD_01 + i * 4, id);
638 data = CIF_ISP_LSC_SECT_SIZE(arg->x_grad_tbl[i * 2 + 8],
639 arg->x_grad_tbl[i * 2 + 9]);
640 isp3_param_write(params_vdev, data, ISP3X_LSC_XGRAD_89 + i * 4, id);
641
642 /* program y size tables */
643 data = CIF_ISP_LSC_SECT_SIZE(arg->y_size_tbl[i * 2],
644 arg->y_size_tbl[i * 2 + 1]);
645 isp3_param_write(params_vdev, data, ISP3X_LSC_YSIZE_01 + i * 4, id);
646 data = CIF_ISP_LSC_SECT_SIZE(arg->y_size_tbl[i * 2 + 8],
647 arg->y_size_tbl[i * 2 + 9]);
648 isp3_param_write(params_vdev, data, ISP3X_LSC_YSIZE_89 + i * 4, id);
649
650 /* program y grad tables */
651 data = CIF_ISP_LSC_SECT_SIZE(arg->y_grad_tbl[i * 2],
652 arg->y_grad_tbl[i * 2 + 1]);
653 isp3_param_write(params_vdev, data, ISP3X_LSC_YGRAD_01 + i * 4, id);
654 data = CIF_ISP_LSC_SECT_SIZE(arg->y_grad_tbl[i * 2 + 8],
655 arg->y_grad_tbl[i * 2 + 9]);
656 isp3_param_write(params_vdev, data, ISP3X_LSC_YGRAD_89 + i * 4, id);
657 }
658
659 if (arg->sector_16x16)
660 lsc_ctrl |= BIT(2);
661 isp3_param_set_bits(params_vdev, ISP3X_LSC_CTRL, lsc_ctrl, id);
662 }
663
664 static void
isp_lsc_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)665 isp_lsc_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
666 {
667 u32 val = ISP_LSC_EN;
668
669 if (en) {
670 isp3_param_set_bits(params_vdev, ISP3X_LSC_CTRL, val, id);
671 } else {
672 isp3_param_clear_bits(params_vdev, ISP3X_LSC_CTRL, ISP_LSC_EN, id);
673 isp3_param_clear_bits(params_vdev, ISP3X_GAIN_CTRL, BIT(8), id);
674 }
675 }
676
677 static void
isp_debayer_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_debayer_cfg * arg,u32 id)678 isp_debayer_config(struct rkisp_isp_params_vdev *params_vdev,
679 const struct isp2x_debayer_cfg *arg, u32 id)
680 {
681 u32 value;
682
683 value = isp3_param_read(params_vdev, ISP3X_DEBAYER_CONTROL, id);
684 value &= ISP_DEBAYER_EN;
685
686 value |= (arg->filter_c_en & 0x01) << 8 |
687 (arg->filter_g_en & 0x01) << 4;
688 isp3_param_write(params_vdev, value, ISP3X_DEBAYER_CONTROL, id);
689
690 value = (arg->thed1 & 0x0F) << 12 |
691 (arg->thed0 & 0x0F) << 8 |
692 (arg->dist_scale & 0x0F) << 4 |
693 (arg->max_ratio & 0x07) << 1 |
694 (arg->clip_en & 0x01);
695 isp3_param_write(params_vdev, value, ISP3X_DEBAYER_G_INTERP, id);
696
697 value = (arg->filter1_coe5 & 0x0F) << 16 |
698 (arg->filter1_coe4 & 0x0F) << 12 |
699 (arg->filter1_coe3 & 0x0F) << 8 |
700 (arg->filter1_coe2 & 0x0F) << 4 |
701 (arg->filter1_coe1 & 0x0F);
702 isp3_param_write(params_vdev, value, ISP3X_DEBAYER_G_INTERP_FILTER1, id);
703
704 value = (arg->filter2_coe5 & 0x0F) << 16 |
705 (arg->filter2_coe4 & 0x0F) << 12 |
706 (arg->filter2_coe3 & 0x0F) << 8 |
707 (arg->filter2_coe2 & 0x0F) << 4 |
708 (arg->filter2_coe1 & 0x0F);
709 isp3_param_write(params_vdev, value, ISP3X_DEBAYER_G_INTERP_FILTER2, id);
710
711 value = (arg->hf_offset & 0xFFFF) << 16 |
712 (arg->gain_offset & 0x0F) << 8 |
713 (arg->offset & 0x1F);
714 isp3_param_write(params_vdev, value, ISP3X_DEBAYER_OFFSET, id);
715
716 value = (arg->shift_num & 0x03) << 16 |
717 (arg->order_max & 0x1F) << 8 |
718 (arg->order_min & 0x1F);
719 isp3_param_write(params_vdev, value, ISP3X_DEBAYER_C_FILTER, id);
720 }
721
722 static void
isp_debayer_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)723 isp_debayer_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
724 {
725 if (en)
726 isp3_param_set_bits(params_vdev,
727 ISP3X_DEBAYER_CONTROL,
728 ISP3X_MODULE_EN, id);
729 else
730 isp3_param_clear_bits(params_vdev,
731 ISP3X_DEBAYER_CONTROL,
732 ISP3X_MODULE_EN, id);
733 }
734
735 static void
isp_awbgain_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp21_awb_gain_cfg * arg,u32 id)736 isp_awbgain_config(struct rkisp_isp_params_vdev *params_vdev,
737 const struct isp21_awb_gain_cfg *arg, u32 id)
738 {
739 struct rkisp_device *dev = params_vdev->dev;
740
741 if (!arg->gain0_red || !arg->gain0_blue ||
742 !arg->gain1_red || !arg->gain1_blue ||
743 !arg->gain2_red || !arg->gain2_blue ||
744 !arg->gain0_green_r || !arg->gain0_green_b ||
745 !arg->gain1_green_r || !arg->gain1_green_b ||
746 !arg->gain2_green_r || !arg->gain2_green_b) {
747 dev_err(dev->dev, "awb gain is zero!\n");
748 return;
749 }
750
751 isp3_param_write(params_vdev,
752 ISP_PACK_2SHORT(arg->gain0_green_b, arg->gain0_green_r),
753 ISP3X_ISP_AWB_GAIN0_G, id);
754 isp3_param_write(params_vdev,
755 ISP_PACK_2SHORT(arg->gain0_blue, arg->gain0_red),
756 ISP3X_ISP_AWB_GAIN0_RB, id);
757
758 isp3_param_write(params_vdev,
759 ISP_PACK_2SHORT(arg->gain1_green_b, arg->gain1_green_r),
760 ISP3X_ISP_AWB_GAIN1_G, id);
761 isp3_param_write(params_vdev,
762 ISP_PACK_2SHORT(arg->gain1_blue, arg->gain1_red),
763 ISP3X_ISP_AWB_GAIN1_RB, id);
764
765 isp3_param_write(params_vdev,
766 ISP_PACK_2SHORT(arg->gain2_green_b, arg->gain2_green_r),
767 ISP3X_ISP_AWB_GAIN2_G, id);
768 isp3_param_write(params_vdev,
769 ISP_PACK_2SHORT(arg->gain2_blue, arg->gain2_red),
770 ISP3X_ISP_AWB_GAIN2_RB, id);
771 }
772
773 static void
isp_awbgain_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)774 isp_awbgain_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
775 {
776 if (en)
777 isp3_param_set_bits(params_vdev, ISP3X_ISP_CTRL0,
778 CIF_ISP_CTRL_ISP_AWB_ENA, id);
779 else
780 isp3_param_clear_bits(params_vdev, ISP3X_ISP_CTRL0,
781 CIF_ISP_CTRL_ISP_AWB_ENA, id);
782 }
783
784 static void
isp_ccm_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp21_ccm_cfg * arg,u32 id)785 isp_ccm_config(struct rkisp_isp_params_vdev *params_vdev,
786 const struct isp21_ccm_cfg *arg, u32 id)
787 {
788 u32 value;
789 u32 i;
790
791 value = isp3_param_read(params_vdev, ISP3X_CCM_CTRL, id);
792 value &= ISP_CCM_EN;
793
794 value |= (arg->highy_adjust_dis & 0x01) << 1;
795 isp3_param_write(params_vdev, value, ISP3X_CCM_CTRL, id);
796
797 value = ISP_PACK_2SHORT(arg->coeff0_r, arg->coeff1_r);
798 isp3_param_write(params_vdev, value, ISP3X_CCM_COEFF0_R, id);
799
800 value = ISP_PACK_2SHORT(arg->coeff2_r, arg->offset_r);
801 isp3_param_write(params_vdev, value, ISP3X_CCM_COEFF1_R, id);
802
803 value = ISP_PACK_2SHORT(arg->coeff0_g, arg->coeff1_g);
804 isp3_param_write(params_vdev, value, ISP3X_CCM_COEFF0_G, id);
805
806 value = ISP_PACK_2SHORT(arg->coeff2_g, arg->offset_g);
807 isp3_param_write(params_vdev, value, ISP3X_CCM_COEFF1_G, id);
808
809 value = ISP_PACK_2SHORT(arg->coeff0_b, arg->coeff1_b);
810 isp3_param_write(params_vdev, value, ISP3X_CCM_COEFF0_B, id);
811
812 value = ISP_PACK_2SHORT(arg->coeff2_b, arg->offset_b);
813 isp3_param_write(params_vdev, value, ISP3X_CCM_COEFF1_B, id);
814
815 value = ISP_PACK_2SHORT(arg->coeff0_y, arg->coeff1_y);
816 isp3_param_write(params_vdev, value, ISP3X_CCM_COEFF0_Y, id);
817
818 value = ISP_PACK_2SHORT(arg->coeff2_y, 0);
819 isp3_param_write(params_vdev, value, ISP3X_CCM_COEFF1_Y, id);
820
821 for (i = 0; i < ISP3X_CCM_CURVE_NUM / 2; i++) {
822 value = ISP_PACK_2SHORT(arg->alp_y[2 * i], arg->alp_y[2 * i + 1]);
823 isp3_param_write(params_vdev, value, ISP3X_CCM_ALP_Y0 + 4 * i, id);
824 }
825 value = ISP_PACK_2SHORT(arg->alp_y[2 * i], 0);
826 isp3_param_write(params_vdev, value, ISP3X_CCM_ALP_Y0 + 4 * i, id);
827
828 value = arg->bound_bit & 0x0F;
829 isp3_param_write(params_vdev, value, ISP3X_CCM_BOUND_BIT, id);
830 }
831
832 static void
isp_ccm_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)833 isp_ccm_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
834 {
835 if (en)
836 isp3_param_set_bits(params_vdev, ISP3X_CCM_CTRL, ISP_CCM_EN, id);
837 else
838 isp3_param_clear_bits(params_vdev, ISP3X_CCM_CTRL, ISP_CCM_EN, id);
839 }
840
841 static void
isp_goc_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp3x_gammaout_cfg * arg,u32 id)842 isp_goc_config(struct rkisp_isp_params_vdev *params_vdev,
843 const struct isp3x_gammaout_cfg *arg, u32 id)
844 {
845 int i;
846 u32 value;
847
848 value = isp3_param_read(params_vdev, ISP3X_GAMMA_OUT_CTRL, id);
849 value &= ISP3X_GAMMA_OUT_EN;
850 value |= (arg->equ_segm & 0x1) << 1 |
851 (arg->finalx4_dense_en & 0x1) << 2;
852 isp3_param_write(params_vdev, value, ISP3X_GAMMA_OUT_CTRL, id);
853
854 isp3_param_write(params_vdev, arg->offset, ISP3X_GAMMA_OUT_OFFSET, id);
855 for (i = 0; i < ISP3X_GAMMA_OUT_MAX_SAMPLES / 2; i++) {
856 value = ISP_PACK_2SHORT(arg->gamma_y[2 * i],
857 arg->gamma_y[2 * i + 1]);
858 isp3_param_write(params_vdev, value, ISP3X_GAMMA_OUT_Y0 + i * 4, id);
859 }
860 isp3_param_write(params_vdev, arg->gamma_y[2 * i], ISP3X_GAMMA_OUT_Y0 + i * 4, id);
861 }
862
863 static void
isp_goc_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)864 isp_goc_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
865 {
866 if (en)
867 isp3_param_set_bits(params_vdev, ISP3X_GAMMA_OUT_CTRL,
868 ISP3X_GAMMA_OUT_EN, id);
869 else
870 isp3_param_clear_bits(params_vdev, ISP3X_GAMMA_OUT_CTRL,
871 ISP3X_GAMMA_OUT_EN, id);
872 }
873
874 static void
isp_cproc_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_cproc_cfg * arg,u32 id)875 isp_cproc_config(struct rkisp_isp_params_vdev *params_vdev,
876 const struct isp2x_cproc_cfg *arg, u32 id)
877 {
878 struct isp3x_isp_params_cfg *params = params_vdev->isp3x_params + id;
879 struct isp3x_isp_other_cfg *cur_other_cfg = ¶ms->others;
880 struct isp2x_ie_cfg *cur_ie_config = &cur_other_cfg->ie_cfg;
881 u32 effect = cur_ie_config->effect;
882 u32 quantization = params_vdev->quantization;
883
884 isp3_param_write(params_vdev, arg->contrast, ISP3X_CPROC_CONTRAST, id);
885 isp3_param_write(params_vdev, arg->hue, ISP3X_CPROC_HUE, id);
886 isp3_param_write(params_vdev, arg->sat, ISP3X_CPROC_SATURATION, id);
887 isp3_param_write(params_vdev, arg->brightness, ISP3X_CPROC_BRIGHTNESS, id);
888
889 if (quantization != V4L2_QUANTIZATION_FULL_RANGE ||
890 effect != V4L2_COLORFX_NONE) {
891 isp3_param_clear_bits(params_vdev, ISP3X_CPROC_CTRL,
892 CIF_C_PROC_YOUT_FULL |
893 CIF_C_PROC_YIN_FULL |
894 CIF_C_PROC_COUT_FULL, id);
895 } else {
896 isp3_param_set_bits(params_vdev, ISP3X_CPROC_CTRL,
897 CIF_C_PROC_YOUT_FULL |
898 CIF_C_PROC_YIN_FULL |
899 CIF_C_PROC_COUT_FULL, id);
900 }
901 }
902
903 static void
isp_cproc_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)904 isp_cproc_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
905 {
906 if (en)
907 isp3_param_set_bits(params_vdev, ISP3X_CPROC_CTRL,
908 CIF_C_PROC_CTR_ENABLE, id);
909 else
910 isp3_param_clear_bits(params_vdev, ISP3X_CPROC_CTRL,
911 CIF_C_PROC_CTR_ENABLE, id);
912 }
913
914 static void
isp_ie_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_ie_cfg * arg,u32 id)915 isp_ie_config(struct rkisp_isp_params_vdev *params_vdev,
916 const struct isp2x_ie_cfg *arg, u32 id)
917 {
918 u32 eff_ctrl;
919
920 eff_ctrl = isp3_param_read(params_vdev, ISP3X_IMG_EFF_CTRL, id);
921 eff_ctrl &= ~CIF_IMG_EFF_CTRL_MODE_MASK;
922
923 if (params_vdev->quantization == V4L2_QUANTIZATION_FULL_RANGE)
924 eff_ctrl |= CIF_IMG_EFF_CTRL_YCBCR_FULL;
925
926 switch (arg->effect) {
927 case V4L2_COLORFX_SEPIA:
928 eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_SEPIA;
929 break;
930 case V4L2_COLORFX_SET_CBCR:
931 isp3_param_write(params_vdev, arg->eff_tint, ISP3X_IMG_EFF_TINT, id);
932 eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_SEPIA;
933 break;
934 /*
935 * Color selection is similar to water color(AQUA):
936 * grayscale + selected color w threshold
937 */
938 case V4L2_COLORFX_AQUA:
939 eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_COLOR_SEL;
940 isp3_param_write(params_vdev, arg->color_sel,
941 ISP3X_IMG_EFF_COLOR_SEL, id);
942 break;
943 case V4L2_COLORFX_EMBOSS:
944 eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_EMBOSS;
945 isp3_param_write(params_vdev, arg->eff_mat_1,
946 CIF_IMG_EFF_MAT_1, id);
947 isp3_param_write(params_vdev, arg->eff_mat_2,
948 CIF_IMG_EFF_MAT_2, id);
949 isp3_param_write(params_vdev, arg->eff_mat_3,
950 CIF_IMG_EFF_MAT_3, id);
951 break;
952 case V4L2_COLORFX_SKETCH:
953 eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_SKETCH;
954 isp3_param_write(params_vdev, arg->eff_mat_3,
955 CIF_IMG_EFF_MAT_3, id);
956 isp3_param_write(params_vdev, arg->eff_mat_4,
957 CIF_IMG_EFF_MAT_4, id);
958 isp3_param_write(params_vdev, arg->eff_mat_5,
959 CIF_IMG_EFF_MAT_5, id);
960 break;
961 case V4L2_COLORFX_BW:
962 eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_BLACKWHITE;
963 break;
964 case V4L2_COLORFX_NEGATIVE:
965 eff_ctrl |= CIF_IMG_EFF_CTRL_MODE_NEGATIVE;
966 break;
967 default:
968 break;
969 }
970
971 isp3_param_write(params_vdev, eff_ctrl, ISP3X_IMG_EFF_CTRL, id);
972 }
973
974 static void
isp_ie_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)975 isp_ie_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
976 {
977 if (en) {
978 isp3_param_set_bits(params_vdev, ISP3X_IMG_EFF_CTRL,
979 CIF_IMG_EFF_CTRL_CFG_UPD |
980 CIF_IMG_EFF_CTRL_ENABLE, id);
981 } else {
982 isp3_param_clear_bits(params_vdev, ISP3X_IMG_EFF_CTRL,
983 CIF_IMG_EFF_CTRL_ENABLE, id);
984 }
985 }
986
987 static void
isp_rawaebig_config_foraf(struct rkisp_isp_params_vdev * params_vdev,const struct isp3x_rawaf_meas_cfg * arg,u32 id)988 isp_rawaebig_config_foraf(struct rkisp_isp_params_vdev *params_vdev,
989 const struct isp3x_rawaf_meas_cfg *arg, u32 id)
990 {
991 u32 block_hsize, block_vsize;
992 u32 addr, value;
993 u32 wnd_num_idx = 2;
994 const u32 ae_wnd_num[] = {
995 1, 5, 15, 15
996 };
997
998 addr = ISP3X_RAWAE_BIG1_BASE;
999 value = isp3_param_read(params_vdev, addr + ISP3X_RAWAE_BIG_CTRL, id);
1000 value &= ISP3X_RAWAE_BIG_EN;
1001
1002 value |= ISP3X_RAWAE_BIG_WND0_NUM(wnd_num_idx);
1003 isp3_param_write(params_vdev, value, addr + ISP3X_RAWAE_BIG_CTRL, id);
1004
1005 isp3_param_write(params_vdev,
1006 ISP_PACK_2SHORT(arg->win[0].h_offs, arg->win[0].v_offs),
1007 addr + ISP3X_RAWAE_BIG_OFFSET, id);
1008
1009 block_hsize = arg->win[0].h_size / ae_wnd_num[wnd_num_idx];
1010 block_vsize = arg->win[0].v_size / ae_wnd_num[wnd_num_idx];
1011 isp3_param_write(params_vdev,
1012 ISP_PACK_2SHORT(block_hsize, block_vsize),
1013 addr + ISP3X_RAWAE_BIG_BLK_SIZE, id);
1014 }
1015
1016 static void
isp_rawaf_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp3x_rawaf_meas_cfg * arg,u32 id)1017 isp_rawaf_config(struct rkisp_isp_params_vdev *params_vdev,
1018 const struct isp3x_rawaf_meas_cfg *arg, u32 id)
1019 {
1020 u32 i, var, ctrl;
1021 u16 h_size, v_size;
1022 u16 h_offs, v_offs;
1023 u8 gaus_en, viir_en, v1_fir_sel;
1024 size_t num_of_win = min_t(size_t, ARRAY_SIZE(arg->win),
1025 arg->num_afm_win);
1026
1027 for (i = 0; i < num_of_win; i++) {
1028 h_size = arg->win[i].h_size;
1029 v_size = arg->win[i].v_size;
1030 h_offs = arg->win[i].h_offs < 2 ? 2 : arg->win[i].h_offs;
1031 v_offs = arg->win[i].v_offs < 1 ? 1 : arg->win[i].v_offs;
1032
1033 if (i == 0) {
1034 h_size = h_size / 15 * 15;
1035 v_size = v_size / 15 * 15;
1036 }
1037
1038 /*
1039 * (horizontal left row), value must be greater or equal 2
1040 * (vertical top line), value must be greater or equal 1
1041 */
1042 isp3_param_write(params_vdev,
1043 ISP_PACK_2SHORT(v_offs, h_offs),
1044 ISP3X_RAWAF_OFFSET_WINA + i * 8, id);
1045
1046 /*
1047 * value must be smaller than [width of picture -2]
1048 * value must be lower than (number of lines -2)
1049 */
1050 isp3_param_write(params_vdev,
1051 ISP_PACK_2SHORT(v_size, h_size),
1052 ISP3X_RAWAF_SIZE_WINA + i * 8, id);
1053 }
1054
1055 var = 0;
1056 for (i = 0; i < ISP3X_RAWAF_LINE_NUM; i++) {
1057 if (arg->line_en[i])
1058 var |= ISP3X_RAWAF_INTLINE0_EN << i;
1059 var |= ISP3X_RAWAF_INELINE0(arg->line_num[i]) << 4 * i;
1060 }
1061 isp3_param_write(params_vdev, var, ISP3X_RAWAF_INT_LINE, id);
1062
1063 var = isp3_param_read(params_vdev, ISP3X_RAWAF_THRES, id);
1064 var &= ~0xFFFF;
1065 var |= arg->afm_thres;
1066 isp3_param_write(params_vdev, var, ISP3X_RAWAF_THRES, id);
1067
1068 var = (arg->lum_var_shift[1] & 0x7) << 20 | (arg->lum_var_shift[0] & 0x7) << 16 |
1069 (arg->afm_var_shift[1] & 0x7) << 4 | (arg->afm_var_shift[0] & 0x7);
1070 isp3_param_write(params_vdev, var, ISP3X_RAWAF_VAR_SHIFT, id);
1071
1072 for (i = 0; i < ISP3X_RAWAF_GAMMA_NUM / 2; i++) {
1073 var = ISP_PACK_2SHORT(arg->gamma_y[2 * i], arg->gamma_y[2 * i + 1]);
1074 isp3_param_write(params_vdev, var, ISP3X_RAWAF_GAMMA_Y0 + i * 4, id);
1075 }
1076 var = ISP_PACK_2SHORT(arg->gamma_y[16], 0);
1077 isp3_param_write(params_vdev, var, ISP3X_RAWAF_GAMMA_Y8, id);
1078
1079 var = (arg->v2iir_var_shift & 0x7) << 12 | (arg->v1iir_var_shift & 0x7) << 8 |
1080 (arg->h2iir_var_shift & 0x7) << 4 | (arg->h1iir_var_shift & 0x7);
1081 isp3_param_write(params_vdev, var, ISP3X_RAWAF_HVIIR_VAR_SHIFT, id);
1082
1083 var = ISP_PACK_2SHORT(arg->h_fv_thresh, arg->v_fv_thresh);
1084 isp3_param_write(params_vdev, var, ISP3X_RAWAF_HIIR_THRESH, id);
1085
1086 for (i = 0; i < ISP3X_RAWAF_VFIR_COE_NUM; i++) {
1087 var = ISP_PACK_2SHORT(arg->v1fir_coe[i], arg->v2fir_coe[i]);
1088 isp3_param_write(params_vdev, var, ISP3X_RAWAF_V_FIR_COE0 + i * 4, id);
1089 }
1090
1091 isp3_param_write(params_vdev, arg->highlit_thresh, ISP3X_RAWAF_HIGHLIT_THRESH, id);
1092
1093 viir_en = arg->viir_en;
1094 gaus_en = arg->gaus_en;
1095 v1_fir_sel = arg->v1_fir_sel;
1096 if (gaus_en == 0)
1097 viir_en = 0;
1098 if (viir_en == 0)
1099 v1_fir_sel = 0;
1100
1101 ctrl = isp3_param_read(params_vdev, ISP3X_RAWAF_CTRL, id);
1102 ctrl &= ISP3X_RAWAF_EN;
1103 if (arg->hiir_en) {
1104 ctrl |= ISP3X_RAWAF_HIIR_EN;
1105 for (i = 0; i < ISP3X_RAWAF_HIIR_COE_NUM / 2; i++) {
1106 var = ISP_PACK_2SHORT(arg->h1iir1_coe[i * 2], arg->h1iir1_coe[i * 2 + 1]);
1107 isp3_param_write(params_vdev, var, ISP3X_RAWAF_H1_IIR1_COE01 + i * 4, id);
1108 var = ISP_PACK_2SHORT(arg->h1iir2_coe[i * 2], arg->h1iir2_coe[i * 2 + 1]);
1109 isp3_param_write(params_vdev, var, ISP3X_RAWAF_H1_IIR2_COE01 + i * 4, id);
1110 var = ISP_PACK_2SHORT(arg->h2iir1_coe[i * 2], arg->h2iir1_coe[i * 2 + 1]);
1111 isp3_param_write(params_vdev, var, ISP3X_RAWAF_H2_IIR1_COE01 + i * 4, id);
1112 var = ISP_PACK_2SHORT(arg->h2iir2_coe[i * 2], arg->h2iir2_coe[i * 2 + 1]);
1113 isp3_param_write(params_vdev, var, ISP3X_RAWAF_H2_IIR2_COE01 + i * 4, id);
1114 }
1115 }
1116 if (viir_en) {
1117 ctrl |= ISP3X_RAWAF_VIIR_EN;
1118 for (i = 0; i < ISP3X_RAWAF_V2IIR_COE_NUM; i++) {
1119 var = ISP_PACK_2SHORT(arg->v1iir_coe[i], arg->v2iir_coe[i]);
1120 isp3_param_write(params_vdev, var, ISP3X_RAWAF_V_IIR_COE0 + i * 4, id);
1121 }
1122 for (; i < ISP3X_RAWAF_V1IIR_COE_NUM; i++) {
1123 var = ISP_PACK_2SHORT(arg->v1iir_coe[i], 0);
1124 isp3_param_write(params_vdev, var, ISP3X_RAWAF_V_IIR_COE0 + i * 4, id);
1125 }
1126 }
1127 if (arg->ldg_en) {
1128 ctrl |= ISP3X_RAWAF_LDG_EN;
1129 for (i = 0; i < ISP3X_RAWAF_CURVE_NUM; i++) {
1130 isp3_param_write(params_vdev,
1131 arg->curve_h[i].ldg_lumth |
1132 arg->curve_h[i].ldg_gain << 8 |
1133 arg->curve_h[i].ldg_gslp << 16,
1134 ISP3X_RAWAF_H_CURVEL + i * 16, id);
1135 isp3_param_write(params_vdev,
1136 arg->curve_v[i].ldg_lumth |
1137 arg->curve_v[i].ldg_gain << 8 |
1138 arg->curve_v[i].ldg_gslp << 16,
1139 ISP3X_RAWAF_V_CURVEL + i * 16, id);
1140 }
1141 }
1142
1143 ctrl |= (arg->y_mode & 0x1) << 13 |
1144 (arg->ae_mode & 0x1) << 12 |
1145 (arg->v2_fv_mode & 0x1) << 11 |
1146 (arg->v1_fv_mode & 0x1) << 10 |
1147 (arg->h2_fv_mode & 0x1) << 9 |
1148 (arg->h1_fv_mode & 0x1) << 8 |
1149 (arg->accu_8bit_mode & 0x1) << 6 |
1150 (v1_fir_sel & 0x1) << 3 |
1151 (gaus_en & 0x1) << 2 |
1152 (arg->gamma_en & 0x1) << 1;
1153 isp3_param_write(params_vdev, ctrl, ISP3X_RAWAF_CTRL, id);
1154
1155 ctrl = isp3_param_read(params_vdev, ISP3X_VI_ISP_PATH, id);
1156 ctrl &= ~(ISP3X_RAWAF_SEL(3));
1157 ctrl |= ISP3X_RAWAF_SEL(arg->rawaf_sel);
1158 isp3_param_write(params_vdev, ctrl, ISP3X_VI_ISP_PATH, id);
1159
1160 params_vdev->afaemode_en = arg->ae_mode;
1161 if (params_vdev->afaemode_en)
1162 isp_rawaebig_config_foraf(params_vdev, arg, id);
1163 }
1164
1165 static void
isp_rawaebig_enable_foraf(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)1166 isp_rawaebig_enable_foraf(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
1167 {
1168 u32 exp_ctrl;
1169 u32 addr = ISP3X_RAWAE_BIG1_BASE;
1170
1171 exp_ctrl = isp3_param_read(params_vdev, addr + ISP3X_RAWAE_BIG_CTRL, id);
1172 exp_ctrl &= ~ISP3X_REG_WR_MASK;
1173 if (en)
1174 exp_ctrl |= ISP3X_MODULE_EN;
1175 else
1176 exp_ctrl &= ~ISP3X_MODULE_EN;
1177
1178 isp3_param_write(params_vdev, exp_ctrl, addr + ISP3X_RAWAE_BIG_CTRL, id);
1179 }
1180
1181 static void
isp_rawaf_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)1182 isp_rawaf_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
1183 {
1184 u32 afm_ctrl = isp3_param_read(params_vdev, ISP3X_RAWAF_CTRL, id);
1185
1186 afm_ctrl &= ~ISP3X_REG_WR_MASK;
1187 if (en)
1188 afm_ctrl |= ISP3X_RAWAF_EN;
1189 else
1190 afm_ctrl &= ~ISP3X_RAWAF_EN;
1191
1192 isp3_param_write(params_vdev, afm_ctrl, ISP3X_RAWAF_CTRL, id);
1193 if (params_vdev->afaemode_en) {
1194 isp_rawaebig_enable_foraf(params_vdev, en, id);
1195 if (!en)
1196 params_vdev->afaemode_en = false;
1197 }
1198 }
1199
1200 static void
isp_rawaelite_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawaelite_meas_cfg * arg,u32 id)1201 isp_rawaelite_config(struct rkisp_isp_params_vdev *params_vdev,
1202 const struct isp2x_rawaelite_meas_cfg *arg, u32 id)
1203 {
1204 struct rkisp_device *ispdev = params_vdev->dev;
1205 struct v4l2_rect *out_crop = &ispdev->isp_sdev.out_crop;
1206 u32 width = out_crop->width;
1207 u32 block_hsize, block_vsize, value;
1208 u32 wnd_num_idx = 0;
1209 const u32 ae_wnd_num[] = {1, 5};
1210
1211 value = isp3_param_read(params_vdev, ISP3X_RAWAE_LITE_CTRL, id);
1212 value &= ~(ISP3X_RAWAE_LITE_WNDNUM);
1213 if (arg->wnd_num) {
1214 value |= ISP3X_RAWAE_LITE_WNDNUM;
1215 wnd_num_idx = 1;
1216 }
1217 value &= ~ISP3X_REG_WR_MASK;
1218 isp3_param_write(params_vdev, value, ISP3X_RAWAE_LITE_CTRL, id);
1219
1220 isp3_param_write(params_vdev,
1221 ISP_PACK_2SHORT(arg->win.h_offs, arg->win.v_offs),
1222 ISP3X_RAWAE_LITE_OFFSET, id);
1223
1224 block_hsize = arg->win.h_size / ae_wnd_num[wnd_num_idx];
1225 value = block_hsize * ae_wnd_num[wnd_num_idx] + arg->win.h_offs;
1226 if (ispdev->hw_dev->is_unite)
1227 width = width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
1228 if (value + 1 > width)
1229 block_hsize -= 1;
1230 block_vsize = arg->win.v_size / ae_wnd_num[wnd_num_idx];
1231 value = block_vsize * ae_wnd_num[wnd_num_idx] + arg->win.v_offs;
1232 if (value + 2 > out_crop->height)
1233 block_vsize -= 1;
1234 if (block_vsize % 2)
1235 block_vsize -= 1;
1236 isp3_param_write(params_vdev,
1237 ISP_PACK_2SHORT(block_hsize, block_vsize),
1238 ISP3X_RAWAE_LITE_BLK_SIZ, id);
1239
1240 value = isp3_param_read(params_vdev, ISP3X_VI_ISP_PATH, id);
1241 value &= ~(ISP3X_RAWAE012_SEL(3));
1242 value |= ISP3X_RAWAE012_SEL(arg->rawae_sel);
1243 isp3_param_write(params_vdev, value, ISP3X_VI_ISP_PATH, id);
1244 }
1245
1246 static void
isp_rawaelite_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)1247 isp_rawaelite_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
1248 {
1249 u32 exp_ctrl;
1250
1251 exp_ctrl = isp3_param_read(params_vdev, ISP3X_RAWAE_LITE_CTRL, id);
1252 exp_ctrl &= ~ISP3X_REG_WR_MASK;
1253 if (en)
1254 exp_ctrl |= ISP3X_RAWAE_LITE_EN;
1255 else
1256 exp_ctrl &= ~ISP3X_RAWAE_LITE_EN;
1257
1258 isp3_param_write(params_vdev, exp_ctrl, ISP3X_RAWAE_LITE_CTRL, id);
1259 }
1260
1261 static void
isp_rawaebig_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawaebig_meas_cfg * arg,u32 blk_no,u32 id)1262 isp_rawaebig_config(struct rkisp_isp_params_vdev *params_vdev,
1263 const struct isp2x_rawaebig_meas_cfg *arg,
1264 u32 blk_no, u32 id)
1265 {
1266 struct rkisp_device *ispdev = params_vdev->dev;
1267 struct v4l2_rect *out_crop = &ispdev->isp_sdev.out_crop;
1268 u32 width = out_crop->width;
1269 u32 block_hsize, block_vsize;
1270 u32 addr, i, value, h_size, v_size;
1271 u32 wnd_num_idx = 0;
1272 const u32 ae_wnd_num[] = {
1273 1, 5, 15, 15
1274 };
1275
1276 switch (blk_no) {
1277 case 1:
1278 addr = ISP3X_RAWAE_BIG2_BASE;
1279 break;
1280 case 2:
1281 addr = ISP3X_RAWAE_BIG3_BASE;
1282 break;
1283 case 0:
1284 default:
1285 addr = ISP3X_RAWAE_BIG1_BASE;
1286 break;
1287 }
1288
1289 /* avoid to override the old enable value */
1290 value = isp3_param_read(params_vdev, addr + ISP3X_RAWAE_BIG_CTRL, id);
1291 value &= ISP3X_RAWAE_BIG_EN;
1292
1293 wnd_num_idx = arg->wnd_num;
1294 value |= ISP3X_RAWAE_BIG_WND0_NUM(wnd_num_idx);
1295
1296 if (arg->subwin_en[0])
1297 value |= ISP3X_RAWAE_BIG_WND1_EN;
1298 if (arg->subwin_en[1])
1299 value |= ISP3X_RAWAE_BIG_WND2_EN;
1300 if (arg->subwin_en[2])
1301 value |= ISP3X_RAWAE_BIG_WND3_EN;
1302 if (arg->subwin_en[3])
1303 value |= ISP3X_RAWAE_BIG_WND4_EN;
1304
1305 isp3_param_write(params_vdev, value, addr + ISP3X_RAWAE_BIG_CTRL, id);
1306
1307 isp3_param_write(params_vdev,
1308 ISP_PACK_2SHORT(arg->win.h_offs, arg->win.v_offs),
1309 addr + ISP3X_RAWAE_BIG_OFFSET, id);
1310
1311 block_hsize = arg->win.h_size / ae_wnd_num[wnd_num_idx];
1312 value = block_hsize * ae_wnd_num[wnd_num_idx] + arg->win.h_offs;
1313 if (ispdev->hw_dev->is_unite)
1314 width = width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
1315 if (value + 1 > width)
1316 block_hsize -= 1;
1317 block_vsize = arg->win.v_size / ae_wnd_num[wnd_num_idx];
1318 value = block_vsize * ae_wnd_num[wnd_num_idx] + arg->win.v_offs;
1319 if (value + 2 > out_crop->height)
1320 block_vsize -= 1;
1321 if (block_vsize % 2)
1322 block_vsize -= 1;
1323 isp3_param_write(params_vdev,
1324 ISP_PACK_2SHORT(block_hsize, block_vsize),
1325 addr + ISP3X_RAWAE_BIG_BLK_SIZE, id);
1326
1327 for (i = 0; i < ISP3X_RAWAEBIG_SUBWIN_NUM; i++) {
1328 isp3_param_write(params_vdev,
1329 ISP_PACK_2SHORT(arg->subwin[i].h_offs, arg->subwin[i].v_offs),
1330 addr + ISP3X_RAWAE_BIG_WND1_OFFSET + 8 * i, id);
1331
1332 v_size = arg->subwin[i].v_size + arg->subwin[i].v_offs;
1333 h_size = arg->subwin[i].h_size + arg->subwin[i].h_offs;
1334 isp3_param_write(params_vdev,
1335 ISP_PACK_2SHORT(h_size, v_size),
1336 addr + ISP3X_RAWAE_BIG_WND1_SIZE + 8 * i, id);
1337 }
1338
1339 if (blk_no == 0) {
1340 value = isp3_param_read(params_vdev, ISP3X_VI_ISP_PATH, id);
1341 value &= ~(ISP3X_RAWAE3_SEL(3));
1342 value |= ISP3X_RAWAE3_SEL(arg->rawae_sel);
1343 isp3_param_write(params_vdev, value, ISP3X_VI_ISP_PATH, id);
1344 } else {
1345 value = isp3_param_read(params_vdev, ISP3X_VI_ISP_PATH, id);
1346 value &= ~(ISP3X_RAWAE012_SEL(3));
1347 value |= ISP3X_RAWAE012_SEL(arg->rawae_sel);
1348 isp3_param_write(params_vdev, value, ISP3X_VI_ISP_PATH, id);
1349 }
1350 }
1351
1352 static void
isp_rawaebig_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 blk_no,u32 id)1353 isp_rawaebig_enable(struct rkisp_isp_params_vdev *params_vdev,
1354 bool en, u32 blk_no, u32 id)
1355 {
1356 u32 exp_ctrl;
1357 u32 addr;
1358
1359 switch (blk_no) {
1360 case 1:
1361 addr = ISP3X_RAWAE_BIG2_BASE;
1362 break;
1363 case 2:
1364 addr = ISP3X_RAWAE_BIG3_BASE;
1365 break;
1366 case 0:
1367 default:
1368 addr = ISP3X_RAWAE_BIG1_BASE;
1369 break;
1370 }
1371
1372 exp_ctrl = isp3_param_read(params_vdev, addr + ISP3X_RAWAE_BIG_CTRL, id);
1373 exp_ctrl &= ~ISP3X_REG_WR_MASK;
1374 if (en)
1375 exp_ctrl |= ISP3X_MODULE_EN;
1376 else
1377 exp_ctrl &= ~ISP3X_MODULE_EN;
1378
1379 isp3_param_write(params_vdev, exp_ctrl, addr + ISP3X_RAWAE_BIG_CTRL, id);
1380 }
1381
1382 static void
isp_rawae1_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawaebig_meas_cfg * arg,u32 id)1383 isp_rawae1_config(struct rkisp_isp_params_vdev *params_vdev,
1384 const struct isp2x_rawaebig_meas_cfg *arg, u32 id)
1385 {
1386 isp_rawaebig_config(params_vdev, arg, 1, id);
1387 }
1388
1389 static void
isp_rawae1_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)1390 isp_rawae1_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
1391 {
1392 isp_rawaebig_enable(params_vdev, en, 1, id);
1393 }
1394
1395 static void
isp_rawae2_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawaebig_meas_cfg * arg,u32 id)1396 isp_rawae2_config(struct rkisp_isp_params_vdev *params_vdev,
1397 const struct isp2x_rawaebig_meas_cfg *arg, u32 id)
1398 {
1399 isp_rawaebig_config(params_vdev, arg, 2, id);
1400 }
1401
1402 static void
isp_rawae2_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)1403 isp_rawae2_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
1404 {
1405 isp_rawaebig_enable(params_vdev, en, 2, id);
1406 }
1407
1408 static void
isp_rawae3_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawaebig_meas_cfg * arg,u32 id)1409 isp_rawae3_config(struct rkisp_isp_params_vdev *params_vdev,
1410 const struct isp2x_rawaebig_meas_cfg *arg, u32 id)
1411 {
1412 isp_rawaebig_config(params_vdev, arg, 0, id);
1413 }
1414
1415 static void
isp_rawae3_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)1416 isp_rawae3_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
1417 {
1418 isp_rawaebig_enable(params_vdev, en, 0, id);
1419 }
1420
1421 static void
isp_rawawb_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp3x_rawawb_meas_cfg * arg,u32 id)1422 isp_rawawb_config(struct rkisp_isp_params_vdev *params_vdev,
1423 const struct isp3x_rawawb_meas_cfg *arg, u32 id)
1424 {
1425 u32 i, value;
1426
1427 isp3_param_write(params_vdev,
1428 (arg->sw_rawawb_blk_measure_enable & 0x1) |
1429 (arg->sw_rawawb_blk_measure_mode & 0x1) << 1 |
1430 (arg->sw_rawawb_blk_measure_xytype & 0x1) << 2 |
1431 (arg->sw_rawawb_blk_rtdw_measure_en & 0x1) << 3 |
1432 (arg->sw_rawawb_blk_measure_illu_idx & 0x7) << 4 |
1433 (arg->sw_rawawb_blk_with_luma_wei_en & 0x1) << 8,
1434 ISP3X_RAWAWB_BLK_CTRL, id);
1435
1436 isp3_param_write(params_vdev,
1437 ISP_PACK_2SHORT(arg->sw_rawawb_h_offs, arg->sw_rawawb_v_offs),
1438 ISP3X_RAWAWB_WIN_OFFS, id);
1439
1440 isp3_param_write(params_vdev,
1441 ISP_PACK_2SHORT(arg->sw_rawawb_h_size, arg->sw_rawawb_v_size),
1442 ISP3X_RAWAWB_WIN_SIZE, id);
1443
1444 isp3_param_write(params_vdev,
1445 ISP_PACK_2SHORT(arg->sw_rawawb_r_max, arg->sw_rawawb_g_max),
1446 ISP3X_RAWAWB_LIMIT_RG_MAX, id);
1447
1448 isp3_param_write(params_vdev,
1449 ISP_PACK_2SHORT(arg->sw_rawawb_b_max, arg->sw_rawawb_y_max),
1450 ISP3X_RAWAWB_LIMIT_BY_MAX, id);
1451
1452 isp3_param_write(params_vdev,
1453 ISP_PACK_2SHORT(arg->sw_rawawb_r_min, arg->sw_rawawb_g_min),
1454 ISP3X_RAWAWB_LIMIT_RG_MIN, id);
1455
1456 isp3_param_write(params_vdev,
1457 ISP_PACK_2SHORT(arg->sw_rawawb_b_min, arg->sw_rawawb_y_min),
1458 ISP3X_RAWAWB_LIMIT_BY_MIN, id);
1459
1460 isp3_param_write(params_vdev,
1461 (arg->sw_rawawb_wp_luma_wei_en0 & 0x1) |
1462 (arg->sw_rawawb_wp_luma_wei_en1 & 0x1) << 1 |
1463 (arg->sw_rawawb_wp_blk_wei_en0 & 0x1) << 2 |
1464 (arg->sw_rawawb_wp_blk_wei_en1 & 0x1) << 3 |
1465 (arg->sw_rawawb_wp_hist_xytype & 0x1) << 4,
1466 ISP3X_RAWAWB_WEIGHT_CURVE_CTRL, id);
1467
1468 isp3_param_write(params_vdev,
1469 ISP_PACK_4BYTE(arg->sw_rawawb_wp_luma_weicurve_y0,
1470 arg->sw_rawawb_wp_luma_weicurve_y1,
1471 arg->sw_rawawb_wp_luma_weicurve_y2,
1472 arg->sw_rawawb_wp_luma_weicurve_y3),
1473 ISP3X_RAWAWB_YWEIGHT_CURVE_XCOOR03, id);
1474
1475 isp3_param_write(params_vdev,
1476 ISP_PACK_4BYTE(arg->sw_rawawb_wp_luma_weicurve_y4,
1477 arg->sw_rawawb_wp_luma_weicurve_y5,
1478 arg->sw_rawawb_wp_luma_weicurve_y6,
1479 arg->sw_rawawb_wp_luma_weicurve_y7),
1480 ISP3X_RAWAWB_YWEIGHT_CURVE_XCOOR47, id);
1481
1482 isp3_param_write(params_vdev,
1483 arg->sw_rawawb_wp_luma_weicurve_y8,
1484 ISP3X_RAWAWB_YWEIGHT_CURVE_XCOOR8, id);
1485
1486 isp3_param_write(params_vdev,
1487 ISP_PACK_4BYTE(arg->sw_rawawb_wp_luma_weicurve_w0,
1488 arg->sw_rawawb_wp_luma_weicurve_w1,
1489 arg->sw_rawawb_wp_luma_weicurve_w2,
1490 arg->sw_rawawb_wp_luma_weicurve_w3),
1491 ISP3X_RAWAWB_YWEIGHT_CURVE_YCOOR03, id);
1492
1493 isp3_param_write(params_vdev,
1494 ISP_PACK_4BYTE(arg->sw_rawawb_wp_luma_weicurve_w4,
1495 arg->sw_rawawb_wp_luma_weicurve_w5,
1496 arg->sw_rawawb_wp_luma_weicurve_w6,
1497 arg->sw_rawawb_wp_luma_weicurve_w7),
1498 ISP3X_RAWAWB_YWEIGHT_CURVE_YCOOR47, id);
1499
1500 isp3_param_write(params_vdev,
1501 ISP_PACK_2SHORT(arg->sw_rawawb_wp_luma_weicurve_w8,
1502 arg->sw_rawawb_pre_wbgain_inv_r),
1503 ISP3X_RAWAWB_YWEIGHT_CURVE_YCOOR8, id);
1504
1505 isp3_param_write(params_vdev,
1506 ISP_PACK_2SHORT(arg->sw_rawawb_pre_wbgain_inv_g,
1507 arg->sw_rawawb_pre_wbgain_inv_b),
1508 ISP3X_RAWAWB_PRE_WBGAIN_INV, id);
1509
1510 isp3_param_write(params_vdev,
1511 ISP_PACK_2SHORT(arg->sw_rawawb_vertex0_u_0,
1512 arg->sw_rawawb_vertex0_v_0),
1513 ISP3X_RAWAWB_UV_DETC_VERTEX0_0, id);
1514
1515 isp3_param_write(params_vdev,
1516 ISP_PACK_2SHORT(arg->sw_rawawb_vertex1_u_0,
1517 arg->sw_rawawb_vertex1_v_0),
1518 ISP3X_RAWAWB_UV_DETC_VERTEX1_0, id);
1519
1520 isp3_param_write(params_vdev,
1521 ISP_PACK_2SHORT(arg->sw_rawawb_vertex2_u_0,
1522 arg->sw_rawawb_vertex2_v_0),
1523 ISP3X_RAWAWB_UV_DETC_VERTEX2_0, id);
1524
1525 isp3_param_write(params_vdev,
1526 ISP_PACK_2SHORT(arg->sw_rawawb_vertex3_u_0,
1527 arg->sw_rawawb_vertex3_v_0),
1528 ISP3X_RAWAWB_UV_DETC_VERTEX3_0, id);
1529
1530 isp3_param_write(params_vdev,
1531 arg->sw_rawawb_islope01_0,
1532 ISP3X_RAWAWB_UV_DETC_ISLOPE01_0, id);
1533
1534 isp3_param_write(params_vdev,
1535 arg->sw_rawawb_islope12_0,
1536 ISP3X_RAWAWB_UV_DETC_ISLOPE12_0, id);
1537
1538 isp3_param_write(params_vdev,
1539 arg->sw_rawawb_islope23_0,
1540 ISP3X_RAWAWB_UV_DETC_ISLOPE23_0, id);
1541
1542 isp3_param_write(params_vdev,
1543 arg->sw_rawawb_islope30_0,
1544 ISP3X_RAWAWB_UV_DETC_ISLOPE30_0, id);
1545
1546 isp3_param_write(params_vdev,
1547 ISP_PACK_2SHORT(arg->sw_rawawb_vertex0_u_1,
1548 arg->sw_rawawb_vertex0_v_1),
1549 ISP3X_RAWAWB_UV_DETC_VERTEX0_1, id);
1550
1551 isp3_param_write(params_vdev,
1552 ISP_PACK_2SHORT(arg->sw_rawawb_vertex1_u_1,
1553 arg->sw_rawawb_vertex1_v_1),
1554 ISP3X_RAWAWB_UV_DETC_VERTEX1_1, id);
1555
1556 isp3_param_write(params_vdev,
1557 ISP_PACK_2SHORT(arg->sw_rawawb_vertex2_u_1,
1558 arg->sw_rawawb_vertex2_v_1),
1559 ISP3X_RAWAWB_UV_DETC_VERTEX2_1, id);
1560
1561 isp3_param_write(params_vdev,
1562 ISP_PACK_2SHORT(arg->sw_rawawb_vertex3_u_1,
1563 arg->sw_rawawb_vertex3_v_1),
1564 ISP3X_RAWAWB_UV_DETC_VERTEX3_1, id);
1565
1566 isp3_param_write(params_vdev,
1567 arg->sw_rawawb_islope01_1,
1568 ISP3X_RAWAWB_UV_DETC_ISLOPE01_1, id);
1569
1570 isp3_param_write(params_vdev,
1571 arg->sw_rawawb_islope12_1,
1572 ISP3X_RAWAWB_UV_DETC_ISLOPE12_1, id);
1573
1574 isp3_param_write(params_vdev,
1575 arg->sw_rawawb_islope23_1,
1576 ISP3X_RAWAWB_UV_DETC_ISLOPE23_1, id);
1577
1578 isp3_param_write(params_vdev,
1579 arg->sw_rawawb_islope30_1,
1580 ISP3X_RAWAWB_UV_DETC_ISLOPE30_1, id);
1581
1582 isp3_param_write(params_vdev,
1583 ISP_PACK_2SHORT(arg->sw_rawawb_vertex0_u_2,
1584 arg->sw_rawawb_vertex0_v_2),
1585 ISP3X_RAWAWB_UV_DETC_VERTEX0_2, id);
1586
1587 isp3_param_write(params_vdev,
1588 ISP_PACK_2SHORT(arg->sw_rawawb_vertex1_u_2,
1589 arg->sw_rawawb_vertex1_v_2),
1590 ISP3X_RAWAWB_UV_DETC_VERTEX1_2, id);
1591
1592 isp3_param_write(params_vdev,
1593 ISP_PACK_2SHORT(arg->sw_rawawb_vertex2_u_2,
1594 arg->sw_rawawb_vertex2_v_2),
1595 ISP3X_RAWAWB_UV_DETC_VERTEX2_2, id);
1596
1597 isp3_param_write(params_vdev,
1598 ISP_PACK_2SHORT(arg->sw_rawawb_vertex3_u_2,
1599 arg->sw_rawawb_vertex3_v_2),
1600 ISP3X_RAWAWB_UV_DETC_VERTEX3_2, id);
1601
1602 isp3_param_write(params_vdev,
1603 arg->sw_rawawb_islope01_2,
1604 ISP3X_RAWAWB_UV_DETC_ISLOPE01_2, id);
1605
1606 isp3_param_write(params_vdev,
1607 arg->sw_rawawb_islope12_2,
1608 ISP3X_RAWAWB_UV_DETC_ISLOPE12_2, id);
1609
1610 isp3_param_write(params_vdev,
1611 arg->sw_rawawb_islope23_2,
1612 ISP3X_RAWAWB_UV_DETC_ISLOPE23_2, id);
1613
1614 isp3_param_write(params_vdev,
1615 arg->sw_rawawb_islope30_2,
1616 ISP3X_RAWAWB_UV_DETC_ISLOPE30_2, id);
1617
1618 isp3_param_write(params_vdev,
1619 ISP_PACK_2SHORT(arg->sw_rawawb_vertex0_u_3,
1620 arg->sw_rawawb_vertex0_v_3),
1621 ISP3X_RAWAWB_UV_DETC_VERTEX0_3, id);
1622
1623 isp3_param_write(params_vdev,
1624 ISP_PACK_2SHORT(arg->sw_rawawb_vertex1_u_3,
1625 arg->sw_rawawb_vertex1_v_3),
1626 ISP3X_RAWAWB_UV_DETC_VERTEX1_3, id);
1627
1628 isp3_param_write(params_vdev,
1629 ISP_PACK_2SHORT(arg->sw_rawawb_vertex2_u_3,
1630 arg->sw_rawawb_vertex2_v_3),
1631 ISP3X_RAWAWB_UV_DETC_VERTEX2_3, id);
1632
1633 isp3_param_write(params_vdev,
1634 ISP_PACK_2SHORT(arg->sw_rawawb_vertex3_u_3,
1635 arg->sw_rawawb_vertex3_v_3),
1636 ISP3X_RAWAWB_UV_DETC_VERTEX3_3, id);
1637
1638 isp3_param_write(params_vdev,
1639 arg->sw_rawawb_islope01_3,
1640 ISP3X_RAWAWB_UV_DETC_ISLOPE01_3, id);
1641
1642 isp3_param_write(params_vdev,
1643 arg->sw_rawawb_islope12_3,
1644 ISP3X_RAWAWB_UV_DETC_ISLOPE12_3, id);
1645
1646 isp3_param_write(params_vdev,
1647 arg->sw_rawawb_islope23_3,
1648 ISP3X_RAWAWB_UV_DETC_ISLOPE23_3, id);
1649
1650 isp3_param_write(params_vdev,
1651 arg->sw_rawawb_islope30_3,
1652 ISP3X_RAWAWB_UV_DETC_ISLOPE30_3, id);
1653
1654 isp3_param_write(params_vdev,
1655 ISP_PACK_2SHORT(arg->sw_rawawb_vertex0_u_4,
1656 arg->sw_rawawb_vertex0_v_4),
1657 ISP3X_RAWAWB_UV_DETC_VERTEX0_4, id);
1658
1659 isp3_param_write(params_vdev,
1660 ISP_PACK_2SHORT(arg->sw_rawawb_vertex1_u_4,
1661 arg->sw_rawawb_vertex1_v_4),
1662 ISP3X_RAWAWB_UV_DETC_VERTEX1_4, id);
1663
1664 isp3_param_write(params_vdev,
1665 ISP_PACK_2SHORT(arg->sw_rawawb_vertex2_u_4,
1666 arg->sw_rawawb_vertex2_v_4),
1667 ISP3X_RAWAWB_UV_DETC_VERTEX2_4, id);
1668
1669 isp3_param_write(params_vdev,
1670 ISP_PACK_2SHORT(arg->sw_rawawb_vertex3_u_4,
1671 arg->sw_rawawb_vertex3_v_4),
1672 ISP3X_RAWAWB_UV_DETC_VERTEX3_4, id);
1673
1674 isp3_param_write(params_vdev,
1675 arg->sw_rawawb_islope01_4,
1676 ISP3X_RAWAWB_UV_DETC_ISLOPE01_4, id);
1677
1678 isp3_param_write(params_vdev,
1679 arg->sw_rawawb_islope12_4,
1680 ISP3X_RAWAWB_UV_DETC_ISLOPE12_4, id);
1681
1682 isp3_param_write(params_vdev,
1683 arg->sw_rawawb_islope23_4,
1684 ISP3X_RAWAWB_UV_DETC_ISLOPE23_4, id);
1685
1686 isp3_param_write(params_vdev,
1687 arg->sw_rawawb_islope30_4,
1688 ISP3X_RAWAWB_UV_DETC_ISLOPE30_4, id);
1689
1690 isp3_param_write(params_vdev,
1691 ISP_PACK_2SHORT(arg->sw_rawawb_vertex0_u_5,
1692 arg->sw_rawawb_vertex0_v_5),
1693 ISP3X_RAWAWB_UV_DETC_VERTEX0_5, id);
1694
1695 isp3_param_write(params_vdev,
1696 ISP_PACK_2SHORT(arg->sw_rawawb_vertex1_u_5,
1697 arg->sw_rawawb_vertex1_v_5),
1698 ISP3X_RAWAWB_UV_DETC_VERTEX1_5, id);
1699
1700 isp3_param_write(params_vdev,
1701 ISP_PACK_2SHORT(arg->sw_rawawb_vertex2_u_5,
1702 arg->sw_rawawb_vertex2_v_5),
1703 ISP3X_RAWAWB_UV_DETC_VERTEX2_5, id);
1704
1705 isp3_param_write(params_vdev,
1706 ISP_PACK_2SHORT(arg->sw_rawawb_vertex3_u_5,
1707 arg->sw_rawawb_vertex3_v_5),
1708 ISP3X_RAWAWB_UV_DETC_VERTEX3_5, id);
1709
1710 isp3_param_write(params_vdev,
1711 arg->sw_rawawb_islope01_5,
1712 ISP3X_RAWAWB_UV_DETC_ISLOPE01_5, id);
1713
1714 isp3_param_write(params_vdev,
1715 arg->sw_rawawb_islope12_5,
1716 ISP3X_RAWAWB_UV_DETC_ISLOPE10_5, id);
1717
1718 isp3_param_write(params_vdev,
1719 arg->sw_rawawb_islope23_5,
1720 ISP3X_RAWAWB_UV_DETC_ISLOPE23_5, id);
1721
1722 isp3_param_write(params_vdev,
1723 arg->sw_rawawb_islope30_5,
1724 ISP3X_RAWAWB_UV_DETC_ISLOPE30_5, id);
1725
1726 isp3_param_write(params_vdev,
1727 ISP_PACK_2SHORT(arg->sw_rawawb_vertex0_u_6,
1728 arg->sw_rawawb_vertex0_v_6),
1729 ISP3X_RAWAWB_UV_DETC_VERTEX0_6, id);
1730
1731 isp3_param_write(params_vdev,
1732 ISP_PACK_2SHORT(arg->sw_rawawb_vertex1_u_6,
1733 arg->sw_rawawb_vertex1_v_6),
1734 ISP3X_RAWAWB_UV_DETC_VERTEX1_6, id);
1735
1736 isp3_param_write(params_vdev,
1737 ISP_PACK_2SHORT(arg->sw_rawawb_vertex2_u_6,
1738 arg->sw_rawawb_vertex2_v_6),
1739 ISP3X_RAWAWB_UV_DETC_VERTEX2_6, id);
1740
1741 isp3_param_write(params_vdev,
1742 ISP_PACK_2SHORT(arg->sw_rawawb_vertex3_u_6,
1743 arg->sw_rawawb_vertex3_v_6),
1744 ISP3X_RAWAWB_UV_DETC_VERTEX3_6, id);
1745
1746 isp3_param_write(params_vdev,
1747 arg->sw_rawawb_islope01_6,
1748 ISP3X_RAWAWB_UV_DETC_ISLOPE01_6, id);
1749
1750 isp3_param_write(params_vdev,
1751 arg->sw_rawawb_islope12_6,
1752 ISP3X_RAWAWB_UV_DETC_ISLOPE10_6, id);
1753
1754 isp3_param_write(params_vdev,
1755 arg->sw_rawawb_islope23_6,
1756 ISP3X_RAWAWB_UV_DETC_ISLOPE23_6, id);
1757
1758 isp3_param_write(params_vdev,
1759 arg->sw_rawawb_islope30_6,
1760 ISP3X_RAWAWB_UV_DETC_ISLOPE30_6, id);
1761
1762 isp3_param_write(params_vdev,
1763 ISP_PACK_2SHORT(arg->sw_rawawb_rgb2ryuvmat0_y,
1764 arg->sw_rawawb_rgb2ryuvmat1_y),
1765 ISP3X_RAWAWB_YUV_RGB2ROTY_0, id);
1766
1767 isp3_param_write(params_vdev,
1768 ISP_PACK_2SHORT(arg->sw_rawawb_rgb2ryuvmat2_y,
1769 arg->sw_rawawb_rgb2ryuvofs_y),
1770 ISP3X_RAWAWB_YUV_RGB2ROTY_1, id);
1771
1772 isp3_param_write(params_vdev,
1773 ISP_PACK_2SHORT(arg->sw_rawawb_rgb2ryuvmat0_u,
1774 arg->sw_rawawb_rgb2ryuvmat1_u),
1775 ISP3X_RAWAWB_YUV_RGB2ROTU_0, id);
1776
1777
1778 isp3_param_write(params_vdev,
1779 ISP_PACK_2SHORT(arg->sw_rawawb_rgb2ryuvmat2_u,
1780 arg->sw_rawawb_rgb2ryuvofs_u),
1781 ISP3X_RAWAWB_YUV_RGB2ROTU_1, id);
1782
1783 isp3_param_write(params_vdev,
1784 ISP_PACK_2SHORT(arg->sw_rawawb_rgb2ryuvmat0_v,
1785 arg->sw_rawawb_rgb2ryuvmat1_v),
1786 ISP3X_RAWAWB_YUV_RGB2ROTV_0, id);
1787
1788 isp3_param_write(params_vdev,
1789 ISP_PACK_2SHORT(arg->sw_rawawb_rgb2ryuvmat2_v,
1790 arg->sw_rawawb_rgb2ryuvofs_v),
1791 ISP3X_RAWAWB_YUV_RGB2ROTV_1, id);
1792
1793 isp3_param_write(params_vdev,
1794 ISP_PACK_2SHORT(arg->sw_rawawb_coor_x1_ls0_y,
1795 arg->sw_rawawb_vec_x21_ls0_y),
1796 ISP3X_RAWAWB_YUV_X_COOR_Y_0, id);
1797
1798 isp3_param_write(params_vdev,
1799 ISP_PACK_2SHORT(arg->sw_rawawb_coor_x1_ls0_u,
1800 arg->sw_rawawb_vec_x21_ls0_u),
1801 ISP3X_RAWAWB_YUV_X_COOR_U_0, id);
1802
1803 isp3_param_write(params_vdev,
1804 ISP_PACK_2SHORT(arg->sw_rawawb_coor_x1_ls0_v,
1805 arg->sw_rawawb_vec_x21_ls0_v),
1806 ISP3X_RAWAWB_YUV_X_COOR_V_0, id);
1807
1808 isp3_param_write(params_vdev,
1809 ISP_PACK_4BYTE(arg->sw_rawawb_dis_x1x2_ls0,
1810 0,
1811 arg->sw_rawawb_rotu0_ls0,
1812 arg->sw_rawawb_rotu1_ls0),
1813 ISP3X_RAWAWB_YUV_X1X2_DIS_0, id);
1814
1815 isp3_param_write(params_vdev,
1816 ISP_PACK_4BYTE(arg->sw_rawawb_rotu2_ls0,
1817 arg->sw_rawawb_rotu3_ls0,
1818 arg->sw_rawawb_rotu4_ls0,
1819 arg->sw_rawawb_rotu5_ls0),
1820 ISP3X_RAWAWB_YUV_INTERP_CURVE_UCOOR_0, id);
1821
1822 isp3_param_write(params_vdev,
1823 ISP_PACK_2SHORT(arg->sw_rawawb_th0_ls0,
1824 arg->sw_rawawb_th1_ls0),
1825 ISP3X_RAWAWB_YUV_INTERP_CURVE_TH0_0, id);
1826
1827 isp3_param_write(params_vdev,
1828 ISP_PACK_2SHORT(arg->sw_rawawb_th2_ls0,
1829 arg->sw_rawawb_th3_ls0),
1830 ISP3X_RAWAWB_YUV_INTERP_CURVE_TH1_0, id);
1831
1832 isp3_param_write(params_vdev,
1833 ISP_PACK_2SHORT(arg->sw_rawawb_th4_ls0,
1834 arg->sw_rawawb_th5_ls0),
1835 ISP3X_RAWAWB_YUV_INTERP_CURVE_TH2_0, id);
1836
1837 isp3_param_write(params_vdev,
1838 ISP_PACK_2SHORT(arg->sw_rawawb_coor_x1_ls1_y,
1839 arg->sw_rawawb_vec_x21_ls1_y),
1840 ISP3X_RAWAWB_YUV_X_COOR_Y_1, id);
1841
1842 isp3_param_write(params_vdev,
1843 ISP_PACK_2SHORT(arg->sw_rawawb_coor_x1_ls1_u,
1844 arg->sw_rawawb_vec_x21_ls1_u),
1845 ISP3X_RAWAWB_YUV_X_COOR_U_1, id);
1846
1847 isp3_param_write(params_vdev,
1848 ISP_PACK_2SHORT(arg->sw_rawawb_coor_x1_ls1_v,
1849 arg->sw_rawawb_vec_x21_ls1_v),
1850 ISP3X_RAWAWB_YUV_X_COOR_V_1, id);
1851
1852 isp3_param_write(params_vdev,
1853 ISP_PACK_4BYTE(arg->sw_rawawb_dis_x1x2_ls1,
1854 0,
1855 arg->sw_rawawb_rotu0_ls1,
1856 arg->sw_rawawb_rotu1_ls1),
1857 ISP3X_RAWAWB_YUV_X1X2_DIS_1, id);
1858
1859 isp3_param_write(params_vdev,
1860 ISP_PACK_4BYTE(arg->sw_rawawb_rotu2_ls1,
1861 arg->sw_rawawb_rotu3_ls1,
1862 arg->sw_rawawb_rotu4_ls1,
1863 arg->sw_rawawb_rotu5_ls1),
1864 ISP3X_RAWAWB_YUV_INTERP_CURVE_UCOOR_1, id);
1865
1866 isp3_param_write(params_vdev,
1867 ISP_PACK_2SHORT(arg->sw_rawawb_th0_ls1,
1868 arg->sw_rawawb_th1_ls1),
1869 ISP3X_RAWAWB_YUV_INTERP_CURVE_TH0_1, id);
1870
1871 isp3_param_write(params_vdev,
1872 ISP_PACK_2SHORT(arg->sw_rawawb_th2_ls1,
1873 arg->sw_rawawb_th3_ls1),
1874 ISP3X_RAWAWB_YUV_INTERP_CURVE_TH1_1, id);
1875
1876 isp3_param_write(params_vdev,
1877 ISP_PACK_2SHORT(arg->sw_rawawb_th4_ls1,
1878 arg->sw_rawawb_th5_ls1),
1879 ISP3X_RAWAWB_YUV_INTERP_CURVE_TH2_1, id);
1880
1881 isp3_param_write(params_vdev,
1882 ISP_PACK_2SHORT(arg->sw_rawawb_coor_x1_ls2_y,
1883 arg->sw_rawawb_vec_x21_ls2_y),
1884 ISP3X_RAWAWB_YUV_X_COOR_Y_2, id);
1885
1886 isp3_param_write(params_vdev,
1887 ISP_PACK_2SHORT(arg->sw_rawawb_coor_x1_ls2_u,
1888 arg->sw_rawawb_vec_x21_ls2_u),
1889 ISP3X_RAWAWB_YUV_X_COOR_U_2, id);
1890
1891 isp3_param_write(params_vdev,
1892 ISP_PACK_2SHORT(arg->sw_rawawb_coor_x1_ls2_v,
1893 arg->sw_rawawb_vec_x21_ls2_v),
1894 ISP3X_RAWAWB_YUV_X_COOR_V_2, id);
1895
1896 isp3_param_write(params_vdev,
1897 ISP_PACK_4BYTE(arg->sw_rawawb_dis_x1x2_ls2,
1898 0,
1899 arg->sw_rawawb_rotu0_ls2,
1900 arg->sw_rawawb_rotu1_ls2),
1901 ISP3X_RAWAWB_YUV_X1X2_DIS_2, id);
1902
1903 isp3_param_write(params_vdev,
1904 ISP_PACK_4BYTE(arg->sw_rawawb_rotu2_ls2,
1905 arg->sw_rawawb_rotu3_ls2,
1906 arg->sw_rawawb_rotu4_ls2,
1907 arg->sw_rawawb_rotu5_ls2),
1908 ISP3X_RAWAWB_YUV_INTERP_CURVE_UCOOR_2, id);
1909
1910 isp3_param_write(params_vdev,
1911 ISP_PACK_2SHORT(arg->sw_rawawb_th0_ls2,
1912 arg->sw_rawawb_th1_ls2),
1913 ISP3X_RAWAWB_YUV_INTERP_CURVE_TH0_2, id);
1914
1915 isp3_param_write(params_vdev,
1916 ISP_PACK_2SHORT(arg->sw_rawawb_th2_ls2,
1917 arg->sw_rawawb_th3_ls2),
1918 ISP3X_RAWAWB_YUV_INTERP_CURVE_TH1_2, id);
1919
1920 isp3_param_write(params_vdev,
1921 ISP_PACK_2SHORT(arg->sw_rawawb_th4_ls2,
1922 arg->sw_rawawb_th5_ls2),
1923 ISP3X_RAWAWB_YUV_INTERP_CURVE_TH2_2, id);
1924
1925 isp3_param_write(params_vdev,
1926 ISP_PACK_2SHORT(arg->sw_rawawb_coor_x1_ls3_y,
1927 arg->sw_rawawb_vec_x21_ls3_y),
1928 ISP3X_RAWAWB_YUV_X_COOR_Y_3, id);
1929
1930 isp3_param_write(params_vdev,
1931 ISP_PACK_2SHORT(arg->sw_rawawb_coor_x1_ls3_u,
1932 arg->sw_rawawb_vec_x21_ls3_u),
1933 ISP3X_RAWAWB_YUV_X_COOR_U_3, id);
1934
1935 isp3_param_write(params_vdev,
1936 ISP_PACK_2SHORT(arg->sw_rawawb_coor_x1_ls3_v,
1937 arg->sw_rawawb_vec_x21_ls3_v),
1938 ISP3X_RAWAWB_YUV_X_COOR_V_3, id);
1939
1940 isp3_param_write(params_vdev,
1941 ISP_PACK_4BYTE(arg->sw_rawawb_dis_x1x2_ls3,
1942 0,
1943 arg->sw_rawawb_rotu0_ls3,
1944 arg->sw_rawawb_rotu1_ls3),
1945 ISP3X_RAWAWB_YUV_X1X2_DIS_3, id);
1946
1947 isp3_param_write(params_vdev,
1948 ISP_PACK_4BYTE(arg->sw_rawawb_rotu2_ls3,
1949 arg->sw_rawawb_rotu3_ls3,
1950 arg->sw_rawawb_rotu4_ls3,
1951 arg->sw_rawawb_rotu5_ls3),
1952 ISP3X_RAWAWB_YUV_INTERP_CURVE_UCOOR_3, id);
1953
1954 isp3_param_write(params_vdev,
1955 ISP_PACK_2SHORT(arg->sw_rawawb_th0_ls3,
1956 arg->sw_rawawb_th1_ls3),
1957 ISP3X_RAWAWB_YUV_INTERP_CURVE_TH0_3, id);
1958
1959 isp3_param_write(params_vdev,
1960 ISP_PACK_2SHORT(arg->sw_rawawb_th2_ls3,
1961 arg->sw_rawawb_th3_ls3),
1962 ISP3X_RAWAWB_YUV_INTERP_CURVE_TH1_3, id);
1963
1964 isp3_param_write(params_vdev,
1965 ISP_PACK_2SHORT(arg->sw_rawawb_th4_ls3,
1966 arg->sw_rawawb_th5_ls3),
1967 ISP3X_RAWAWB_YUV_INTERP_CURVE_TH2_3, id);
1968
1969 isp3_param_write(params_vdev,
1970 ISP_PACK_2SHORT(arg->sw_rawawb_wt0,
1971 arg->sw_rawawb_wt1),
1972 ISP3X_RAWAWB_RGB2XY_WT01, id);
1973
1974 isp3_param_write(params_vdev,
1975 arg->sw_rawawb_wt2,
1976 ISP3X_RAWAWB_RGB2XY_WT2, id);
1977
1978 isp3_param_write(params_vdev,
1979 ISP_PACK_2SHORT(arg->sw_rawawb_mat0_x,
1980 arg->sw_rawawb_mat0_y),
1981 ISP3X_RAWAWB_RGB2XY_MAT0_XY, id);
1982
1983 isp3_param_write(params_vdev,
1984 ISP_PACK_2SHORT(arg->sw_rawawb_mat1_x,
1985 arg->sw_rawawb_mat1_y),
1986 ISP3X_RAWAWB_RGB2XY_MAT1_XY, id);
1987
1988 isp3_param_write(params_vdev,
1989 ISP_PACK_2SHORT(arg->sw_rawawb_mat2_x,
1990 arg->sw_rawawb_mat2_y),
1991 ISP3X_RAWAWB_RGB2XY_MAT2_XY, id);
1992
1993 isp3_param_write(params_vdev,
1994 ISP_PACK_2SHORT(arg->sw_rawawb_nor_x0_0,
1995 arg->sw_rawawb_nor_x1_0),
1996 ISP3X_RAWAWB_XY_DETC_NOR_X_0, id);
1997
1998 isp3_param_write(params_vdev,
1999 ISP_PACK_2SHORT(arg->sw_rawawb_nor_y0_0,
2000 arg->sw_rawawb_nor_y1_0),
2001 ISP3X_RAWAWB_XY_DETC_NOR_Y_0, id);
2002
2003 isp3_param_write(params_vdev,
2004 ISP_PACK_2SHORT(arg->sw_rawawb_big_x0_0,
2005 arg->sw_rawawb_big_x1_0),
2006 ISP3X_RAWAWB_XY_DETC_BIG_X_0, id);
2007
2008 isp3_param_write(params_vdev,
2009 ISP_PACK_2SHORT(arg->sw_rawawb_big_y0_0,
2010 arg->sw_rawawb_big_y1_0),
2011 ISP3X_RAWAWB_XY_DETC_BIG_Y_0, id);
2012
2013 isp3_param_write(params_vdev,
2014 ISP_PACK_2SHORT(arg->sw_rawawb_nor_x0_1,
2015 arg->sw_rawawb_nor_x1_1),
2016 ISP3X_RAWAWB_XY_DETC_NOR_X_1, id);
2017
2018 isp3_param_write(params_vdev,
2019 ISP_PACK_2SHORT(arg->sw_rawawb_nor_y0_1,
2020 arg->sw_rawawb_nor_y1_1),
2021 ISP3X_RAWAWB_XY_DETC_NOR_Y_1, id);
2022
2023 isp3_param_write(params_vdev,
2024 ISP_PACK_2SHORT(arg->sw_rawawb_big_x0_1,
2025 arg->sw_rawawb_big_x1_1),
2026 ISP3X_RAWAWB_XY_DETC_BIG_X_1, id);
2027
2028 isp3_param_write(params_vdev,
2029 ISP_PACK_2SHORT(arg->sw_rawawb_big_y0_1,
2030 arg->sw_rawawb_big_y1_1),
2031 ISP3X_RAWAWB_XY_DETC_BIG_Y_1, id);
2032
2033 isp3_param_write(params_vdev,
2034 ISP_PACK_2SHORT(arg->sw_rawawb_nor_x0_2,
2035 arg->sw_rawawb_nor_x1_2),
2036 ISP3X_RAWAWB_XY_DETC_NOR_X_2, id);
2037
2038 isp3_param_write(params_vdev,
2039 ISP_PACK_2SHORT(arg->sw_rawawb_nor_y0_2,
2040 arg->sw_rawawb_nor_y1_2),
2041 ISP3X_RAWAWB_XY_DETC_NOR_Y_2, id);
2042
2043 isp3_param_write(params_vdev,
2044 ISP_PACK_2SHORT(arg->sw_rawawb_big_x0_2,
2045 arg->sw_rawawb_big_x1_2),
2046 ISP3X_RAWAWB_XY_DETC_BIG_X_2, id);
2047
2048 isp3_param_write(params_vdev,
2049 ISP_PACK_2SHORT(arg->sw_rawawb_big_y0_2,
2050 arg->sw_rawawb_big_y1_2),
2051 ISP3X_RAWAWB_XY_DETC_BIG_Y_2, id);
2052
2053 isp3_param_write(params_vdev,
2054 ISP_PACK_2SHORT(arg->sw_rawawb_nor_x0_3,
2055 arg->sw_rawawb_nor_x1_3),
2056 ISP3X_RAWAWB_XY_DETC_NOR_X_3, id);
2057
2058 isp3_param_write(params_vdev,
2059 ISP_PACK_2SHORT(arg->sw_rawawb_nor_y0_3,
2060 arg->sw_rawawb_nor_y1_3),
2061 ISP3X_RAWAWB_XY_DETC_NOR_Y_3, id);
2062
2063 isp3_param_write(params_vdev,
2064 ISP_PACK_2SHORT(arg->sw_rawawb_big_x0_3,
2065 arg->sw_rawawb_big_x1_3),
2066 ISP3X_RAWAWB_XY_DETC_BIG_X_3, id);
2067
2068 isp3_param_write(params_vdev,
2069 ISP_PACK_2SHORT(arg->sw_rawawb_big_y0_3,
2070 arg->sw_rawawb_big_y1_3),
2071 ISP3X_RAWAWB_XY_DETC_BIG_Y_3, id);
2072
2073 isp3_param_write(params_vdev,
2074 ISP_PACK_2SHORT(arg->sw_rawawb_nor_x0_4,
2075 arg->sw_rawawb_nor_x1_4),
2076 ISP3X_RAWAWB_XY_DETC_NOR_X_4, id);
2077
2078 isp3_param_write(params_vdev,
2079 ISP_PACK_2SHORT(arg->sw_rawawb_nor_y0_4,
2080 arg->sw_rawawb_nor_y1_4),
2081 ISP3X_RAWAWB_XY_DETC_NOR_Y_4, id);
2082
2083 isp3_param_write(params_vdev,
2084 ISP_PACK_2SHORT(arg->sw_rawawb_big_x0_4,
2085 arg->sw_rawawb_big_x1_4),
2086 ISP3X_RAWAWB_XY_DETC_BIG_X_4, id);
2087
2088 isp3_param_write(params_vdev,
2089 ISP_PACK_2SHORT(arg->sw_rawawb_big_y0_4,
2090 arg->sw_rawawb_big_y1_4),
2091 ISP3X_RAWAWB_XY_DETC_BIG_Y_4, id);
2092
2093 isp3_param_write(params_vdev,
2094 ISP_PACK_2SHORT(arg->sw_rawawb_nor_x0_5,
2095 arg->sw_rawawb_nor_x1_5),
2096 ISP3X_RAWAWB_XY_DETC_NOR_X_5, id);
2097
2098 isp3_param_write(params_vdev,
2099 ISP_PACK_2SHORT(arg->sw_rawawb_nor_y0_5,
2100 arg->sw_rawawb_nor_y1_5),
2101 ISP3X_RAWAWB_XY_DETC_NOR_Y_5, id);
2102
2103 isp3_param_write(params_vdev,
2104 ISP_PACK_2SHORT(arg->sw_rawawb_big_x0_5,
2105 arg->sw_rawawb_big_x1_5),
2106 ISP3X_RAWAWB_XY_DETC_BIG_X_5, id);
2107
2108 isp3_param_write(params_vdev,
2109 ISP_PACK_2SHORT(arg->sw_rawawb_big_y0_5,
2110 arg->sw_rawawb_big_y1_5),
2111 ISP3X_RAWAWB_XY_DETC_BIG_Y_5, id);
2112
2113 isp3_param_write(params_vdev,
2114 ISP_PACK_2SHORT(arg->sw_rawawb_nor_x0_6,
2115 arg->sw_rawawb_nor_x1_6),
2116 ISP3X_RAWAWB_XY_DETC_NOR_X_6, id);
2117
2118 isp3_param_write(params_vdev,
2119 ISP_PACK_2SHORT(arg->sw_rawawb_nor_y0_6,
2120 arg->sw_rawawb_nor_y1_6),
2121 ISP3X_RAWAWB_XY_DETC_NOR_Y_6, id);
2122
2123 isp3_param_write(params_vdev,
2124 ISP_PACK_2SHORT(arg->sw_rawawb_big_x0_6,
2125 arg->sw_rawawb_big_x1_6),
2126 ISP3X_RAWAWB_XY_DETC_BIG_X_6, id);
2127
2128 isp3_param_write(params_vdev,
2129 ISP_PACK_2SHORT(arg->sw_rawawb_big_y0_6,
2130 arg->sw_rawawb_big_y1_6),
2131 ISP3X_RAWAWB_XY_DETC_BIG_Y_6, id);
2132
2133 isp3_param_write(params_vdev,
2134 (arg->sw_rawawb_exc_wp_region0_excen0 & 0x1) << 0 |
2135 (arg->sw_rawawb_exc_wp_region0_excen1 & 0x1) << 1 |
2136 (arg->sw_rawawb_exc_wp_region0_measen & 0x1) << 2 |
2137 (arg->sw_rawawb_exc_wp_region0_domain & 0x1) << 3 |
2138 (arg->sw_rawawb_exc_wp_region1_excen0 & 0x1) << 4 |
2139 (arg->sw_rawawb_exc_wp_region1_excen1 & 0x1) << 5 |
2140 (arg->sw_rawawb_exc_wp_region1_measen & 0x1) << 6 |
2141 (arg->sw_rawawb_exc_wp_region1_domain & 0x1) << 7 |
2142 (arg->sw_rawawb_exc_wp_region2_excen0 & 0x1) << 8 |
2143 (arg->sw_rawawb_exc_wp_region2_excen1 & 0x1) << 9 |
2144 (arg->sw_rawawb_exc_wp_region2_measen & 0x1) << 10 |
2145 (arg->sw_rawawb_exc_wp_region2_domain & 0x1) << 11 |
2146 (arg->sw_rawawb_exc_wp_region3_excen0 & 0x1) << 12 |
2147 (arg->sw_rawawb_exc_wp_region3_excen1 & 0x1) << 13 |
2148 (arg->sw_rawawb_exc_wp_region3_measen & 0x1) << 14 |
2149 (arg->sw_rawawb_exc_wp_region3_domain & 0x1) << 15 |
2150 (arg->sw_rawawb_exc_wp_region4_excen0 & 0x1) << 16 |
2151 (arg->sw_rawawb_exc_wp_region4_excen1 & 0x1) << 17 |
2152 (arg->sw_rawawb_exc_wp_region4_domain & 0x1) << 19 |
2153 (arg->sw_rawawb_exc_wp_region5_excen0 & 0x1) << 20 |
2154 (arg->sw_rawawb_exc_wp_region5_excen1 & 0x1) << 21 |
2155 (arg->sw_rawawb_exc_wp_region5_domain & 0x1) << 23 |
2156 (arg->sw_rawawb_exc_wp_region6_excen0 & 0x1) << 24 |
2157 (arg->sw_rawawb_exc_wp_region6_excen1 & 0x1) << 25 |
2158 (arg->sw_rawawb_exc_wp_region6_domain & 0x1) << 27 |
2159 (arg->sw_rawawb_multiwindow_en & 0x1) << 31,
2160 ISP3X_RAWAWB_MULTIWINDOW_EXC_CTRL, id);
2161
2162 isp3_param_write(params_vdev,
2163 ISP_PACK_2SHORT(arg->sw_rawawb_multiwindow0_h_offs,
2164 arg->sw_rawawb_multiwindow0_v_offs),
2165 ISP3X_RAWAWB_MULTIWINDOW0_OFFS, id);
2166 isp3_param_write(params_vdev,
2167 ISP_PACK_2SHORT(arg->sw_rawawb_multiwindow0_h_size,
2168 arg->sw_rawawb_multiwindow0_v_size),
2169 ISP3X_RAWAWB_MULTIWINDOW0_SIZE, id);
2170 isp3_param_write(params_vdev,
2171 ISP_PACK_2SHORT(arg->sw_rawawb_multiwindow1_h_offs,
2172 arg->sw_rawawb_multiwindow1_v_offs),
2173 ISP3X_RAWAWB_MULTIWINDOW1_OFFS, id);
2174 isp3_param_write(params_vdev,
2175 ISP_PACK_2SHORT(arg->sw_rawawb_multiwindow1_h_size,
2176 arg->sw_rawawb_multiwindow1_v_size),
2177 ISP3X_RAWAWB_MULTIWINDOW1_SIZE, id);
2178 isp3_param_write(params_vdev,
2179 ISP_PACK_2SHORT(arg->sw_rawawb_multiwindow2_h_offs,
2180 arg->sw_rawawb_multiwindow2_v_offs),
2181 ISP3X_RAWAWB_MULTIWINDOW2_OFFS, id);
2182 isp3_param_write(params_vdev,
2183 ISP_PACK_2SHORT(arg->sw_rawawb_multiwindow2_h_size,
2184 arg->sw_rawawb_multiwindow2_v_size),
2185 ISP3X_RAWAWB_MULTIWINDOW2_SIZE, id);
2186 isp3_param_write(params_vdev,
2187 ISP_PACK_2SHORT(arg->sw_rawawb_multiwindow3_h_offs,
2188 arg->sw_rawawb_multiwindow3_v_offs),
2189 ISP3X_RAWAWB_MULTIWINDOW3_OFFS, id);
2190 isp3_param_write(params_vdev,
2191 ISP_PACK_2SHORT(arg->sw_rawawb_multiwindow3_h_size,
2192 arg->sw_rawawb_multiwindow3_v_size),
2193 ISP3X_RAWAWB_MULTIWINDOW3_SIZE, id);
2194
2195 isp3_param_write(params_vdev,
2196 ISP_PACK_2SHORT(arg->sw_rawawb_exc_wp_region0_xu0,
2197 arg->sw_rawawb_exc_wp_region0_xu1),
2198 ISP3X_RAWAWB_EXC_WP_REGION0_XU, id);
2199
2200 isp3_param_write(params_vdev,
2201 ISP_PACK_2SHORT(arg->sw_rawawb_exc_wp_region0_yv0,
2202 arg->sw_rawawb_exc_wp_region0_yv1),
2203 ISP3X_RAWAWB_EXC_WP_REGION0_YV, id);
2204
2205 isp3_param_write(params_vdev,
2206 ISP_PACK_2SHORT(arg->sw_rawawb_exc_wp_region1_xu0,
2207 arg->sw_rawawb_exc_wp_region1_xu1),
2208 ISP3X_RAWAWB_EXC_WP_REGION1_XU, id);
2209
2210 isp3_param_write(params_vdev,
2211 ISP_PACK_2SHORT(arg->sw_rawawb_exc_wp_region1_yv0,
2212 arg->sw_rawawb_exc_wp_region1_yv1),
2213 ISP3X_RAWAWB_EXC_WP_REGION1_YV, id);
2214
2215 isp3_param_write(params_vdev,
2216 ISP_PACK_2SHORT(arg->sw_rawawb_exc_wp_region2_xu0,
2217 arg->sw_rawawb_exc_wp_region2_xu1),
2218 ISP3X_RAWAWB_EXC_WP_REGION2_XU, id);
2219
2220 isp3_param_write(params_vdev,
2221 ISP_PACK_2SHORT(arg->sw_rawawb_exc_wp_region2_yv0,
2222 arg->sw_rawawb_exc_wp_region2_yv1),
2223 ISP3X_RAWAWB_EXC_WP_REGION2_YV, id);
2224
2225 isp3_param_write(params_vdev,
2226 ISP_PACK_2SHORT(arg->sw_rawawb_exc_wp_region3_xu0,
2227 arg->sw_rawawb_exc_wp_region3_xu1),
2228 ISP3X_RAWAWB_EXC_WP_REGION3_XU, id);
2229
2230 isp3_param_write(params_vdev,
2231 ISP_PACK_2SHORT(arg->sw_rawawb_exc_wp_region3_yv0,
2232 arg->sw_rawawb_exc_wp_region3_yv1),
2233 ISP3X_RAWAWB_EXC_WP_REGION3_YV, id);
2234
2235 isp3_param_write(params_vdev,
2236 ISP_PACK_2SHORT(arg->sw_rawawb_exc_wp_region4_xu0,
2237 arg->sw_rawawb_exc_wp_region4_xu1),
2238 ISP3X_RAWAWB_EXC_WP_REGION4_XU, id);
2239
2240 isp3_param_write(params_vdev,
2241 ISP_PACK_2SHORT(arg->sw_rawawb_exc_wp_region4_yv0,
2242 arg->sw_rawawb_exc_wp_region4_yv1),
2243 ISP3X_RAWAWB_EXC_WP_REGION4_YV, id);
2244
2245 isp3_param_write(params_vdev,
2246 ISP_PACK_2SHORT(arg->sw_rawawb_exc_wp_region5_xu0,
2247 arg->sw_rawawb_exc_wp_region5_xu1),
2248 ISP3X_RAWAWB_EXC_WP_REGION5_XU, id);
2249
2250 isp3_param_write(params_vdev,
2251 ISP_PACK_2SHORT(arg->sw_rawawb_exc_wp_region5_yv0,
2252 arg->sw_rawawb_exc_wp_region5_yv1),
2253 ISP3X_RAWAWB_EXC_WP_REGION5_YV, id);
2254
2255 isp3_param_write(params_vdev,
2256 ISP_PACK_2SHORT(arg->sw_rawawb_exc_wp_region6_xu0,
2257 arg->sw_rawawb_exc_wp_region6_xu1),
2258 ISP3X_RAWAWB_EXC_WP_REGION6_XU, id);
2259
2260 isp3_param_write(params_vdev,
2261 ISP_PACK_2SHORT(arg->sw_rawawb_exc_wp_region6_yv0,
2262 arg->sw_rawawb_exc_wp_region6_yv1),
2263 ISP3X_RAWAWB_EXC_WP_REGION6_YV, id);
2264
2265 for (i = 0; i < ISP3X_RAWAWB_WEIGHT_NUM / 5; i++) {
2266 isp3_param_write(params_vdev,
2267 (arg->sw_rawawb_wp_blk_wei_w[5 * i] & 0x3f) << 0 |
2268 (arg->sw_rawawb_wp_blk_wei_w[5 * i + 1] & 0x3f) << 6 |
2269 (arg->sw_rawawb_wp_blk_wei_w[5 * i + 2] & 0x3f) << 12 |
2270 (arg->sw_rawawb_wp_blk_wei_w[5 * i + 3] & 0x3f) << 18 |
2271 (arg->sw_rawawb_wp_blk_wei_w[5 * i + 4] & 0x3f) << 24,
2272 ISP3X_RAWAWB_WRAM_DATA_BASE, id);
2273 }
2274
2275 /* avoid to override the old enable value */
2276 value = isp3_param_read(params_vdev, ISP3X_RAWAWB_CTRL, id);
2277 value &= ISP3X_MODULE_EN;
2278 isp3_param_write(params_vdev,
2279 value |
2280 (arg->sw_rawawb_uv_en0 & 0x1) << 1 |
2281 (arg->sw_rawawb_xy_en0 & 0x1) << 2 |
2282 (arg->sw_rawawb_3dyuv_en0 & 0x1) << 3 |
2283 (arg->sw_rawawb_3dyuv_ls_idx0 & 0x7) << 4 |
2284 (arg->sw_rawawb_3dyuv_ls_idx1 & 0x7) << 7 |
2285 (arg->sw_rawawb_3dyuv_ls_idx2 & 0x7) << 10 |
2286 (arg->sw_rawawb_3dyuv_ls_idx3 & 0x7) << 13 |
2287 (arg->sw_rawawb_wind_size & 0x1) << 18 |
2288 (arg->sw_rawlsc_bypass_en & 0x1) << 19 |
2289 (arg->sw_rawawb_light_num & 0x7) << 20 |
2290 (arg->sw_rawawb_uv_en1 & 0x1) << 24 |
2291 (arg->sw_rawawb_xy_en1 & 0x1) << 25 |
2292 (arg->sw_rawawb_3dyuv_en1 & 0x1) << 26,
2293 ISP3X_RAWAWB_CTRL, id);
2294
2295 value = isp3_param_read(params_vdev, ISP3X_VI_ISP_PATH, id);
2296 value &= ~(ISP3X_RAWAWB_SEL(3));
2297 value |= ISP3X_RAWAWB_SEL(arg->rawawb_sel);
2298 isp3_param_write(params_vdev, value, ISP3X_VI_ISP_PATH, id);
2299 }
2300
2301 static void
isp_rawawb_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)2302 isp_rawawb_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
2303 {
2304 u32 awb_ctrl;
2305
2306 awb_ctrl = isp3_param_read(params_vdev, ISP3X_RAWAWB_CTRL, id);
2307 awb_ctrl &= ~ISP3X_REG_WR_MASK;
2308 if (en)
2309 awb_ctrl |= ISP3X_MODULE_EN;
2310 else
2311 awb_ctrl &= ~ISP3X_MODULE_EN;
2312
2313 isp3_param_write(params_vdev, awb_ctrl, ISP3X_RAWAWB_CTRL, id);
2314 }
2315
2316 static void
isp_rawhstlite_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawhistlite_cfg * arg,u32 id)2317 isp_rawhstlite_config(struct rkisp_isp_params_vdev *params_vdev,
2318 const struct isp2x_rawhistlite_cfg *arg, u32 id)
2319 {
2320 u32 i;
2321 u32 value;
2322 u32 hist_ctrl;
2323 u32 block_hsize, block_vsize;
2324
2325 /* avoid to override the old enable value */
2326 hist_ctrl = isp3_param_read(params_vdev, ISP3X_RAWHIST_LITE_CTRL, id);
2327 hist_ctrl &= ISP3X_RAWHIST_EN;
2328 hist_ctrl = hist_ctrl |
2329 ISP3X_RAWHIST_MODE(arg->mode) |
2330 ISP3X_RAWHIST_DATASEL(arg->data_sel) |
2331 ISP3X_RAWHIST_WATERLINE(arg->waterline) |
2332 ISP3X_RAWHIST_STEPSIZE(arg->stepsize);
2333 isp3_param_write(params_vdev, hist_ctrl, ISP3X_RAWHIST_LITE_CTRL, id);
2334
2335 isp3_param_write(params_vdev,
2336 ISP_PACK_2SHORT(arg->win.h_offs, arg->win.v_offs),
2337 ISP3X_RAWHIST_LITE_OFFS, id);
2338
2339 block_hsize = arg->win.h_size / ISP3X_RAWHISTLITE_ROW_NUM - 1;
2340 block_vsize = arg->win.v_size / ISP3X_RAWHISTLITE_COLUMN_NUM - 1;
2341 block_hsize &= 0xFFFE;
2342 block_vsize &= 0xFFFE;
2343 isp3_param_write(params_vdev,
2344 ISP_PACK_2SHORT(block_hsize, block_vsize),
2345 ISP3X_RAWHIST_LITE_SIZE, id);
2346
2347 isp3_param_write(params_vdev,
2348 ISP_PACK_4BYTE(arg->rcc, arg->gcc, arg->bcc, arg->off),
2349 ISP3X_RAWHIST_LITE_RAW2Y_CC, id);
2350
2351 for (i = 0; i < (ISP3X_RAWHISTLITE_WEIGHT_REG_SIZE / 4); i++) {
2352 value = ISP_PACK_4BYTE(arg->weight[4 * i + 0],
2353 arg->weight[4 * i + 1],
2354 arg->weight[4 * i + 2],
2355 arg->weight[4 * i + 3]);
2356 isp3_param_write(params_vdev, value,
2357 ISP3X_RAWHIST_LITE_WEIGHT + 4 * i, id);
2358 }
2359
2360 value = ISP_PACK_4BYTE(arg->weight[4 * i + 0], 0, 0, 0);
2361 isp3_param_write(params_vdev, value,
2362 ISP3X_RAWHIST_LITE_WEIGHT + 4 * i, id);
2363 }
2364
2365 static void
isp_rawhstlite_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)2366 isp_rawhstlite_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
2367 {
2368 u32 hist_ctrl;
2369
2370 hist_ctrl = isp3_param_read(params_vdev, ISP3X_RAWHIST_LITE_CTRL, id);
2371 hist_ctrl &= ~(ISP3X_MODULE_EN | ISP3X_REG_WR_MASK);
2372
2373 if (en)
2374 hist_ctrl |= ISP3X_MODULE_EN;
2375
2376 isp3_param_write(params_vdev, hist_ctrl, ISP3X_RAWHIST_LITE_CTRL, id);
2377 }
2378
2379 static void
isp_rawhstbig_cfg_sram(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawhistbig_cfg * arg,u32 blk_no,bool is_check,u32 id)2380 isp_rawhstbig_cfg_sram(struct rkisp_isp_params_vdev *params_vdev,
2381 const struct isp2x_rawhistbig_cfg *arg,
2382 u32 blk_no, bool is_check, u32 id)
2383 {
2384 u32 i, j, wnd_num_idx, value;
2385 u8 weight15x15[ISP3X_RAWHISTBIG_WEIGHT_REG_SIZE];
2386 const u32 hist_wnd_num[] = {5, 5, 15, 15};
2387 u32 addr;
2388
2389 switch (blk_no) {
2390 case 1:
2391 addr = ISP3X_RAWHIST_BIG2_BASE;
2392 break;
2393 case 2:
2394 addr = ISP3X_RAWHIST_BIG3_BASE;
2395 break;
2396 case 0:
2397 default:
2398 addr = ISP3X_RAWHIST_BIG1_BASE;
2399 break;
2400 }
2401
2402 value = ISP3X_RAWHIST_EN;
2403 if (is_check &&
2404 !(isp3_param_read(params_vdev, addr + ISP3X_RAWHIST_BIG_CTRL, id) & value))
2405 return;
2406
2407 wnd_num_idx = arg->wnd_num;
2408 memset(weight15x15, 0, sizeof(weight15x15));
2409 for (i = 0; i < hist_wnd_num[wnd_num_idx]; i++) {
2410 for (j = 0; j < hist_wnd_num[wnd_num_idx]; j++) {
2411 weight15x15[i * ISP3X_RAWHISTBIG_ROW_NUM + j] =
2412 arg->weight[i * hist_wnd_num[wnd_num_idx] + j];
2413 }
2414 }
2415
2416 for (i = 0; i < (ISP3X_RAWHISTBIG_WEIGHT_REG_SIZE / 5); i++) {
2417 value = (weight15x15[5 * i + 0] & 0x3f) |
2418 (weight15x15[5 * i + 1] & 0x3f) << 6 |
2419 (weight15x15[5 * i + 2] & 0x3f) << 12 |
2420 (weight15x15[5 * i + 3] & 0x3f) << 18 |
2421 (weight15x15[5 * i + 4] & 0x3f) << 24;
2422 isp3_param_write_direct(params_vdev, value,
2423 addr + ISP3X_RAWHIST_BIG_WEIGHT_BASE, id);
2424 }
2425 }
2426
2427 static void
isp_rawhstbig_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawhistbig_cfg * arg,u32 blk_no,u32 id)2428 isp_rawhstbig_config(struct rkisp_isp_params_vdev *params_vdev,
2429 const struct isp2x_rawhistbig_cfg *arg, u32 blk_no, u32 id)
2430 {
2431 struct isp3x_isp_params_cfg *params_rec = params_vdev->isp3x_params + id;
2432 struct rkisp_device *dev = params_vdev->dev;
2433 struct isp2x_rawhistbig_cfg *arg_rec;
2434 u32 hist_ctrl, block_hsize, block_vsize, wnd_num_idx;
2435 const u32 hist_wnd_num[] = {5, 5, 15, 15};
2436 u32 addr;
2437
2438 switch (blk_no) {
2439 case 1:
2440 addr = ISP3X_RAWHIST_BIG2_BASE;
2441 arg_rec = ¶ms_rec->meas.rawhist1;
2442 break;
2443 case 2:
2444 addr = ISP3X_RAWHIST_BIG3_BASE;
2445 arg_rec = ¶ms_rec->meas.rawhist2;
2446 break;
2447 case 0:
2448 default:
2449 addr = ISP3X_RAWHIST_BIG1_BASE;
2450 arg_rec = ¶ms_rec->meas.rawhist3;
2451 break;
2452 }
2453
2454 wnd_num_idx = arg->wnd_num;
2455 /* avoid to override the old enable value */
2456 hist_ctrl = isp3_param_read(params_vdev, addr + ISP3X_RAWHIST_BIG_CTRL, id);
2457 hist_ctrl &= ISP3X_RAWHIST_EN;
2458 hist_ctrl = hist_ctrl |
2459 ISP3X_RAWHIST_MODE(arg->mode) |
2460 ISP3X_RAWHIST_DATASEL(arg->data_sel) |
2461 ISP3X_RAWHIST_WATERLINE(arg->waterline) |
2462 ISP3X_RAWHIST_WND_NUM(arg->wnd_num) |
2463 ISP3X_RAWHIST_STEPSIZE(arg->stepsize);
2464 isp3_param_write(params_vdev, hist_ctrl, addr + ISP3X_RAWHIST_BIG_CTRL, id);
2465
2466 isp3_param_write(params_vdev,
2467 ISP_PACK_2SHORT(arg->win.h_offs, arg->win.v_offs),
2468 addr + ISP3X_RAWHIST_BIG_OFFS, id);
2469
2470 block_hsize = arg->win.h_size / hist_wnd_num[wnd_num_idx] - 1;
2471 block_vsize = arg->win.v_size / hist_wnd_num[wnd_num_idx] - 1;
2472 block_hsize &= 0xFFFE;
2473 block_vsize &= 0xFFFE;
2474 isp3_param_write(params_vdev,
2475 ISP_PACK_2SHORT(block_hsize, block_vsize),
2476 addr + ISP3X_RAWHIST_BIG_SIZE, id);
2477
2478 isp3_param_write(params_vdev,
2479 ISP_PACK_4BYTE(arg->rcc, arg->gcc, arg->bcc, arg->off),
2480 addr + ISP3X_RAWHIST_BIG_RAW2Y_CC, id);
2481
2482 if (dev->hw_dev->is_single)
2483 isp_rawhstbig_cfg_sram(params_vdev, arg, blk_no, false, id);
2484 else
2485 *arg_rec = *arg;
2486 }
2487
2488 static void
isp_rawhstbig_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 blk_no,u32 id)2489 isp_rawhstbig_enable(struct rkisp_isp_params_vdev *params_vdev,
2490 bool en, u32 blk_no, u32 id)
2491 {
2492 u32 hist_ctrl;
2493 u32 addr;
2494
2495 switch (blk_no) {
2496 case 1:
2497 addr = ISP3X_RAWHIST_BIG2_BASE;
2498 break;
2499 case 2:
2500 addr = ISP3X_RAWHIST_BIG3_BASE;
2501 break;
2502 case 0:
2503 default:
2504 addr = ISP3X_RAWHIST_BIG1_BASE;
2505 break;
2506 }
2507
2508 hist_ctrl = isp3_param_read(params_vdev, addr + ISP3X_RAWHIST_BIG_CTRL, id);
2509 hist_ctrl &= ~(ISP3X_RAWHIST_EN | ISP3X_REG_WR_MASK);
2510 if (en)
2511 hist_ctrl |= ISP3X_RAWHIST_EN;
2512
2513 isp3_param_write(params_vdev, hist_ctrl, addr + ISP3X_RAWHIST_BIG_CTRL, id);
2514 }
2515
2516 static void
isp_rawhst1_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawhistbig_cfg * arg,u32 id)2517 isp_rawhst1_config(struct rkisp_isp_params_vdev *params_vdev,
2518 const struct isp2x_rawhistbig_cfg *arg, u32 id)
2519 {
2520 isp_rawhstbig_config(params_vdev, arg, 1, id);
2521 }
2522
2523 static void
isp_rawhst1_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)2524 isp_rawhst1_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
2525 {
2526 isp_rawhstbig_enable(params_vdev, en, 1, id);
2527 }
2528
2529 static void
isp_rawhst2_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawhistbig_cfg * arg,u32 id)2530 isp_rawhst2_config(struct rkisp_isp_params_vdev *params_vdev,
2531 const struct isp2x_rawhistbig_cfg *arg, u32 id)
2532 {
2533 isp_rawhstbig_config(params_vdev, arg, 2, id);
2534 }
2535
2536 static void
isp_rawhst2_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)2537 isp_rawhst2_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
2538 {
2539 isp_rawhstbig_enable(params_vdev, en, 2, id);
2540 }
2541
2542 static void
isp_rawhst3_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_rawhistbig_cfg * arg,u32 id)2543 isp_rawhst3_config(struct rkisp_isp_params_vdev *params_vdev,
2544 const struct isp2x_rawhistbig_cfg *arg, u32 id)
2545 {
2546 isp_rawhstbig_config(params_vdev, arg, 0, id);
2547 }
2548
2549 static void
isp_rawhst3_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)2550 isp_rawhst3_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
2551 {
2552 isp_rawhstbig_enable(params_vdev, en, 0, id);
2553 }
2554
2555 static void
isp_hdrmge_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp3x_hdrmge_cfg * arg,enum rkisp_params_type type,u32 id)2556 isp_hdrmge_config(struct rkisp_isp_params_vdev *params_vdev,
2557 const struct isp3x_hdrmge_cfg *arg,
2558 enum rkisp_params_type type, u32 id)
2559 {
2560 u32 value;
2561 int i;
2562
2563 if (type == RKISP_PARAMS_SHD || type == RKISP_PARAMS_ALL) {
2564 value = ISP_PACK_2SHORT(arg->gain0, arg->gain0_inv);
2565 isp3_param_write(params_vdev, value, ISP3X_HDRMGE_GAIN0, id);
2566
2567 value = ISP_PACK_2SHORT(arg->gain1, arg->gain1_inv);
2568 isp3_param_write(params_vdev, value, ISP3X_HDRMGE_GAIN1, id);
2569
2570 value = arg->gain2;
2571 isp3_param_write(params_vdev, value, ISP3X_HDRMGE_GAIN2, id);
2572
2573 value = isp3_param_read_cache(params_vdev, ISP3X_HDRMGE_CTRL, id);
2574 if (arg->s_base)
2575 value |= BIT(1);
2576 else
2577 value &= ~BIT(1);
2578 isp3_param_write(params_vdev, value, ISP3X_HDRMGE_CTRL, id);
2579 }
2580
2581 if (type == RKISP_PARAMS_IMD || type == RKISP_PARAMS_ALL) {
2582 value = ISP_PACK_4BYTE(arg->ms_dif_0p8, arg->ms_diff_0p15,
2583 arg->lm_dif_0p9, arg->lm_dif_0p15);
2584 isp3_param_write(params_vdev, value, ISP3X_HDRMGE_LIGHTZ, id);
2585 value = (arg->ms_scl & 0x7ff) |
2586 (arg->ms_thd0 & 0x3ff) << 12 |
2587 (arg->ms_thd1 & 0x3ff) << 22;
2588 isp3_param_write(params_vdev, value, ISP3X_HDRMGE_MS_DIFF, id);
2589 value = (arg->lm_scl & 0x7ff) |
2590 (arg->lm_thd0 & 0x3ff) << 12 |
2591 (arg->lm_thd1 & 0x3ff) << 22;
2592 isp3_param_write(params_vdev, value, ISP3X_HDRMGE_LM_DIFF, id);
2593
2594 for (i = 0; i < ISP3X_HDRMGE_L_CURVE_NUM; i++) {
2595 value = ISP_PACK_2SHORT(arg->curve.curve_0[i], arg->curve.curve_1[i]);
2596 isp3_param_write(params_vdev, value, ISP3X_HDRMGE_DIFF_Y0 + 4 * i, id);
2597 }
2598
2599 for (i = 0; i < ISP3X_HDRMGE_E_CURVE_NUM; i++) {
2600 value = arg->e_y[i];
2601 isp3_param_write(params_vdev, value, ISP3X_HDRMGE_OVER_Y0 + 4 * i, id);
2602 }
2603 }
2604 }
2605
2606 static void
isp_hdrmge_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)2607 isp_hdrmge_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
2608 {
2609 }
2610
2611 static void
isp_hdrdrc_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp3x_drc_cfg * arg,enum rkisp_params_type type,u32 id)2612 isp_hdrdrc_config(struct rkisp_isp_params_vdev *params_vdev,
2613 const struct isp3x_drc_cfg *arg,
2614 enum rkisp_params_type type, u32 id)
2615 {
2616 u32 i, value;
2617
2618 if (type == RKISP_PARAMS_IMD)
2619 return;
2620
2621 value = (arg->offset_pow2 & 0x0F) << 28 |
2622 (arg->compres_scl & 0x1FFF) << 14 |
2623 (arg->position & 0x03FFF);
2624 isp3_param_write(params_vdev, value, ISP3X_DRC_CTRL1, id);
2625
2626 value = (arg->delta_scalein & 0xFF) << 24 |
2627 (arg->hpdetail_ratio & 0xFFF) << 12 |
2628 (arg->lpdetail_ratio & 0xFFF);
2629 isp3_param_write(params_vdev, value, ISP3X_DRC_LPRATIO, id);
2630
2631 value = ISP_PACK_4BYTE(arg->bilat_wt_off, 0, arg->weipre_frame, arg->weicur_pix);
2632 isp3_param_write(params_vdev, value, ISP3X_DRC_EXPLRATIO, id);
2633
2634 value = (arg->force_sgm_inv0 & 0xFFFF) << 16 |
2635 (arg->motion_scl & 0xFF) << 8 |
2636 (arg->edge_scl & 0xFF);
2637 isp3_param_write(params_vdev, value, ISP3X_DRC_SIGMA, id);
2638
2639 value = ISP_PACK_2SHORT(arg->space_sgm_inv0, arg->space_sgm_inv1);
2640 isp3_param_write(params_vdev, value, ISP3X_DRC_SPACESGM, id);
2641
2642 value = ISP_PACK_2SHORT(arg->range_sgm_inv0, arg->range_sgm_inv1);
2643 isp3_param_write(params_vdev, value, ISP3X_DRC_RANESGM, id);
2644
2645 value = (arg->weig_bilat & 0x1f) | (arg->weig_maxl & 0x1f) << 8 |
2646 (arg->bilat_soft_thd & 0x3fff) << 16;
2647 if (arg->enable_soft_thd)
2648 value |= BIT(31);
2649 isp3_param_write(params_vdev, value, ISP3X_DRC_BILAT, id);
2650
2651 for (i = 0; i < ISP3X_DRC_Y_NUM / 2; i++) {
2652 value = ISP_PACK_2SHORT(arg->gain_y[2 * i],
2653 arg->gain_y[2 * i + 1]);
2654 isp3_param_write(params_vdev, value, ISP3X_DRC_GAIN_Y0 + 4 * i, id);
2655 }
2656 value = ISP_PACK_2SHORT(arg->gain_y[2 * i], 0);
2657 isp3_param_write(params_vdev, value, ISP3X_DRC_GAIN_Y0 + 4 * i, id);
2658
2659 for (i = 0; i < ISP3X_DRC_Y_NUM / 2; i++) {
2660 value = ISP_PACK_2SHORT(arg->compres_y[2 * i],
2661 arg->compres_y[2 * i + 1]);
2662 isp3_param_write(params_vdev, value, ISP3X_DRC_COMPRES_Y0 + 4 * i, id);
2663 }
2664 value = ISP_PACK_2SHORT(arg->compres_y[2 * i], 0);
2665 isp3_param_write(params_vdev, value, ISP3X_DRC_COMPRES_Y0 + 4 * i, id);
2666
2667 for (i = 0; i < ISP3X_DRC_Y_NUM / 2; i++) {
2668 value = ISP_PACK_2SHORT(arg->scale_y[2 * i],
2669 arg->scale_y[2 * i + 1]);
2670 isp3_param_write(params_vdev, value, ISP3X_DRC_SCALE_Y0 + 4 * i, id);
2671 }
2672 value = ISP_PACK_2SHORT(arg->scale_y[2 * i], 0);
2673 isp3_param_write(params_vdev, value, ISP3X_DRC_SCALE_Y0 + 4 * i, id);
2674
2675 value = ISP_PACK_2SHORT(arg->min_ogain, arg->iir_weight);
2676 isp3_param_write(params_vdev, value, ISP3X_DRC_IIRWG_GAIN, id);
2677 }
2678
2679 static void
isp_hdrdrc_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)2680 isp_hdrdrc_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
2681 {
2682 u32 value;
2683 bool real_en;
2684
2685 value = isp3_param_read(params_vdev, ISP3X_DRC_CTRL0, id);
2686 real_en = !!(value & ISP3X_MODULE_EN);
2687 if ((en && real_en) || (!en && !real_en))
2688 return;
2689
2690 if (en) {
2691 value |= ISP3X_MODULE_EN;
2692 isp3_param_set_bits(params_vdev, ISP3X_ISP_CTRL1,
2693 ISP3X_ADRC_FST_FRAME, id);
2694 } else {
2695 value = 0;
2696 isp_param_clear_bits(params_vdev, ISP3X_GAIN_CTRL, BIT(12));
2697 }
2698 isp3_param_write(params_vdev, value, ISP3X_DRC_CTRL0, id);
2699 }
2700
2701 static void
isp_gic_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp21_gic_cfg * arg,u32 id)2702 isp_gic_config(struct rkisp_isp_params_vdev *params_vdev,
2703 const struct isp21_gic_cfg *arg, u32 id)
2704 {
2705 u32 value;
2706 s32 i;
2707
2708 value = (arg->regmingradthrdark2 & 0x03FF) << 20 |
2709 (arg->regmingradthrdark1 & 0x03FF) << 10 |
2710 (arg->regminbusythre & 0x03FF);
2711 isp3_param_write(params_vdev, value, ISP3X_GIC_DIFF_PARA1, id);
2712
2713 value = (arg->regdarkthre & 0x07FF) << 21 |
2714 (arg->regmaxcorvboth & 0x03FF) << 11 |
2715 (arg->regdarktthrehi & 0x07FF);
2716 isp3_param_write(params_vdev, value, ISP3X_GIC_DIFF_PARA2, id);
2717
2718 value = (arg->regkgrad2dark & 0x0F) << 28 |
2719 (arg->regkgrad1dark & 0x0F) << 24 |
2720 (arg->regstrengthglobal_fix & 0xFF) << 16 |
2721 (arg->regdarkthrestep & 0x0F) << 12 |
2722 (arg->regkgrad2 & 0x0F) << 8 |
2723 (arg->regkgrad1 & 0x0F) << 4 |
2724 (arg->reggbthre & 0x0F);
2725 isp3_param_write(params_vdev, value, ISP3X_GIC_DIFF_PARA3, id);
2726
2727 value = (arg->regmaxcorv & 0x03FF) << 20 |
2728 (arg->regmingradthr2 & 0x03FF) << 10 |
2729 (arg->regmingradthr1 & 0x03FF);
2730 isp3_param_write(params_vdev, value, ISP3X_GIC_DIFF_PARA4, id);
2731
2732 value = (arg->gr_ratio & 0x03) << 28 |
2733 (arg->noise_scale & 0x7F) << 12 |
2734 (arg->noise_base & 0xFFF);
2735 isp3_param_write(params_vdev, value, ISP3X_GIC_NOISE_PARA1, id);
2736
2737 isp3_param_write(params_vdev, arg->diff_clip, ISP3X_GIC_NOISE_PARA2, id);
2738
2739 for (i = 0; i < ISP3X_GIC_SIGMA_Y_NUM / 2; i++) {
2740 value = ISP_PACK_2SHORT(arg->sigma_y[2 * i], arg->sigma_y[2 * i + 1]);
2741 isp3_param_write(params_vdev, value, ISP3X_GIC_SIGMA_VALUE0 + 4 * i, id);
2742 }
2743 value = ISP_PACK_2SHORT(arg->sigma_y[2 * i], 0);
2744 isp3_param_write(params_vdev, value, ISP3X_GIC_SIGMA_VALUE0 + 4 * i, id);
2745 }
2746
2747 static void
isp_gic_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)2748 isp_gic_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
2749 {
2750 u32 value = 0;
2751
2752 if (en)
2753 value |= ISP3X_MODULE_EN;
2754 isp3_param_write(params_vdev, value, ISP3X_GIC_CONTROL, id);
2755 }
2756
2757 static void
isp_dhaz_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp3x_dhaz_cfg * arg,u32 id)2758 isp_dhaz_config(struct rkisp_isp_params_vdev *params_vdev,
2759 const struct isp3x_dhaz_cfg *arg, u32 id)
2760 {
2761 struct rkisp_device *dev = params_vdev->dev;
2762 u32 i, value, ctrl;
2763
2764 ctrl = isp3_param_read(params_vdev, ISP3X_DHAZ_CTRL, id);
2765 ctrl &= ISP3X_DHAZ_ENMUX;
2766
2767 ctrl |= (arg->enhance_en & 0x1) << 20 |
2768 (arg->air_lc_en & 0x1) << 16 |
2769 (arg->hpara_en & 0x1) << 12 |
2770 (arg->hist_en & 0x1) << 8 |
2771 (arg->dc_en & 0x1) << 4 |
2772 (arg->round_en & 0x1) << 26;
2773 if (arg->soft_wr_en)
2774 ctrl |= (arg->soft_wr_en & 0x1) << 25;
2775 /* merge dual unite isp params at frame end */
2776 if (arg->soft_wr_en &&
2777 (!dev->hw_dev->is_unite ||
2778 (dev->hw_dev->is_unite && !(ctrl & ISP3X_DHAZ_ENMUX)))) {
2779 value = ISP_PACK_2SHORT(arg->adp_wt_wr, arg->adp_air_wr);
2780 isp3_param_write(params_vdev, value, ISP3X_DHAZ_ADT_WR0, id);
2781 value = ISP_PACK_2SHORT(arg->adp_tmax_wr, arg->adp_gratio_wr);
2782 isp3_param_write(params_vdev, value, ISP3X_DHAZ_ADT_WR1, id);
2783 for (i = 0; i < ISP3X_DHAZ_HIST_WR_NUM / 3; i++) {
2784 value = (arg->hist_wr[i * 3] & 0x3ff) |
2785 (arg->hist_wr[i * 3 + 1] & 0x3ff) << 10 |
2786 (arg->hist_wr[i * 3 + 2] & 0x3ff) << 20;
2787 isp3_param_write(params_vdev, value, ISP3X_DHAZ_HIST_WR0 + i * 4, id);
2788 }
2789 value = arg->hist_wr[i * 3] & 0x3ff;
2790 isp3_param_write(params_vdev, value, ISP3X_DHAZ_HIST_WR0 + i * 4, id);
2791 }
2792 isp3_param_write(params_vdev, ctrl, ISP3X_DHAZ_CTRL, id);
2793
2794 value = ISP_PACK_4BYTE(arg->dc_min_th, arg->dc_max_th,
2795 arg->yhist_th, arg->yblk_th);
2796 isp3_param_write(params_vdev, value, ISP3X_DHAZ_ADP0, id);
2797
2798 value = ISP_PACK_4BYTE(arg->bright_min, arg->bright_max,
2799 arg->wt_max, 0);
2800 isp3_param_write(params_vdev, value, ISP3X_DHAZ_ADP1, id);
2801
2802 value = ISP_PACK_4BYTE(arg->air_min, arg->air_max,
2803 arg->dark_th, arg->tmax_base);
2804 isp3_param_write(params_vdev, value, ISP3X_DHAZ_ADP2, id);
2805
2806 value = ISP_PACK_2SHORT(arg->tmax_off, arg->tmax_max);
2807 isp3_param_write(params_vdev, value, ISP3X_DHAZ_ADP_TMAX, id);
2808
2809 value = (arg->hist_min & 0xFFFF) << 16 |
2810 (arg->hist_th_off & 0xFF) << 8 |
2811 (arg->hist_k & 0x1F);
2812 isp3_param_write(params_vdev, value, ISP3X_DHAZ_ADP_HIST0, id);
2813
2814 value = ISP_PACK_2SHORT(arg->hist_scale, arg->hist_gratio);
2815 isp3_param_write(params_vdev, value, ISP3X_DHAZ_ADP_HIST1, id);
2816
2817 value = ISP_PACK_2SHORT(arg->enhance_chroma, arg->enhance_value);
2818 isp3_param_write(params_vdev, value, ISP3X_DHAZ_ENHANCE, id);
2819
2820 value = (arg->iir_wt_sigma & 0x07FF) << 16 |
2821 (arg->iir_sigma & 0xFF) << 8 |
2822 (arg->stab_fnum & 0x1F);
2823 isp3_param_write(params_vdev, value, ISP3X_DHAZ_IIR0, id);
2824
2825 value = (arg->iir_pre_wet & 0x0F) << 24 |
2826 (arg->iir_tmax_sigma & 0x7FF) << 8 |
2827 (arg->iir_air_sigma & 0xFF);
2828 isp3_param_write(params_vdev, value, ISP3X_DHAZ_IIR1, id);
2829
2830 value = (arg->cfg_wt & 0x01FF) << 16 |
2831 (arg->cfg_air & 0xFF) << 8 |
2832 (arg->cfg_alpha & 0xFF);
2833 isp3_param_write(params_vdev, value, ISP3X_DHAZ_SOFT_CFG0, id);
2834
2835 value = ISP_PACK_2SHORT(arg->cfg_tmax, arg->cfg_gratio);
2836 isp3_param_write(params_vdev, value, ISP3X_DHAZ_SOFT_CFG1, id);
2837
2838 value = (arg->range_sima & 0x01FF) << 16 |
2839 (arg->space_sigma_pre & 0xFF) << 8 |
2840 (arg->space_sigma_cur & 0xFF);
2841 isp3_param_write(params_vdev, value, ISP3X_DHAZ_BF_SIGMA, id);
2842
2843 value = ISP_PACK_2SHORT(arg->bf_weight, arg->dc_weitcur);
2844 isp3_param_write(params_vdev, value, ISP3X_DHAZ_BF_WET, id);
2845
2846 for (i = 0; i < ISP3X_DHAZ_ENH_CURVE_NUM / 2; i++) {
2847 value = ISP_PACK_2SHORT(arg->enh_curve[2 * i], arg->enh_curve[2 * i + 1]);
2848 isp3_param_write(params_vdev, value, ISP3X_DHAZ_ENH_CURVE0 + 4 * i, id);
2849 }
2850 value = ISP_PACK_2SHORT(arg->enh_curve[2 * i], 0);
2851 isp3_param_write(params_vdev, value, ISP3X_DHAZ_ENH_CURVE0 + 4 * i, id);
2852
2853 value = ISP_PACK_4BYTE(arg->gaus_h0, arg->gaus_h1, arg->gaus_h2, 0);
2854 isp3_param_write(params_vdev, value, ISP3X_DHAZ_GAUS, id);
2855
2856 for (i = 0; i < ISP3X_DHAZ_SIGMA_IDX_NUM / 4; i++) {
2857 value = ISP_PACK_4BYTE(arg->sigma_idx[i * 4], arg->sigma_idx[i * 4 + 1],
2858 arg->sigma_idx[i * 4 + 2], arg->sigma_idx[i * 4 + 3]);
2859 isp3_param_write(params_vdev, value, ISP3X_DHAZ_GAIN_IDX0 + i * 4, id);
2860 }
2861 value = ISP_PACK_4BYTE(arg->sigma_idx[i * 4], arg->sigma_idx[i * 4 + 1],
2862 arg->sigma_idx[i * 4 + 2], 0);
2863 isp3_param_write(params_vdev, value, ISP3X_DHAZ_GAIN_IDX0 + i * 4, id);
2864
2865 for (i = 0; i < ISP3X_DHAZ_SIGMA_LUT_NUM / 2; i++) {
2866 value = ISP_PACK_2SHORT(arg->sigma_lut[i * 2], arg->sigma_lut[i * 2 + 1]);
2867 isp3_param_write(params_vdev, value, ISP3X_DHAZ_GAIN_LUT0 + i * 4, id);
2868 }
2869 value = ISP_PACK_2SHORT(arg->sigma_lut[i * 2], 0);
2870 isp3_param_write(params_vdev, value, ISP3X_DHAZ_GAIN_LUT0 + i * 4, id);
2871 }
2872
2873 static void
isp_dhaz_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)2874 isp_dhaz_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
2875 {
2876 u32 value;
2877 bool real_en;
2878
2879 value = isp3_param_read(params_vdev, ISP3X_DHAZ_CTRL, id);
2880 real_en = !!(value & ISP3X_DHAZ_ENMUX);
2881 if ((en && real_en) || (!en && !real_en))
2882 return;
2883
2884 if (en) {
2885 value |= ISP3X_SELF_FORCE_UPD | ISP3X_DHAZ_ENMUX;
2886 isp3_param_set_bits(params_vdev, ISP3X_ISP_CTRL1,
2887 ISP3X_DHAZ_FST_FRAME, id);
2888 } else {
2889 value &= ~ISP3X_DHAZ_ENMUX;
2890 isp_param_clear_bits(params_vdev, ISP3X_GAIN_CTRL, BIT(16));
2891 }
2892 isp3_param_write(params_vdev, value, ISP3X_DHAZ_CTRL, id);
2893 }
2894
2895 static void
isp_3dlut_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_3dlut_cfg * arg,u32 id)2896 isp_3dlut_config(struct rkisp_isp_params_vdev *params_vdev,
2897 const struct isp2x_3dlut_cfg *arg, u32 id)
2898 {
2899 struct rkisp_isp_params_val_v3x *priv_val;
2900 u32 value, buf_idx, i;
2901 u32 *data;
2902
2903 priv_val = (struct rkisp_isp_params_val_v3x *)params_vdev->priv_val;
2904 buf_idx = (priv_val->buf_3dlut_idx[id]++) % ISP3X_3DLUT_BUF_NUM;
2905
2906 data = (u32 *)priv_val->buf_3dlut[id][buf_idx].vaddr;
2907 for (i = 0; i < arg->actual_size; i++)
2908 data[i] = (arg->lut_b[i] & 0x3FF) |
2909 (arg->lut_g[i] & 0xFFF) << 10 |
2910 (arg->lut_r[i] & 0x3FF) << 22;
2911 rkisp_prepare_buffer(params_vdev->dev, &priv_val->buf_3dlut[id][buf_idx]);
2912 value = priv_val->buf_3dlut[id][buf_idx].dma_addr;
2913 isp3_param_write(params_vdev, value, ISP3X_MI_LUT_3D_RD_BASE, id);
2914 isp3_param_write(params_vdev, arg->actual_size, ISP3X_MI_LUT_3D_RD_WSIZE, id);
2915
2916 value = isp3_param_read(params_vdev, ISP3X_3DLUT_CTRL, id);
2917 value &= ISP3X_3DLUT_EN;
2918
2919 if (value)
2920 isp3_param_set_bits(params_vdev, ISP3X_3DLUT_UPDATE, 0x01, id);
2921
2922 isp3_param_write(params_vdev, value, ISP3X_3DLUT_CTRL, id);
2923 }
2924
2925 static void
isp_3dlut_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)2926 isp_3dlut_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
2927 {
2928 u32 value;
2929 bool en_state;
2930
2931 value = isp3_param_read(params_vdev, ISP3X_3DLUT_CTRL, id);
2932 en_state = (value & ISP3X_3DLUT_EN) ? true : false;
2933
2934 if (en == en_state)
2935 return;
2936
2937 if (en) {
2938 isp3_param_set_bits(params_vdev, ISP3X_3DLUT_CTRL, 0x01, id);
2939 isp3_param_set_bits(params_vdev, ISP3X_3DLUT_UPDATE, 0x01, id);
2940 } else {
2941 isp3_param_clear_bits(params_vdev, ISP3X_3DLUT_CTRL, 0x01, id);
2942 isp3_param_clear_bits(params_vdev, ISP3X_3DLUT_UPDATE, 0x01, id);
2943 isp3_param_clear_bits(params_vdev, ISP3X_GAIN_CTRL, BIT(20), id);
2944 }
2945 }
2946
2947 static void
isp_ldch_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp2x_ldch_cfg * arg,u32 id)2948 isp_ldch_config(struct rkisp_isp_params_vdev *params_vdev,
2949 const struct isp2x_ldch_cfg *arg, u32 id)
2950 {
2951 struct rkisp_device *dev = params_vdev->dev;
2952 struct rkisp_isp_params_val_v3x *priv_val;
2953 struct isp2x_mesh_head *head;
2954 int buf_idx, i;
2955 u32 value;
2956
2957 priv_val = (struct rkisp_isp_params_val_v3x *)params_vdev->priv_val;
2958 for (i = 0; i < ISP3X_MESH_BUF_NUM; i++) {
2959 if (arg->buf_fd == priv_val->buf_ldch[id][i].dma_fd)
2960 break;
2961 }
2962 if (i == ISP3X_MESH_BUF_NUM) {
2963 dev_err(dev->dev, "cannot find ldch buf fd(%d)\n", arg->buf_fd);
2964 return;
2965 }
2966
2967 if (!priv_val->buf_ldch[id][i].vaddr) {
2968 dev_err(dev->dev, "no ldch buffer allocated\n");
2969 return;
2970 }
2971
2972 buf_idx = priv_val->buf_ldch_idx[id];
2973 head = (struct isp2x_mesh_head *)priv_val->buf_ldch[id][buf_idx].vaddr;
2974 head->stat = MESH_BUF_INIT;
2975
2976 buf_idx = i;
2977 head = (struct isp2x_mesh_head *)priv_val->buf_ldch[id][buf_idx].vaddr;
2978 head->stat = MESH_BUF_CHIPINUSE;
2979 priv_val->buf_ldch_idx[id] = buf_idx;
2980 rkisp_prepare_buffer(dev, &priv_val->buf_ldch[id][buf_idx]);
2981 value = priv_val->buf_ldch[id][buf_idx].dma_addr + head->data_oft;
2982 isp3_param_write(params_vdev, value, ISP3X_MI_LUT_LDCH_RD_BASE, id);
2983 isp3_param_write(params_vdev, arg->hsize, ISP3X_MI_LUT_LDCH_RD_H_WSIZE, id);
2984 isp3_param_write(params_vdev, arg->vsize, ISP3X_MI_LUT_LDCH_RD_V_SIZE, id);
2985 }
2986
2987 static void
isp_ldch_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)2988 isp_ldch_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
2989 {
2990 struct rkisp_device *dev = params_vdev->dev;
2991 struct rkisp_isp_params_val_v3x *priv_val;
2992 u32 buf_idx;
2993
2994 priv_val = (struct rkisp_isp_params_val_v3x *)params_vdev->priv_val;
2995 if (en) {
2996 buf_idx = priv_val->buf_ldch_idx[id];
2997 if (!priv_val->buf_ldch[id][buf_idx].vaddr) {
2998 dev_err(dev->dev, "no ldch buffer allocated\n");
2999 return;
3000 }
3001 isp3_param_set_bits(params_vdev, ISP3X_LDCH_STS, 0x01, id);
3002 } else {
3003 isp3_param_clear_bits(params_vdev, ISP3X_LDCH_STS, 0x01, id);
3004 }
3005 }
3006
3007 static void
isp_ynr_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp3x_ynr_cfg * arg,u32 id)3008 isp_ynr_config(struct rkisp_isp_params_vdev *params_vdev,
3009 const struct isp3x_ynr_cfg *arg, u32 id)
3010 {
3011 u32 i, value;
3012
3013 value = isp3_param_read(params_vdev, ISP3X_YNR_GLOBAL_CTRL, id);
3014 value &= ISP3X_MODULE_EN;
3015
3016 value |= (arg->rnr_en & 0x1) << 26 |
3017 (arg->thumb_mix_cur_en & 0x1) << 24 |
3018 (arg->global_gain_alpha & 0xF) << 20 |
3019 (arg->global_gain & 0x3FF) << 8 |
3020 (arg->flt1x1_bypass_sel & 0x3) << 6 |
3021 (arg->sft5x5_bypass & 0x1) << 5 |
3022 (arg->flt1x1_bypass & 0x1) << 4 |
3023 (arg->lgft3x3_bypass & 0x1) << 3 |
3024 (arg->lbft5x5_bypass & 0x1) << 2 |
3025 (arg->bft3x3_bypass & 0x1) << 1;
3026 isp3_param_write(params_vdev, value, ISP3X_YNR_GLOBAL_CTRL, id);
3027
3028 value = ISP_PACK_2SHORT(arg->rnr_max_r, arg->local_gainscale);
3029 isp3_param_write(params_vdev, value, ISP3X_YNR_RNR_MAX_R, id);
3030
3031 value = ISP_PACK_2SHORT(arg->rnr_center_coorh, arg->rnr_center_coorv);
3032 isp3_param_write(params_vdev, value, ISP3X_YNR_RNR_CENTER_COOR, id);
3033
3034 value = ISP_PACK_2SHORT(arg->loclagain_adj_thresh, arg->localgain_adj);
3035 isp3_param_write(params_vdev, value, ISP3X_YNR_LOCAL_GAIN_CTRL, id);
3036
3037 value = ISP_PACK_2SHORT(arg->low_bf_inv0, arg->low_bf_inv1);
3038 isp3_param_write(params_vdev, value, ISP3X_YNR_LOWNR_CTRL0, id);
3039
3040 value = ISP_PACK_2SHORT(arg->low_thred_adj, arg->low_peak_supress);
3041 isp3_param_write(params_vdev, value, ISP3X_YNR_LOWNR_CTRL1, id);
3042
3043 value = ISP_PACK_2SHORT(arg->low_edge_adj_thresh, arg->low_dist_adj);
3044 isp3_param_write(params_vdev, value, ISP3X_YNR_LOWNR_CTRL2, id);
3045
3046 value = (arg->low_bi_weight & 0xFF) << 24 |
3047 (arg->low_weight & 0xFF) << 16 |
3048 (arg->low_center_weight & 0xFFFF);
3049 isp3_param_write(params_vdev, value, ISP3X_YNR_LOWNR_CTRL3, id);
3050
3051 value = ISP_PACK_2SHORT(arg->high_thred_adj, arg->hi_min_adj);
3052 isp3_param_write(params_vdev, value, ISP3X_YNR_HIGHNR_CTRL0, id);
3053
3054 value = ISP_PACK_2SHORT(arg->hi_edge_thed, arg->high_retain_weight);
3055 isp3_param_write(params_vdev, value, ISP3X_YNR_HIGHNR_CTRL1, id);
3056
3057 value = ISP_PACK_4BYTE(arg->base_filter_weight0,
3058 arg->base_filter_weight1,
3059 arg->base_filter_weight2,
3060 0);
3061 isp3_param_write(params_vdev, value, ISP3X_YNR_HIGHNR_BASE_FILTER_WEIGHT, id);
3062
3063 value = ISP_PACK_2SHORT(arg->lbf_weight_thres, arg->frame_full_size);
3064 isp3_param_write(params_vdev, value, ISP3X_YNR_LOWNR_CTRL4, id);
3065
3066 value = (arg->low_gauss1_coeff2 & 0xFFFF) << 16 |
3067 (arg->low_gauss1_coeff1 & 0xFF) << 8 |
3068 (arg->low_gauss1_coeff0 & 0xFF);
3069 isp3_param_write(params_vdev, value, ISP3X_YNR_GAUSS1_COEFF, id);
3070
3071 value = (arg->low_gauss2_coeff2 & 0xFFFF) << 16 |
3072 (arg->low_gauss2_coeff1 & 0xFF) << 8 |
3073 (arg->low_gauss2_coeff0 & 0xFF);
3074 isp3_param_write(params_vdev, value, ISP3X_YNR_GAUSS2_COEFF, id);
3075
3076 value = ISP_PACK_4BYTE(arg->direction_weight0,
3077 arg->direction_weight1,
3078 arg->direction_weight2,
3079 arg->direction_weight3);
3080 isp3_param_write(params_vdev, value, ISP3X_YNR_DIRECTION_W_0_3, id);
3081
3082 value = ISP_PACK_4BYTE(arg->direction_weight4,
3083 arg->direction_weight5,
3084 arg->direction_weight6,
3085 arg->direction_weight7);
3086 isp3_param_write(params_vdev, value, ISP3X_YNR_DIRECTION_W_4_7, id);
3087
3088 for (i = 0; i < ISP3X_YNR_XY_NUM / 2; i++) {
3089 value = ISP_PACK_2SHORT(arg->luma_points_x[2 * i],
3090 arg->luma_points_x[2 * i + 1]);
3091 isp3_param_write(params_vdev, value, ISP3X_YNR_SGM_DX_0_1 + 4 * i, id);
3092 }
3093 value = ISP_PACK_2SHORT(arg->luma_points_x[2 * i], 0);
3094 isp3_param_write(params_vdev, value, ISP3X_YNR_SGM_DX_0_1 + 4 * i, id);
3095
3096 for (i = 0; i < ISP3X_YNR_XY_NUM / 2; i++) {
3097 value = ISP_PACK_2SHORT(arg->lsgm_y[2 * i],
3098 arg->lsgm_y[2 * i + 1]);
3099 isp3_param_write(params_vdev, value, ISP3X_YNR_LSGM_Y_0_1 + 4 * i, id);
3100 }
3101 value = ISP_PACK_2SHORT(arg->lsgm_y[2 * i], 0);
3102 isp3_param_write(params_vdev, value, ISP3X_YNR_LSGM_Y_0_1 + 4 * i, id);
3103
3104 for (i = 0; i < ISP3X_YNR_XY_NUM / 2; i++) {
3105 value = ISP_PACK_2SHORT(arg->hsgm_y[2 * i],
3106 arg->hsgm_y[2 * i + 1]);
3107 isp3_param_write(params_vdev, value, ISP3X_YNR_HSGM_Y_0_1 + 4 * i, id);
3108 }
3109 value = ISP_PACK_2SHORT(arg->hsgm_y[2 * i], 0);
3110 isp3_param_write(params_vdev, value, ISP3X_YNR_HSGM_Y_0_1 + 4 * i, id);
3111
3112 for (i = 0; i < ISP3X_YNR_XY_NUM / 4; i++) {
3113 value = ISP_PACK_4BYTE(arg->rnr_strength3[4 * i],
3114 arg->rnr_strength3[4 * i + 1],
3115 arg->rnr_strength3[4 * i + 2],
3116 arg->rnr_strength3[4 * i + 3]);
3117 isp3_param_write(params_vdev, value, ISP3X_YNR_RNR_STRENGTH03 + 4 * i, id);
3118 }
3119 value = ISP_PACK_4BYTE(arg->rnr_strength3[4 * i], 0, 0, 0);
3120 isp3_param_write(params_vdev, value, ISP3X_YNR_RNR_STRENGTH03 + 4 * i, id);
3121 }
3122
3123 static void
isp_ynr_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)3124 isp_ynr_enable(struct rkisp_isp_params_vdev *params_vdev,
3125 bool en, u32 id)
3126 {
3127 u32 ynr_ctrl;
3128 bool real_en;
3129
3130 ynr_ctrl = isp3_param_read_cache(params_vdev, ISP3X_YNR_GLOBAL_CTRL, id);
3131 real_en = !!(ynr_ctrl & ISP3X_MODULE_EN);
3132 if ((en && real_en) || (!en && !real_en))
3133 return;
3134
3135 if (en) {
3136 ynr_ctrl |= ISP3X_MODULE_EN;
3137 isp3_param_set_bits(params_vdev, ISP3X_ISP_CTRL1,
3138 ISP3X_YNR_FST_FRAME, id);
3139 } else {
3140 ynr_ctrl &= ~ISP3X_MODULE_EN;
3141 }
3142
3143 isp3_param_write(params_vdev, ynr_ctrl, ISP3X_YNR_GLOBAL_CTRL, id);
3144 }
3145
3146 static void
isp_cnr_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp3x_cnr_cfg * arg,u32 id)3147 isp_cnr_config(struct rkisp_isp_params_vdev *params_vdev,
3148 const struct isp3x_cnr_cfg *arg, u32 id)
3149 {
3150 u32 i, value, ctrl, gain_ctrl;
3151
3152 gain_ctrl = isp3_param_read(params_vdev, ISP3X_GAIN_CTRL, id);
3153 ctrl = isp3_param_read(params_vdev, ISP3X_CNR_CTRL, id);
3154 ctrl &= ISP3X_MODULE_EN;
3155
3156 ctrl |= (arg->thumb_mix_cur_en & 0x1) << 4 |
3157 (arg->lq_bila_bypass & 0x1) << 3 |
3158 (arg->hq_bila_bypass & 0x1) << 2 |
3159 (arg->exgain_bypass & 0x1) << 1;
3160 value = (arg->global_gain & 0x3ff) |
3161 (arg->global_gain_alpha & 0xf) << 12;
3162 /* gain disable, using global gain for cnr */
3163 if (ctrl & ISP3X_MODULE_EN && !(gain_ctrl & ISP3X_MODULE_EN)) {
3164 ctrl |= BIT(1);
3165 value &= 0x3ff;
3166 value |= 0x8000;
3167 }
3168 isp3_param_write(params_vdev, ctrl, ISP3X_CNR_CTRL, id);
3169 isp3_param_write(params_vdev, value, ISP3X_CNR_EXGAIN, id);
3170
3171 value = ISP_PACK_4BYTE(arg->gain_1sigma, arg->gain_offset,
3172 arg->gain_iso, 0);
3173 isp3_param_write(params_vdev, value, ISP3X_CNR_GAIN_PARA, id);
3174
3175 value = ISP_PACK_4BYTE(arg->gain_uvgain0, arg->gain_uvgain1, 0, 0);
3176 isp3_param_write(params_vdev, value, ISP3X_CNR_GAIN_UV_PARA, id);
3177
3178 isp3_param_write(params_vdev, arg->lmed3_alpha, ISP3X_CNR_LMED3, id);
3179
3180 value = ISP_PACK_4BYTE(arg->lbf5_gain_c, arg->lbf5_gain_y, 0, 0);
3181 isp3_param_write(params_vdev, value, ISP3X_CNR_LBF5_GAIN, id);
3182
3183 value = ISP_PACK_4BYTE(arg->lbf5_weit_d0, arg->lbf5_weit_d1,
3184 arg->lbf5_weit_d2, arg->lbf5_weit_d3);
3185 isp3_param_write(params_vdev, value, ISP3X_CNR_LBF5_WEITD0_3, id);
3186
3187 isp3_param_write(params_vdev, arg->lbf5_weit_d4, ISP3X_CNR_LBF5_WEITD4, id);
3188
3189 isp3_param_write(params_vdev, arg->hmed3_alpha, ISP3X_CNR_HMED3, id);
3190
3191 value = (arg->hbf5_weit_src & 0xFF) << 24 |
3192 (arg->hbf5_min_wgt & 0xFF) << 16 |
3193 (arg->hbf5_sigma & 0xFFFF);
3194 isp3_param_write(params_vdev, value, ISP3X_CNR_HBF5, id);
3195
3196 value = ISP_PACK_2SHORT(arg->lbf3_sigma, arg->lbf5_weit_src);
3197 isp3_param_write(params_vdev, value, ISP3X_CNR_LBF3, id);
3198
3199 for (i = 0; i < ISP3X_CNR_SIGMA_Y_NUM / 4; i++) {
3200 value = ISP_PACK_4BYTE(arg->sigma_y[i * 4], arg->sigma_y[i * 4 + 1],
3201 arg->sigma_y[i * 4 + 2], arg->sigma_y[i * 4 + 3]);
3202 isp3_param_write(params_vdev, value, ISP3X_CNR_SIGMA0 + i * 4, id);
3203 }
3204 value = arg->sigma_y[i * 4];
3205 isp3_param_write(params_vdev, value, ISP3X_CNR_SIGMA0 + i * 4, id);
3206 }
3207
3208 static void
isp_cnr_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)3209 isp_cnr_enable(struct rkisp_isp_params_vdev *params_vdev,
3210 bool en, u32 id)
3211 {
3212 u32 cnr_ctrl;
3213 bool real_en;
3214
3215 cnr_ctrl = isp3_param_read_cache(params_vdev, ISP3X_CNR_CTRL, id);
3216 real_en = !!(cnr_ctrl & ISP3X_MODULE_EN);
3217 if ((en && real_en) || (!en && !real_en))
3218 return;
3219
3220 if (en) {
3221 cnr_ctrl |= ISP3X_MODULE_EN;
3222 isp3_param_set_bits(params_vdev, ISP3X_ISP_CTRL1,
3223 ISP3X_CNR_FST_FRAME, id);
3224 } else {
3225 cnr_ctrl &= ~ISP3X_MODULE_EN;
3226 }
3227
3228 isp3_param_write(params_vdev, cnr_ctrl, ISP3X_CNR_CTRL, id);
3229 }
3230
3231 static void
isp_sharp_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp3x_sharp_cfg * arg,u32 id)3232 isp_sharp_config(struct rkisp_isp_params_vdev *params_vdev,
3233 const struct isp3x_sharp_cfg *arg, u32 id)
3234 {
3235 u32 value;
3236
3237 value = isp3_param_read(params_vdev, ISP3X_SHARP_EN, id);
3238 value &= ISP3X_MODULE_EN;
3239
3240 value |= (arg->bypass & 0x1) << 1 |
3241 (arg->center_mode & 0x1) << 2 |
3242 (arg->exgain_bypass & 0x1) << 3;
3243 isp3_param_write(params_vdev, value, ISP3X_SHARP_EN, id);
3244
3245 value = ISP_PACK_4BYTE(arg->pbf_ratio, arg->gaus_ratio,
3246 arg->bf_ratio, arg->sharp_ratio);
3247 isp3_param_write(params_vdev, value, ISP3X_SHARP_RATIO, id);
3248
3249 value = (arg->luma_dx[6] & 0x0F) << 24 |
3250 (arg->luma_dx[5] & 0x0F) << 20 |
3251 (arg->luma_dx[4] & 0x0F) << 16 |
3252 (arg->luma_dx[3] & 0x0F) << 12 |
3253 (arg->luma_dx[2] & 0x0F) << 8 |
3254 (arg->luma_dx[1] & 0x0F) << 4 |
3255 (arg->luma_dx[0] & 0x0F);
3256 isp3_param_write(params_vdev, value, ISP3X_SHARP_LUMA_DX, id);
3257
3258 value = (arg->pbf_sigma_inv[2] & 0x3FF) << 20 |
3259 (arg->pbf_sigma_inv[1] & 0x3FF) << 10 |
3260 (arg->pbf_sigma_inv[0] & 0x3FF);
3261 isp3_param_write(params_vdev, value, ISP3X_SHARP_PBF_SIGMA_INV_0, id);
3262
3263 value = (arg->pbf_sigma_inv[5] & 0x3FF) << 20 |
3264 (arg->pbf_sigma_inv[4] & 0x3FF) << 10 |
3265 (arg->pbf_sigma_inv[3] & 0x3FF);
3266 isp3_param_write(params_vdev, value, ISP3X_SHARP_PBF_SIGMA_INV_1, id);
3267
3268 value = (arg->pbf_sigma_inv[7] & 0x3FF) << 10 |
3269 (arg->pbf_sigma_inv[6] & 0x3FF);
3270 isp3_param_write(params_vdev, value, ISP3X_SHARP_PBF_SIGMA_INV_2, id);
3271
3272 value = (arg->bf_sigma_inv[2] & 0x3FF) << 20 |
3273 (arg->bf_sigma_inv[1] & 0x3FF) << 10 |
3274 (arg->bf_sigma_inv[0] & 0x3FF);
3275 isp3_param_write(params_vdev, value, ISP3X_SHARP_BF_SIGMA_INV_0, id);
3276
3277 value = (arg->bf_sigma_inv[5] & 0x3FF) << 20 |
3278 (arg->bf_sigma_inv[4] & 0x3FF) << 10 |
3279 (arg->bf_sigma_inv[3] & 0x3FF);
3280 isp3_param_write(params_vdev, value, ISP3X_SHARP_BF_SIGMA_INV_1, id);
3281
3282 value = (arg->bf_sigma_inv[7] & 0x3FF) << 10 |
3283 (arg->bf_sigma_inv[6] & 0x3FF);
3284 isp3_param_write(params_vdev, value, ISP3X_SHARP_BF_SIGMA_INV_2, id);
3285
3286 value = (arg->bf_sigma_shift & 0x0F) << 4 |
3287 (arg->pbf_sigma_shift & 0x0F);
3288 isp3_param_write(params_vdev, value, ISP3X_SHARP_SIGMA_SHIFT, id);
3289
3290 value = (arg->ehf_th[2] & 0x3FF) << 20 |
3291 (arg->ehf_th[1] & 0x3FF) << 10 |
3292 (arg->ehf_th[0] & 0x3FF);
3293 isp3_param_write(params_vdev, value, ISP3X_SHARP_EHF_TH_0, id);
3294
3295 value = (arg->ehf_th[5] & 0x3FF) << 20 |
3296 (arg->ehf_th[4] & 0x3FF) << 10 |
3297 (arg->ehf_th[3] & 0x3FF);
3298 isp3_param_write(params_vdev, value, ISP3X_SHARP_EHF_TH_1, id);
3299
3300 value = (arg->ehf_th[7] & 0x3FF) << 10 |
3301 (arg->ehf_th[6] & 0x3FF);
3302 isp3_param_write(params_vdev, value, ISP3X_SHARP_EHF_TH_2, id);
3303
3304 value = (arg->clip_hf[2] & 0x3FF) << 20 |
3305 (arg->clip_hf[1] & 0x3FF) << 10 |
3306 (arg->clip_hf[0] & 0x3FF);
3307 isp3_param_write(params_vdev, value, ISP3X_SHARP_CLIP_HF_0, id);
3308
3309 value = (arg->clip_hf[5] & 0x3FF) << 20 |
3310 (arg->clip_hf[4] & 0x3FF) << 10 |
3311 (arg->clip_hf[3] & 0x3FF);
3312 isp3_param_write(params_vdev, value, ISP3X_SHARP_CLIP_HF_1, id);
3313
3314 value = (arg->clip_hf[7] & 0x3FF) << 10 |
3315 (arg->clip_hf[6] & 0x3FF);
3316 isp3_param_write(params_vdev, value, ISP3X_SHARP_CLIP_HF_2, id);
3317
3318 value = ISP_PACK_4BYTE(arg->pbf_coef0, arg->pbf_coef1, arg->pbf_coef2, 0);
3319 isp3_param_write(params_vdev, value, ISP3X_SHARP_PBF_COEF, id);
3320
3321 value = ISP_PACK_4BYTE(arg->bf_coef0, arg->bf_coef1, arg->bf_coef2, 0);
3322 isp3_param_write(params_vdev, value, ISP3X_SHARP_BF_COEF, id);
3323
3324 value = ISP_PACK_4BYTE(arg->gaus_coef[0], arg->gaus_coef[1], arg->gaus_coef[2], 0);
3325 isp3_param_write(params_vdev, value, ISP3X_SHARP_GAUS_COEF0, id);
3326
3327 value = ISP_PACK_4BYTE(arg->gaus_coef[3], arg->gaus_coef[4], arg->gaus_coef[5], 0);
3328 isp3_param_write(params_vdev, value, ISP3X_SHARP_GAUS_COEF1, id);
3329 }
3330
3331 static void
isp_sharp_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)3332 isp_sharp_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
3333 {
3334 u32 value;
3335
3336 value = isp3_param_read_cache(params_vdev, ISP3X_SHARP_EN, id);
3337 value &= ~ISP3X_MODULE_EN;
3338
3339 if (en)
3340 value |= ISP3X_MODULE_EN;
3341
3342 isp3_param_write(params_vdev, value, ISP3X_SHARP_EN, id);
3343 }
3344
3345 static void
isp_baynr_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp3x_baynr_cfg * arg,u32 id)3346 isp_baynr_config(struct rkisp_isp_params_vdev *params_vdev,
3347 const struct isp3x_baynr_cfg *arg, u32 id)
3348 {
3349 u32 i, value;
3350
3351 value = isp3_param_read(params_vdev, ISP3X_BAYNR_CTRL, id);
3352 value &= ISP3X_MODULE_EN;
3353
3354 value |= (arg->lg2_mode & 0x3) << 12 |
3355 (arg->gauss_en & 0x1) << 8 |
3356 (arg->log_bypass & 0x1) << 4;
3357 isp3_param_write(params_vdev, value, ISP3X_BAYNR_CTRL, id);
3358
3359 value = ISP_PACK_2SHORT(arg->dgain0, arg->dgain1);
3360 isp3_param_write(params_vdev, value, ISP3X_BAYNR_DGAIN0, id);
3361
3362 isp3_param_write(params_vdev, arg->dgain2, ISP3X_BAYNR_DGAIN1, id);
3363 isp3_param_write(params_vdev, arg->pix_diff, ISP3X_BAYNR_PIXDIFF, id);
3364
3365 value = ISP_PACK_2SHORT(arg->softthld, arg->diff_thld);
3366 isp3_param_write(params_vdev, value, ISP3X_BAYNR_THLD, id);
3367
3368 value = ISP_PACK_2SHORT(arg->reg_w1, arg->bltflt_streng);
3369 isp3_param_write(params_vdev, value, ISP3X_BAYNR_W1_STRENG, id);
3370
3371 for (i = 0; i < ISP3X_BAYNR_XY_NUM / 2; i++) {
3372 value = ISP_PACK_2SHORT(arg->sigma_x[2 * i], arg->sigma_x[2 * i + 1]);
3373 isp3_param_write(params_vdev, value, ISP3X_BAYNR_SIGMAX01 + 4 * i, id);
3374 }
3375
3376 for (i = 0; i < ISP3X_BAYNR_XY_NUM / 2; i++) {
3377 value = ISP_PACK_2SHORT(arg->sigma_y[2 * i], arg->sigma_y[2 * i + 1]);
3378 isp3_param_write(params_vdev, value, ISP3X_BAYNR_SIGMAY01 + 4 * i, id);
3379 }
3380
3381 value = (arg->weit_d2 & 0x3FF) << 20 |
3382 (arg->weit_d1 & 0x3FF) << 10 |
3383 (arg->weit_d0 & 0x3FF);
3384 isp3_param_write(params_vdev, value, ISP3X_BAYNR_WRIT_D, id);
3385
3386 value = ISP_PACK_2SHORT(arg->lg2_off, arg->lg2_lgoff);
3387 isp3_param_write(params_vdev, value, ISP3X_BAYNR_LG_OFF, id);
3388
3389 value = arg->dat_max & 0xfffff;
3390 isp3_param_write(params_vdev, value, ISP3X_BAYNR_DAT_MAX, id);
3391 }
3392
3393 static void
isp_baynr_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)3394 isp_baynr_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
3395 {
3396 u32 value;
3397
3398 value = isp3_param_read_cache(params_vdev, ISP3X_BAYNR_CTRL, id);
3399 value &= ~ISP3X_MODULE_EN;
3400
3401 if (en)
3402 value |= ISP3X_MODULE_EN;
3403
3404 isp3_param_write(params_vdev, value, ISP3X_BAYNR_CTRL, id);
3405 }
3406
3407 static void
isp_bay3d_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp3x_bay3d_cfg * arg,u32 id)3408 isp_bay3d_config(struct rkisp_isp_params_vdev *params_vdev,
3409 const struct isp3x_bay3d_cfg *arg, u32 id)
3410 {
3411 struct rkisp_device *dev = params_vdev->dev;
3412 u32 i, value;
3413
3414 value = isp3_param_read(params_vdev, ISP3X_BAY3D_CTRL, id);
3415 value &= ISP3X_MODULE_EN;
3416
3417 if (dev->rd_mode == HDR_NORMAL ||
3418 dev->rd_mode == HDR_RDBK_FRAME1)
3419 value |= BIT(13); //bandwidth save
3420 value |= (arg->loswitch_protect & 0x1) << 12 |
3421 (arg->glbpk_en & 0x1) << 11 |
3422 (arg->logaus3_bypass_en & 0x1) << 10 |
3423 (arg->logaus5_bypass_en & 0x1) << 9 |
3424 (arg->lomed_bypass_en & 0x1) << 8 |
3425 (arg->hichnsplit_en & 0x1) << 7 |
3426 (arg->hiabs_possel & 0x1) << 6 |
3427 (arg->higaus_bypass_en & 0x1) << 5 |
3428 (arg->himed_bypass_en & 0x1) << 4 |
3429 (arg->lobypass_en & 0x1) << 3 |
3430 (arg->hibypass_en & 0x1) << 2 |
3431 (arg->bypass_en & 0x1) << 1;
3432 isp3_param_write(params_vdev, value, ISP3X_BAY3D_CTRL, id);
3433
3434 value = ISP_PACK_2SHORT(arg->softwgt, arg->hidif_th);
3435 isp3_param_write(params_vdev, value, ISP3X_BAY3D_KALRATIO, id);
3436
3437 isp3_param_write(params_vdev, arg->glbpk2, ISP3X_BAY3D_GLBPK2, id);
3438
3439 value = ISP_PACK_2SHORT(arg->wgtlmt, arg->wgtratio);
3440 isp3_param_write(params_vdev, value, ISP3X_BAY3D_WGTLMT, id);
3441
3442 for (i = 0; i < ISP3X_BAY3D_XY_NUM / 2; i++) {
3443 value = ISP_PACK_2SHORT(arg->sig0_x[2 * i],
3444 arg->sig0_x[2 * i + 1]);
3445 isp3_param_write(params_vdev, value, ISP3X_BAY3D_SIG0_X0 + 4 * i, id);
3446
3447 value = ISP_PACK_2SHORT(arg->sig1_x[2 * i],
3448 arg->sig1_x[2 * i + 1]);
3449 isp3_param_write(params_vdev, value, ISP3X_BAY3D_SIG1_X0 + 4 * i, id);
3450 }
3451
3452 for (i = 0; i < ISP3X_BAY3D_XY_NUM / 2; i++) {
3453 value = ISP_PACK_2SHORT(arg->sig0_y[2 * i],
3454 arg->sig0_y[2 * i + 1]);
3455 isp3_param_write(params_vdev, value, ISP3X_BAY3D_SIG0_Y0 + 4 * i, id);
3456
3457 value = ISP_PACK_2SHORT(arg->sig1_y[2 * i],
3458 arg->sig1_y[2 * i + 1]);
3459 isp3_param_write(params_vdev, value, ISP3X_BAY3D_SIG1_Y0 + 4 * i, id);
3460
3461 value = ISP_PACK_2SHORT(arg->sig2_y[2 * i],
3462 arg->sig2_y[2 * i + 1]);
3463 isp3_param_write(params_vdev, value, ISP3X_BAY3D_SIG2_Y0 + 4 * i, id);
3464 }
3465 }
3466
3467 static void
isp_bay3d_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)3468 isp_bay3d_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
3469 {
3470 struct rkisp_device *ispdev = params_vdev->dev;
3471 struct rkisp_isp_params_val_v3x *priv_val;
3472 u32 value, bay3d_ctrl;
3473
3474 priv_val = (struct rkisp_isp_params_val_v3x *)params_vdev->priv_val;
3475 bay3d_ctrl = isp3_param_read_cache(params_vdev, ISP3X_BAY3D_CTRL, id);
3476 if ((en && (bay3d_ctrl & ISP3X_MODULE_EN)) ||
3477 (!en && !(bay3d_ctrl & ISP3X_MODULE_EN)))
3478 return;
3479
3480 if (en) {
3481 if (!priv_val->buf_3dnr_iir[id].mem_priv) {
3482 dev_err(ispdev->dev, "no bay3d buffer available\n");
3483 return;
3484 }
3485
3486 value = priv_val->buf_3dnr_iir[id].size;
3487 isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_IIR_WR_SIZE, id);
3488 value = priv_val->buf_3dnr_iir[id].dma_addr;
3489 isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_IIR_WR_BASE, id);
3490 isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_IIR_RD_BASE, id);
3491
3492 value = priv_val->buf_3dnr_cur[id].size;
3493 isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_CUR_WR_SIZE, id);
3494 value = priv_val->buf_3dnr_cur[id].dma_addr;
3495 isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_CUR_WR_BASE, id);
3496 isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_CUR_RD_BASE, id);
3497
3498 value = priv_val->buf_3dnr_ds[id].size;
3499 isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_DS_WR_SIZE, id);
3500 value = priv_val->buf_3dnr_ds[id].dma_addr;
3501 isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_DS_WR_BASE, id);
3502 isp3_param_write(params_vdev, value, ISP3X_MI_BAY3D_DS_RD_BASE, id);
3503
3504 bay3d_ctrl |= ISP3X_MODULE_EN;
3505 isp3_param_write(params_vdev, bay3d_ctrl, ISP3X_BAY3D_CTRL, id);
3506
3507 value = ISP3X_BAY3D_IIR_WR_AUTO_UPD | ISP3X_BAY3D_CUR_WR_AUTO_UPD |
3508 ISP3X_BAY3D_DS_WR_AUTO_UPD | ISP3X_BAY3D_IIRSELF_UPD |
3509 ISP3X_BAY3D_CURSELF_UPD | ISP3X_BAY3D_DSSELF_UPD |
3510 ISP3X_BAY3D_RDSELF_UPD;
3511 isp3_param_set_bits(params_vdev, MI_WR_CTRL2, value, id);
3512
3513 isp3_param_set_bits(params_vdev, ISP3X_ISP_CTRL1, ISP3X_RAW3D_FST_FRAME, id);
3514 } else {
3515 bay3d_ctrl &= ~ISP3X_MODULE_EN;
3516 isp3_param_write(params_vdev, bay3d_ctrl, ISP3X_BAY3D_CTRL, id);
3517 isp3_param_clear_bits(params_vdev, ISP3X_GAIN_CTRL, BIT(4), id);
3518 }
3519 }
3520
3521 static void
isp_gain_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp3x_gain_cfg * arg,u32 id)3522 isp_gain_config(struct rkisp_isp_params_vdev *params_vdev,
3523 const struct isp3x_gain_cfg *arg, u32 id)
3524 {
3525 u32 val;
3526
3527 val = arg->g0 & 0x3ffff;
3528 isp3_param_write(params_vdev, val, ISP3X_GAIN_G0, id);
3529 val = ISP_PACK_2SHORT(arg->g1, arg->g2);
3530 isp3_param_write(params_vdev, val, ISP3X_GAIN_G1_G2, id);
3531 }
3532
3533 static void
isp_gain_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)3534 isp_gain_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
3535 {
3536 struct rkisp_isp_params_val_v3x *priv_val =
3537 (struct rkisp_isp_params_val_v3x *)params_vdev->priv_val;
3538 u32 val = isp3_param_read_cache(params_vdev, ISP3X_LDCH_STS, id);
3539
3540 /* gain will affect ldch, no support for ldch and gain enable */
3541 if (val & ISP3X_MODULE_EN && en)
3542 return;
3543
3544 val = 0;
3545 if (en) {
3546 val |= priv_val->lut3d_en << 20 |
3547 priv_val->dhaz_en << 16 |
3548 priv_val->drc_en << 12 |
3549 priv_val->lsc_en << 8 |
3550 priv_val->bay3d_en << 4;
3551 if (isp3_param_read(params_vdev, ISP3X_HDRMGE_CTRL, id) & BIT(0))
3552 val |= BIT(1);
3553 if (val)
3554 val |= ISP3X_MODULE_EN;
3555 }
3556 isp3_param_write(params_vdev, val, ISP3X_GAIN_CTRL, id);
3557 }
3558
3559 static void
isp_cac_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp3x_cac_cfg * arg,u32 id)3560 isp_cac_config(struct rkisp_isp_params_vdev *params_vdev,
3561 const struct isp3x_cac_cfg *arg, u32 id)
3562 {
3563 struct rkisp_device *dev = params_vdev->dev;
3564 struct rkisp_isp_params_val_v3x *priv_val;
3565 struct isp2x_mesh_head *head;
3566 u32 i, val, ctrl;
3567
3568 priv_val = (struct rkisp_isp_params_val_v3x *)params_vdev->priv_val;
3569
3570 ctrl = isp3_param_read(params_vdev, ISP3X_CAC_CTRL, id);
3571 ctrl &= ISP3X_CAC_EN;
3572 ctrl |= (arg->bypass_en & 0x1) << 1 | (arg->center_en & 0x1) << 3;
3573
3574 val = (arg->psf_sft_bit & 0xff) |
3575 (arg->cfg_num & 0x7ff) << 8;
3576 isp3_param_write(params_vdev, val, ISP3X_CAC_PSF_PARA, id);
3577
3578 val = ISP_PACK_2SHORT(arg->center_width, arg->center_height);
3579 isp3_param_write(params_vdev, val, ISP3X_CAC_STRENGTH_CENTER, id);
3580
3581 for (i = 0; i < ISP3X_CAC_STRENGTH_NUM / 2; i++) {
3582 val = ISP_PACK_2SHORT(arg->strength[2 * i], arg->strength[2 * i + 1]);
3583 isp3_param_write(params_vdev, val, ISP3X_CAC_STRENGTH0 + i * 4, id);
3584 }
3585
3586 /* two buf, buf0 for no bigmode, buf1 for bigmode */
3587 i = 0;
3588 if (priv_val->is_bigmode)
3589 i = 1;
3590 head = (struct isp2x_mesh_head *)priv_val->buf_cac[id][i].vaddr;
3591 rkisp_prepare_buffer(dev, &priv_val->buf_cac[id][i]);
3592 val = priv_val->buf_cac[id][i].dma_addr + head->data_oft;
3593 isp3_param_write(params_vdev, val, ISP3X_MI_LUT_CAC_RD_BASE, id);
3594 isp3_param_write(params_vdev, arg->hsize, ISP3X_MI_LUT_CAC_RD_H_WSIZE, id);
3595 isp3_param_write(params_vdev, arg->vsize, ISP3X_MI_LUT_CAC_RD_V_SIZE, id);
3596 if (ctrl & ISP3X_CAC_EN)
3597 ctrl |= ISP3X_CAC_LUT_EN;
3598 isp3_param_write(params_vdev, ctrl, ISP3X_CAC_CTRL, id);
3599 }
3600
3601 static void
isp_cac_enable(struct rkisp_isp_params_vdev * params_vdev,bool en,u32 id)3602 isp_cac_enable(struct rkisp_isp_params_vdev *params_vdev, bool en, u32 id)
3603 {
3604 u32 val;
3605
3606 val = isp3_param_read(params_vdev, ISP3X_CAC_CTRL, id);
3607 val &= ~ISP3X_CAC_EN;
3608 if (en)
3609 val |= ISP3X_CAC_EN | ISP3X_CAC_LUT_EN;
3610 isp3_param_write(params_vdev, val, ISP3X_CAC_CTRL, id);
3611 }
3612
3613 static void
isp_csm_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp21_csm_cfg * arg,u32 id)3614 isp_csm_config(struct rkisp_isp_params_vdev *params_vdev,
3615 const struct isp21_csm_cfg *arg, u32 id)
3616 {
3617 u32 i, val, eff_ctrl, cproc_ctrl;
3618
3619 for (i = 0; i < ISP3X_CSM_COEFF_NUM; i++) {
3620 if (i == 0)
3621 val = (arg->csm_y_offset & 0x3f) << 24 |
3622 (arg->csm_c_offset & 0xff) << 16 |
3623 (arg->csm_coeff[i] & 0x1ff);
3624 else
3625 val = arg->csm_coeff[i] & 0x1ff;
3626 isp3_param_write(params_vdev, val, ISP3X_ISP_CC_COEFF_0 + i * 4, id);
3627 }
3628
3629 val = CIF_ISP_CTRL_ISP_CSM_Y_FULL_ENA | CIF_ISP_CTRL_ISP_CSM_C_FULL_ENA;
3630 if (arg->csm_full_range) {
3631 params_vdev->quantization = V4L2_QUANTIZATION_FULL_RANGE;
3632 isp3_param_set_bits(params_vdev, ISP3X_ISP_CTRL0, val, id);
3633 } else {
3634 params_vdev->quantization = V4L2_QUANTIZATION_LIM_RANGE;
3635 isp3_param_clear_bits(params_vdev, ISP3X_ISP_CTRL0, val, id);
3636 }
3637
3638 eff_ctrl = isp3_param_read(params_vdev, ISP3X_IMG_EFF_CTRL, id);
3639 if (eff_ctrl & CIF_IMG_EFF_CTRL_ENABLE) {
3640 if (arg->csm_full_range)
3641 eff_ctrl |= CIF_IMG_EFF_CTRL_YCBCR_FULL;
3642 else
3643 eff_ctrl &= ~CIF_IMG_EFF_CTRL_YCBCR_FULL;
3644 isp3_param_write(params_vdev, eff_ctrl, ISP3X_IMG_EFF_CTRL, id);
3645 }
3646
3647 cproc_ctrl = isp3_param_read(params_vdev, ISP3X_CPROC_CTRL, id);
3648 if (cproc_ctrl & CIF_C_PROC_CTR_ENABLE) {
3649 val = CIF_C_PROC_YOUT_FULL | CIF_C_PROC_YIN_FULL | CIF_C_PROC_COUT_FULL;
3650 if (eff_ctrl & CIF_IMG_EFF_CTRL_ENABLE || !arg->csm_full_range)
3651 cproc_ctrl &= ~val;
3652 else
3653 cproc_ctrl |= val;
3654 isp3_param_write(params_vdev, cproc_ctrl, ISP3X_CPROC_CTRL, id);
3655 }
3656 }
3657
3658 struct rkisp_isp_params_ops_v3x isp_params_ops_v3x = {
3659 .dpcc_config = isp_dpcc_config,
3660 .dpcc_enable = isp_dpcc_enable,
3661 .bls_config = isp_bls_config,
3662 .bls_enable = isp_bls_enable,
3663 .sdg_config = isp_sdg_config,
3664 .sdg_enable = isp_sdg_enable,
3665 .lsc_config = isp_lsc_config,
3666 .lsc_enable = isp_lsc_enable,
3667 .awbgain_config = isp_awbgain_config,
3668 .awbgain_enable = isp_awbgain_enable,
3669 .debayer_config = isp_debayer_config,
3670 .debayer_enable = isp_debayer_enable,
3671 .ccm_config = isp_ccm_config,
3672 .ccm_enable = isp_ccm_enable,
3673 .goc_config = isp_goc_config,
3674 .goc_enable = isp_goc_enable,
3675 .csm_config = isp_csm_config,
3676 .cproc_config = isp_cproc_config,
3677 .cproc_enable = isp_cproc_enable,
3678 .ie_config = isp_ie_config,
3679 .ie_enable = isp_ie_enable,
3680 .rawaf_config = isp_rawaf_config,
3681 .rawaf_enable = isp_rawaf_enable,
3682 .rawae0_config = isp_rawaelite_config,
3683 .rawae0_enable = isp_rawaelite_enable,
3684 .rawae1_config = isp_rawae1_config,
3685 .rawae1_enable = isp_rawae1_enable,
3686 .rawae2_config = isp_rawae2_config,
3687 .rawae2_enable = isp_rawae2_enable,
3688 .rawae3_config = isp_rawae3_config,
3689 .rawae3_enable = isp_rawae3_enable,
3690 .rawawb_config = isp_rawawb_config,
3691 .rawawb_enable = isp_rawawb_enable,
3692 .rawhst0_config = isp_rawhstlite_config,
3693 .rawhst0_enable = isp_rawhstlite_enable,
3694 .rawhst1_config = isp_rawhst1_config,
3695 .rawhst1_enable = isp_rawhst1_enable,
3696 .rawhst2_config = isp_rawhst2_config,
3697 .rawhst2_enable = isp_rawhst2_enable,
3698 .rawhst3_config = isp_rawhst3_config,
3699 .rawhst3_enable = isp_rawhst3_enable,
3700 .hdrmge_config = isp_hdrmge_config,
3701 .hdrmge_enable = isp_hdrmge_enable,
3702 .hdrdrc_config = isp_hdrdrc_config,
3703 .hdrdrc_enable = isp_hdrdrc_enable,
3704 .gic_config = isp_gic_config,
3705 .gic_enable = isp_gic_enable,
3706 .dhaz_config = isp_dhaz_config,
3707 .dhaz_enable = isp_dhaz_enable,
3708 .isp3dlut_config = isp_3dlut_config,
3709 .isp3dlut_enable = isp_3dlut_enable,
3710 .ldch_config = isp_ldch_config,
3711 .ldch_enable = isp_ldch_enable,
3712 .ynr_config = isp_ynr_config,
3713 .ynr_enable = isp_ynr_enable,
3714 .cnr_config = isp_cnr_config,
3715 .cnr_enable = isp_cnr_enable,
3716 .sharp_config = isp_sharp_config,
3717 .sharp_enable = isp_sharp_enable,
3718 .baynr_config = isp_baynr_config,
3719 .baynr_enable = isp_baynr_enable,
3720 .bay3d_config = isp_bay3d_config,
3721 .bay3d_enable = isp_bay3d_enable,
3722 .gain_config = isp_gain_config,
3723 .gain_enable = isp_gain_enable,
3724 .cac_config = isp_cac_config,
3725 .cac_enable = isp_cac_enable,
3726 };
3727
3728 static __maybe_unused
__isp_isr_other_config(struct rkisp_isp_params_vdev * params_vdev,const struct isp3x_isp_params_cfg * new_params,enum rkisp_params_type type,enum isp3x_unite_id id)3729 void __isp_isr_other_config(struct rkisp_isp_params_vdev *params_vdev,
3730 const struct isp3x_isp_params_cfg *new_params,
3731 enum rkisp_params_type type, enum isp3x_unite_id id)
3732 {
3733 struct rkisp_isp_params_ops_v3x *ops =
3734 (struct rkisp_isp_params_ops_v3x *)params_vdev->priv_ops;
3735 u64 module_cfg_update = new_params->module_cfg_update;
3736
3737 if (type == RKISP_PARAMS_SHD) {
3738 if ((module_cfg_update & ISP3X_MODULE_HDRMGE))
3739 ops->hdrmge_config(params_vdev, &new_params->others.hdrmge_cfg, type, id);
3740
3741 if ((module_cfg_update & ISP3X_MODULE_DRC))
3742 ops->hdrdrc_config(params_vdev, &new_params->others.drc_cfg, type, id);
3743 return;
3744 }
3745
3746 v4l2_dbg(4, rkisp_debug, ¶ms_vdev->dev->v4l2_dev,
3747 "%s id:%d seq:%d module_cfg_update:0x%llx\n",
3748 __func__, id, new_params->frame_id, module_cfg_update);
3749
3750 if ((module_cfg_update & ISP3X_MODULE_LSC))
3751 ops->lsc_config(params_vdev, &new_params->others.lsc_cfg, id);
3752
3753 if ((module_cfg_update & ISP3X_MODULE_DPCC))
3754 ops->dpcc_config(params_vdev, &new_params->others.dpcc_cfg, id);
3755
3756 if ((module_cfg_update & ISP3X_MODULE_BLS))
3757 ops->bls_config(params_vdev, &new_params->others.bls_cfg, id);
3758
3759 if ((module_cfg_update & ISP3X_MODULE_SDG))
3760 ops->sdg_config(params_vdev, &new_params->others.sdg_cfg, id);
3761
3762 if ((module_cfg_update & ISP3X_MODULE_AWB_GAIN))
3763 ops->awbgain_config(params_vdev, &new_params->others.awb_gain_cfg, id);
3764
3765 if ((module_cfg_update & ISP3X_MODULE_DEBAYER))
3766 ops->debayer_config(params_vdev, &new_params->others.debayer_cfg, id);
3767
3768 if ((module_cfg_update & ISP3X_MODULE_CCM))
3769 ops->ccm_config(params_vdev, &new_params->others.ccm_cfg, id);
3770
3771 if ((module_cfg_update & ISP3X_MODULE_GOC))
3772 ops->goc_config(params_vdev, &new_params->others.gammaout_cfg, id);
3773
3774 if ((module_cfg_update & ISP3X_MODULE_CSM))
3775 ops->csm_config(params_vdev, &new_params->others.csm_cfg, id);
3776
3777 if ((module_cfg_update & ISP3X_MODULE_CPROC))
3778 ops->cproc_config(params_vdev, &new_params->others.cproc_cfg, id);
3779
3780 if ((module_cfg_update & ISP3X_MODULE_IE))
3781 ops->ie_config(params_vdev, &new_params->others.ie_cfg, id);
3782
3783 if ((module_cfg_update & ISP3X_MODULE_HDRMGE))
3784 ops->hdrmge_config(params_vdev, &new_params->others.hdrmge_cfg, type, id);
3785
3786 if ((module_cfg_update & ISP3X_MODULE_DRC))
3787 ops->hdrdrc_config(params_vdev, &new_params->others.drc_cfg, type, id);
3788
3789 if ((module_cfg_update & ISP3X_MODULE_GIC))
3790 ops->gic_config(params_vdev, &new_params->others.gic_cfg, id);
3791
3792 if ((module_cfg_update & ISP3X_MODULE_DHAZ))
3793 ops->dhaz_config(params_vdev, &new_params->others.dhaz_cfg, id);
3794
3795 if ((module_cfg_update & ISP3X_MODULE_3DLUT))
3796 ops->isp3dlut_config(params_vdev, &new_params->others.isp3dlut_cfg, id);
3797
3798 if ((module_cfg_update & ISP3X_MODULE_LDCH))
3799 ops->ldch_config(params_vdev, &new_params->others.ldch_cfg, id);
3800
3801 if ((module_cfg_update & ISP3X_MODULE_YNR))
3802 ops->ynr_config(params_vdev, &new_params->others.ynr_cfg, id);
3803
3804 if ((module_cfg_update & ISP3X_MODULE_CNR))
3805 ops->cnr_config(params_vdev, &new_params->others.cnr_cfg, id);
3806
3807 if ((module_cfg_update & ISP3X_MODULE_SHARP))
3808 ops->sharp_config(params_vdev, &new_params->others.sharp_cfg, id);
3809
3810 if ((module_cfg_update & ISP3X_MODULE_BAYNR))
3811 ops->baynr_config(params_vdev, &new_params->others.baynr_cfg, id);
3812
3813 if ((module_cfg_update & ISP3X_MODULE_BAY3D))
3814 ops->bay3d_config(params_vdev, &new_params->others.bay3d_cfg, id);
3815
3816 if ((module_cfg_update & ISP3X_MODULE_CAC))
3817 ops->cac_config(params_vdev, &new_params->others.cac_cfg, id);
3818
3819 if ((module_cfg_update & ISP3X_MODULE_GAIN))
3820 ops->gain_config(params_vdev, &new_params->others.gain_cfg, id);
3821 }
3822
3823 static __maybe_unused
__isp_isr_other_en(struct rkisp_isp_params_vdev * params_vdev,const struct isp3x_isp_params_cfg * new_params,enum rkisp_params_type type,enum isp3x_unite_id id)3824 void __isp_isr_other_en(struct rkisp_isp_params_vdev *params_vdev,
3825 const struct isp3x_isp_params_cfg *new_params,
3826 enum rkisp_params_type type, enum isp3x_unite_id id)
3827 {
3828 struct rkisp_isp_params_ops_v3x *ops =
3829 (struct rkisp_isp_params_ops_v3x *)params_vdev->priv_ops;
3830 struct rkisp_isp_params_val_v3x *priv_val =
3831 (struct rkisp_isp_params_val_v3x *)params_vdev->priv_val;
3832 u64 module_en_update = new_params->module_en_update;
3833 u64 module_ens = new_params->module_ens;
3834 u32 gain_ctrl, cnr_ctrl, val;
3835
3836 if (type == RKISP_PARAMS_SHD)
3837 return;
3838
3839 v4l2_dbg(4, rkisp_debug, ¶ms_vdev->dev->v4l2_dev,
3840 "%s id:%d seq:%d module_en_update:0x%llx module_ens:0x%llx\n",
3841 __func__, id, new_params->frame_id, module_en_update, module_ens);
3842
3843 if (module_en_update & ISP3X_MODULE_DPCC)
3844 ops->dpcc_enable(params_vdev, !!(module_ens & ISP3X_MODULE_DPCC), id);
3845
3846 if (module_en_update & ISP3X_MODULE_BLS)
3847 ops->bls_enable(params_vdev, !!(module_ens & ISP3X_MODULE_BLS), id);
3848
3849 if (module_en_update & ISP3X_MODULE_SDG)
3850 ops->sdg_enable(params_vdev, !!(module_ens & ISP3X_MODULE_SDG), id);
3851
3852 if (module_en_update & ISP3X_MODULE_LSC) {
3853 ops->lsc_enable(params_vdev, !!(module_ens & ISP3X_MODULE_LSC), id);
3854 priv_val->lsc_en = !!(module_ens & ISP3X_MODULE_LSC);
3855 }
3856
3857 if (module_en_update & ISP3X_MODULE_AWB_GAIN)
3858 ops->awbgain_enable(params_vdev, !!(module_ens & ISP3X_MODULE_AWB_GAIN), id);
3859
3860 if (module_en_update & ISP3X_MODULE_DEBAYER)
3861 ops->debayer_enable(params_vdev, !!(module_ens & ISP3X_MODULE_DEBAYER), id);
3862
3863 if (module_en_update & ISP3X_MODULE_CCM)
3864 ops->ccm_enable(params_vdev, !!(module_ens & ISP3X_MODULE_CCM), id);
3865
3866 if (module_en_update & ISP3X_MODULE_GOC)
3867 ops->goc_enable(params_vdev, !!(module_ens & ISP3X_MODULE_GOC), id);
3868
3869 if (module_en_update & ISP3X_MODULE_CPROC)
3870 ops->cproc_enable(params_vdev, !!(module_ens & ISP3X_MODULE_CPROC), id);
3871
3872 if (module_en_update & ISP3X_MODULE_IE)
3873 ops->ie_enable(params_vdev, !!(module_ens & ISP3X_MODULE_IE), id);
3874
3875 if (module_en_update & ISP3X_MODULE_HDRMGE) {
3876 ops->hdrmge_enable(params_vdev, !!(module_ens & ISP3X_MODULE_HDRMGE), id);
3877 priv_val->mge_en = !!(module_ens & ISP3X_MODULE_HDRMGE);
3878 }
3879
3880 if (module_en_update & ISP3X_MODULE_DRC) {
3881 ops->hdrdrc_enable(params_vdev, !!(module_ens & ISP3X_MODULE_DRC), id);
3882 priv_val->drc_en = !!(module_ens & ISP3X_MODULE_DRC);
3883 }
3884
3885 if (module_en_update & ISP3X_MODULE_GIC)
3886 ops->gic_enable(params_vdev, !!(module_ens & ISP3X_MODULE_GIC), id);
3887
3888 if (module_en_update & ISP3X_MODULE_DHAZ) {
3889 ops->dhaz_enable(params_vdev, !!(module_ens & ISP3X_MODULE_DHAZ), id);
3890 priv_val->dhaz_en = !!(module_ens & ISP3X_MODULE_DHAZ);
3891 }
3892
3893 if (module_en_update & ISP3X_MODULE_3DLUT) {
3894 ops->isp3dlut_enable(params_vdev, !!(module_ens & ISP3X_MODULE_3DLUT), id);
3895 priv_val->lut3d_en = !!(module_ens & ISP3X_MODULE_3DLUT);
3896 }
3897
3898 if (module_en_update & ISP3X_MODULE_LDCH)
3899 ops->ldch_enable(params_vdev, !!(module_ens & ISP3X_MODULE_LDCH), id);
3900
3901 if (module_en_update & ISP3X_MODULE_YNR)
3902 ops->ynr_enable(params_vdev, !!(module_ens & ISP3X_MODULE_YNR), id);
3903
3904 if (module_en_update & ISP3X_MODULE_CNR)
3905 ops->cnr_enable(params_vdev, !!(module_ens & ISP3X_MODULE_CNR), id);
3906
3907 if (module_en_update & ISP3X_MODULE_SHARP)
3908 ops->sharp_enable(params_vdev, !!(module_ens & ISP3X_MODULE_SHARP), id);
3909
3910 if (module_en_update & ISP3X_MODULE_BAYNR)
3911 ops->baynr_enable(params_vdev, !!(module_ens & ISP3X_MODULE_BAYNR), id);
3912
3913 if (module_en_update & ISP3X_MODULE_BAY3D) {
3914 ops->bay3d_enable(params_vdev, !!(module_ens & ISP3X_MODULE_BAY3D), id);
3915 priv_val->bay3d_en = !!(module_ens & ISP3X_MODULE_BAY3D);
3916 }
3917
3918 if (module_en_update & ISP3X_MODULE_CAC)
3919 ops->cac_enable(params_vdev, !!(module_ens & ISP3X_MODULE_CAC), id);
3920
3921 if (module_en_update & ISP3X_MODULE_GAIN)
3922 ops->gain_enable(params_vdev, !!(module_ens & ISP3X_MODULE_GAIN), id);
3923
3924 /* gain disable, using global gain for cnr */
3925 gain_ctrl = isp3_param_read_cache(params_vdev, ISP3X_GAIN_CTRL, id);
3926 cnr_ctrl = isp3_param_read_cache(params_vdev, ISP3X_CNR_CTRL, id);
3927 if (!(gain_ctrl & ISP3X_MODULE_EN) && cnr_ctrl & ISP3X_MODULE_EN) {
3928 cnr_ctrl |= BIT(1);
3929 isp3_param_write(params_vdev, cnr_ctrl, ISP3X_CNR_CTRL, id);
3930 val = isp3_param_read(params_vdev, ISP3X_CNR_EXGAIN, id) & 0x3ff;
3931 isp3_param_write(params_vdev, val | 0x8000, ISP3X_CNR_EXGAIN, id);
3932 }
3933 }
3934
3935 static __maybe_unused
__isp_isr_meas_config(struct rkisp_isp_params_vdev * params_vdev,struct isp3x_isp_params_cfg * new_params,enum rkisp_params_type type,enum isp3x_unite_id id)3936 void __isp_isr_meas_config(struct rkisp_isp_params_vdev *params_vdev,
3937 struct isp3x_isp_params_cfg *new_params,
3938 enum rkisp_params_type type, enum isp3x_unite_id id)
3939 {
3940 struct rkisp_isp_params_ops_v3x *ops =
3941 (struct rkisp_isp_params_ops_v3x *)params_vdev->priv_ops;
3942 u64 module_cfg_update = new_params->module_cfg_update;
3943
3944 if (type == RKISP_PARAMS_SHD)
3945 return;
3946
3947 v4l2_dbg(4, rkisp_debug, ¶ms_vdev->dev->v4l2_dev,
3948 "%s id:%d seq:%d module_cfg_update:0x%llx\n",
3949 __func__, id, new_params->frame_id, module_cfg_update);
3950
3951 if ((module_cfg_update & ISP3X_MODULE_RAWAF))
3952 ops->rawaf_config(params_vdev, &new_params->meas.rawaf, id);
3953
3954 if ((module_cfg_update & ISP3X_MODULE_RAWAE0))
3955 ops->rawae0_config(params_vdev, &new_params->meas.rawae0, id);
3956
3957 if ((module_cfg_update & ISP3X_MODULE_RAWAE1))
3958 ops->rawae1_config(params_vdev, &new_params->meas.rawae1, id);
3959
3960 if ((module_cfg_update & ISP3X_MODULE_RAWAE2))
3961 ops->rawae2_config(params_vdev, &new_params->meas.rawae2, id);
3962
3963 if ((module_cfg_update & ISP3X_MODULE_RAWAE3) && !params_vdev->afaemode_en)
3964 ops->rawae3_config(params_vdev, &new_params->meas.rawae3, id);
3965
3966 if ((module_cfg_update & ISP3X_MODULE_RAWHIST0))
3967 ops->rawhst0_config(params_vdev, &new_params->meas.rawhist0, id);
3968
3969 if ((module_cfg_update & ISP3X_MODULE_RAWHIST1))
3970 ops->rawhst1_config(params_vdev, &new_params->meas.rawhist1, id);
3971
3972 if ((module_cfg_update & ISP3X_MODULE_RAWHIST2))
3973 ops->rawhst2_config(params_vdev, &new_params->meas.rawhist2, id);
3974
3975 if ((module_cfg_update & ISP3X_MODULE_RAWHIST3))
3976 ops->rawhst3_config(params_vdev, &new_params->meas.rawhist3, id);
3977
3978 if ((module_cfg_update & ISP3X_MODULE_RAWAWB))
3979 ops->rawawb_config(params_vdev, &new_params->meas.rawawb, id);
3980 }
3981
3982 static __maybe_unused
__isp_isr_meas_en(struct rkisp_isp_params_vdev * params_vdev,struct isp3x_isp_params_cfg * new_params,enum rkisp_params_type type,enum isp3x_unite_id id)3983 void __isp_isr_meas_en(struct rkisp_isp_params_vdev *params_vdev,
3984 struct isp3x_isp_params_cfg *new_params,
3985 enum rkisp_params_type type, enum isp3x_unite_id id)
3986 {
3987 struct rkisp_isp_params_ops_v3x *ops =
3988 (struct rkisp_isp_params_ops_v3x *)params_vdev->priv_ops;
3989 u64 module_en_update = new_params->module_en_update;
3990 u64 module_ens = new_params->module_ens;
3991
3992 if (type == RKISP_PARAMS_SHD)
3993 return;
3994
3995 v4l2_dbg(4, rkisp_debug, ¶ms_vdev->dev->v4l2_dev,
3996 "%s id:%d seq:%d module_en_update:0x%llx module_ens:0x%llx\n",
3997 __func__, id, new_params->frame_id, module_en_update, module_ens);
3998
3999 if (module_en_update & ISP3X_MODULE_RAWAF)
4000 ops->rawaf_enable(params_vdev, !!(module_ens & ISP3X_MODULE_RAWAF), id);
4001
4002 if (module_en_update & ISP3X_MODULE_RAWAE0)
4003 ops->rawae0_enable(params_vdev, !!(module_ens & ISP3X_MODULE_RAWAE0), id);
4004
4005 if (module_en_update & ISP3X_MODULE_RAWAE1)
4006 ops->rawae1_enable(params_vdev, !!(module_ens & ISP3X_MODULE_RAWAE1), id);
4007
4008 if (module_en_update & ISP3X_MODULE_RAWAE2)
4009 ops->rawae2_enable(params_vdev, !!(module_ens & ISP3X_MODULE_RAWAE2), id);
4010
4011 if ((module_en_update & ISP3X_MODULE_RAWAE3) && !params_vdev->afaemode_en)
4012 ops->rawae3_enable(params_vdev, !!(module_ens & ISP3X_MODULE_RAWAE3), id);
4013
4014 if (module_en_update & ISP3X_MODULE_RAWHIST0)
4015 ops->rawhst0_enable(params_vdev, !!(module_ens & ISP3X_MODULE_RAWHIST0), id);
4016
4017 if (module_en_update & ISP3X_MODULE_RAWHIST1)
4018 ops->rawhst1_enable(params_vdev, !!(module_ens & ISP3X_MODULE_RAWHIST1), id);
4019
4020 if (module_en_update & ISP3X_MODULE_RAWHIST2)
4021 ops->rawhst2_enable(params_vdev, !!(module_ens & ISP3X_MODULE_RAWHIST2), id);
4022
4023 if (module_en_update & ISP3X_MODULE_RAWHIST3)
4024 ops->rawhst3_enable(params_vdev, !!(module_ens & ISP3X_MODULE_RAWHIST3), id);
4025
4026 if (module_en_update & ISP3X_MODULE_RAWAWB)
4027 ops->rawawb_enable(params_vdev, !!(module_ens & ISP3X_MODULE_RAWAWB), id);
4028 }
4029
4030 static __maybe_unused
__isp_config_hdrshd(struct rkisp_isp_params_vdev * params_vdev)4031 void __isp_config_hdrshd(struct rkisp_isp_params_vdev *params_vdev)
4032 {
4033 struct rkisp_isp_params_ops_v3x *ops =
4034 (struct rkisp_isp_params_ops_v3x *)params_vdev->priv_ops;
4035 struct rkisp_isp_params_val_v3x *priv_val =
4036 (struct rkisp_isp_params_val_v3x *)params_vdev->priv_val;
4037
4038 ops->hdrmge_config(params_vdev, &priv_val->last_hdrmge, RKISP_PARAMS_SHD, 0);
4039 ops->hdrdrc_config(params_vdev, &priv_val->last_hdrdrc, RKISP_PARAMS_SHD, 0);
4040 }
4041
4042 static
rkisp_params_cfgsram_v3x(struct rkisp_isp_params_vdev * params_vdev)4043 void rkisp_params_cfgsram_v3x(struct rkisp_isp_params_vdev *params_vdev)
4044 {
4045 struct isp3x_isp_params_cfg *params = params_vdev->isp3x_params;
4046
4047 isp_lsc_matrix_cfg_sram(params_vdev, ¶ms->others.lsc_cfg, true, 0);
4048 isp_rawhstbig_cfg_sram(params_vdev, ¶ms->meas.rawhist1, 1, true, 0);
4049 isp_rawhstbig_cfg_sram(params_vdev, ¶ms->meas.rawhist2, 2, true, 0);
4050 isp_rawhstbig_cfg_sram(params_vdev, ¶ms->meas.rawhist3, 0, true, 0);
4051 if (params_vdev->dev->hw_dev->is_unite) {
4052 params++;
4053 isp_lsc_matrix_cfg_sram(params_vdev, ¶ms->others.lsc_cfg, true, 1);
4054 isp_rawhstbig_cfg_sram(params_vdev, ¶ms->meas.rawhist1, 1, true, 1);
4055 isp_rawhstbig_cfg_sram(params_vdev, ¶ms->meas.rawhist2, 2, true, 1);
4056 isp_rawhstbig_cfg_sram(params_vdev, ¶ms->meas.rawhist3, 0, true, 1);
4057 }
4058 }
4059
4060 static int
rkisp_alloc_internal_buf(struct rkisp_isp_params_vdev * params_vdev,const struct isp3x_isp_params_cfg * new_params)4061 rkisp_alloc_internal_buf(struct rkisp_isp_params_vdev *params_vdev,
4062 const struct isp3x_isp_params_cfg *new_params)
4063 {
4064 struct rkisp_device *ispdev = params_vdev->dev;
4065 struct rkisp_isp_subdev *isp_sdev = &ispdev->isp_sdev;
4066 struct rkisp_isp_params_val_v3x *priv_val;
4067 u64 module_en_update, module_ens;
4068 int ret, w, h, size, id, i;
4069
4070 priv_val = (struct rkisp_isp_params_val_v3x *)params_vdev->priv_val;
4071 module_en_update = new_params->module_en_update;
4072 module_ens = new_params->module_ens;
4073
4074 for (id = 0; id <= ispdev->hw_dev->is_unite; id++) {
4075 priv_val->buf_3dlut_idx[id] = 0;
4076 for (i = 0; i < ISP3X_3DLUT_BUF_NUM; i++) {
4077 priv_val->buf_3dlut[id][i].is_need_vaddr = true;
4078 priv_val->buf_3dlut[id][i].size = ISP3X_3DLUT_BUF_SIZE;
4079 ret = rkisp_alloc_buffer(ispdev, &priv_val->buf_3dlut[id][i]);
4080 if (ret) {
4081 dev_err(ispdev->dev, "alloc 3dlut buf fail:%d\n", ret);
4082 goto err_3dlut;
4083 }
4084 }
4085
4086 priv_val->buf_lsclut_idx[id] = 0;
4087 for (i = 0; i < ISP3X_LSC_LUT_BUF_NUM; i++) {
4088 priv_val->buf_lsclut[id][i].is_need_vaddr = true;
4089 priv_val->buf_lsclut[id][i].size = ISP3X_LSC_LUT_BUF_SIZE;
4090 ret = rkisp_alloc_buffer(ispdev, &priv_val->buf_lsclut[id][i]);
4091 if (ret) {
4092 dev_err(ispdev->dev, "alloc lsclut buf fail:%d\n", ret);
4093 goto err_lsclut;
4094 }
4095 }
4096 }
4097
4098 if ((module_en_update & ISP3X_MODULE_BAY3D) &&
4099 (module_ens & ISP3X_MODULE_BAY3D)) {
4100 w = ALIGN(isp_sdev->in_crop.width, 16);
4101 h = ALIGN(isp_sdev->in_crop.height, 16);
4102 if (ispdev->hw_dev->is_unite)
4103 w = ALIGN(isp_sdev->in_crop.width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL, 16);
4104
4105 for (id = 0; id <= ispdev->hw_dev->is_unite; id++) {
4106 size = ALIGN((w + w / 8) * h * 2, 16);
4107
4108 priv_val->buf_3dnr_iir[id].size = size;
4109 ret = rkisp_alloc_buffer(ispdev, &priv_val->buf_3dnr_iir[id]);
4110 if (ret) {
4111 dev_err(ispdev->dev, "alloc bay3d iir buf fail:%d\n", ret);
4112 goto err_3dnr;
4113 }
4114
4115 priv_val->buf_3dnr_cur[id].size = size;
4116 ret = rkisp_alloc_buffer(ispdev, &priv_val->buf_3dnr_cur[id]);
4117 if (ret) {
4118 rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_iir[id]);
4119 dev_err(ispdev->dev, "alloc bay3d cur buf fail:%d\n", ret);
4120 goto err_3dnr;
4121 }
4122
4123 size = 2 * ALIGN(w * h / 64, 16);
4124 priv_val->buf_3dnr_ds[id].size = size;
4125 ret = rkisp_alloc_buffer(ispdev, &priv_val->buf_3dnr_ds[id]);
4126 if (ret) {
4127 rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_iir[id]);
4128 rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_cur[id]);
4129 dev_err(ispdev->dev, "alloc bay3d ds buf fail:%d\n", ret);
4130 goto err_3dnr;
4131 }
4132 }
4133 }
4134 return 0;
4135 err_3dnr:
4136 for (id -= 1; id >= 0; id--) {
4137 rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_iir[id]);
4138 rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_cur[id]);
4139 rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_ds[id]);
4140 }
4141 id = ispdev->hw_dev->is_unite ? 1 : 0;
4142 i = ISP3X_LSC_LUT_BUF_NUM;
4143 err_lsclut:
4144 for (; id >= 0; id--) {
4145 for (i -= 1; i >= 0; i--)
4146 rkisp_free_buffer(ispdev, &priv_val->buf_lsclut[id][i]);
4147 i = ISP3X_LSC_LUT_BUF_NUM;
4148 }
4149 id = ispdev->hw_dev->is_unite ? 1 : 0;
4150 i = ISP3X_3DLUT_BUF_NUM;
4151 err_3dlut:
4152 for (; id >= 0; id--) {
4153 for (i -= 1; i >= 0; i--)
4154 rkisp_free_buffer(ispdev, &priv_val->buf_3dlut[id][i]);
4155 i = ISP3X_3DLUT_BUF_NUM;
4156 }
4157 return ret;
4158 }
4159
4160 /* Not called when the camera active, thus not isr protection. */
4161 static void
rkisp_params_first_cfg_v3x(struct rkisp_isp_params_vdev * params_vdev)4162 rkisp_params_first_cfg_v3x(struct rkisp_isp_params_vdev *params_vdev)
4163 {
4164 struct device *dev = params_vdev->dev->dev;
4165 struct rkisp_isp_params_val_v3x *priv_val =
4166 (struct rkisp_isp_params_val_v3x *)params_vdev->priv_val;
4167 struct rkisp_hw_dev *hw = params_vdev->dev->hw_dev;
4168 struct v4l2_rect *out_crop = ¶ms_vdev->dev->isp_sdev.out_crop;
4169 u32 width = hw->max_in.w ? hw->max_in.w : out_crop->width;
4170 u32 height = hw->max_in.h ? hw->max_in.h : out_crop->height;
4171 u32 size = width * height;
4172 u32 bigmode_max_w, bigmode_max_size;
4173
4174 tasklet_enable(&priv_val->lsc_tasklet);
4175
4176 if (hw->dev_num > 2) {
4177 bigmode_max_w = ISP3X_VIR4_AUTO_BIGMODE_WIDTH;
4178 bigmode_max_size = ISP3X_VIR4_NOBIG_OVERFLOW_SIZE;
4179 if (width > ISP3X_VIR4_MAX_WIDTH || size > ISP3X_VIR4_MAX_SIZE)
4180 dev_err(dev, "%dx%d > max:2560x1536 for %d virtual isp\n",
4181 width, height, hw->dev_num);
4182 } else if (hw->dev_num > 1) {
4183 bigmode_max_w = ISP3X_VIR2_AUTO_BIGMODE_WIDTH;
4184 bigmode_max_size = ISP3X_VIR2_NOBIG_OVERFLOW_SIZE;
4185 if (width > ISP3X_VIR2_MAX_WIDTH || size > ISP3X_VIR2_MAX_SIZE)
4186 dev_err(dev, "%dx%d > max:3840x2160 for %d virtual isp\n",
4187 width, height, hw->dev_num);
4188 } else {
4189 bigmode_max_w = ISP3X_AUTO_BIGMODE_WIDTH;
4190 bigmode_max_size = ISP3X_NOBIG_OVERFLOW_SIZE;
4191 }
4192 rkisp_alloc_internal_buf(params_vdev, params_vdev->isp3x_params);
4193 spin_lock(¶ms_vdev->config_lock);
4194 /* override the default things */
4195 if (!params_vdev->isp3x_params->module_cfg_update &&
4196 !params_vdev->isp3x_params->module_en_update)
4197 dev_warn(dev, "can not get first iq setting in stream on\n");
4198
4199 priv_val->bay3d_en = 0;
4200 priv_val->dhaz_en = 0;
4201 priv_val->drc_en = 0;
4202 priv_val->lsc_en = 0;
4203 priv_val->mge_en = 0;
4204 priv_val->lut3d_en = 0;
4205 priv_val->is_bigmode = 0;
4206 if (hw->is_unite) {
4207 width = width / 2 + RKMOUDLE_UNITE_EXTEND_PIXEL;
4208 size = width * out_crop->height;
4209 if (width > bigmode_max_w || size > bigmode_max_size) {
4210 priv_val->is_bigmode = true;
4211 rkisp_next_set_bits(params_vdev->dev, ISP3X_ISP_CTRL1, 0,
4212 ISP3X_BIGMODE_MANUAL | ISP3X_BIGMODE_FORCE_EN, false);
4213 }
4214 __isp_isr_meas_config(params_vdev, params_vdev->isp3x_params + 1, RKISP_PARAMS_ALL, 1);
4215 __isp_isr_other_config(params_vdev, params_vdev->isp3x_params + 1, RKISP_PARAMS_ALL, 1);
4216 __isp_isr_other_en(params_vdev, params_vdev->isp3x_params + 1, RKISP_PARAMS_ALL, 1);
4217 __isp_isr_meas_en(params_vdev, params_vdev->isp3x_params + 1, RKISP_PARAMS_ALL, 1);
4218 if (width > bigmode_max_w || size > bigmode_max_size) {
4219 priv_val->is_bigmode = true;
4220 rkisp_next_set_bits(params_vdev->dev, ISP3X_ISP_CTRL1, 0,
4221 ISP3X_BIGMODE_MANUAL | ISP3X_BIGMODE_FORCE_EN, false);
4222 }
4223 }
4224 if (width > bigmode_max_w || size > bigmode_max_size) {
4225 priv_val->is_bigmode = true;
4226 rkisp_set_bits(params_vdev->dev, ISP3X_ISP_CTRL1, 0,
4227 ISP3X_BIGMODE_MANUAL | ISP3X_BIGMODE_FORCE_EN, false);
4228 }
4229 __isp_isr_meas_config(params_vdev, params_vdev->isp3x_params, RKISP_PARAMS_ALL, 0);
4230 __isp_isr_other_config(params_vdev, params_vdev->isp3x_params, RKISP_PARAMS_ALL, 0);
4231 __isp_isr_other_en(params_vdev, params_vdev->isp3x_params, RKISP_PARAMS_ALL, 0);
4232 __isp_isr_meas_en(params_vdev, params_vdev->isp3x_params, RKISP_PARAMS_ALL, 0);
4233
4234 priv_val->cur_hdrmge = params_vdev->isp3x_params->others.hdrmge_cfg;
4235 priv_val->cur_hdrdrc = params_vdev->isp3x_params->others.drc_cfg;
4236 priv_val->last_hdrmge = priv_val->cur_hdrmge;
4237 priv_val->last_hdrdrc = priv_val->cur_hdrdrc;
4238 spin_unlock(¶ms_vdev->config_lock);
4239 }
4240
rkisp_save_first_param_v3x(struct rkisp_isp_params_vdev * params_vdev,void * param)4241 static void rkisp_save_first_param_v3x(struct rkisp_isp_params_vdev *params_vdev, void *param)
4242 {
4243 memcpy(params_vdev->isp3x_params, param, params_vdev->vdev_fmt.fmt.meta.buffersize);
4244 }
4245
rkisp_clear_first_param_v3x(struct rkisp_isp_params_vdev * params_vdev)4246 static void rkisp_clear_first_param_v3x(struct rkisp_isp_params_vdev *params_vdev)
4247 {
4248 u32 mult = params_vdev->dev->hw_dev->is_unite ? ISP3_UNITE_MAX : 1;
4249 u32 size = sizeof(struct isp3x_isp_params_cfg) * mult;
4250
4251 memset(params_vdev->isp3x_params, 0, size);
4252 }
4253
rkisp_deinit_mesh_buf(struct rkisp_isp_params_vdev * params_vdev,u64 module_id,u32 id)4254 static void rkisp_deinit_mesh_buf(struct rkisp_isp_params_vdev *params_vdev,
4255 u64 module_id, u32 id)
4256 {
4257 struct rkisp_isp_params_val_v3x *priv_val;
4258 struct rkisp_dummy_buffer *buf;
4259 int i;
4260
4261 priv_val = params_vdev->priv_val;
4262 if (!priv_val)
4263 return;
4264
4265 switch (module_id) {
4266 case ISP3X_MODULE_CAC:
4267 buf = priv_val->buf_cac[id];
4268 break;
4269 case ISP3X_MODULE_LDCH:
4270 default:
4271 buf = priv_val->buf_ldch[id];
4272 break;
4273 }
4274
4275 for (i = 0; i < ISP3X_MESH_BUF_NUM; i++)
4276 rkisp_free_buffer(params_vdev->dev, buf + i);
4277 }
4278
rkisp_init_mesh_buf(struct rkisp_isp_params_vdev * params_vdev,struct rkisp_meshbuf_size * meshsize)4279 static int rkisp_init_mesh_buf(struct rkisp_isp_params_vdev *params_vdev,
4280 struct rkisp_meshbuf_size *meshsize)
4281 {
4282 struct rkisp_device *ispdev = params_vdev->dev;
4283 struct device *dev = ispdev->dev;
4284 struct rkisp_isp_params_val_v3x *priv_val;
4285 struct isp2x_mesh_head *mesh_head;
4286 struct rkisp_dummy_buffer *buf;
4287 u32 mesh_w = meshsize->meas_width;
4288 u32 mesh_h = meshsize->meas_height;
4289 u32 mesh_size, buf_size;
4290 int i, ret, id = meshsize->unite_isp_id;
4291
4292 priv_val = params_vdev->priv_val;
4293 if (!priv_val) {
4294 dev_err(dev, "priv_val is NULL\n");
4295 return -EINVAL;
4296 }
4297
4298 switch (meshsize->module_id) {
4299 case ISP3X_MODULE_CAC:
4300 priv_val->buf_cac_idx[id] = 0;
4301 buf = priv_val->buf_cac[id];
4302 mesh_w = (mesh_w + 62) / 64 * 9;
4303 mesh_h = (mesh_h + 62) / 64 * 2;
4304 mesh_size = mesh_w * 4 * mesh_h;
4305 break;
4306 case ISP3X_MODULE_LDCH:
4307 default:
4308 priv_val->buf_ldch_idx[id] = 0;
4309 buf = priv_val->buf_ldch[id];
4310 mesh_w = ((mesh_w + 15) / 16 + 2) / 2;
4311 mesh_h = (mesh_h + 7) / 8 + 1;
4312 mesh_size = mesh_w * 4 * mesh_h;
4313 break;
4314 }
4315
4316 buf_size = PAGE_ALIGN(mesh_size + ALIGN(sizeof(struct isp2x_mesh_head), 16));
4317 for (i = 0; i < ISP3X_MESH_BUF_NUM; i++) {
4318 buf->is_need_vaddr = true;
4319 buf->is_need_dbuf = true;
4320 buf->is_need_dmafd = true;
4321 buf->size = buf_size;
4322 ret = rkisp_alloc_buffer(params_vdev->dev, buf);
4323 if (ret) {
4324 dev_err(dev, "%s failed\n", __func__);
4325 goto err;
4326 }
4327
4328 mesh_head = (struct isp2x_mesh_head *)buf->vaddr;
4329 mesh_head->stat = MESH_BUF_INIT;
4330 mesh_head->data_oft = ALIGN(sizeof(struct isp2x_mesh_head), 16);
4331 buf++;
4332 }
4333
4334 return 0;
4335 err:
4336 rkisp_deinit_mesh_buf(params_vdev, meshsize->module_id, id);
4337 return -ENOMEM;
4338 }
4339
4340 static void
rkisp_get_param_size_v3x(struct rkisp_isp_params_vdev * params_vdev,unsigned int sizes[])4341 rkisp_get_param_size_v3x(struct rkisp_isp_params_vdev *params_vdev,
4342 unsigned int sizes[])
4343 {
4344 u32 mult = params_vdev->dev->hw_dev->is_unite ? ISP3_UNITE_MAX : 1;
4345
4346 sizes[0] = sizeof(struct isp3x_isp_params_cfg) * mult;
4347 }
4348
4349 static void
rkisp_params_get_meshbuf_inf_v3x(struct rkisp_isp_params_vdev * params_vdev,void * meshbuf_inf)4350 rkisp_params_get_meshbuf_inf_v3x(struct rkisp_isp_params_vdev *params_vdev,
4351 void *meshbuf_inf)
4352 {
4353 struct rkisp_isp_params_val_v3x *priv_val;
4354 struct rkisp_meshbuf_info *meshbuf = meshbuf_inf;
4355 struct rkisp_dummy_buffer *buf;
4356 int i, id = meshbuf->unite_isp_id;
4357
4358 priv_val = params_vdev->priv_val;
4359 switch (meshbuf->module_id) {
4360 case ISP3X_MODULE_CAC:
4361 priv_val->buf_cac_idx[id] = 0;
4362 buf = priv_val->buf_cac[id];
4363 break;
4364 case ISP3X_MODULE_LDCH:
4365 default:
4366 priv_val->buf_ldch_idx[id] = 0;
4367 buf = priv_val->buf_ldch[id];
4368 break;
4369 }
4370
4371 for (i = 0; i < ISP3X_MESH_BUF_NUM; i++) {
4372 if (!buf->mem_priv) {
4373 meshbuf->buf_fd[i] = -1;
4374 meshbuf->buf_size[i] = 0;
4375 } else {
4376 meshbuf->buf_fd[i] = buf->dma_fd;
4377 meshbuf->buf_size[i] = buf->size;
4378 }
4379 buf++;
4380 }
4381 }
4382
4383 static void
rkisp_params_set_meshbuf_size_v3x(struct rkisp_isp_params_vdev * params_vdev,void * size)4384 rkisp_params_set_meshbuf_size_v3x(struct rkisp_isp_params_vdev *params_vdev,
4385 void *size)
4386 {
4387 struct rkisp_meshbuf_size *meshsize = size;
4388
4389 if (!params_vdev->dev->hw_dev->is_unite)
4390 meshsize->unite_isp_id = 0;
4391 rkisp_deinit_mesh_buf(params_vdev, meshsize->module_id, meshsize->unite_isp_id);
4392 rkisp_init_mesh_buf(params_vdev, meshsize);
4393 }
4394
4395 static void
rkisp_params_stream_stop_v3x(struct rkisp_isp_params_vdev * params_vdev)4396 rkisp_params_stream_stop_v3x(struct rkisp_isp_params_vdev *params_vdev)
4397 {
4398 struct rkisp_device *ispdev = params_vdev->dev;
4399 struct rkisp_isp_params_val_v3x *priv_val;
4400 u32 id, i;
4401
4402 priv_val = (struct rkisp_isp_params_val_v3x *)params_vdev->priv_val;
4403 tasklet_disable(&priv_val->lsc_tasklet);
4404 for (id = 0; id <= ispdev->hw_dev->is_unite; id++) {
4405 rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_iir[id]);
4406 rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_cur[id]);
4407 rkisp_free_buffer(ispdev, &priv_val->buf_3dnr_ds[id]);
4408 for (i = 0; i < ISP3X_3DLUT_BUF_NUM; i++)
4409 rkisp_free_buffer(ispdev, &priv_val->buf_3dlut[id][i]);
4410 for (i = 0; i < ISP3X_LSC_LUT_BUF_NUM; i++)
4411 rkisp_free_buffer(ispdev, &priv_val->buf_lsclut[id][i]);
4412 }
4413 for (i = 0; i < RKISP_STATS_DDR_BUF_NUM; i++)
4414 rkisp_free_buffer(ispdev, &ispdev->stats_vdev.stats_buf[i]);
4415 }
4416
4417 static void
rkisp_params_fop_release_v3x(struct rkisp_isp_params_vdev * params_vdev)4418 rkisp_params_fop_release_v3x(struct rkisp_isp_params_vdev *params_vdev)
4419 {
4420 int id;
4421
4422 for (id = 0; id <= params_vdev->dev->hw_dev->is_unite; id++) {
4423 rkisp_deinit_mesh_buf(params_vdev, ISP3X_MODULE_LDCH, id);
4424 rkisp_deinit_mesh_buf(params_vdev, ISP3X_MODULE_CAC, id);
4425 }
4426 }
4427
4428 /* Not called when the camera active, thus not isr protection. */
4429 static void
rkisp_params_disable_isp_v3x(struct rkisp_isp_params_vdev * params_vdev)4430 rkisp_params_disable_isp_v3x(struct rkisp_isp_params_vdev *params_vdev)
4431 {
4432 params_vdev->isp3x_params->module_ens = 0;
4433 params_vdev->isp3x_params->module_en_update = 0x7ffffffffff;
4434
4435 __isp_isr_other_en(params_vdev, params_vdev->isp3x_params, RKISP_PARAMS_ALL, 0);
4436 __isp_isr_meas_en(params_vdev, params_vdev->isp3x_params, RKISP_PARAMS_ALL, 0);
4437 if (params_vdev->dev->hw_dev->is_unite) {
4438 __isp_isr_other_en(params_vdev, params_vdev->isp3x_params, RKISP_PARAMS_ALL, 1);
4439 __isp_isr_meas_en(params_vdev, params_vdev->isp3x_params, RKISP_PARAMS_ALL, 1);
4440 }
4441 }
4442
4443 static void
module_data_abandon(struct rkisp_isp_params_vdev * params_vdev,struct isp3x_isp_params_cfg * params,u32 id)4444 module_data_abandon(struct rkisp_isp_params_vdev *params_vdev,
4445 struct isp3x_isp_params_cfg *params, u32 id)
4446 {
4447 struct rkisp_isp_params_val_v3x *priv_val;
4448 struct isp2x_mesh_head *mesh_head;
4449 int i;
4450
4451 priv_val = (struct rkisp_isp_params_val_v3x *)params_vdev->priv_val;
4452 if (params->module_cfg_update & ISP3X_MODULE_LDCH) {
4453 const struct isp2x_ldch_cfg *arg = ¶ms->others.ldch_cfg;
4454
4455 for (i = 0; i < ISP3X_MESH_BUF_NUM; i++) {
4456 if (arg->buf_fd == priv_val->buf_ldch[id][i].dma_fd &&
4457 priv_val->buf_ldch[id][i].vaddr) {
4458 mesh_head = (struct isp2x_mesh_head *)priv_val->buf_ldch[id][i].vaddr;
4459 mesh_head->stat = MESH_BUF_CHIPINUSE;
4460 break;
4461 }
4462 }
4463 }
4464
4465 if (params->module_cfg_update & ISP3X_MODULE_CAC) {
4466 const struct isp3x_cac_cfg *arg = ¶ms->others.cac_cfg;
4467
4468 for (i = 0; i < ISP3X_MESH_BUF_NUM; i++) {
4469 if (arg->buf_fd == priv_val->buf_cac[id][i].dma_fd &&
4470 priv_val->buf_cac[id][i].vaddr) {
4471 mesh_head = (struct isp2x_mesh_head *)priv_val->buf_cac[id][i].vaddr;
4472 mesh_head->stat = MESH_BUF_CHIPINUSE;
4473 break;
4474 }
4475 }
4476 }
4477 }
4478
4479 static void
rkisp_params_cfg_v3x(struct rkisp_isp_params_vdev * params_vdev,u32 frame_id,enum rkisp_params_type type)4480 rkisp_params_cfg_v3x(struct rkisp_isp_params_vdev *params_vdev,
4481 u32 frame_id, enum rkisp_params_type type)
4482 {
4483 struct isp3x_isp_params_cfg *new_params = NULL;
4484 struct rkisp_buffer *cur_buf = params_vdev->cur_buf;
4485 struct rkisp_device *dev = params_vdev->dev;
4486 struct rkisp_hw_dev *hw_dev = dev->hw_dev;
4487
4488 spin_lock(¶ms_vdev->config_lock);
4489 if (!params_vdev->streamon)
4490 goto unlock;
4491
4492 /* get buffer by frame_id */
4493 while (!list_empty(¶ms_vdev->params) && !cur_buf) {
4494 cur_buf = list_first_entry(¶ms_vdev->params,
4495 struct rkisp_buffer, queue);
4496
4497 new_params = (struct isp3x_isp_params_cfg *)(cur_buf->vaddr[0]);
4498 if (new_params->frame_id < frame_id) {
4499 list_del(&cur_buf->queue);
4500 if (list_empty(¶ms_vdev->params))
4501 break;
4502 else if (new_params->module_en_update) {
4503 /* update en immediately */
4504 __isp_isr_other_en(params_vdev, new_params, type, 0);
4505 __isp_isr_meas_en(params_vdev, new_params, type, 0);
4506 if (hw_dev->is_unite) {
4507 __isp_isr_other_en(params_vdev, new_params + 1, type, 1);
4508 __isp_isr_meas_en(params_vdev, new_params + 1, type, 1);
4509 }
4510 }
4511 if (new_params->module_cfg_update &
4512 (ISP3X_MODULE_LDCH | ISP3X_MODULE_CAC)) {
4513 module_data_abandon(params_vdev, new_params, 0);
4514 if (hw_dev->is_unite)
4515 module_data_abandon(params_vdev, new_params, 1);
4516 }
4517 vb2_buffer_done(&cur_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
4518 cur_buf = NULL;
4519 continue;
4520 } else if (new_params->frame_id == frame_id) {
4521 list_del(&cur_buf->queue);
4522 } else {
4523 cur_buf = NULL;
4524 }
4525 break;
4526 }
4527
4528 if (!cur_buf)
4529 goto unlock;
4530
4531 new_params = (struct isp3x_isp_params_cfg *)(cur_buf->vaddr[0]);
4532 if (hw_dev->is_unite) {
4533 __isp_isr_meas_config(params_vdev, new_params + 1, type, 1);
4534 __isp_isr_other_config(params_vdev, new_params + 1, type, 1);
4535 __isp_isr_other_en(params_vdev, new_params + 1, type, 1);
4536 __isp_isr_meas_en(params_vdev, new_params + 1, type, 1);
4537 }
4538 __isp_isr_meas_config(params_vdev, new_params, type, 0);
4539 __isp_isr_other_config(params_vdev, new_params, type, 0);
4540 __isp_isr_other_en(params_vdev, new_params, type, 0);
4541 __isp_isr_meas_en(params_vdev, new_params, type, 0);
4542 if (!hw_dev->is_single && type != RKISP_PARAMS_SHD)
4543 __isp_config_hdrshd(params_vdev);
4544
4545 if (type != RKISP_PARAMS_IMD) {
4546 struct rkisp_isp_params_val_v3x *priv_val =
4547 (struct rkisp_isp_params_val_v3x *)params_vdev->priv_val;
4548
4549 priv_val->last_hdrmge = priv_val->cur_hdrmge;
4550 priv_val->last_hdrdrc = priv_val->cur_hdrdrc;
4551 priv_val->cur_hdrmge = new_params->others.hdrmge_cfg;
4552 priv_val->cur_hdrdrc = new_params->others.drc_cfg;
4553 vb2_buffer_done(&cur_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
4554 cur_buf = NULL;
4555 }
4556
4557 unlock:
4558 params_vdev->cur_buf = cur_buf;
4559 spin_unlock(¶ms_vdev->config_lock);
4560 }
4561
4562 static void
rkisp_params_clear_fstflg(struct rkisp_isp_params_vdev * params_vdev)4563 rkisp_params_clear_fstflg(struct rkisp_isp_params_vdev *params_vdev)
4564 {
4565 struct rkisp_device *dev = params_vdev->dev;
4566 struct rkisp_hw_dev *hw_dev = dev->hw_dev;
4567 u32 value;
4568
4569 value = rkisp_read(dev, ISP3X_ISP_CTRL1, false);
4570 if (value & ISP3X_YNR_FST_FRAME)
4571 rkisp_clear_bits(params_vdev->dev, ISP3X_ISP_CTRL1,
4572 ISP3X_YNR_FST_FRAME, false);
4573 if (value & ISP3X_ADRC_FST_FRAME)
4574 rkisp_clear_bits(params_vdev->dev, ISP3X_ISP_CTRL1,
4575 ISP3X_ADRC_FST_FRAME, false);
4576 if (value & ISP3X_DHAZ_FST_FRAME)
4577 rkisp_clear_bits(params_vdev->dev, ISP3X_ISP_CTRL1,
4578 ISP3X_DHAZ_FST_FRAME, false);
4579 if (value & ISP3X_CNR_FST_FRAME)
4580 rkisp_clear_bits(params_vdev->dev, ISP3X_ISP_CTRL1,
4581 ISP3X_CNR_FST_FRAME, false);
4582 if (value & ISP3X_RAW3D_FST_FRAME)
4583 rkisp_clear_bits(params_vdev->dev, ISP3X_ISP_CTRL1,
4584 ISP3X_RAW3D_FST_FRAME, false);
4585 if (hw_dev->is_unite) {
4586 value = rkisp_next_read(dev, ISP3X_ISP_CTRL1, false);
4587 if (value & ISP3X_YNR_FST_FRAME)
4588 rkisp_next_clear_bits(params_vdev->dev, ISP3X_ISP_CTRL1,
4589 ISP3X_YNR_FST_FRAME, false);
4590 if (value & ISP3X_ADRC_FST_FRAME)
4591 rkisp_next_clear_bits(params_vdev->dev, ISP3X_ISP_CTRL1,
4592 ISP3X_ADRC_FST_FRAME, false);
4593 if (value & ISP3X_DHAZ_FST_FRAME)
4594 rkisp_next_clear_bits(params_vdev->dev, ISP3X_ISP_CTRL1,
4595 ISP3X_DHAZ_FST_FRAME, false);
4596 if (value & ISP3X_CNR_FST_FRAME)
4597 rkisp_next_clear_bits(params_vdev->dev, ISP3X_ISP_CTRL1,
4598 ISP3X_CNR_FST_FRAME, false);
4599 if (value & ISP3X_RAW3D_FST_FRAME)
4600 rkisp_next_clear_bits(params_vdev->dev, ISP3X_ISP_CTRL1,
4601 ISP3X_RAW3D_FST_FRAME, false);
4602 }
4603 }
4604
4605 static void
rkisp_params_isr_v3x(struct rkisp_isp_params_vdev * params_vdev,u32 isp_mis)4606 rkisp_params_isr_v3x(struct rkisp_isp_params_vdev *params_vdev,
4607 u32 isp_mis)
4608 {
4609 struct rkisp_device *dev = params_vdev->dev;
4610 u32 cur_frame_id;
4611
4612 rkisp_dmarx_get_frame(dev, &cur_frame_id, NULL, NULL, true);
4613 if (isp_mis & CIF_ISP_V_START) {
4614 if (params_vdev->rdbk_times)
4615 params_vdev->rdbk_times--;
4616 if (!params_vdev->cur_buf)
4617 return;
4618
4619 if (IS_HDR_RDBK(dev->rd_mode) && !params_vdev->rdbk_times) {
4620 rkisp_params_cfg_v3x(params_vdev, cur_frame_id, RKISP_PARAMS_SHD);
4621 return;
4622 }
4623 }
4624
4625 if (isp_mis & CIF_ISP_FRAME)
4626 rkisp_params_clear_fstflg(params_vdev);
4627
4628 if ((isp_mis & CIF_ISP_FRAME) && !IS_HDR_RDBK(dev->rd_mode))
4629 rkisp_params_cfg_v3x(params_vdev, cur_frame_id + 1, RKISP_PARAMS_ALL);
4630 }
4631
4632 static struct rkisp_isp_params_ops rkisp_isp_params_ops_tbl = {
4633 .save_first_param = rkisp_save_first_param_v3x,
4634 .clear_first_param = rkisp_clear_first_param_v3x,
4635 .get_param_size = rkisp_get_param_size_v3x,
4636 .first_cfg = rkisp_params_first_cfg_v3x,
4637 .disable_isp = rkisp_params_disable_isp_v3x,
4638 .isr_hdl = rkisp_params_isr_v3x,
4639 .param_cfg = rkisp_params_cfg_v3x,
4640 .param_cfgsram = rkisp_params_cfgsram_v3x,
4641 .get_meshbuf_inf = rkisp_params_get_meshbuf_inf_v3x,
4642 .set_meshbuf_size = rkisp_params_set_meshbuf_size_v3x,
4643 .stream_stop = rkisp_params_stream_stop_v3x,
4644 .fop_release = rkisp_params_fop_release_v3x,
4645 };
4646
rkisp_init_params_vdev_v3x(struct rkisp_isp_params_vdev * params_vdev)4647 int rkisp_init_params_vdev_v3x(struct rkisp_isp_params_vdev *params_vdev)
4648 {
4649 struct rkisp_device *ispdev = params_vdev->dev;
4650 struct rkisp_isp_params_val_v3x *priv_val;
4651 int size;
4652
4653 priv_val = kzalloc(sizeof(*priv_val), GFP_KERNEL);
4654 if (!priv_val)
4655 return -ENOMEM;
4656
4657 size = sizeof(struct isp3x_isp_params_cfg);
4658 if (ispdev->hw_dev->is_unite)
4659 size *= 2;
4660 params_vdev->isp3x_params = vmalloc(size);
4661 if (!params_vdev->isp3x_params) {
4662 kfree(priv_val);
4663 return -ENOMEM;
4664 }
4665
4666 params_vdev->priv_val = (void *)priv_val;
4667 params_vdev->ops = &rkisp_isp_params_ops_tbl;
4668 params_vdev->priv_ops = &isp_params_ops_v3x;
4669 rkisp_clear_first_param_v3x(params_vdev);
4670 tasklet_init(&priv_val->lsc_tasklet,
4671 isp_lsc_cfg_sram_task,
4672 (unsigned long)params_vdev);
4673 tasklet_disable(&priv_val->lsc_tasklet);
4674 return 0;
4675 }
4676
rkisp_uninit_params_vdev_v3x(struct rkisp_isp_params_vdev * params_vdev)4677 void rkisp_uninit_params_vdev_v3x(struct rkisp_isp_params_vdev *params_vdev)
4678 {
4679 struct rkisp_isp_params_val_v3x *priv_val = params_vdev->priv_val;
4680
4681 if (params_vdev->isp3x_params)
4682 vfree(params_vdev->isp3x_params);
4683 if (priv_val) {
4684 tasklet_kill(&priv_val->lsc_tasklet);
4685 kfree(priv_val);
4686 params_vdev->priv_val = NULL;
4687 }
4688 }
4689