1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 *
3 * Copyright (C) 2019 Rockchip Electronics Co., Ltd.
4 */
5
6 #ifndef _RKISP_REGS_V2X_H
7 #define _RKISP_REGS_V2X_H
8
9 #define CTRL_BASE 0x00000000
10 #define CTRL_VI_ISP_EN (CTRL_BASE + 0x00000)
11 #define CTRL_VI_ISP_PATH (CTRL_BASE + 0x00004)
12 #define CTRL_VI_ID (CTRL_BASE + 0x00008)
13 #define CTRL_VI_ISP_CLK_CTRL (CTRL_BASE + 0x0000c)
14 #define CTRL_VI_ICCL (CTRL_BASE + 0x00010)
15 #define CTRL_VI_IRCL (CTRL_BASE + 0x00014)
16 #define CTRL_VI_DPCL (CTRL_BASE + 0x00018)
17 #define CTRL_SWS_CFG (CTRL_BASE + 0x0001c)
18 #define LVDS_CTRL (CTRL_BASE + 0x00020)
19 #define LVDS_SAV_EAV_ACT (CTRL_BASE + 0x00024)
20 #define LVDS_SAV_EAV_BLK (CTRL_BASE + 0x00028)
21
22 #define IMG_EFF_BASE 0x00000200
23 #define IMG_EFF_CTRL (IMG_EFF_BASE + 0x00000)
24 #define IMG_EFF_COLOR_SEL (IMG_EFF_BASE + 0x00004)
25 #define IMG_EFF_MAT_1 (IMG_EFF_BASE + 0x00008)
26 #define IMG_EFF_MAT_2 (IMG_EFF_BASE + 0x0000c)
27 #define IMG_EFF_MAT_3 (IMG_EFF_BASE + 0x00010)
28 #define IMG_EFF_MAT_4 (IMG_EFF_BASE + 0x00014)
29 #define IMG_EFF_MAT_5 (IMG_EFF_BASE + 0x00018)
30 #define IMG_EFF_TINT (IMG_EFF_BASE + 0x0001c)
31 #define IMG_EFF_CTRL_SHD (IMG_EFF_BASE + 0x00020)
32 #define IMG_EFF_SHARPEN (IMG_EFF_BASE + 0x00024)
33 #define IMG_EFF_RKSHARP_CTRL (IMG_EFF_BASE + 0x00030)
34 #define IMG_EFF_RKSHARP_YAVG_THR (IMG_EFF_BASE + 0x00034)
35 #define IMG_EFF_RKSHARP_DELTA_P0_P1 (IMG_EFF_BASE + 0x00038)
36 #define IMG_EFF_RKSHARP_DELTA_P2_P3 (IMG_EFF_BASE + 0x0003c)
37 #define IMG_EFF_RKSHARP_DELTA_P4 (IMG_EFF_BASE + 0x00040)
38 #define IMG_EFF_RKSHARP_NPIXEL_P0_P1_P2_P3 (IMG_EFF_BASE + 0x00044)
39 #define IMG_EFF_RKSHARP_NPIXEL_P4 (IMG_EFF_BASE + 0x00048)
40 #define IMG_EFF_RKSHARP_GAUSS_FLAT_COE1 (IMG_EFF_BASE + 0x0004c)
41 #define IMG_EFF_RKSHARP_GAUSS_FLAT_COE2 (IMG_EFF_BASE + 0x00050)
42 #define IMG_EFF_RKSHARP_GAUSS_FLAT_COE3 (IMG_EFF_BASE + 0x00054)
43 #define IMG_EFF_RKSHARP_GAUSS_NOISE_COE1 (IMG_EFF_BASE + 0x00058)
44 #define IMG_EFF_RKSHARP_GAUSS_NOISE_COE2 (IMG_EFF_BASE + 0x0005c)
45 #define IMG_EFF_RKSHARP_GAUSS_NOISE_COE3 (IMG_EFF_BASE + 0x00060)
46 #define IMG_EFF_RKSHARP_GAUSS_OTHER_COE1 (IMG_EFF_BASE + 0x00064)
47 #define IMG_EFF_RKSHARP_GAUSS_OTHER_COE2 (IMG_EFF_BASE + 0x00068)
48 #define IMG_EFF_RKSHARP_GAUSS_OTHER_COE3 (IMG_EFF_BASE + 0x0006c)
49 #define IMG_EFF_RKSHARP_LINE1_FILTER_COE1 (IMG_EFF_BASE + 0x00070)
50 #define IMG_EFF_RKSHARP_LINE1_FILTER_COE2 (IMG_EFF_BASE + 0x00074)
51 #define IMG_EFF_RKSHARP_LINE2_FILTER_COE1 (IMG_EFF_BASE + 0x00078)
52 #define IMG_EFF_RKSHARP_LINE2_FILTER_COE2 (IMG_EFF_BASE + 0x0007c)
53 #define IMG_EFF_RKSHARP_LINE2_FILTER_COE3 (IMG_EFF_BASE + 0x00080)
54 #define IMG_EFF_RKSHARP_LINE3_FILTER_COE1 (IMG_EFF_BASE + 0x00084)
55 #define IMG_EFF_RKSHARP_LINE3_FILTER_COE2 (IMG_EFF_BASE + 0x00088)
56 #define IMG_EFF_RKSHARP_GRAD_SEQ_P0_P1 (IMG_EFF_BASE + 0x0008c)
57 #define IMG_EFF_RKSHARP_GRAD_SEQ_P2_P3 (IMG_EFF_BASE + 0x00090)
58 #define IMG_EFF_RKSHARP_SHARP_FACTOR_P0_P1_P2 (IMG_EFF_BASE + 0x00094)
59 #define IMG_EFF_RKSHARP_SHARP_FACTOR_P3_P4 (IMG_EFF_BASE + 0x00098)
60 #define IMG_EFF_RKSHARP_UV_GAUSS_FLAT_COE11_COE14 (IMG_EFF_BASE + 0x0009c)
61 #define IMG_EFF_RKSHARP_UV_GAUSS_FLAT_COE15_COE23 (IMG_EFF_BASE + 0x000a0)
62 #define IMG_EFF_RKSHARP_UV_GAUSS_FLAT_COE24_COE32 (IMG_EFF_BASE + 0x000a4)
63 #define IMG_EFF_RKSHARP_UV_GAUSS_FLAT_COE33_COE35 (IMG_EFF_BASE + 0x000a8)
64 #define IMG_EFF_RKSHARP_UV_GAUSS_NOISE_COE11_COE14 (IMG_EFF_BASE + 0x000ac)
65 #define IMG_EFF_RKSHARP_UV_GAUSS_NOISE_COE15_COE23 (IMG_EFF_BASE + 0x000b0)
66 #define IMG_EFF_RKSHARP_UV_GAUSS_NOISE_COE24_COE32 (IMG_EFF_BASE + 0x000b4)
67 #define IMG_EFF_RKSHARP_UV_GAUSS_NOISE_COE33_COE35 (IMG_EFF_BASE + 0x000b8)
68 #define IMG_EFF_RKSHARP_UV_GAUSS_OTHER_COE11_COE14 (IMG_EFF_BASE + 0x000bc)
69 #define IMG_EFF_RKSHARP_UV_GAUSS_OTHER_COE15_COE23 (IMG_EFF_BASE + 0x000c0)
70 #define IMG_EFF_RKSHARP_UV_GAUSS_OTHER_COE24_COE32 (IMG_EFF_BASE + 0x000c4)
71 #define IMG_EFF_RKSHARP_UV_GAUSS_OTHER_COE33_COE35 (IMG_EFF_BASE + 0x000c8)
72
73 #define SUPER_IMP_BASE 0x00000300
74 #define SUPER_IMP_CTRL (SUPER_IMP_BASE + 0x00000)
75 #define SUPER_IMP_OFFSET_X (SUPER_IMP_BASE + 0x00004)
76 #define SUPER_IMP_OFFSET_Y (SUPER_IMP_BASE + 0x00008)
77 #define SUPER_IMP_COLOR_Y (SUPER_IMP_BASE + 0x0000c)
78 #define SUPER_IMP_COLOR_CB (SUPER_IMP_BASE + 0x00010)
79 #define SUPER_IMP_COLOR_CR (SUPER_IMP_BASE + 0x00014)
80
81 #define ISP_BASE 0x00000400
82 #define ISP_CTRL (ISP_BASE + 0x00000)
83 #define ISP_ACQ_PROP (ISP_BASE + 0x00004)
84 #define ISP_CTRL1 (ISP_BASE + 0x00004)
85 #define ISP_ACQ_H_OFFS (ISP_BASE + 0x00008)
86 #define ISP_ACQ_V_OFFS (ISP_BASE + 0x0000c)
87 #define ISP_ACQ_H_SIZE (ISP_BASE + 0x00010)
88 #define ISP_ACQ_V_SIZE (ISP_BASE + 0x00014)
89 #define ISP_ACQ_NR_FRAMES (ISP_BASE + 0x00018)
90 #define ISP_GAMMA_DX_LO (ISP_BASE + 0x0001c)
91 #define ISP_GAMMA_DX_HI (ISP_BASE + 0x00020)
92 #define ISP_GAMMA_R_Y_0 (ISP_BASE + 0x00024)
93 #define ISP_GAMMA_R_Y_1 (ISP_BASE + 0x00028)
94 #define ISP_GAMMA_R_Y_2 (ISP_BASE + 0x0002c)
95 #define ISP_GAMMA_R_Y_3 (ISP_BASE + 0x00030)
96 #define ISP_GAMMA_R_Y_4 (ISP_BASE + 0x00034)
97 #define ISP_GAMMA_R_Y_5 (ISP_BASE + 0x00038)
98 #define ISP_GAMMA_R_Y_6 (ISP_BASE + 0x0003c)
99 #define ISP_GAMMA_R_Y_7 (ISP_BASE + 0x00040)
100 #define ISP_GAMMA_R_Y_8 (ISP_BASE + 0x00044)
101 #define ISP_GAMMA_R_Y_9 (ISP_BASE + 0x00048)
102 #define ISP_GAMMA_R_Y_10 (ISP_BASE + 0x0004c)
103 #define ISP_GAMMA_R_Y_11 (ISP_BASE + 0x00050)
104 #define ISP_GAMMA_R_Y_12 (ISP_BASE + 0x00054)
105 #define ISP_GAMMA_R_Y_13 (ISP_BASE + 0x00058)
106 #define ISP_GAMMA_R_Y_14 (ISP_BASE + 0x0005c)
107 #define ISP_GAMMA_R_Y_15 (ISP_BASE + 0x00060)
108 #define ISP_GAMMA_R_Y_16 (ISP_BASE + 0x00064)
109 #define ISP_GAMMA_G_Y_0 (ISP_BASE + 0x00068)
110 #define ISP_GAMMA_G_Y_1 (ISP_BASE + 0x0006c)
111 #define ISP_GAMMA_G_Y_2 (ISP_BASE + 0x00070)
112 #define ISP_GAMMA_G_Y_3 (ISP_BASE + 0x00074)
113 #define ISP_GAMMA_G_Y_4 (ISP_BASE + 0x00078)
114 #define ISP_GAMMA_G_Y_5 (ISP_BASE + 0x0007c)
115 #define ISP_GAMMA_G_Y_6 (ISP_BASE + 0x00080)
116 #define ISP_GAMMA_G_Y_7 (ISP_BASE + 0x00084)
117 #define ISP_GAMMA_G_Y_8 (ISP_BASE + 0x00088)
118 #define ISP_GAMMA_G_Y_9 (ISP_BASE + 0x0008c)
119 #define ISP_GAMMA_G_Y_10 (ISP_BASE + 0x00090)
120 #define ISP_GAMMA_G_Y_11 (ISP_BASE + 0x00094)
121 #define ISP_GAMMA_G_Y_12 (ISP_BASE + 0x00098)
122 #define ISP_GAMMA_G_Y_13 (ISP_BASE + 0x0009c)
123 #define ISP_GAMMA_G_Y_14 (ISP_BASE + 0x000a0)
124 #define ISP_GAMMA_G_Y_15 (ISP_BASE + 0x000a4)
125 #define ISP_GAMMA_G_Y_16 (ISP_BASE + 0x000a8)
126 #define ISP_GAMMA_B_Y_0 (ISP_BASE + 0x000ac)
127 #define ISP_GAMMA_B_Y_1 (ISP_BASE + 0x000b0)
128 #define ISP_GAMMA_B_Y_2 (ISP_BASE + 0x000b4)
129 #define ISP_GAMMA_B_Y_3 (ISP_BASE + 0x000b8)
130 #define ISP_GAMMA_B_Y_4 (ISP_BASE + 0x000bc)
131 #define ISP_GAMMA_B_Y_5 (ISP_BASE + 0x000c0)
132 #define ISP_GAMMA_B_Y_6 (ISP_BASE + 0x000c4)
133 #define ISP_GAMMA_B_Y_7 (ISP_BASE + 0x000c8)
134 #define ISP_GAMMA_B_Y_8 (ISP_BASE + 0x000cc)
135 #define ISP_GAMMA_B_Y_9 (ISP_BASE + 0x000d0)
136 #define ISP_GAMMA_B_Y_10 (ISP_BASE + 0x000d4)
137 #define ISP_GAMMA_B_Y_11 (ISP_BASE + 0x000d8)
138 #define ISP_GAMMA_B_Y_12 (ISP_BASE + 0x000dc)
139 #define ISP_GAMMA_B_Y_13 (ISP_BASE + 0x000e0)
140 #define ISP_GAMMA_B_Y_14 (ISP_BASE + 0x000e4)
141 #define ISP_GAMMA_B_Y_15 (ISP_BASE + 0x000e8)
142 #define ISP_GAMMA_B_Y_16 (ISP_BASE + 0x000ec)
143
144 #define ISP_AWB_PROP (ISP_BASE + 0x00110)
145 #define ISP_AWB_SIZE (ISP_BASE + 0x00114)
146 #define ISP_AWB_OFFS (ISP_BASE + 0x00118)
147 #define ISP_AWB_REF (ISP_BASE + 0x0011c)
148 #define ISP_AWB_THRESH (ISP_BASE + 0x00120)
149 #define ISP_X_COOR_12 (ISP_BASE + 0x00124)
150 #define ISP_X_COOR_34 (ISP_BASE + 0x00128)
151 #define ISP_AWB_WHITE_CNT (ISP_BASE + 0x0012c)
152 #define ISP_AWB_MEAN (ISP_BASE + 0x00130)
153 #define ISP_DEGAIN (ISP_BASE + 0x00134)
154 #define ISP_AWB_GAIN_G (ISP_BASE + 0x00138)
155 #define ISP_AWB_GAIN_RB (ISP_BASE + 0x0013c)
156 #define ISP_REGION0_LINE0 (ISP_BASE + 0x00140)
157 #define ISP_WP_CNT_REGION0 (ISP_BASE + 0x00160)
158 #define ISP_WP_CNT_REGION1 (ISP_BASE + 0x00164)
159 #define ISP_WP_CNT_REGION2 (ISP_BASE + 0x00168)
160 #define ISP_WP_CNT_REGION3 (ISP_BASE + 0x0016c)
161
162 #define ISP21_AWB_GAIN0_G (ISP_BASE + 0x00138)
163 #define ISP21_AWB_GAIN0_RB (ISP_BASE + 0x0013c)
164 #define ISP21_AWB_GAIN1_G (ISP_BASE + 0x00140)
165 #define ISP21_AWB_GAIN1_RB (ISP_BASE + 0x00144)
166 #define ISP21_AWB_GAIN2_G (ISP_BASE + 0x00148)
167 #define ISP21_AWB_GAIN2_RB (ISP_BASE + 0x0014c)
168
169 #define ISP_CC_COEFF_0 (ISP_BASE + 0x00170)
170 #define ISP_CC_COEFF_1 (ISP_BASE + 0x00174)
171 #define ISP_CC_COEFF_2 (ISP_BASE + 0x00178)
172 #define ISP_CC_COEFF_3 (ISP_BASE + 0x0017c)
173 #define ISP_CC_COEFF_4 (ISP_BASE + 0x00180)
174 #define ISP_CC_COEFF_5 (ISP_BASE + 0x00184)
175 #define ISP_CC_COEFF_6 (ISP_BASE + 0x00188)
176 #define ISP_CC_COEFF_7 (ISP_BASE + 0x0018c)
177 #define ISP_CC_COEFF_8 (ISP_BASE + 0x00190)
178 #define ISP_OUT_H_OFFS (ISP_BASE + 0x00194)
179 #define ISP_OUT_V_OFFS (ISP_BASE + 0x00198)
180 #define ISP_OUT_H_SIZE (ISP_BASE + 0x0019c)
181 #define ISP_OUT_V_SIZE (ISP_BASE + 0x001a0)
182 #define ISP_DEMOSAIC (ISP_BASE + 0x001a4)
183 #define ISP_FLAGS_SHD (ISP_BASE + 0x001a8)
184 #define ISP_OUT_H_OFFS_SHD (ISP_BASE + 0x001ac)
185 #define ISP_OUT_V_OFFS_SHD (ISP_BASE + 0x001b0)
186 #define ISP_OUT_H_SIZE_SHD (ISP_BASE + 0x001b4)
187 #define ISP_OUT_V_SIZE_SHD (ISP_BASE + 0x001b8)
188 #define ISP_ISP_IMSC (ISP_BASE + 0x001bc)
189 #define ISP_ISP_RIS (ISP_BASE + 0x001c0)
190 #define ISP_ISP_MIS (ISP_BASE + 0x001c4)
191 #define ISP_ISP_ICR (ISP_BASE + 0x001c8)
192 #define ISP_ISP_ISR (ISP_BASE + 0x001cc)
193
194 #define ISP_ISP3A_IMSC (ISP_BASE + 0x001d0)
195 #define ISP_ISP3A_RIS (ISP_BASE + 0x001d4)
196 #define ISP_ISP3A_MIS (ISP_BASE + 0x001d8)
197 #define ISP_ISP3A_ICR (ISP_BASE + 0x001dc)
198
199 #define ISP_ERR (ISP_BASE + 0x0023c)
200 #define ISP_ERR_CLR (ISP_BASE + 0x00240)
201 #define ISP_FRAME_COUNT (ISP_BASE + 0x00244)
202 #define ISP_CT_OFFSET_R (ISP_BASE + 0x00248)
203 #define ISP_CT_OFFSET_G (ISP_BASE + 0x0024c)
204 #define ISP_CT_OFFSET_B (ISP_BASE + 0x00250)
205 #define ISP_DEBUG1 (ISP_BASE + 0x00254)
206
207 #define ISP_FLASH_BASE 0x00000660
208 #define ISP_FLASH_CMD (ISP_FLASH_BASE + 0x00000)
209 #define ISP_FLASH_CONFIG (ISP_FLASH_BASE + 0x00004)
210 #define ISP_FLASH_PREDIV (ISP_FLASH_BASE + 0x00008)
211 #define ISP_FLASH_DELAY (ISP_FLASH_BASE + 0x0000c)
212 #define ISP_FLASH_TIME (ISP_FLASH_BASE + 0x00010)
213 #define ISP_FLASH_MAXP (ISP_FLASH_BASE + 0x00014)
214
215 #define ISP_SHUTTER_BASE 0x00000680
216 #define ISP_SHUTTER_CTRL (ISP_SHUTTER_BASE + 0x00000)
217 #define ISP_SHUTTER_PREDIV (ISP_SHUTTER_BASE + 0x00004)
218 #define ISP_SHUTTER_DELAY (ISP_SHUTTER_BASE + 0x00008)
219 #define ISP_SHUTTER_TIME (ISP_SHUTTER_BASE + 0x0000c)
220
221 #define ISP_CCM_BASE 0x00000700
222 #define ISP_CCM_CTRL (ISP_CCM_BASE + 0x00000)
223 #define ISP_CCM_COEFF0_R (ISP_CCM_BASE + 0x00004)
224 #define ISP_CCM_COEFF1_R (ISP_CCM_BASE + 0x00008)
225 #define ISP_CCM_COEFF0_G (ISP_CCM_BASE + 0x0000c)
226 #define ISP_CCM_COEFF1_G (ISP_CCM_BASE + 0x00010)
227 #define ISP_CCM_COEFF0_B (ISP_CCM_BASE + 0x00014)
228 #define ISP_CCM_COEFF1_B (ISP_CCM_BASE + 0x00018)
229 #define ISP_CCM_COEFF0_Y (ISP_CCM_BASE + 0x0001c)
230 #define ISP_CCM_COEFF1_Y (ISP_CCM_BASE + 0x00020)
231 #define ISP_CCM_ALP_Y0 (ISP_CCM_BASE + 0x00024)
232 #define ISP_CCM_ALP_Y1 (ISP_CCM_BASE + 0x00028)
233 #define ISP_CCM_ALP_Y2 (ISP_CCM_BASE + 0x0002c)
234 #define ISP_CCM_ALP_Y3 (ISP_CCM_BASE + 0x00030)
235 #define ISP_CCM_ALP_Y4 (ISP_CCM_BASE + 0x00034)
236 #define ISP_CCM_ALP_Y5 (ISP_CCM_BASE + 0x00038)
237 #define ISP_CCM_ALP_Y6 (ISP_CCM_BASE + 0x0003c)
238 #define ISP_CCM_ALP_Y7 (ISP_CCM_BASE + 0x00040)
239 #define ISP_CCM_ALP_Y8 (ISP_CCM_BASE + 0x00044)
240 #define ISP_CCM_BOUND_BIT (ISP_CCM_BASE + 0x00048)
241
242 #define CPROC_BASE 0x00000800
243 #define CPROC_CTRL (CPROC_BASE + 0x00000)
244 #define CPROC_CONTRAST (CPROC_BASE + 0x00004)
245 #define CPROC_BRIGHTNESS (CPROC_BASE + 0x00008)
246 #define CPROC_SATURATION (CPROC_BASE + 0x0000c)
247 #define CPROC_HUE (CPROC_BASE + 0x00010)
248
249 #define DUAL_CROP_BASE 0x00000880
250 #define DUAL_CROP_CTRL (DUAL_CROP_BASE + 0x00000)
251 #define DUAL_CROP_M_H_OFFS (DUAL_CROP_BASE + 0x00004)
252 #define DUAL_CROP_M_V_OFFS (DUAL_CROP_BASE + 0x00008)
253 #define DUAL_CROP_M_H_SIZE (DUAL_CROP_BASE + 0x0000c)
254 #define DUAL_CROP_M_V_SIZE (DUAL_CROP_BASE + 0x00010)
255 #define DUAL_CROP_S_H_OFFS (DUAL_CROP_BASE + 0x00014)
256 #define DUAL_CROP_S_V_OFFS (DUAL_CROP_BASE + 0x00018)
257 #define DUAL_CROP_S_H_SIZE (DUAL_CROP_BASE + 0x0001c)
258 #define DUAL_CROP_S_V_SIZE (DUAL_CROP_BASE + 0x00020)
259
260 #define ISP_GAMMA_OUT_BASE 0x00000900
261 #define ISP_GAMMA_OUT_CTRL (ISP_GAMMA_OUT_BASE + 0x00000)
262 #define ISP_GAMMA_OUT_OFFSET (ISP_GAMMA_OUT_BASE + 0x00004)
263 #define ISP_GAMMA_OUT_Y0 (ISP_GAMMA_OUT_BASE + 0x00010)
264 #define ISP_GAMMA_OUT_Y1 (ISP_GAMMA_OUT_BASE + 0x00014)
265 #define ISP_GAMMA_OUT_Y2 (ISP_GAMMA_OUT_BASE + 0x00018)
266 #define ISP_GAMMA_OUT_Y3 (ISP_GAMMA_OUT_BASE + 0x0001c)
267 #define ISP_GAMMA_OUT_Y4 (ISP_GAMMA_OUT_BASE + 0x00020)
268 #define ISP_GAMMA_OUT_Y5 (ISP_GAMMA_OUT_BASE + 0x00024)
269 #define ISP_GAMMA_OUT_Y6 (ISP_GAMMA_OUT_BASE + 0x00028)
270 #define ISP_GAMMA_OUT_Y7 (ISP_GAMMA_OUT_BASE + 0x0002c)
271 #define ISP_GAMMA_OUT_Y8 (ISP_GAMMA_OUT_BASE + 0x00030)
272 #define ISP_GAMMA_OUT_Y9 (ISP_GAMMA_OUT_BASE + 0x00034)
273 #define ISP_GAMMA_OUT_Y10 (ISP_GAMMA_OUT_BASE + 0x00038)
274 #define ISP_GAMMA_OUT_Y11 (ISP_GAMMA_OUT_BASE + 0x0003c)
275 #define ISP_GAMMA_OUT_Y12 (ISP_GAMMA_OUT_BASE + 0x00040)
276 #define ISP_GAMMA_OUT_Y13 (ISP_GAMMA_OUT_BASE + 0x00044)
277 #define ISP_GAMMA_OUT_Y14 (ISP_GAMMA_OUT_BASE + 0x00048)
278 #define ISP_GAMMA_OUT_Y15 (ISP_GAMMA_OUT_BASE + 0x0004c)
279 #define ISP_GAMMA_OUT_Y16 (ISP_GAMMA_OUT_BASE + 0x00050)
280 #define ISP_GAMMA_OUT_Y17 (ISP_GAMMA_OUT_BASE + 0x00054)
281 #define ISP_GAMMA_OUT_Y18 (ISP_GAMMA_OUT_BASE + 0x00058)
282 #define ISP_GAMMA_OUT_Y19 (ISP_GAMMA_OUT_BASE + 0x0005c)
283 #define ISP_GAMMA_OUT_Y20 (ISP_GAMMA_OUT_BASE + 0x00060)
284 #define ISP_GAMMA_OUT_Y21 (ISP_GAMMA_OUT_BASE + 0x00064)
285 #define ISP_GAMMA_OUT_Y22 (ISP_GAMMA_OUT_BASE + 0x00068)
286 #define ISP_GAMMA_OUT_Y23 (ISP_GAMMA_OUT_BASE + 0x0006c)
287 #define ISP_GAMMA_OUT_Y24 (ISP_GAMMA_OUT_BASE + 0x00070)
288 #define ISP_GAMMA_OUT_Y25 (ISP_GAMMA_OUT_BASE + 0x00074)
289 #define ISP_GAMMA_OUT_Y26 (ISP_GAMMA_OUT_BASE + 0x00078)
290 #define ISP_GAMMA_OUT_Y27 (ISP_GAMMA_OUT_BASE + 0x0007c)
291 #define ISP_GAMMA_OUT_Y28 (ISP_GAMMA_OUT_BASE + 0x00080)
292 #define ISP_GAMMA_OUT_Y29 (ISP_GAMMA_OUT_BASE + 0x00084)
293 #define ISP_GAMMA_OUT_Y30 (ISP_GAMMA_OUT_BASE + 0x00088)
294 #define ISP_GAMMA_OUT_Y31 (ISP_GAMMA_OUT_BASE + 0x0008c)
295 #define ISP_GAMMA_OUT_Y32 (ISP_GAMMA_OUT_BASE + 0x00090)
296 #define ISP_GAMMA_OUT_Y33 (ISP_GAMMA_OUT_BASE + 0x00094)
297 #define ISP_GAMMA_OUT_Y34 (ISP_GAMMA_OUT_BASE + 0x00098)
298 #define ISP_GAMMA_OUT_Y35 (ISP_GAMMA_OUT_BASE + 0x0009c)
299 #define ISP_GAMMA_OUT_Y36 (ISP_GAMMA_OUT_BASE + 0x000a0)
300 #define ISP_GAMMA_OUT_Y37 (ISP_GAMMA_OUT_BASE + 0x000a4)
301 #define ISP_GAMMA_OUT_Y38 (ISP_GAMMA_OUT_BASE + 0x000a8)
302 #define ISP_GAMMA_OUT_Y39 (ISP_GAMMA_OUT_BASE + 0x000ac)
303 #define ISP_GAMMA_OUT_Y40 (ISP_GAMMA_OUT_BASE + 0x000b0)
304
305 #define MAIN_RESIZE_BASE 0x00000C00
306 #define MAIN_RESIZE_CTRL (MAIN_RESIZE_BASE + 0x00000)
307 #define MAIN_RESIZE_SCALE_HY (MAIN_RESIZE_BASE + 0x00004)
308 #define MAIN_RESIZE_SCALE_HCB (MAIN_RESIZE_BASE + 0x00008)
309 #define MAIN_RESIZE_SCALE_HCR (MAIN_RESIZE_BASE + 0x0000c)
310 #define MAIN_RESIZE_SCALE_VY (MAIN_RESIZE_BASE + 0x00010)
311 #define MAIN_RESIZE_SCALE_VC (MAIN_RESIZE_BASE + 0x00014)
312 #define MAIN_RESIZE_PHASE_HY (MAIN_RESIZE_BASE + 0x00018)
313 #define MAIN_RESIZE_PHASE_HC (MAIN_RESIZE_BASE + 0x0001c)
314 #define MAIN_RESIZE_PHASE_VY (MAIN_RESIZE_BASE + 0x00020)
315 #define MAIN_RESIZE_PHASE_VC (MAIN_RESIZE_BASE + 0x00024)
316 #define MAIN_RESIZE_SCALE_LUT_ADDR (MAIN_RESIZE_BASE + 0x00028)
317 #define MAIN_RESIZE_SCALE_LUT (MAIN_RESIZE_BASE + 0x0002c)
318 #define MAIN_RESIZE_CTRL_SHD (MAIN_RESIZE_BASE + 0x00030)
319 #define MAIN_RESIZE_SCALE_HY_SHD (MAIN_RESIZE_BASE + 0x00034)
320 #define MAIN_RESIZE_SCALE_HCB_SHD (MAIN_RESIZE_BASE + 0x00038)
321 #define MAIN_RESIZE_SCALE_HCR_SHD (MAIN_RESIZE_BASE + 0x0003c)
322 #define MAIN_RESIZE_SCALE_VY_SHD (MAIN_RESIZE_BASE + 0x00040)
323 #define MAIN_RESIZE_SCALE_VC_SHD (MAIN_RESIZE_BASE + 0x00044)
324 #define MAIN_RESIZE_PHASE_HY_SHD (MAIN_RESIZE_BASE + 0x00048)
325 #define MAIN_RESIZE_PHASE_HC_SHD (MAIN_RESIZE_BASE + 0x0004c)
326 #define MAIN_RESIZE_PHASE_VY_SHD (MAIN_RESIZE_BASE + 0x00050)
327 #define MAIN_RESIZE_PHASE_VC_SHD (MAIN_RESIZE_BASE + 0x00054)
328
329 #define SELF_RESIZE_BASE 0x00001000
330 #define SELF_RESIZE_CTRL (SELF_RESIZE_BASE + 0x00000)
331 #define SELF_RESIZE_SCALE_HY (SELF_RESIZE_BASE + 0x00004)
332 #define SELF_RESIZE_SCALE_HCB (SELF_RESIZE_BASE + 0x00008)
333 #define SELF_RESIZE_SCALE_HCR (SELF_RESIZE_BASE + 0x0000c)
334 #define SELF_RESIZE_SCALE_VY (SELF_RESIZE_BASE + 0x00010)
335 #define SELF_RESIZE_SCALE_VC (SELF_RESIZE_BASE + 0x00014)
336 #define SELF_RESIZE_PHASE_HY (SELF_RESIZE_BASE + 0x00018)
337 #define SELF_RESIZE_PHASE_HC (SELF_RESIZE_BASE + 0x0001c)
338 #define SELF_RESIZE_PHASE_VY (SELF_RESIZE_BASE + 0x00020)
339 #define SELF_RESIZE_PHASE_VC (SELF_RESIZE_BASE + 0x00024)
340 #define SELF_RESIZE_SCALE_LUT_ADDR (SELF_RESIZE_BASE + 0x00028)
341 #define SELF_RESIZE_SCALE_LUT (SELF_RESIZE_BASE + 0x0002c)
342 #define SELF_RESIZE_CTRL_SHD (SELF_RESIZE_BASE + 0x00030)
343 #define SELF_RESIZE_SCALE_HY_SHD (SELF_RESIZE_BASE + 0x00034)
344 #define SELF_RESIZE_SCALE_HCB_SHD (SELF_RESIZE_BASE + 0x00038)
345 #define SELF_RESIZE_SCALE_HCR_SHD (SELF_RESIZE_BASE + 0x0003c)
346 #define SELF_RESIZE_SCALE_VY_SHD (SELF_RESIZE_BASE + 0x00040)
347 #define SELF_RESIZE_SCALE_VC_SHD (SELF_RESIZE_BASE + 0x00044)
348 #define SELF_RESIZE_PHASE_HY_SHD (SELF_RESIZE_BASE + 0x00048)
349 #define SELF_RESIZE_PHASE_HC_SHD (SELF_RESIZE_BASE + 0x0004c)
350 #define SELF_RESIZE_PHASE_VY_SHD (SELF_RESIZE_BASE + 0x00050)
351 #define SELF_RESIZE_PHASE_VC_SHD (SELF_RESIZE_BASE + 0x00054)
352
353 #define MI_BASE 0x00001400
354 #define MI_WR_CTRL (MI_BASE + 0x00000)
355 #define MI_WR_INIT (MI_BASE + 0x00004)
356 #define MI_MP_WR_Y_BASE (MI_BASE + 0x00008)
357 #define MI_MP_WR_Y_SIZE (MI_BASE + 0x0000c)
358 #define MI_MP_WR_Y_OFFS_CNT (MI_BASE + 0x00010)
359 #define MI_MP_WR_Y_OFFS_CNT_START (MI_BASE + 0x00014)
360 #define MI_MP_WR_Y_IRQ_OFFS (MI_BASE + 0x00018)
361 #define MI_MP_WR_CB_BASE (MI_BASE + 0x0001c)
362 #define MI_MP_WR_CB_SIZE (MI_BASE + 0x00020)
363 #define MI_MP_WR_CB_OFFS_CNT (MI_BASE + 0x00024)
364 #define MI_MP_WR_CB_OFFS_CNT_START (MI_BASE + 0x00028)
365 #define MI_MP_WR_CR_BASE (MI_BASE + 0x0002c)
366 #define MI_MP_WR_CR_SIZE (MI_BASE + 0x00030)
367 #define MI_MP_WR_CR_OFFS_CNT (MI_BASE + 0x00034)
368 #define MI_MP_WR_CR_OFFS_CNT_START (MI_BASE + 0x00038)
369 #define MI_SP_WR_Y_BASE (MI_BASE + 0x0003c)
370 #define MI_SP_WR_Y_SIZE (MI_BASE + 0x00040)
371 #define MI_SP_WR_Y_OFFS_CNT (MI_BASE + 0x00044)
372 #define MI_SP_WR_Y_OFFS_CNT_START (MI_BASE + 0x00048)
373 #define MI_SP_WR_Y_LLENGTH (MI_BASE + 0x0004c)
374 #define MI_SP_WR_CB_BASE (MI_BASE + 0x00050)
375 #define MI_SP_WR_CB_SIZE (MI_BASE + 0x00054)
376 #define MI_SP_WR_CB_OFFS_CNT (MI_BASE + 0x00058)
377 #define MI_SP_WR_CB_OFFS_CNT_START (MI_BASE + 0x0005c)
378 #define MI_SP_WR_CR_BASE (MI_BASE + 0x00060)
379 #define MI_SP_WR_CR_SIZE (MI_BASE + 0x00064)
380 #define MI_SP_WR_CR_OFFS_CNT (MI_BASE + 0x00068)
381 #define MI_SP_WR_CR_OFFS_CNT_START (MI_BASE + 0x0006c)
382 #define MI_WR_BYTE_CNT (MI_BASE + 0x00070)
383 #define MI_WR_CTRL_SHD (MI_BASE + 0x00074)
384 #define MI_MP_WR_Y_BASE_SHD (MI_BASE + 0x00078)
385 #define MI_MP_WR_Y_SIZE_SHD (MI_BASE + 0x0007c)
386 #define MI_MP_WR_Y_OFFS_CNT_SHD (MI_BASE + 0x00080)
387 #define MI_MP_WR_Y_IRQ_OFFS_SHD (MI_BASE + 0x00084)
388 #define MI_MP_WR_CB_BASE_SHD (MI_BASE + 0x00088)
389 #define MI_MP_WR_CB_SIZE_SHD (MI_BASE + 0x0008c)
390 #define MI_MP_WR_CB_OFFS_CNT_SHD (MI_BASE + 0x00090)
391 #define MI_MP_WR_CR_BASE_SHD (MI_BASE + 0x00094)
392 #define MI_MP_WR_CR_SIZE_SHD (MI_BASE + 0x00098)
393 #define MI_MP_WR_CR_OFFS_CNT_SHD (MI_BASE + 0x0009c)
394 #define MI_SP_WR_Y_BASE_SHD (MI_BASE + 0x000a0)
395 #define MI_SP_WR_Y_SIZE_SHD (MI_BASE + 0x000a4)
396 #define MI_SP_WR_Y_OFFS_CNT_SHD (MI_BASE + 0x000a8)
397 #define MI_SP_WR_CB_BASE_AD_SHD (MI_BASE + 0x000b0)
398 #define MI_SP_WR_CB_SIZE_SHD (MI_BASE + 0x000b4)
399 #define MI_SP_WR_CB_OFFS_CNT_SHD (MI_BASE + 0x000b8)
400 #define MI_SP_WR_CR_BASE_AD_SHD (MI_BASE + 0x000bc)
401 #define MI_SP_WR_CR_SIZE_SHD (MI_BASE + 0x000c0)
402 #define MI_SP_WR_CR_OFFS_CNT_SHD (MI_BASE + 0x000c4)
403 #define MI_RD_Y_PIC_START_AD (MI_BASE + 0x000c8)
404 #define MI_RD_Y_PIC_WIDTH (MI_BASE + 0x000cc)
405 #define MI_RD_Y_LLENGTH (MI_BASE + 0x000d0)
406 #define MI_RD_Y_PIC_SIZE (MI_BASE + 0x000d4)
407 #define MI_RD_CB_PIC_START_AD (MI_BASE + 0x000d8)
408 #define MI_RD_CR_PIC_START_AD (MI_BASE + 0x000e8)
409 #define MI_IMSC (MI_BASE + 0x000f8)
410 #define MI_RIS (MI_BASE + 0x000fc)
411 #define MI_MIS (MI_BASE + 0x00100)
412 #define MI_ICR (MI_BASE + 0x00104)
413 #define MI_ISR (MI_BASE + 0x00108)
414 #define MI_STATUS (MI_BASE + 0x0010c)
415 #define MI_STATUS_CLR (MI_BASE + 0x00110)
416 #define MI_SP_WR_Y_PIC_WIDTH (MI_BASE + 0x00114)
417 #define MI_SP_WR_Y_PIC_HEIGHT (MI_BASE + 0x00118)
418 #define MI_SP_WR_Y_PIC_SIZE (MI_BASE + 0x0011c)
419 #define MI_RD_CTRL (MI_BASE + 0x00120)
420 #define MI_RD_START (MI_BASE + 0x00124)
421 #define MI_RD_STATUS (MI_BASE + 0x00128)
422 #define MI_WR_PIXEL_CNT (MI_BASE + 0x0012c)
423 #define MI_MP_WR_Y_BASE2 (MI_BASE + 0x00130)
424 #define MI_MP_WR_CB_BASE2 (MI_BASE + 0x00134)
425 #define MI_MP_WR_CR_BASE2 (MI_BASE + 0x00138)
426 #define MI_WR_XTD_FORMAT_CTRL (MI_BASE + 0x00148)
427 #define MI_WR_ID (MI_BASE + 0x00154)
428 #define MI_MP_WR_Y_IRQ_OFFS2 (MI_BASE + 0x001e0)
429 #define MI_MP_WR_Y_IRQ_OFFS2_SHD (MI_BASE + 0x001e4)
430 #define MI_MP_WR_Y_LLENGTH (MI_BASE + 0x001e8)
431 #define MI_WR_CTRL2 (MI_BASE + 0x00400)
432 #define MI_WR_ID2 (MI_BASE + 0x00404)
433 #define MI_RD_CTRL2 (MI_BASE + 0x00408)
434 #define MI_RD_ID (MI_BASE + 0x0040c)
435 #define MI_RD_FIFO_LEVEL (MI_BASE + 0x0041c)
436 #define MI_RAW0_WR_BASE (MI_BASE + 0x00420)
437 #define MI_RAW0_WR_SIZE (MI_BASE + 0x00424)
438 #define MI_RAW0_WR_LENGTH (MI_BASE + 0x00428)
439 #define MI_RAW0_WR_BASE_SHD (MI_BASE + 0x0042c)
440 #define MI_RAW1_WR_BASE (MI_BASE + 0x00430)
441 #define MI_RAW1_WR_SIZE (MI_BASE + 0x00434)
442 #define MI_RAW1_WR_LENGTH (MI_BASE + 0x00438)
443 #define MI_RAW1_WR_BASE_SHD (MI_BASE + 0x0043c)
444 #define MI_RAW2_WR_BASE (MI_BASE + 0x00440)
445 #define MI_RAW2_WR_SIZE (MI_BASE + 0x00444)
446 #define MI_RAW2_WR_LENGTH (MI_BASE + 0x00448)
447 #define MI_RAW2_WR_BASE_SHD (MI_BASE + 0x0044c)
448 #define MI_RAW3_WR_BASE (MI_BASE + 0x00450)
449 #define MI_RAW3_WR_SIZE (MI_BASE + 0x00454)
450 #define MI_RAW3_WR_LENGTH (MI_BASE + 0x00458)
451 #define MI_RAW3_WR_BASE_SHD (MI_BASE + 0x0045c)
452 #define MI_RW0_WR_LAST_FRAME_ADDR (MI_BASE + 0x00460)
453 #define MI_RW1_WR_LAST_FRAME_ADDR (MI_BASE + 0x00464)
454 #define MI_RW2_WR_LAST_FRAME_ADDR (MI_BASE + 0x00468)
455 #define MI_RW3_WR_LAST_FRAME_ADDR (MI_BASE + 0x0046c)
456 #define MI_RAW0_RD_BASE (MI_BASE + 0x00470)
457 #define MI_RAW0_RD_LENGTH (MI_BASE + 0x00474)
458 #define MI_RAW0_RD_BASE_SHD (MI_BASE + 0x00478)
459 #define MI_RAW1_RD_BASE (MI_BASE + 0x00480)
460 #define MI_RAW1_RD_LENGTH (MI_BASE + 0x00484)
461 #define MI_RAW1_RD_BASE_SHD (MI_BASE + 0x00488)
462 #define MI_RAW2_RD_BASE (MI_BASE + 0x00490)
463 #define MI_RAW2_RD_LENGTH (MI_BASE + 0x00494)
464 #define MI_RAW2_RD_BASE_SHD (MI_BASE + 0x00498)
465 #define MI_RAWFBC_WR_BURST_LEN (MI_BASE + 0x00500)
466 #define MI_RAWFBC_RD_BURST_LEN (MI_BASE + 0x00504)
467 #define MI_RAW0FBC_WR_BASE (MI_BASE + 0x00510)
468 #define MI_RAW1FBC_WR_BASE (MI_BASE + 0x00514)
469 #define MI_RAW0FBC_RD_BASE (MI_BASE + 0x00518)
470 #define MI_RAW1FBC_RD_BASE (MI_BASE + 0x0051c)
471 #define MI_RAW0FBC_WR_BASE_SHD (MI_BASE + 0x00520)
472 #define MI_RAW1FBC_WR_BASE_SHD (MI_BASE + 0x00524)
473 #define MI_RAW0FBC_RD_BASE_SHD (MI_BASE + 0x00528)
474 #define MI_RAW1FBC_RD_BASE_SHD (MI_BASE + 0x0052c)
475 #define MI_LUT_3D_RD_BASE (MI_BASE + 0x00540)
476 #define MI_LUT_LSC_RD_BASE (MI_BASE + 0x00544)
477 #define MI_LUT_LDCH_RD_BASE (MI_BASE + 0x00548)
478 #define MI_LUT_3D_RD_WSIZE (MI_BASE + 0x00550)
479 #define MI_LUT_LSC_RD_WSIZE (MI_BASE + 0x00554)
480 #define MI_LUT_LDCH_RD_H_WSIZE (MI_BASE + 0x00558)
481 #define MI_LUT_LDCH_RD_V_SIZE (MI_BASE + 0x0055c)
482 #define MI_DBR_WR_BASE (MI_BASE + 0x00560)
483 #define MI_DBR_WR_SIZE (MI_BASE + 0x00564)
484 #define MI_DBR_WR_LENGTH (MI_BASE + 0x00568)
485 #define MI_DBR_WR_BASE_SHD (MI_BASE + 0x0056c)
486 #define MI_DBR_RD_BASE (MI_BASE + 0x00570)
487 #define MI_DBR_RD_LENGTH (MI_BASE + 0x00574)
488 #define MI_DBR_RD_BASE_SHD (MI_BASE + 0x00578)
489 #define MI_SWS_3A_WR_BASE (MI_BASE + 0x0057c)
490 #define MI_GAIN_WR_BASE (MI_BASE + 0x00580)
491 #define MI_GAIN_WR_SIZE (MI_BASE + 0x00584)
492 #define MI_GAIN_WR_LENGTH (MI_BASE + 0x00588)
493 #define MI_GAIN_WR_BASE2 (MI_BASE + 0x0058c)
494 #define MI_GAIN_WR_BASE_SHD (MI_BASE + 0x00590)
495
496 #define ISP21_MI_BAY3D_WR_BASE (MI_BASE + 0x005a0)
497 #define ISP21_MI_BAY3D_WR_SIZE (MI_BASE + 0x005a4)
498 #define ISP21_MI_BAY3D_WR_LENGTH (MI_BASE + 0x005a8)
499 #define ISP21_MI_BAY3D_WR_BASE_SHD (MI_BASE + 0x005ac)
500 #define ISP21_MI_BAY3D_RD_BASE (MI_BASE + 0x005b0)
501 #define ISP21_MI_BAY3D_RD_LENGTH (MI_BASE + 0x005b4)
502 #define ISP21_MI_BAY3D_RD_BASE_SHD (MI_BASE + 0x005b8)
503
504 #define ISP_MPFBC_BASE 0x000018C0
505 #define ISP_MPFBC_CTRL (ISP_MPFBC_BASE + 0x00000)
506 #define ISP_MPFBC_VIR_WIDTH (ISP_MPFBC_BASE + 0x00004)
507 #define ISP_MPFBC_VIR_HEIGHT (ISP_MPFBC_BASE + 0x00008)
508 #define ISP_MPFBC_HEAD_PTR (ISP_MPFBC_BASE + 0x0000c)
509 #define ISP_MPFBC_PAYL_PTR (ISP_MPFBC_BASE + 0x00010)
510 #define ISP_MPFBC_HEAD_PTR2 (ISP_MPFBC_BASE + 0x00014)
511 #define ISP_MPFBC_PAYL_PTR2 (ISP_MPFBC_BASE + 0x00018)
512 #define ISP_MPFBC_ENC_POS (ISP_MPFBC_BASE + 0x00030)
513
514 #define CSI2RX_BASE 0x00001C00
515 #define CSI2RX_CTRL0 (CSI2RX_BASE + 0x00000)
516 #define CSI2RX_CTRL1 (CSI2RX_BASE + 0x00004)
517 #define CSI2RX_CTRL2 (CSI2RX_BASE + 0x00008)
518 #define CSI2RX_CSI2_RESETN (CSI2RX_BASE + 0x00010)
519 #define CSI2RX_PHY_STATE_RO (CSI2RX_BASE + 0x00014)
520 #define CSI2RX_DATA_IDS_1 (CSI2RX_BASE + 0x00018)
521 #define CSI2RX_DATA_IDS_2 (CSI2RX_BASE + 0x0001c)
522 #define CSI2RX_ERR_PHY (CSI2RX_BASE + 0x00020)
523 #define CSI2RX_ERR_PACKET (CSI2RX_BASE + 0x00024)
524 #define CSI2RX_ERR_OVERFLOW (CSI2RX_BASE + 0x00028)
525 #define CSI2RX_ERR_STAT (CSI2RX_BASE + 0x0002c)
526 #define CSI2RX_MASK_PHY (CSI2RX_BASE + 0x00030)
527 #define CSI2RX_MASK_PACKET (CSI2RX_BASE + 0x00034)
528 #define CSI2RX_MASK_OVERFLOW (CSI2RX_BASE + 0x00038)
529 #define CSI2RX_MASK_STAT (CSI2RX_BASE + 0x0003c)
530 #define CSI2RX_RAW0_WR_CTRL (CSI2RX_BASE + 0x00040)
531 #define CSI2RX_RAW0_WR_LINECNT_RO (CSI2RX_BASE + 0x00044)
532 #define CSI2RX_RAW0_WR_PIC_SIZE (CSI2RX_BASE + 0x00048)
533 #define CSI2RX_RAW0_WR_PIC_OFF (CSI2RX_BASE + 0x0004c)
534 #define CSI2RX_RAW1_WR_CTRL (CSI2RX_BASE + 0x00050)
535 #define CSI2RX_RAW1_WR_LINECNT_RO (CSI2RX_BASE + 0x00054)
536 #define CSI2RX_RAW1_WR_PIC_SIZE (CSI2RX_BASE + 0x00058)
537 #define CSI2RX_RAW1_WR_PIC_OFF (CSI2RX_BASE + 0x0005c)
538 #define CSI2RX_RAW2_WR_CTRL (CSI2RX_BASE + 0x00060)
539 #define CSI2RX_RAW2_WR_LINECNT_RO (CSI2RX_BASE + 0x00064)
540 #define CSI2RX_RAW2_WR_PIC_SIZE (CSI2RX_BASE + 0x00068)
541 #define CSI2RX_RAW2_WR_PIC_OFF (CSI2RX_BASE + 0x0006c)
542 #define CSI2RX_RAW3_WR_CTRL (CSI2RX_BASE + 0x00070)
543 #define CSI2RX_RAW3_WR_LINECNT_RO (CSI2RX_BASE + 0x00074)
544 #define CSI2RX_RAW3_WR_PIC_SIZE (CSI2RX_BASE + 0x00078)
545 #define CSI2RX_RAW3_WR_PIC_OFF (CSI2RX_BASE + 0x0007c)
546 #define CSI2RX_RAW_RD_CTRL (CSI2RX_BASE + 0x00080)
547 #define CSI2RX_RAW_RD_LINECNT_RO (CSI2RX_BASE + 0x00084)
548 #define CSI2RX_RAW_RD_PIC_SIZE (CSI2RX_BASE + 0x00088)
549 #define CSI2RX_RAW2_RD_LINECNT_RO (CSI2RX_BASE + 0x0008c)
550 #define CSI2RX_RAWFBC_CTRL (CSI2RX_BASE + 0x00090)
551 #define CSI2RX_ESPHDR_LCNT (CSI2RX_BASE + 0x00094)
552 #define CSI2RX_ESPHDR_IDCD (CSI2RX_BASE + 0x00098)
553 #define CSI2RX_VC0_FRAME_NUM_RO (CSI2RX_BASE + 0x000a0)
554 #define CSI2RX_VC1_FRAME_NUM_RO (CSI2RX_BASE + 0x000a4)
555 #define CSI2RX_VC2_FRAME_NUM_RO (CSI2RX_BASE + 0x000a8)
556 #define CSI2RX_VC3_FRAME_NUM_RO (CSI2RX_BASE + 0x000ac)
557 #define CSI2RX_ISP_LINECNT_RO (CSI2RX_BASE + 0x000b0)
558 #define CSI2RX_RAW_WR_IBUF_STATUS_RO (CSI2RX_BASE + 0x000b4)
559 #define CSI2RX_RAW_WR_IBUF3_STATUS_RO (CSI2RX_BASE + 0x000b8)
560 #define CSI2RX_CUR_HEADER_RO (CSI2RX_BASE + 0x000c4)
561 #define CSI2RX_RAWFBC_EN_SHD (CSI2RX_BASE + 0x000c8)
562 #define CSI2RX_FPN_CTRL (CSI2RX_BASE + 0x000d0)
563 #define CSI2RX_FPN_TABLE_CTRL (CSI2RX_BASE + 0x000d4)
564 #define CSI2RX_FPN_TABLE_DATA (CSI2RX_BASE + 0x000d8)
565 #define CSI2RX_Y_STAT_CTRL (CSI2RX_BASE + 0x000f0)
566 #define CSI2RX_Y_STAT_RO (CSI2RX_BASE + 0x000f4)
567 #define CSI2RX_VERSION (CSI2RX_BASE + 0x000fc)
568
569 #define ISP_LSC_BASE 0x00002200
570 #define ISP_LSC_CTRL (ISP_LSC_BASE + 0x00000)
571 #define ISP_LSC_R_TABLE_ADDR (ISP_LSC_BASE + 0x00004)
572 #define ISP_LSC_GR_TABLE_ADDR (ISP_LSC_BASE + 0x00008)
573 #define ISP_LSC_B_TABLE_ADDR (ISP_LSC_BASE + 0x0000c)
574 #define ISP_LSC_GB_TABLE_ADDR (ISP_LSC_BASE + 0x00010)
575 #define ISP_LSC_R_TABLE_DATA (ISP_LSC_BASE + 0x00014)
576 #define ISP_LSC_GR_TABLE_DATA (ISP_LSC_BASE + 0x00018)
577 #define ISP_LSC_B_TABLE_DATA (ISP_LSC_BASE + 0x0001c)
578 #define ISP_LSC_GB_TABLE_DATA (ISP_LSC_BASE + 0x00020)
579 #define ISP_LSC_XGRAD_01 (ISP_LSC_BASE + 0x00024)
580 #define ISP_LSC_XGRAD_23 (ISP_LSC_BASE + 0x00028)
581 #define ISP_LSC_XGRAD_45 (ISP_LSC_BASE + 0x0002c)
582 #define ISP_LSC_XGRAD_67 (ISP_LSC_BASE + 0x00030)
583 #define ISP_LSC_YGRAD_01 (ISP_LSC_BASE + 0x00034)
584 #define ISP_LSC_YGRAD_23 (ISP_LSC_BASE + 0x00038)
585 #define ISP_LSC_YGRAD_45 (ISP_LSC_BASE + 0x0003c)
586 #define ISP_LSC_YGRAD_67 (ISP_LSC_BASE + 0x00040)
587 #define ISP_LSC_XSIZE_01 (ISP_LSC_BASE + 0x00044)
588 #define ISP_LSC_XSIZE_23 (ISP_LSC_BASE + 0x00048)
589 #define ISP_LSC_XSIZE_45 (ISP_LSC_BASE + 0x0004c)
590 #define ISP_LSC_XSIZE_67 (ISP_LSC_BASE + 0x00050)
591 #define ISP_LSC_YSIZE_01 (ISP_LSC_BASE + 0x00054)
592 #define ISP_LSC_YSIZE_23 (ISP_LSC_BASE + 0x00058)
593 #define ISP_LSC_YSIZE_45 (ISP_LSC_BASE + 0x0005c)
594 #define ISP_LSC_YSIZE_67 (ISP_LSC_BASE + 0x00060)
595 #define ISP_LSC_TABLE_SEL (ISP_LSC_BASE + 0x00064)
596 #define ISP_LSC_STATUS (ISP_LSC_BASE + 0x00068)
597
598 #define ISP_DEBAYER_BASE 0x00002500
599 #define ISP_DEBAYER_CONTROL (ISP_DEBAYER_BASE + 0x00000)
600 #define ISP_DEBAYER_G_INTERP (ISP_DEBAYER_BASE + 0x00004)
601 #define ISP_DEBAYER_G_INTERP_FILTER1 (ISP_DEBAYER_BASE + 0x00008)
602 #define ISP_DEBAYER_G_INTERP_FILTER2 (ISP_DEBAYER_BASE + 0x0000c)
603 #define ISP_DEBAYER_G_FILTER (ISP_DEBAYER_BASE + 0x00010)
604 #define ISP_DEBAYER_C_FILTER (ISP_DEBAYER_BASE + 0x00014)
605
606 #define ISP21_YNR_BASE 0x00002700
607 #define ISP21_YNR_GLOBAL_CTRL (ISP21_YNR_BASE + 0x00000)
608 #define ISP21_YNR_RNR_MAX_R (ISP21_YNR_BASE + 0x00004)
609 #define ISP21_YNR_LOWNR_CTRL0 (ISP21_YNR_BASE + 0x00010)
610 #define ISP21_YNR_LOWNR_CTRL1 (ISP21_YNR_BASE + 0x00014)
611 #define ISP21_YNR_LOWNR_CTRL2 (ISP21_YNR_BASE + 0x00018)
612 #define ISP21_YNR_LOWNR_CTRL3 (ISP21_YNR_BASE + 0x0001c)
613 #define ISP21_YNR_HIGHNR_CTRL0 (ISP21_YNR_BASE + 0x00020)
614 #define ISP21_YNR_HIGHNR_CTRL1 (ISP21_YNR_BASE + 0x00024)
615 #define ISP21_YNR_HIGHNR_BASE_FILTER_WEIGHT (ISP21_YNR_BASE + 0x00028)
616 #define ISP21_YNR_GAUSS1_COEFF (ISP21_YNR_BASE + 0x00030)
617 #define ISP21_YNR_GAUSS2_COEFF (ISP21_YNR_BASE + 0x00034)
618 #define ISP21_YNR_DIRECTION_W_0_3 (ISP21_YNR_BASE + 0x00038)
619 #define ISP21_YNR_DIRECTION_W_4_7 (ISP21_YNR_BASE + 0x0003c)
620 #define ISP21_YNR_SGM_DX_0_1 (ISP21_YNR_BASE + 0x00040)
621 #define ISP21_YNR_SGM_DX_2_3 (ISP21_YNR_BASE + 0x00044)
622 #define ISP21_YNR_SGM_DX_4_5 (ISP21_YNR_BASE + 0x00048)
623 #define ISP21_YNR_SGM_DX_6_7 (ISP21_YNR_BASE + 0x0004c)
624 #define ISP21_YNR_SGM_DX_8_9 (ISP21_YNR_BASE + 0x00050)
625 #define ISP21_YNR_SGM_DX_10_11 (ISP21_YNR_BASE + 0x00055)
626 #define ISP21_YNR_SGM_DX_12_13 (ISP21_YNR_BASE + 0x00058)
627 #define ISP21_YNR_SGM_DX_14_15 (ISP21_YNR_BASE + 0x0005c)
628 #define ISP21_YNR_SGM_DX_16 (ISP21_YNR_BASE + 0x00060)
629 #define ISP21_YNR_LSGM_Y_0_1 (ISP21_YNR_BASE + 0x00070)
630 #define ISP21_YNR_LSGM_Y_2_3 (ISP21_YNR_BASE + 0x00074)
631 #define ISP21_YNR_LSGM_Y_4_5 (ISP21_YNR_BASE + 0x00078)
632 #define ISP21_YNR_LSGM_Y_6_7 (ISP21_YNR_BASE + 0x0007c)
633 #define ISP21_YNR_LSGM_Y_8_9 (ISP21_YNR_BASE + 0x00080)
634 #define ISP21_YNR_LSGM_Y_10_11 (ISP21_YNR_BASE + 0x00084)
635 #define ISP21_YNR_LSGM_Y_12_13 (ISP21_YNR_BASE + 0x00088)
636 #define ISP21_YNR_LSGM_Y_14_15 (ISP21_YNR_BASE + 0x0008c)
637 #define ISP21_YNR_LSGM_Y_16 (ISP21_YNR_BASE + 0x00090)
638 #define ISP21_YNR_HSGM_Y_0_1 (ISP21_YNR_BASE + 0x000a0)
639 #define ISP21_YNR_HSGM_Y_2_3 (ISP21_YNR_BASE + 0x000a4)
640 #define ISP21_YNR_HSGM_Y_4_5 (ISP21_YNR_BASE + 0x000a8)
641 #define ISP21_YNR_HSGM_Y_6_7 (ISP21_YNR_BASE + 0x000ac)
642 #define ISP21_YNR_HSGM_Y_8_9 (ISP21_YNR_BASE + 0x000b0)
643 #define ISP21_YNR_HSGM_Y_10_11 (ISP21_YNR_BASE + 0x000b4)
644 #define ISP21_YNR_HSGM_Y_12_13 (ISP21_YNR_BASE + 0x000b8)
645 #define ISP21_YNR_HSGM_Y_14_15 (ISP21_YNR_BASE + 0x000bc)
646 #define ISP21_YNR_HSGM_Y_16 (ISP21_YNR_BASE + 0x000c0)
647 #define ISP21_YNR_RNR_STRENGTH03 (ISP21_YNR_BASE + 0x000d0)
648 #define ISP21_YNR_RNR_STRENGTH47 (ISP21_YNR_BASE + 0x000d4)
649 #define ISP21_YNR_RNR_STRENGTH8B (ISP21_YNR_BASE + 0x000d8)
650 #define ISP21_YNR_RNR_STRENGTHCF (ISP21_YNR_BASE + 0x000dc)
651 #define ISP21_YNR_RNR_STRENGTH16 (ISP21_YNR_BASE + 0x000e0)
652
653 #define ISP21_CNR_BASE 0x00002800
654 #define ISP21_CNR_CTRL (ISP21_CNR_BASE + 0x00000)
655 #define ISP21_CNR_EXGAIN (ISP21_CNR_BASE + 0x00004)
656 #define ISP21_CNR_GAIN_PARA (ISP21_CNR_BASE + 0x00008)
657 #define ISP21_CNR_GAIN_UV_PARA (ISP21_CNR_BASE + 0x0000c)
658 #define ISP21_CNR_LMED3 (ISP21_CNR_BASE + 0x00010)
659 #define ISP21_CNR_LBF5_GAIN (ISP21_CNR_BASE + 0x00014)
660 #define ISP21_CNR_LBF5_WEITD0_3 (ISP21_CNR_BASE + 0x00018)
661 #define ISP21_CNR_LBF5_WEITD4 (ISP21_CNR_BASE + 0x0001c)
662 #define ISP21_CNR_HMED3 (ISP21_CNR_BASE + 0x00020)
663 #define ISP21_CNR_HBF5 (ISP21_CNR_BASE + 0x00024)
664 #define ISP21_CNR_LBF3 (ISP21_CNR_BASE + 0x00028)
665
666 #define ISP21_SHARP_BASE 0x00002900
667 #define ISP21_SHARP_SHARP_EN (ISP21_SHARP_BASE + 0x00000)
668 #define ISP21_SHARP_SHARP_RATIO (ISP21_SHARP_BASE + 0x00004)
669 #define ISP21_SHARP_SHARP_LUMA_DX (ISP21_SHARP_BASE + 0x00008)
670 #define ISP21_SHARP_SHARP_PBF_SIGMA_INV_0 (ISP21_SHARP_BASE + 0x0000c)
671 #define ISP21_SHARP_SHARP_PBF_SIGMA_INV_1 (ISP21_SHARP_BASE + 0x00010)
672 #define ISP21_SHARP_SHARP_PBF_SIGMA_INV_2 (ISP21_SHARP_BASE + 0x00014)
673 #define ISP21_SHARP_SHARP_BF_SIGMA_INV_0 (ISP21_SHARP_BASE + 0x00018)
674 #define ISP21_SHARP_SHARP_BF_SIGMA_INV_1 (ISP21_SHARP_BASE + 0x0001c)
675 #define ISP21_SHARP_SHARP_BF_SIGMA_INV_2 (ISP21_SHARP_BASE + 0x00020)
676 #define ISP21_SHARP_SHARP_SIGMA_SHIFT (ISP21_SHARP_BASE + 0x00024)
677 #define ISP21_SHARP_SHARP_EHF_TH_0 (ISP21_SHARP_BASE + 0x00028)
678 #define ISP21_SHARP_SHARP_EHF_TH_1 (ISP21_SHARP_BASE + 0x0002c)
679 #define ISP21_SHARP_SHARP_EHF_TH_2 (ISP21_SHARP_BASE + 0x00030)
680 #define ISP21_SHARP_SHARP_CLIP_HF_0 (ISP21_SHARP_BASE + 0x00034)
681 #define ISP21_SHARP_SHARP_CLIP_HF_1 (ISP21_SHARP_BASE + 0x00038)
682 #define ISP21_SHARP_SHARP_CLIP_HF_2 (ISP21_SHARP_BASE + 0x0003c)
683 #define ISP21_SHARP_SHARP_PBF_COEF (ISP21_SHARP_BASE + 0x00040)
684 #define ISP21_SHARP_SHARP_BF_COEF (ISP21_SHARP_BASE + 0x00044)
685 #define ISP21_SHARP_SHARP_GAUS_COEF (ISP21_SHARP_BASE + 0x00048)
686
687 #define ISP_WDR_BASE 0x00002A00
688 #define ISP_WDR_CTRL (ISP_WDR_BASE + 0x00000)
689 #define ISP_WDR_WDR_TONECURVE_DYN1 (ISP_WDR_BASE + 0x00004)
690 #define ISP_WDR_WDR_TONECURVE_DYN2 (ISP_WDR_BASE + 0x00008)
691 #define ISP_WDR_WDR_TONECURVE_DYN3 (ISP_WDR_BASE + 0x0000c)
692 #define ISP_WDR_WDR_TONECURVE_DYN4 (ISP_WDR_BASE + 0x00010)
693 #define ISP_WDR_TONECURVE_YM_0 (ISP_WDR_BASE + 0x00014)
694 #define ISP_WDR_TONECURVE_YM_1 (ISP_WDR_BASE + 0x00018)
695 #define ISP_WDR_TONECURVE_YM_2 (ISP_WDR_BASE + 0x0001c)
696 #define ISP_WDR_TONECURVE_YM_3 (ISP_WDR_BASE + 0x00020)
697 #define ISP_WDR_TONECURVE_YM_4 (ISP_WDR_BASE + 0x00024)
698 #define ISP_WDR_TONECURVE_YM_5 (ISP_WDR_BASE + 0x00028)
699 #define ISP_WDR_TONECURVE_YM_6 (ISP_WDR_BASE + 0x0002c)
700 #define ISP_WDR_TONECURVE_YM_7 (ISP_WDR_BASE + 0x00030)
701 #define ISP_WDR_TONECURVE_YM_8 (ISP_WDR_BASE + 0x00034)
702 #define ISP_WDR_TONECURVE_YM_9 (ISP_WDR_BASE + 0x00038)
703 #define ISP_WDR_TONECURVE_YM_10 (ISP_WDR_BASE + 0x0003c)
704 #define ISP_WDR_TONECURVE_YM_11 (ISP_WDR_BASE + 0x00040)
705 #define ISP_WDR_TONECURVE_YM_12 (ISP_WDR_BASE + 0x00044)
706 #define ISP_WDR_TONECURVE_YM_13 (ISP_WDR_BASE + 0x00048)
707 #define ISP_WDR_TONECURVE_YM_14 (ISP_WDR_BASE + 0x0004c)
708 #define ISP_WDR_TONECURVE_YM_15 (ISP_WDR_BASE + 0x00050)
709 #define ISP_WDR_TONECURVE_YM_16 (ISP_WDR_BASE + 0x00054)
710 #define ISP_WDR_TONECURVE_YM_17 (ISP_WDR_BASE + 0x00058)
711 #define ISP_WDR_TONECURVE_YM_18 (ISP_WDR_BASE + 0x0005c)
712 #define ISP_WDR_TONECURVE_YM_19 (ISP_WDR_BASE + 0x00060)
713 #define ISP_WDR_TONECURVE_YM_20 (ISP_WDR_BASE + 0x00064)
714 #define ISP_WDR_TONECURVE_YM_21 (ISP_WDR_BASE + 0x00068)
715 #define ISP_WDR_TONECURVE_YM_22 (ISP_WDR_BASE + 0x0006c)
716 #define ISP_WDR_TONECURVE_YM_23 (ISP_WDR_BASE + 0x00070)
717 #define ISP_WDR_TONECURVE_YM_24 (ISP_WDR_BASE + 0x00074)
718 #define ISP_WDR_TONECURVE_YM_25 (ISP_WDR_BASE + 0x00078)
719 #define ISP_WDR_TONECURVE_YM_26 (ISP_WDR_BASE + 0x0007c)
720 #define ISP_WDR_TONECURVE_YM_27 (ISP_WDR_BASE + 0x00080)
721 #define ISP_WDR_TONECURVE_YM_28 (ISP_WDR_BASE + 0x00084)
722 #define ISP_WDR_TONECURVE_YM_29 (ISP_WDR_BASE + 0x00088)
723 #define ISP_WDR_TONECURVE_YM_30 (ISP_WDR_BASE + 0x0008c)
724 #define ISP_WDR_TONECURVE_YM_31 (ISP_WDR_BASE + 0x00090)
725 #define ISP_WDR_TONECURVE_YM_32 (ISP_WDR_BASE + 0x00094)
726 #define ISP_WDR_OFFSET (ISP_WDR_BASE + 0x00098)
727 #define ISP_WDR_CTRL0 (ISP_WDR_BASE + 0x00150)
728 #define ISP_WDR_CTRL1 (ISP_WDR_BASE + 0x00154)
729 #define ISP_WDR_BLKOFF0 (ISP_WDR_BASE + 0x00158)
730 #define ISP_WDR_AVGCLIP (ISP_WDR_BASE + 0x0015c)
731 #define ISP_WDR_COE_0 (ISP_WDR_BASE + 0x00160)
732 #define ISP_WDR_COE_1 (ISP_WDR_BASE + 0x00164)
733 #define ISP_WDR_COE_2 (ISP_WDR_BASE + 0x00168)
734 #define ISP_WDR_COE_OFF (ISP_WDR_BASE + 0x0016c)
735 #define ISP_WDR_BLKOFF1 (ISP_WDR_BASE + 0x00174)
736 #define ISP_WDR_BLKMEAN8_ROW0_0TO3 (ISP_WDR_BASE + 0x00180)
737 #define ISP_WDR_BLKMEAN8_ROW0_4TO7 (ISP_WDR_BASE + 0x00184)
738 #define ISP_WDR_BLKMEAN8_ROW1_0TO3 (ISP_WDR_BASE + 0x00188)
739 #define ISP_WDR_BLKMEAN8_ROW1_4TO7 (ISP_WDR_BASE + 0x0018c)
740 #define ISP_WDR_BLKMEAN8_ROW2_0TO3 (ISP_WDR_BASE + 0x00190)
741 #define ISP_WDR_BLKMEAN8_ROW2_4TO7 (ISP_WDR_BASE + 0x00194)
742 #define ISP_WDR_BLKMEAN8_ROW3_0TO3 (ISP_WDR_BASE + 0x00198)
743 #define ISP_WDR_BLKMEAN8_ROW3_4TO7 (ISP_WDR_BASE + 0x0019c)
744 #define ISP_WDR_BLKMEAN8_ROW4_0TO3 (ISP_WDR_BASE + 0x001a0)
745 #define ISP_WDR_BLKMEAN8_ROW4_4TO7 (ISP_WDR_BASE + 0x001a4)
746 #define ISP_WDR_BLKMEAN8_ROW5_0TO3 (ISP_WDR_BASE + 0x001a8)
747 #define ISP_WDR_BLKMEAN8_ROW5_4TO7 (ISP_WDR_BASE + 0x001ac)
748 #define ISP_WDR_BLKMEAN8_ROW6_0TO3 (ISP_WDR_BASE + 0x001b0)
749 #define ISP_WDR_BLKMEAN8_ROW6_4TO7 (ISP_WDR_BASE + 0x001b4)
750 #define ISP_WDR_BLKMEAN8_ROW7_0TO3 (ISP_WDR_BASE + 0x001b8)
751 #define ISP_WDR_BLKMEAN8_ROW7_4TO7 (ISP_WDR_BASE + 0x001bc)
752 #define ISP_WDR_BLKMEAN8_ROW8_0TO3 (ISP_WDR_BASE + 0x001c0)
753 #define ISP_WDR_BLKMEAN8_ROW8_4TO7 (ISP_WDR_BASE + 0x001c4)
754 #define ISP_WDR_BLKMEAN8_ROW9_0TO3 (ISP_WDR_BASE + 0x001c8)
755 #define ISP_WDR_BLKMEAN8_ROW9_4TO7 (ISP_WDR_BASE + 0x001cc)
756
757 #define ISP_GIC_BASE 0x00002F00
758 #define ISP_GIC_CONTROL (ISP_GIC_BASE + 0x00000)
759 #define ISP_GIC_DIFF_PARA1 (ISP_GIC_BASE + 0x00004)
760 #define ISP_GIC_DIFF_PARA2 (ISP_GIC_BASE + 0x00008)
761 #define ISP_GIC_DIFF_PARA3 (ISP_GIC_BASE + 0x0000c)
762 #define ISP_GIC_DIFF_PARA4 (ISP_GIC_BASE + 0x00010)
763 #define ISP_GIC_NOISE_PARA1 (ISP_GIC_BASE + 0x00014)
764 #define ISP_GIC_NOISE_PARA2 (ISP_GIC_BASE + 0x00018)
765 #define ISP_GIC_NOISE_PARA3 (ISP_GIC_BASE + 0x0001c)
766 #define ISP_GIC_SIGMA_VALUE0 (ISP_GIC_BASE + 0x00020)
767 #define ISP_GIC_SIGMA_VALUE1 (ISP_GIC_BASE + 0x00024)
768 #define ISP_GIC_SIGMA_VALUE2 (ISP_GIC_BASE + 0x00028)
769 #define ISP_GIC_SIGMA_VALUE3 (ISP_GIC_BASE + 0x0002c)
770 #define ISP_GIC_SIGMA_VALUE4 (ISP_GIC_BASE + 0x00030)
771 #define ISP_GIC_SIGMA_VALUE5 (ISP_GIC_BASE + 0x00034)
772 #define ISP_GIC_SIGMA_VALUE6 (ISP_GIC_BASE + 0x00038)
773 #define ISP_GIC_SIGMA_VALUE7 (ISP_GIC_BASE + 0x0003c)
774 #define ISP_GIC_NOISE_CTRL0 (ISP_GIC_BASE + 0x00040)
775 #define ISP_GIC_NOISE_CTRL1 (ISP_GIC_BASE + 0x00044)
776
777 #define ISP_BLS_BASE 0x00003000
778 #define ISP_BLS_CTRL (ISP_BLS_BASE + 0x00000)
779 #define ISP_BLS_SAMPLES (ISP_BLS_BASE + 0x00004)
780 #define ISP_BLS_H1_START (ISP_BLS_BASE + 0x00008)
781 #define ISP_BLS_H1_STOP (ISP_BLS_BASE + 0x0000c)
782 #define ISP_BLS_V1_START (ISP_BLS_BASE + 0x00010)
783 #define ISP_BLS_V1_STOP (ISP_BLS_BASE + 0x00014)
784 #define ISP_BLS_H2_START (ISP_BLS_BASE + 0x00018)
785 #define ISP_BLS_H2_STOP (ISP_BLS_BASE + 0x0001c)
786 #define ISP_BLS_V2_START (ISP_BLS_BASE + 0x00020)
787 #define ISP_BLS_V2_STOP (ISP_BLS_BASE + 0x00024)
788 #define ISP_BLS_A_FIXED (ISP_BLS_BASE + 0x00028)
789 #define ISP_BLS_B_FIXED (ISP_BLS_BASE + 0x0002c)
790 #define ISP_BLS_C_FIXED (ISP_BLS_BASE + 0x00030)
791 #define ISP_BLS_D_FIXED (ISP_BLS_BASE + 0x00034)
792 #define ISP_BLS_A_MEASURED (ISP_BLS_BASE + 0x00038)
793 #define ISP_BLS_B_MEASURED (ISP_BLS_BASE + 0x0003c)
794 #define ISP_BLS_C_MEASURED (ISP_BLS_BASE + 0x00040)
795 #define ISP_BLS_D_MEASURED (ISP_BLS_BASE + 0x00044)
796 #define ISP_BLS1_A_FIXED (ISP_BLS_BASE + 0x00048)
797 #define ISP_BLS1_B_FIXED (ISP_BLS_BASE + 0x0004c)
798 #define ISP_BLS1_C_FIXED (ISP_BLS_BASE + 0x00050)
799 #define ISP_BLS1_D_FIXED (ISP_BLS_BASE + 0x00054)
800
801 #define ISP_DPCC0_BASE 0x00003400
802 #define ISP_DPCC1_BASE 0x00003500
803 #define ISP_DPCC2_BASE 0x00003600
804 #define ISP_DPCC0_MODE (ISP_DPCC0_BASE + 0x00000)
805 #define ISP_DPCC0_OUTPUT_MODE (ISP_DPCC0_BASE + 0x00004)
806 #define ISP_DPCC0_SET_USE (ISP_DPCC0_BASE + 0x00008)
807 #define ISP_DPCC0_METHODS_SET_1 (ISP_DPCC0_BASE + 0x0000c)
808 #define ISP_DPCC0_METHODS_SET_2 (ISP_DPCC0_BASE + 0x00010)
809 #define ISP_DPCC0_METHODS_SET_3 (ISP_DPCC0_BASE + 0x00014)
810 #define ISP_DPCC0_LINE_THRESH_1 (ISP_DPCC0_BASE + 0x00018)
811 #define ISP_DPCC0_LINE_MAD_FAC_1 (ISP_DPCC0_BASE + 0x0001c)
812 #define ISP_DPCC0_PG_FAC_1 (ISP_DPCC0_BASE + 0x00020)
813 #define ISP_DPCC0_RND_THRESH_1 (ISP_DPCC0_BASE + 0x00024)
814 #define ISP_DPCC0_RG_FAC_1 (ISP_DPCC0_BASE + 0x00028)
815 #define ISP_DPCC0_LINE_THRESH_2 (ISP_DPCC0_BASE + 0x0002c)
816 #define ISP_DPCC0_LINE_MAD_FAC_2 (ISP_DPCC0_BASE + 0x00030)
817 #define ISP_DPCC0_PG_FAC_2 (ISP_DPCC0_BASE + 0x00034)
818 #define ISP_DPCC0_RND_THRESH_2 (ISP_DPCC0_BASE + 0x00038)
819 #define ISP_DPCC0_RG_FAC_2 (ISP_DPCC0_BASE + 0x0003c)
820 #define ISP_DPCC0_LINE_THRESH_3 (ISP_DPCC0_BASE + 0x00040)
821 #define ISP_DPCC0_LINE_MAD_FAC_3 (ISP_DPCC0_BASE + 0x00044)
822 #define ISP_DPCC0_PG_FAC_3 (ISP_DPCC0_BASE + 0x00048)
823 #define ISP_DPCC0_RND_THRESH_3 (ISP_DPCC0_BASE + 0x0004c)
824 #define ISP_DPCC0_RG_FAC_3 (ISP_DPCC0_BASE + 0x00050)
825 #define ISP_DPCC0_RO_LIMITS (ISP_DPCC0_BASE + 0x00054)
826 #define ISP_DPCC0_RND_OFFS (ISP_DPCC0_BASE + 0x00058)
827 #define ISP_DPCC0_BPT_CTRL (ISP_DPCC0_BASE + 0x0005c)
828 #define ISP_DPCC0_BPT_NUMBER (ISP_DPCC0_BASE + 0x00060)
829 #define ISP_DPCC0_BPT_ADDR (ISP_DPCC0_BASE + 0x00064)
830 #define ISP_DPCC0_BPT_DATA (ISP_DPCC0_BASE + 0x00068)
831 #define ISP_DPCC0_BP_CNT (ISP_DPCC0_BASE + 0x0006c)
832 #define ISP_DPCC0_PDAF_EN (ISP_DPCC0_BASE + 0x00070)
833 #define ISP_DPCC0_PDAF_POINT_EN (ISP_DPCC0_BASE + 0x00074)
834 #define ISP_DPCC0_PDAF_OFFSET (ISP_DPCC0_BASE + 0x00078)
835 #define ISP_DPCC0_PDAF_WRAP (ISP_DPCC0_BASE + 0x0007c)
836 #define ISP_DPCC0_PDAF_SCOPE (ISP_DPCC0_BASE + 0x00080)
837 #define ISP_DPCC0_PDAF_POINT_0 (ISP_DPCC0_BASE + 0x00084)
838 #define ISP_DPCC0_PDAF_POINT_1 (ISP_DPCC0_BASE + 0x00088)
839 #define ISP_DPCC0_PDAF_POINT_2 (ISP_DPCC0_BASE + 0x0008c)
840 #define ISP_DPCC0_PDAF_POINT_3 (ISP_DPCC0_BASE + 0x00090)
841 #define ISP_DPCC0_PDAF_POINT_4 (ISP_DPCC0_BASE + 0x00094)
842 #define ISP_DPCC0_PDAF_POINT_5 (ISP_DPCC0_BASE + 0x00098)
843 #define ISP_DPCC0_PDAF_POINT_6 (ISP_DPCC0_BASE + 0x0009c)
844 #define ISP_DPCC0_PDAF_POINT_7 (ISP_DPCC0_BASE + 0x000a0)
845 #define ISP_DPCC0_PDAF_FORWARD_MED (ISP_DPCC0_BASE + 0x000a4)
846
847 #define ISP_DPCC1_MODE (ISP_DPCC1_BASE + 0x00000)
848 #define ISP_DPCC1_OUTPUT_MODE (ISP_DPCC1_BASE + 0x00004)
849 #define ISP_DPCC1_SET_USE (ISP_DPCC1_BASE + 0x00008)
850 #define ISP_DPCC1_METHODS_SET_1 (ISP_DPCC1_BASE + 0x0000c)
851 #define ISP_DPCC1_METHODS_SET_2 (ISP_DPCC1_BASE + 0x00010)
852 #define ISP_DPCC1_METHODS_SET_3 (ISP_DPCC1_BASE + 0x00014)
853 #define ISP_DPCC1_LINE_THRESH_1 (ISP_DPCC1_BASE + 0x00018)
854 #define ISP_DPCC1_LINE_MAD_FAC_1 (ISP_DPCC1_BASE + 0x0001c)
855 #define ISP_DPCC1_PG_FAC_1 (ISP_DPCC1_BASE + 0x00020)
856 #define ISP_DPCC1_RND_THRESH_1 (ISP_DPCC1_BASE + 0x00024)
857 #define ISP_DPCC1_RG_FAC_1 (ISP_DPCC1_BASE + 0x00028)
858 #define ISP_DPCC1_LINE_THRESH_2 (ISP_DPCC1_BASE + 0x0002c)
859 #define ISP_DPCC1_LINE_MAD_FAC_2 (ISP_DPCC1_BASE + 0x00030)
860 #define ISP_DPCC1_PG_FAC_2 (ISP_DPCC1_BASE + 0x00034)
861 #define ISP_DPCC1_RND_THRESH_2 (ISP_DPCC1_BASE + 0x00038)
862 #define ISP_DPCC1_RG_FAC_2 (ISP_DPCC1_BASE + 0x0003c)
863 #define ISP_DPCC1_LINE_THRESH_3 (ISP_DPCC1_BASE + 0x00040)
864 #define ISP_DPCC1_LINE_MAD_FAC_3 (ISP_DPCC1_BASE + 0x00044)
865 #define ISP_DPCC1_PG_FAC_3 (ISP_DPCC1_BASE + 0x00048)
866 #define ISP_DPCC1_RND_THRESH_3 (ISP_DPCC1_BASE + 0x0004c)
867 #define ISP_DPCC1_RG_FAC_3 (ISP_DPCC1_BASE + 0x00050)
868 #define ISP_DPCC1_RO_LIMITS (ISP_DPCC1_BASE + 0x00054)
869 #define ISP_DPCC1_RND_OFFS (ISP_DPCC1_BASE + 0x00058)
870 #define ISP_DPCC1_BPT_CTRL (ISP_DPCC1_BASE + 0x0005c)
871 #define ISP_DPCC1_BPT_NUMBER (ISP_DPCC1_BASE + 0x00060)
872 #define ISP_DPCC1_BPT_ADDR (ISP_DPCC1_BASE + 0x00064)
873 #define ISP_DPCC1_BPT_DATA (ISP_DPCC1_BASE + 0x00068)
874 #define ISP_DPCC1_BP_CNT (ISP_DPCC1_BASE + 0x0006c)
875 #define ISP_DPCC1_PDAF_EN (ISP_DPCC1_BASE + 0x00070)
876 #define ISP_DPCC1_PDAF_POINT_EN (ISP_DPCC1_BASE + 0x00074)
877 #define ISP_DPCC1_PDAF_OFFSET (ISP_DPCC1_BASE + 0x00078)
878 #define ISP_DPCC1_PDAF_WRAP (ISP_DPCC1_BASE + 0x0007c)
879 #define ISP_DPCC1_PDAF_SCOPE (ISP_DPCC1_BASE + 0x00080)
880 #define ISP_DPCC1_PDAF_POINT_0 (ISP_DPCC1_BASE + 0x00084)
881 #define ISP_DPCC1_PDAF_POINT_1 (ISP_DPCC1_BASE + 0x00088)
882 #define ISP_DPCC1_PDAF_POINT_2 (ISP_DPCC1_BASE + 0x0008c)
883 #define ISP_DPCC1_PDAF_POINT_3 (ISP_DPCC1_BASE + 0x00090)
884 #define ISP_DPCC1_PDAF_POINT_4 (ISP_DPCC1_BASE + 0x00094)
885 #define ISP_DPCC1_PDAF_POINT_5 (ISP_DPCC1_BASE + 0x00098)
886 #define ISP_DPCC1_PDAF_POINT_6 (ISP_DPCC1_BASE + 0x0009c)
887 #define ISP_DPCC1_PDAF_POINT_7 (ISP_DPCC1_BASE + 0x000a0)
888 #define ISP_DPCC1_PDAF_FORWARD_MED (ISP_DPCC1_BASE + 0x000a4)
889
890 #define ISP_DPCC2_MODE (ISP_DPCC2_BASE + 0x00000)
891 #define ISP_DPCC2_OUTPUT_MODE (ISP_DPCC2_BASE + 0x00004)
892 #define ISP_DPCC2_SET_USE (ISP_DPCC2_BASE + 0x00008)
893 #define ISP_DPCC2_METHODS_SET_1 (ISP_DPCC2_BASE + 0x0000c)
894 #define ISP_DPCC2_METHODS_SET_2 (ISP_DPCC2_BASE + 0x00010)
895 #define ISP_DPCC2_METHODS_SET_3 (ISP_DPCC2_BASE + 0x00014)
896 #define ISP_DPCC2_LINE_THRESH_1 (ISP_DPCC2_BASE + 0x00018)
897 #define ISP_DPCC2_LINE_MAD_FAC_1 (ISP_DPCC2_BASE + 0x0001c)
898 #define ISP_DPCC2_PG_FAC_1 (ISP_DPCC2_BASE + 0x00020)
899 #define ISP_DPCC2_RND_THRESH_1 (ISP_DPCC2_BASE + 0x00024)
900 #define ISP_DPCC2_RG_FAC_1 (ISP_DPCC2_BASE + 0x00028)
901 #define ISP_DPCC2_LINE_THRESH_2 (ISP_DPCC2_BASE + 0x0002c)
902 #define ISP_DPCC2_LINE_MAD_FAC_2 (ISP_DPCC2_BASE + 0x00030)
903 #define ISP_DPCC2_PG_FAC_2 (ISP_DPCC2_BASE + 0x00034)
904 #define ISP_DPCC2_RND_THRESH_2 (ISP_DPCC2_BASE + 0x00038)
905 #define ISP_DPCC2_RG_FAC_2 (ISP_DPCC2_BASE + 0x0003c)
906 #define ISP_DPCC2_LINE_THRESH_3 (ISP_DPCC2_BASE + 0x00040)
907 #define ISP_DPCC2_LINE_MAD_FAC_3 (ISP_DPCC2_BASE + 0x00044)
908 #define ISP_DPCC2_PG_FAC_3 (ISP_DPCC2_BASE + 0x00048)
909 #define ISP_DPCC2_RND_THRESH_3 (ISP_DPCC2_BASE + 0x0004c)
910 #define ISP_DPCC2_RG_FAC_3 (ISP_DPCC2_BASE + 0x00050)
911 #define ISP_DPCC2_RO_LIMITS (ISP_DPCC2_BASE + 0x00054)
912 #define ISP_DPCC2_RND_OFFS (ISP_DPCC2_BASE + 0x00058)
913 #define ISP_DPCC2_BPT_CTRL (ISP_DPCC2_BASE + 0x0005c)
914 #define ISP_DPCC2_BPT_NUMBER (ISP_DPCC2_BASE + 0x00060)
915 #define ISP_DPCC2_BPT_ADDR (ISP_DPCC2_BASE + 0x00064)
916 #define ISP_DPCC2_BPT_DATA (ISP_DPCC2_BASE + 0x00068)
917 #define ISP_DPCC2_BP_CNT (ISP_DPCC2_BASE + 0x0006c)
918 #define ISP_DPCC2_PDAF_EN (ISP_DPCC2_BASE + 0x00070)
919 #define ISP_DPCC2_PDAF_POINT_EN (ISP_DPCC2_BASE + 0x00074)
920 #define ISP_DPCC2_PDAF_OFFSET (ISP_DPCC2_BASE + 0x00078)
921 #define ISP_DPCC2_PDAF_WRAP (ISP_DPCC2_BASE + 0x0007c)
922 #define ISP_DPCC2_PDAF_SCOPE (ISP_DPCC2_BASE + 0x00080)
923 #define ISP_DPCC2_PDAF_POINT_0 (ISP_DPCC2_BASE + 0x00084)
924 #define ISP_DPCC2_PDAF_POINT_1 (ISP_DPCC2_BASE + 0x00088)
925 #define ISP_DPCC2_PDAF_POINT_2 (ISP_DPCC2_BASE + 0x0008c)
926 #define ISP_DPCC2_PDAF_POINT_3 (ISP_DPCC2_BASE + 0x00090)
927 #define ISP_DPCC2_PDAF_POINT_4 (ISP_DPCC2_BASE + 0x00094)
928 #define ISP_DPCC2_PDAF_POINT_5 (ISP_DPCC2_BASE + 0x00098)
929 #define ISP_DPCC2_PDAF_POINT_6 (ISP_DPCC2_BASE + 0x0009c)
930 #define ISP_DPCC2_PDAF_POINT_7 (ISP_DPCC2_BASE + 0x000a0)
931 #define ISP_DPCC2_PDAF_FORWARD_MED (ISP_DPCC2_BASE + 0x000a4)
932
933 #define ISP_HDRMGE_BASE 0x00003800
934 #define ISP_HDRMGE_CTRL (ISP_HDRMGE_BASE + 0x00000)
935 #define ISP_HDRMGE_GAIN0 (ISP_HDRMGE_BASE + 0x00008)
936 #define ISP_HDRMGE_GAIN1 (ISP_HDRMGE_BASE + 0x0000c)
937 #define ISP_HDRMGE_GAIN2 (ISP_HDRMGE_BASE + 0x00010)
938 #define ISP_HDRMGE_CONS_DIFF (ISP_HDRMGE_BASE + 0x00014)
939 #define ISP_HDRMGE_DIFF_Y0 (ISP_HDRMGE_BASE + 0x00020)
940 #define ISP_HDRMGE_DIFF_Y1 (ISP_HDRMGE_BASE + 0x00024)
941 #define ISP_HDRMGE_DIFF_Y2 (ISP_HDRMGE_BASE + 0x00028)
942 #define ISP_HDRMGE_DIFF_Y3 (ISP_HDRMGE_BASE + 0x0002c)
943 #define ISP_HDRMGE_DIFF_Y4 (ISP_HDRMGE_BASE + 0x00030)
944 #define ISP_HDRMGE_DIFF_Y5 (ISP_HDRMGE_BASE + 0x00034)
945 #define ISP_HDRMGE_DIFF_Y6 (ISP_HDRMGE_BASE + 0x00038)
946 #define ISP_HDRMGE_DIFF_Y7 (ISP_HDRMGE_BASE + 0x0003c)
947 #define ISP_HDRMGE_DIFF_Y8 (ISP_HDRMGE_BASE + 0x00040)
948 #define ISP_HDRMGE_DIFF_Y9 (ISP_HDRMGE_BASE + 0x00044)
949 #define ISP_HDRMGE_DIFF_Y10 (ISP_HDRMGE_BASE + 0x00048)
950 #define ISP_HDRMGE_DIFF_Y11 (ISP_HDRMGE_BASE + 0x0004c)
951 #define ISP_HDRMGE_DIFF_Y12 (ISP_HDRMGE_BASE + 0x00050)
952 #define ISP_HDRMGE_DIFF_Y13 (ISP_HDRMGE_BASE + 0x00054)
953 #define ISP_HDRMGE_DIFF_Y14 (ISP_HDRMGE_BASE + 0x00058)
954 #define ISP_HDRMGE_DIFF_Y15 (ISP_HDRMGE_BASE + 0x0005c)
955 #define ISP_HDRMGE_DIFF_Y16 (ISP_HDRMGE_BASE + 0x00060)
956 #define ISP_HDRMGE_OVER_Y0 (ISP_HDRMGE_BASE + 0x00070)
957 #define ISP_HDRMGE_OVER_Y1 (ISP_HDRMGE_BASE + 0x00074)
958 #define ISP_HDRMGE_OVER_Y2 (ISP_HDRMGE_BASE + 0x00078)
959 #define ISP_HDRMGE_OVER_Y3 (ISP_HDRMGE_BASE + 0x0007c)
960 #define ISP_HDRMGE_OVER_Y4 (ISP_HDRMGE_BASE + 0x00080)
961 #define ISP_HDRMGE_OVER_Y5 (ISP_HDRMGE_BASE + 0x00084)
962 #define ISP_HDRMGE_OVER_Y6 (ISP_HDRMGE_BASE + 0x00088)
963 #define ISP_HDRMGE_OVER_Y7 (ISP_HDRMGE_BASE + 0x0008c)
964 #define ISP_HDRMGE_OVER_Y8 (ISP_HDRMGE_BASE + 0x00090)
965 #define ISP_HDRMGE_OVER_Y9 (ISP_HDRMGE_BASE + 0x00094)
966 #define ISP_HDRMGE_OVER_Y10 (ISP_HDRMGE_BASE + 0x00098)
967 #define ISP_HDRMGE_OVER_Y11 (ISP_HDRMGE_BASE + 0x0009c)
968 #define ISP_HDRMGE_OVER_Y12 (ISP_HDRMGE_BASE + 0x000a0)
969 #define ISP_HDRMGE_OVER_Y13 (ISP_HDRMGE_BASE + 0x000a4)
970 #define ISP_HDRMGE_OVER_Y14 (ISP_HDRMGE_BASE + 0x000a8)
971 #define ISP_HDRMGE_OVER_Y15 (ISP_HDRMGE_BASE + 0x000ac)
972 #define ISP_HDRMGE_OVER_Y16 (ISP_HDRMGE_BASE + 0x000b0)
973
974 #define ISP_HDRTMO_BASE 0x00003900
975 #define ISP_HDRTMO_CTRL (ISP_HDRTMO_BASE + 0x00000)
976 #define ISP_HDRTMO_CTRL_CFG (ISP_HDRTMO_BASE + 0x00004)
977 #define ISP_HDRTMO_LG_CFG0 (ISP_HDRTMO_BASE + 0x00008)
978 #define ISP_HDRTMO_LG_CFG1 (ISP_HDRTMO_BASE + 0x0000c)
979 #define ISP_HDRTMO_LG_CFG2 (ISP_HDRTMO_BASE + 0x00010)
980 #define ISP_HDRTMO_LG_CFG3 (ISP_HDRTMO_BASE + 0x00014)
981 #define ISP_HDRTMO_LG_CFG4 (ISP_HDRTMO_BASE + 0x00018)
982 #define ISP_HDRTMO_CLIPRATIO (ISP_HDRTMO_BASE + 0x00020)
983 #define ISP_HDRTMO_LG_SCL (ISP_HDRTMO_BASE + 0x00024)
984 #define ISP_HDRTMO_LG_MAX (ISP_HDRTMO_BASE + 0x00028)
985 #define ISP_HDRTMO_HIST_LOW (ISP_HDRTMO_BASE + 0x0002c)
986 #define ISP_HDRTMO_HIST_HIGH (ISP_HDRTMO_BASE + 0x00030)
987 #define ISP_HDRTMO_PALPHA (ISP_HDRTMO_BASE + 0x00034)
988 #define ISP_HDRTMO_MAXGAIN (ISP_HDRTMO_BASE + 0x00038)
989 #define ISP_HDRTMO_LG_RO0 (ISP_HDRTMO_BASE + 0x00040)
990 #define ISP_HDRTMO_LG_RO1 (ISP_HDRTMO_BASE + 0x00044)
991 #define ISP_HDRTMO_LG_RO2 (ISP_HDRTMO_BASE + 0x00048)
992 #define ISP_HDRTMO_LG_RO3 (ISP_HDRTMO_BASE + 0x0004c)
993 #define ISP_HDRTMO_LG_RO4 (ISP_HDRTMO_BASE + 0x00050)
994 #define ISP_HDRTMO_LG_RO5 (ISP_HDRTMO_BASE + 0x00054)
995 #define ISP_HDRTMO_HIST_RO0 (ISP_HDRTMO_BASE + 0x00060)
996 #define ISP_HDRTMO_HIST_RO1 (ISP_HDRTMO_BASE + 0x00064)
997 #define ISP_HDRTMO_HIST_RO2 (ISP_HDRTMO_BASE + 0x00068)
998 #define ISP_HDRTMO_HIST_RO3 (ISP_HDRTMO_BASE + 0x0006c)
999 #define ISP_HDRTMO_HIST_RO4 (ISP_HDRTMO_BASE + 0x00070)
1000 #define ISP_HDRTMO_HIST_RO5 (ISP_HDRTMO_BASE + 0x00074)
1001 #define ISP_HDRTMO_HIST_RO6 (ISP_HDRTMO_BASE + 0x00078)
1002 #define ISP_HDRTMO_HIST_RO7 (ISP_HDRTMO_BASE + 0x0007c)
1003 #define ISP_HDRTMO_HIST_RO8 (ISP_HDRTMO_BASE + 0x00080)
1004 #define ISP_HDRTMO_HIST_RO9 (ISP_HDRTMO_BASE + 0x00084)
1005 #define ISP_HDRTMO_HIST_RO10 (ISP_HDRTMO_BASE + 0x00088)
1006 #define ISP_HDRTMO_HIST_RO11 (ISP_HDRTMO_BASE + 0x0008c)
1007 #define ISP_HDRTMO_HIST_RO12 (ISP_HDRTMO_BASE + 0x00090)
1008 #define ISP_HDRTMO_HIST_RO13 (ISP_HDRTMO_BASE + 0x00094)
1009 #define ISP_HDRTMO_HIST_RO14 (ISP_HDRTMO_BASE + 0x00098)
1010 #define ISP_HDRTMO_HIST_RO15 (ISP_HDRTMO_BASE + 0x0009c)
1011 #define ISP_HDRTMO_HIST_RO16 (ISP_HDRTMO_BASE + 0x000a0)
1012 #define ISP_HDRTMO_HIST_RO17 (ISP_HDRTMO_BASE + 0x000a4)
1013 #define ISP_HDRTMO_HIST_RO18 (ISP_HDRTMO_BASE + 0x000a8)
1014 #define ISP_HDRTMO_HIST_RO19 (ISP_HDRTMO_BASE + 0x000ac)
1015 #define ISP_HDRTMO_HIST_RO20 (ISP_HDRTMO_BASE + 0x000b0)
1016 #define ISP_HDRTMO_HIST_RO21 (ISP_HDRTMO_BASE + 0x000b4)
1017 #define ISP_HDRTMO_HIST_RO22 (ISP_HDRTMO_BASE + 0x000b8)
1018 #define ISP_HDRTMO_HIST_RO23 (ISP_HDRTMO_BASE + 0x000bc)
1019 #define ISP_HDRTMO_HIST_RO24 (ISP_HDRTMO_BASE + 0x000c0)
1020 #define ISP_HDRTMO_HIST_RO25 (ISP_HDRTMO_BASE + 0x000c4)
1021 #define ISP_HDRTMO_HIST_RO26 (ISP_HDRTMO_BASE + 0x000c8)
1022 #define ISP_HDRTMO_HIST_RO27 (ISP_HDRTMO_BASE + 0x000cc)
1023 #define ISP_HDRTMO_HIST_RO28 (ISP_HDRTMO_BASE + 0x000d0)
1024 #define ISP_HDRTMO_HIST_RO29 (ISP_HDRTMO_BASE + 0x000d4)
1025 #define ISP_HDRTMO_HIST_RO30 (ISP_HDRTMO_BASE + 0x000d8)
1026 #define ISP_HDRTMO_HIST_RO31 (ISP_HDRTMO_BASE + 0x000dc)
1027
1028 #define ISP21_DRC_BASE 0x00003900
1029 #define ISP21_DRC_CTRL0 (ISP21_DRC_BASE + 0x00000)
1030 #define ISP21_DRC_CTRL1 (ISP21_DRC_BASE + 0x00004)
1031 #define ISP21_DRC_LPRATIO (ISP21_DRC_BASE + 0x00008)
1032 #define ISP21_DRC_EXPLRATIO (ISP21_DRC_BASE + 0x0000c)
1033 #define ISP21_DRC_SIGMA (ISP21_DRC_BASE + 0x00010)
1034 #define ISP21_DRC_SPACESGM (ISP21_DRC_BASE + 0x00014)
1035 #define ISP21_DRC_RANESGM (ISP21_DRC_BASE + 0x00018)
1036 #define ISP21_DRC_BILAT (ISP21_DRC_BASE + 0x0001c)
1037 #define ISP21_DRC_GAIN_Y0 (ISP21_DRC_BASE + 0x00020)
1038 #define ISP21_DRC_GAIN_Y1 (ISP21_DRC_BASE + 0x00024)
1039 #define ISP21_DRC_GAIN_Y2 (ISP21_DRC_BASE + 0x00028)
1040 #define ISP21_DRC_GAIN_Y3 (ISP21_DRC_BASE + 0x0002c)
1041 #define ISP21_DRC_GAIN_Y4 (ISP21_DRC_BASE + 0x00030)
1042 #define ISP21_DRC_GAIN_Y5 (ISP21_DRC_BASE + 0x00034)
1043 #define ISP21_DRC_GAIN_Y6 (ISP21_DRC_BASE + 0x00038)
1044 #define ISP21_DRC_GAIN_Y7 (ISP21_DRC_BASE + 0x0003c)
1045 #define ISP21_DRC_GAIN_Y8 (ISP21_DRC_BASE + 0x00040)
1046 #define ISP21_DRC_COMPRES_Y0 (ISP21_DRC_BASE + 0x00044)
1047 #define ISP21_DRC_COMPRES_Y1 (ISP21_DRC_BASE + 0x00048)
1048 #define ISP21_DRC_COMPRES_Y2 (ISP21_DRC_BASE + 0x0004c)
1049 #define ISP21_DRC_COMPRES_Y3 (ISP21_DRC_BASE + 0x00050)
1050 #define ISP21_DRC_COMPRES_Y4 (ISP21_DRC_BASE + 0x00054)
1051 #define ISP21_DRC_COMPRES_Y5 (ISP21_DRC_BASE + 0x00058)
1052 #define ISP21_DRC_COMPRES_Y6 (ISP21_DRC_BASE + 0x0005c)
1053 #define ISP21_DRC_COMPRES_Y7 (ISP21_DRC_BASE + 0x00060)
1054 #define ISP21_DRC_COMPRES_Y8 (ISP21_DRC_BASE + 0x00064)
1055 #define ISP21_DRC_SCALE_Y0 (ISP21_DRC_BASE + 0x00068)
1056 #define ISP21_DRC_SCALE_Y1 (ISP21_DRC_BASE + 0x0006c)
1057 #define ISP21_DRC_SCALE_Y2 (ISP21_DRC_BASE + 0x00070)
1058 #define ISP21_DRC_SCALE_Y3 (ISP21_DRC_BASE + 0x00074)
1059 #define ISP21_DRC_SCALE_Y4 (ISP21_DRC_BASE + 0x00078)
1060 #define ISP21_DRC_SCALE_Y5 (ISP21_DRC_BASE + 0x0007c)
1061 #define ISP21_DRC_SCALE_Y6 (ISP21_DRC_BASE + 0x00080)
1062 #define ISP21_DRC_SCALE_Y7 (ISP21_DRC_BASE + 0x00084)
1063 #define ISP21_DRC_SCALE_Y8 (ISP21_DRC_BASE + 0x00088)
1064 #define ISP21_DRC_IIRWG_GAIN (ISP21_DRC_BASE + 0x0008c)
1065
1066 #define ISP_RAWNR_BASE 0x00003A00
1067 #define ISP_RAWNR_CTRL (ISP_RAWNR_BASE + 0x00000)
1068 #define ISP_RAWNR_FILTPAR0 (ISP_RAWNR_BASE + 0x00008)
1069 #define ISP_RAWNR_FILTPAR1 (ISP_RAWNR_BASE + 0x0000c)
1070 #define ISP_RAWNR_FILTPAR2 (ISP_RAWNR_BASE + 0x00010)
1071 #define ISP_RAWNR_DGAIN0 (ISP_RAWNR_BASE + 0x00014)
1072 #define ISP_RAWNR_DGAIN1 (ISP_RAWNR_BASE + 0x00018)
1073 #define ISP_RAWNR_DGAIN2 (ISP_RAWNR_BASE + 0x0001c)
1074 #define ISP_RAWNR_LURTION0_1 (ISP_RAWNR_BASE + 0x00020)
1075 #define ISP_RAWNR_LURTION3_2 (ISP_RAWNR_BASE + 0x00024)
1076 #define ISP_RAWNR_LURTION5_4 (ISP_RAWNR_BASE + 0x00028)
1077 #define ISP_RAWNR_LURTION6_7 (ISP_RAWNR_BASE + 0x0002c)
1078 #define ISP_RAWNR_LULEVEL0_1 (ISP_RAWNR_BASE + 0x00030)
1079 #define ISP_RAWNR_LULEVEL2_3 (ISP_RAWNR_BASE + 0x00034)
1080 #define ISP_RAWNR_LULEVEL4_5 (ISP_RAWNR_BASE + 0x00038)
1081 #define ISP_RAWNR_LULEVEL6_7 (ISP_RAWNR_BASE + 0x0003c)
1082 #define ISP_RAWNR_GAUSS (ISP_RAWNR_BASE + 0x00040)
1083 #define ISP_RAWNR_SIGMA (ISP_RAWNR_BASE + 0x00044)
1084 #define ISP_RAWNR_PIX_DIFF (ISP_RAWNR_BASE + 0x00048)
1085 #define ISP_RAWNR_HILD_DIFF (ISP_RAWNR_BASE + 0x0004c)
1086 #define ISP_RAWNR_THLD_CHANELW (ISP_RAWNR_BASE + 0x00050)
1087 #define ISP_RAWNR_LAMDA (ISP_RAWNR_BASE + 0x00054)
1088 #define ISP_RAWNR_FIXW0_1 (ISP_RAWNR_BASE + 0x00058)
1089 #define ISP_RAWNR_FIXW2_3 (ISP_RAWNR_BASE + 0x0005c)
1090 #define ISP_RAWNR_WLAMDA0 (ISP_RAWNR_BASE + 0x00060)
1091 #define ISP_RAWNR_WLAMDA1 (ISP_RAWNR_BASE + 0x00064)
1092 #define ISP_RAWNR_WLAMDA2 (ISP_RAWNR_BASE + 0x00068)
1093 #define ISP_RAWNR_RGBAIN_FLIP (ISP_RAWNR_BASE + 0x0006c)
1094
1095 #define ISP21_BAYNR_CTRL (ISP_RAWNR_BASE + 0x00000)
1096 #define ISP21_BAYNR_DGAIN0 (ISP_RAWNR_BASE + 0x00004)
1097 #define ISP21_BAYNR_DGAIN1 (ISP_RAWNR_BASE + 0x00008)
1098 #define ISP21_BAYNR_PIXDIFF (ISP_RAWNR_BASE + 0x0000c)
1099 #define ISP21_BAYNR_THLD (ISP_RAWNR_BASE + 0x00010)
1100 #define ISP21_BAYNR_W1_STRENG (ISP_RAWNR_BASE + 0x00014)
1101 #define ISP21_BAYNR_SIGMAX01 (ISP_RAWNR_BASE + 0x00018)
1102 #define ISP21_BAYNR_SIGMAX23 (ISP_RAWNR_BASE + 0x0001c)
1103 #define ISP21_BAYNR_SIGMAX45 (ISP_RAWNR_BASE + 0x00020)
1104 #define ISP21_BAYNR_SIGMAX67 (ISP_RAWNR_BASE + 0x00024)
1105 #define ISP21_BAYNR_SIGMAX89 (ISP_RAWNR_BASE + 0x00028)
1106 #define ISP21_BAYNR_SIGMAX1011 (ISP_RAWNR_BASE + 0x0002c)
1107 #define ISP21_BAYNR_SIGMAX1213 (ISP_RAWNR_BASE + 0x00030)
1108 #define ISP21_BAYNR_SIGMAX1415 (ISP_RAWNR_BASE + 0x00034)
1109 #define ISP21_BAYNR_SIGMAY01 (ISP_RAWNR_BASE + 0x00038)
1110 #define ISP21_BAYNR_SIGMAY23 (ISP_RAWNR_BASE + 0x0003c)
1111 #define ISP21_BAYNR_SIGMAY45 (ISP_RAWNR_BASE + 0x00040)
1112 #define ISP21_BAYNR_SIGMAY67 (ISP_RAWNR_BASE + 0x00044)
1113 #define ISP21_BAYNR_SIGMAY89 (ISP_RAWNR_BASE + 0x00048)
1114 #define ISP21_BAYNR_SIGMAY1011 (ISP_RAWNR_BASE + 0x0004c)
1115 #define ISP21_BAYNR_SIGMAY1213 (ISP_RAWNR_BASE + 0x00050)
1116 #define ISP21_BAYNR_SIGMAY1415 (ISP_RAWNR_BASE + 0x00054)
1117 #define ISP21_BAYNR_WRIT_D (ISP_RAWNR_BASE + 0x00058)
1118
1119 #define ISP21_BAY3D_BASE 0x00003A00
1120 #define ISP21_BAY3D_CTRL (ISP21_BAY3D_BASE + 0x00080)
1121 #define ISP21_BAY3D_KALRATIO (ISP21_BAY3D_BASE + 0x00084)
1122 #define ISP21_BAY3D_GLBPK2 (ISP21_BAY3D_BASE + 0x00088)
1123 #define ISP21_BAY3D_KALSTR (ISP21_BAY3D_BASE + 0x0008c)
1124 #define ISP21_BAY3D_WGTLMT (ISP21_BAY3D_BASE + 0x00090)
1125 #define ISP21_BAY3D_SIG_X0 (ISP21_BAY3D_BASE + 0x00094)
1126 #define ISP21_BAY3D_SIG_X1 (ISP21_BAY3D_BASE + 0x00098)
1127 #define ISP21_BAY3D_SIG_X2 (ISP21_BAY3D_BASE + 0x0009c)
1128 #define ISP21_BAY3D_SIG_X3 (ISP21_BAY3D_BASE + 0x000a0)
1129 #define ISP21_BAY3D_SIG_X4 (ISP21_BAY3D_BASE + 0x000a4)
1130 #define ISP21_BAY3D_SIG_X5 (ISP21_BAY3D_BASE + 0x000a8)
1131 #define ISP21_BAY3D_SIG_X6 (ISP21_BAY3D_BASE + 0x000ac)
1132 #define ISP21_BAY3D_SIG_X7 (ISP21_BAY3D_BASE + 0x000b0)
1133 #define ISP21_BAY3D_SIG_Y0 (ISP21_BAY3D_BASE + 0x000b4)
1134 #define ISP21_BAY3D_SIG_Y1 (ISP21_BAY3D_BASE + 0x000b8)
1135 #define ISP21_BAY3D_SIG_Y2 (ISP21_BAY3D_BASE + 0x000bc)
1136 #define ISP21_BAY3D_SIG_Y3 (ISP21_BAY3D_BASE + 0x000c0)
1137 #define ISP21_BAY3D_SIG_Y4 (ISP21_BAY3D_BASE + 0x000c4)
1138 #define ISP21_BAY3D_SIG_Y5 (ISP21_BAY3D_BASE + 0x000c8)
1139 #define ISP21_BAY3D_SIG_Y6 (ISP21_BAY3D_BASE + 0x000cc)
1140 #define ISP21_BAY3D_SIG_Y7 (ISP21_BAY3D_BASE + 0x000d0)
1141
1142 #define ISP_LDCH_BASE 0x00003B00
1143 #define ISP_LDCH_STS (ISP_LDCH_BASE + 0x00000)
1144
1145 #define ISP_DHAZ_BASE 0x00003C00
1146 #define ISP_DHAZ_CTRL (ISP_DHAZ_BASE + 0x00000)
1147 #define ISP_DHAZ_ADP0 (ISP_DHAZ_BASE + 0x00004)
1148 #define ISP_DHAZ_ADP1 (ISP_DHAZ_BASE + 0x00008)
1149 #define ISP_DHAZ_ADP2 (ISP_DHAZ_BASE + 0x0000c)
1150 #define ISP_DHAZ_ADP_TMAX (ISP_DHAZ_BASE + 0x00010)
1151 #define ISP_DHAZ_ADP_HIST0 (ISP_DHAZ_BASE + 0x00014)
1152 #define ISP_DHAZ_ADP_HIST1 (ISP_DHAZ_BASE + 0x00018)
1153 #define ISP_DHAZ_HIST_ENH (ISP_DHAZ_BASE + 0x0001c)
1154 #define ISP_DHAZ_IIR0 (ISP_DHAZ_BASE + 0x00020)
1155 #define ISP_DHAZ_IIR1 (ISP_DHAZ_BASE + 0x00024)
1156 #define ISP_DHAZ_ALPHA0 (ISP_DHAZ_BASE + 0x00028)
1157 #define ISP_DHAZ_ALPHA1 (ISP_DHAZ_BASE + 0x0002c)
1158 #define ISP_DHAZ_BI_DC (ISP_DHAZ_BASE + 0x00030)
1159 #define ISP_DHAZ_DC_BF0 (ISP_DHAZ_BASE + 0x00034)
1160 #define ISP_DHAZ_DC_BF1 (ISP_DHAZ_BASE + 0x00038)
1161 #define ISP_DHAZ_BI_AIR (ISP_DHAZ_BASE + 0x0003c)
1162 #define ISP_DHAZ_AIR_BF (ISP_DHAZ_BASE + 0x00040)
1163 #define ISP_DHAZ_GAUS (ISP_DHAZ_BASE + 0x00044)
1164 #define ISP_DHAZ_HIST_CONV0 (ISP_DHAZ_BASE + 0x00048)
1165 #define ISP_DHAZ_HIST_CONV1 (ISP_DHAZ_BASE + 0x0004c)
1166 #define ISP_DHAZ_HIST_CONV2 (ISP_DHAZ_BASE + 0x00050)
1167 #define ISP_DHAZ_CTRL_SHD (ISP_DHAZ_BASE + 0x00060)
1168 #define ISP_DHAZ_ADP_RD0 (ISP_DHAZ_BASE + 0x00064)
1169 #define ISP_DHAZ_ADP_RD1 (ISP_DHAZ_BASE + 0x00068)
1170 #define ISP_DHAZ_HIST_REG0 (ISP_DHAZ_BASE + 0x00070)
1171 #define ISP_DHAZ_HIST_REG1 (ISP_DHAZ_BASE + 0x00074)
1172 #define ISP_DHAZ_HIST_REG2 (ISP_DHAZ_BASE + 0x00078)
1173 #define ISP_DHAZ_HIST_REG3 (ISP_DHAZ_BASE + 0x0007c)
1174 #define ISP_DHAZ_HIST_REG4 (ISP_DHAZ_BASE + 0x00080)
1175 #define ISP_DHAZ_HIST_REG5 (ISP_DHAZ_BASE + 0x00084)
1176 #define ISP_DHAZ_HIST_REG6 (ISP_DHAZ_BASE + 0x00088)
1177 #define ISP_DHAZ_HIST_REG7 (ISP_DHAZ_BASE + 0x0008c)
1178 #define ISP_DHAZ_HIST_REG8 (ISP_DHAZ_BASE + 0x00090)
1179 #define ISP_DHAZ_HIST_REG9 (ISP_DHAZ_BASE + 0x00094)
1180 #define ISP_DHAZ_HIST_REG10 (ISP_DHAZ_BASE + 0x00098)
1181 #define ISP_DHAZ_HIST_REG11 (ISP_DHAZ_BASE + 0x0009c)
1182 #define ISP_DHAZ_HIST_REG12 (ISP_DHAZ_BASE + 0x000a0)
1183 #define ISP_DHAZ_HIST_REG13 (ISP_DHAZ_BASE + 0x000a4)
1184 #define ISP_DHAZ_HIST_REG14 (ISP_DHAZ_BASE + 0x000a8)
1185 #define ISP_DHAZ_HIST_REG15 (ISP_DHAZ_BASE + 0x000ac)
1186 #define ISP_DHAZ_HIST_REG16 (ISP_DHAZ_BASE + 0x000b0)
1187 #define ISP_DHAZ_HIST_REG17 (ISP_DHAZ_BASE + 0x000b4)
1188 #define ISP_DHAZ_HIST_REG18 (ISP_DHAZ_BASE + 0x000b8)
1189 #define ISP_DHAZ_HIST_REG19 (ISP_DHAZ_BASE + 0x000bc)
1190 #define ISP_DHAZ_HIST_REG20 (ISP_DHAZ_BASE + 0x000c0)
1191 #define ISP_DHAZ_HIST_REG21 (ISP_DHAZ_BASE + 0x000c4)
1192 #define ISP_DHAZ_HIST_REG22 (ISP_DHAZ_BASE + 0x000c8)
1193 #define ISP_DHAZ_HIST_REG23 (ISP_DHAZ_BASE + 0x000cc)
1194 #define ISP_DHAZ_HIST_REG24 (ISP_DHAZ_BASE + 0x000d0)
1195 #define ISP_DHAZ_HIST_REG25 (ISP_DHAZ_BASE + 0x000d4)
1196 #define ISP_DHAZ_HIST_REG26 (ISP_DHAZ_BASE + 0x000d8)
1197 #define ISP_DHAZ_HIST_REG27 (ISP_DHAZ_BASE + 0x000dc)
1198 #define ISP_DHAZ_HIST_REG28 (ISP_DHAZ_BASE + 0x000e0)
1199 #define ISP_DHAZ_HIST_REG29 (ISP_DHAZ_BASE + 0x000e4)
1200 #define ISP_DHAZ_HIST_REG30 (ISP_DHAZ_BASE + 0x000e8)
1201 #define ISP_DHAZ_HIST_REG31 (ISP_DHAZ_BASE + 0x000ec)
1202 #define ISP_DHAZ_HIST_REG32 (ISP_DHAZ_BASE + 0x000f0)
1203 #define ISP_DHAZ_HIST_REG33 (ISP_DHAZ_BASE + 0x000f4)
1204 #define ISP_DHAZ_HIST_REG34 (ISP_DHAZ_BASE + 0x000f8)
1205 #define ISP_DHAZ_HIST_REG35 (ISP_DHAZ_BASE + 0x000fc)
1206 #define ISP_DHAZ_HIST_REG36 (ISP_DHAZ_BASE + 0x00100)
1207 #define ISP_DHAZ_HIST_REG37 (ISP_DHAZ_BASE + 0x00104)
1208 #define ISP_DHAZ_HIST_REG38 (ISP_DHAZ_BASE + 0x00108)
1209 #define ISP_DHAZ_HIST_REG39 (ISP_DHAZ_BASE + 0x0010c)
1210 #define ISP_DHAZ_HIST_REG40 (ISP_DHAZ_BASE + 0x00110)
1211 #define ISP_DHAZ_HIST_REG41 (ISP_DHAZ_BASE + 0x00114)
1212 #define ISP_DHAZ_HIST_REG42 (ISP_DHAZ_BASE + 0x00118)
1213 #define ISP_DHAZ_HIST_REG43 (ISP_DHAZ_BASE + 0x0011c)
1214 #define ISP_DHAZ_HIST_REG44 (ISP_DHAZ_BASE + 0x00120)
1215 #define ISP_DHAZ_HIST_REG45 (ISP_DHAZ_BASE + 0x00124)
1216 #define ISP_DHAZ_HIST_REG46 (ISP_DHAZ_BASE + 0x00128)
1217 #define ISP_DHAZ_HIST_REG47 (ISP_DHAZ_BASE + 0x0012c)
1218 #define ISP_DHAZ_HIST_REG48 (ISP_DHAZ_BASE + 0x00130)
1219 #define ISP_DHAZ_HIST_REG49 (ISP_DHAZ_BASE + 0x00134)
1220 #define ISP_DHAZ_HIST_REG50 (ISP_DHAZ_BASE + 0x00138)
1221 #define ISP_DHAZ_HIST_REG51 (ISP_DHAZ_BASE + 0x0013c)
1222 #define ISP_DHAZ_HIST_REG52 (ISP_DHAZ_BASE + 0x00140)
1223 #define ISP_DHAZ_HIST_REG53 (ISP_DHAZ_BASE + 0x00144)
1224 #define ISP_DHAZ_HIST_REG54 (ISP_DHAZ_BASE + 0x00148)
1225 #define ISP_DHAZ_HIST_REG55 (ISP_DHAZ_BASE + 0x0014c)
1226 #define ISP_DHAZ_HIST_REG56 (ISP_DHAZ_BASE + 0x00150)
1227 #define ISP_DHAZ_HIST_REG57 (ISP_DHAZ_BASE + 0x00154)
1228 #define ISP_DHAZ_HIST_REG58 (ISP_DHAZ_BASE + 0x00158)
1229 #define ISP_DHAZ_HIST_REG59 (ISP_DHAZ_BASE + 0x0015c)
1230 #define ISP_DHAZ_HIST_REG60 (ISP_DHAZ_BASE + 0x00160)
1231 #define ISP_DHAZ_HIST_REG61 (ISP_DHAZ_BASE + 0x00164)
1232 #define ISP_DHAZ_HIST_REG62 (ISP_DHAZ_BASE + 0x00168)
1233 #define ISP_DHAZ_HIST_REG63 (ISP_DHAZ_BASE + 0x0016c)
1234 #define ISP_DHAZ_HIST_REG64 (ISP_DHAZ_BASE + 0x00170)
1235 #define ISP_DHAZ_HIST_REG65 (ISP_DHAZ_BASE + 0x00174)
1236 #define ISP_DHAZ_HIST_REG66 (ISP_DHAZ_BASE + 0x00178)
1237 #define ISP_DHAZ_HIST_REG67 (ISP_DHAZ_BASE + 0x0017c)
1238 #define ISP_DHAZ_HIST_REG68 (ISP_DHAZ_BASE + 0x00180)
1239 #define ISP_DHAZ_HIST_REG69 (ISP_DHAZ_BASE + 0x00184)
1240 #define ISP_DHAZ_HIST_REG70 (ISP_DHAZ_BASE + 0x00188)
1241 #define ISP_DHAZ_HIST_REG71 (ISP_DHAZ_BASE + 0x0018c)
1242 #define ISP_DHAZ_HIST_REG72 (ISP_DHAZ_BASE + 0x00190)
1243 #define ISP_DHAZ_HIST_REG73 (ISP_DHAZ_BASE + 0x00194)
1244 #define ISP_DHAZ_HIST_REG74 (ISP_DHAZ_BASE + 0x00198)
1245 #define ISP_DHAZ_HIST_REG75 (ISP_DHAZ_BASE + 0x0019c)
1246 #define ISP_DHAZ_HIST_REG76 (ISP_DHAZ_BASE + 0x001a0)
1247 #define ISP_DHAZ_HIST_REG77 (ISP_DHAZ_BASE + 0x001a4)
1248 #define ISP_DHAZ_HIST_REG78 (ISP_DHAZ_BASE + 0x001a8)
1249 #define ISP_DHAZ_HIST_REG79 (ISP_DHAZ_BASE + 0x001ac)
1250 #define ISP_DHAZ_HIST_REG80 (ISP_DHAZ_BASE + 0x001b0)
1251 #define ISP_DHAZ_HIST_REG81 (ISP_DHAZ_BASE + 0x001b4)
1252 #define ISP_DHAZ_HIST_REG82 (ISP_DHAZ_BASE + 0x001b8)
1253 #define ISP_DHAZ_HIST_REG83 (ISP_DHAZ_BASE + 0x001bc)
1254 #define ISP_DHAZ_HIST_REG84 (ISP_DHAZ_BASE + 0x001c0)
1255 #define ISP_DHAZ_HIST_REG85 (ISP_DHAZ_BASE + 0x001c4)
1256 #define ISP_DHAZ_HIST_REG86 (ISP_DHAZ_BASE + 0x001c8)
1257 #define ISP_DHAZ_HIST_REG87 (ISP_DHAZ_BASE + 0x001cc)
1258 #define ISP_DHAZ_HIST_REG88 (ISP_DHAZ_BASE + 0x001d0)
1259 #define ISP_DHAZ_HIST_REG89 (ISP_DHAZ_BASE + 0x001d4)
1260 #define ISP_DHAZ_HIST_REG90 (ISP_DHAZ_BASE + 0x001d8)
1261 #define ISP_DHAZ_HIST_REG91 (ISP_DHAZ_BASE + 0x001dc)
1262 #define ISP_DHAZ_HIST_REG92 (ISP_DHAZ_BASE + 0x001e0)
1263 #define ISP_DHAZ_HIST_REG93 (ISP_DHAZ_BASE + 0x001e4)
1264 #define ISP_DHAZ_HIST_REG94 (ISP_DHAZ_BASE + 0x001e8)
1265 #define ISP_DHAZ_HIST_REG95 (ISP_DHAZ_BASE + 0x001ec)
1266
1267 #define ISP21_DHAZ_CTRL (ISP_DHAZ_BASE + 0x00000)
1268 #define ISP21_DHAZ_ADP0 (ISP_DHAZ_BASE + 0x00004)
1269 #define ISP21_DHAZ_ADP1 (ISP_DHAZ_BASE + 0x00008)
1270 #define ISP21_DHAZ_ADP2 (ISP_DHAZ_BASE + 0x0000c)
1271 #define ISP21_DHAZ_ADP_TMAX (ISP_DHAZ_BASE + 0x00010)
1272 #define ISP21_DHAZ_ADP_HIST0 (ISP_DHAZ_BASE + 0x00014)
1273 #define ISP21_DHAZ_ADP_HIST1 (ISP_DHAZ_BASE + 0x00018)
1274 #define ISP21_DHAZ_ENHANCE (ISP_DHAZ_BASE + 0x0001c)
1275 #define ISP21_DHAZ_IIR0 (ISP_DHAZ_BASE + 0x00020)
1276 #define ISP21_DHAZ_IIR1 (ISP_DHAZ_BASE + 0x00024)
1277 #define ISP21_DHAZ_SOFT_CFG0 (ISP_DHAZ_BASE + 0x00028)
1278 #define ISP21_DHAZ_SOFT_CFG1 (ISP_DHAZ_BASE + 0x0002c)
1279 #define ISP21_DHAZ_BF_SIGMA (ISP_DHAZ_BASE + 0x00030)
1280 #define ISP21_DHAZ_BF_WET (ISP_DHAZ_BASE + 0x00034)
1281 #define ISP21_DHAZ_ENH_CURVE0 (ISP_DHAZ_BASE + 0x00038)
1282 #define ISP21_DHAZ_ENH_CURVE1 (ISP_DHAZ_BASE + 0x0003c)
1283 #define ISP21_DHAZ_ENH_CURVE2 (ISP_DHAZ_BASE + 0x00040)
1284 #define ISP21_DHAZ_ENH_CURVE3 (ISP_DHAZ_BASE + 0x00044)
1285 #define ISP21_DHAZ_ENH_CURVE4 (ISP_DHAZ_BASE + 0x00048)
1286 #define ISP21_DHAZ_ENH_CURVE5 (ISP_DHAZ_BASE + 0x0004c)
1287 #define ISP21_DHAZ_ENH_CURVE6 (ISP_DHAZ_BASE + 0x00050)
1288 #define ISP21_DHAZ_ENH_CURVE7 (ISP_DHAZ_BASE + 0x00054)
1289 #define ISP21_DHAZ_ENH_CURVE8 (ISP_DHAZ_BASE + 0x00058)
1290 #define ISP21_DHAZ_GAUS (ISP_DHAZ_BASE + 0x0005c)
1291 #define ISP21_DHAZ_CTRL_SHD (ISP_DHAZ_BASE + 0x00060)
1292 #define ISP21_DHAZ_ADP_RD0 (ISP_DHAZ_BASE + 0x00064)
1293 #define ISP21_DHAZ_ADP_RD1 (ISP_DHAZ_BASE + 0x00068)
1294 #define ISP21_DHAZ_HIST_REG0 (ISP_DHAZ_BASE + 0x00070)
1295 #define ISP21_DHAZ_HIST_REG1 (ISP_DHAZ_BASE + 0x00074)
1296 #define ISP21_DHAZ_HIST_REG2 (ISP_DHAZ_BASE + 0x00078)
1297 #define ISP21_DHAZ_HIST_REG3 (ISP_DHAZ_BASE + 0x0007c)
1298 #define ISP21_DHAZ_HIST_REG4 (ISP_DHAZ_BASE + 0x00080)
1299 #define ISP21_DHAZ_HIST_REG5 (ISP_DHAZ_BASE + 0x00084)
1300 #define ISP21_DHAZ_HIST_REG6 (ISP_DHAZ_BASE + 0x00088)
1301 #define ISP21_DHAZ_HIST_REG7 (ISP_DHAZ_BASE + 0x0008c)
1302 #define ISP21_DHAZ_HIST_REG8 (ISP_DHAZ_BASE + 0x00090)
1303 #define ISP21_DHAZ_HIST_REG9 (ISP_DHAZ_BASE + 0x00094)
1304 #define ISP21_DHAZ_HIST_REG10 (ISP_DHAZ_BASE + 0x00098)
1305 #define ISP21_DHAZ_HIST_REG11 (ISP_DHAZ_BASE + 0x0009c)
1306 #define ISP21_DHAZ_HIST_REG12 (ISP_DHAZ_BASE + 0x000a0)
1307 #define ISP21_DHAZ_HIST_REG13 (ISP_DHAZ_BASE + 0x000a4)
1308 #define ISP21_DHAZ_HIST_REG14 (ISP_DHAZ_BASE + 0x000a8)
1309 #define ISP21_DHAZ_HIST_REG15 (ISP_DHAZ_BASE + 0x000ac)
1310 #define ISP21_DHAZ_HIST_REG16 (ISP_DHAZ_BASE + 0x000b0)
1311 #define ISP21_DHAZ_HIST_REG17 (ISP_DHAZ_BASE + 0x000b4)
1312 #define ISP21_DHAZ_HIST_REG18 (ISP_DHAZ_BASE + 0x000b8)
1313 #define ISP21_DHAZ_HIST_REG19 (ISP_DHAZ_BASE + 0x000bc)
1314 #define ISP21_DHAZ_HIST_REG20 (ISP_DHAZ_BASE + 0x000c0)
1315 #define ISP21_DHAZ_HIST_REG21 (ISP_DHAZ_BASE + 0x000c4)
1316 #define ISP21_DHAZ_HIST_REG22 (ISP_DHAZ_BASE + 0x000c8)
1317 #define ISP21_DHAZ_HIST_REG23 (ISP_DHAZ_BASE + 0x000cc)
1318 #define ISP21_DHAZ_HIST_REG24 (ISP_DHAZ_BASE + 0x000d0)
1319 #define ISP21_DHAZ_HIST_REG25 (ISP_DHAZ_BASE + 0x000d4)
1320 #define ISP21_DHAZ_HIST_REG26 (ISP_DHAZ_BASE + 0x000d8)
1321 #define ISP21_DHAZ_HIST_REG27 (ISP_DHAZ_BASE + 0x000dc)
1322 #define ISP21_DHAZ_HIST_REG28 (ISP_DHAZ_BASE + 0x000e0)
1323 #define ISP21_DHAZ_HIST_REG29 (ISP_DHAZ_BASE + 0x000e4)
1324 #define ISP21_DHAZ_HIST_REG30 (ISP_DHAZ_BASE + 0x000e8)
1325 #define ISP21_DHAZ_HIST_REG31 (ISP_DHAZ_BASE + 0x000ec)
1326
1327 #define ISP_3DLUT_BASE 0x00003E00
1328 #define ISP_3DLUT_CTRL (ISP_3DLUT_BASE + 0x00000)
1329 #define ISP_3DLUT_UPDATE (ISP_3DLUT_BASE + 0x00004)
1330
1331 #define ISP_GAIN_BASE 0x00003F00
1332 #define ISP_GAIN_CTRL (ISP_GAIN_BASE + 0x00000)
1333 #define ISP_GAIN_G0 (ISP_GAIN_BASE + 0x00004)
1334 #define ISP_GAIN_G1_G2 (ISP_GAIN_BASE + 0x00008)
1335 #define ISP_GAIN_IDX0 (ISP_GAIN_BASE + 0x0000c)
1336 #define ISP_GAIN_IDX1 (ISP_GAIN_BASE + 0x00010)
1337 #define ISP_GAIN_IDX2 (ISP_GAIN_BASE + 0x00014)
1338 #define ISP_GAIN_IDX3 (ISP_GAIN_BASE + 0x00018)
1339 #define ISP_GAIN_LUT0 (ISP_GAIN_BASE + 0x0001c)
1340 #define ISP_GAIN_LUT1 (ISP_GAIN_BASE + 0x00020)
1341 #define ISP_GAIN_LUT2 (ISP_GAIN_BASE + 0x00024)
1342 #define ISP_GAIN_LUT3 (ISP_GAIN_BASE + 0x00028)
1343 #define ISP_GAIN_LUT4 (ISP_GAIN_BASE + 0x0002c)
1344 #define ISP_GAIN_LUT5 (ISP_GAIN_BASE + 0x00030)
1345 #define ISP_GAIN_LUT6 (ISP_GAIN_BASE + 0x00034)
1346 #define ISP_GAIN_LUT7 (ISP_GAIN_BASE + 0x00038)
1347 #define ISP_GAIN_LUT8 (ISP_GAIN_BASE + 0x0003c)
1348
1349 #define ISP_AFM_BASE 0x00004100
1350 #define ISP_AFM_CTRL (ISP_AFM_BASE + 0x00000)
1351 #define ISP_AFM_LT_A (ISP_AFM_BASE + 0x00004)
1352 #define ISP_AFM_RB_A (ISP_AFM_BASE + 0x00008)
1353 #define ISP_AFM_LT_B (ISP_AFM_BASE + 0x0000c)
1354 #define ISP_AFM_RB_B (ISP_AFM_BASE + 0x00010)
1355 #define ISP_AFM_LT_C (ISP_AFM_BASE + 0x00014)
1356 #define ISP_AFM_RB_C (ISP_AFM_BASE + 0x00018)
1357 #define ISP_AFM_THRES (ISP_AFM_BASE + 0x0001c)
1358 #define ISP_AFM_VAR_SHIFT (ISP_AFM_BASE + 0x00020)
1359 #define ISP_AFM_SUM_A (ISP_AFM_BASE + 0x00024)
1360 #define ISP_AFM_SUM_B (ISP_AFM_BASE + 0x00028)
1361 #define ISP_AFM_SUM_C (ISP_AFM_BASE + 0x0002c)
1362 #define ISP_AFM_LUM_A (ISP_AFM_BASE + 0x00030)
1363 #define ISP_AFM_LUM_B (ISP_AFM_BASE + 0x00034)
1364 #define ISP_AFM_LUM_C (ISP_AFM_BASE + 0x00038)
1365
1366 #define ISP_HIST_BASE 0x00004200
1367 #define ISP_HIST_HIST_CTRL (ISP_HIST_BASE + 0x00000)
1368 #define ISP_HIST_HIST_SIZE (ISP_HIST_BASE + 0x00004)
1369 #define ISP_HIST_HIST_OFFS (ISP_HIST_BASE + 0x00008)
1370 #define ISP_HIST_HIST_DBG1 (ISP_HIST_BASE + 0x0000c)
1371 #define ISP_HIST_HIST1_CTRL (ISP_HIST_BASE + 0x00010)
1372 #define ISP_HIST_HIST1_SIZE (ISP_HIST_BASE + 0x00014)
1373 #define ISP_HIST_HIST1_OFFS (ISP_HIST_BASE + 0x00018)
1374 #define ISP_HIST_HIST_DBG2 (ISP_HIST_BASE + 0x0001c)
1375 #define ISP_HIST_HIST2_CTRL (ISP_HIST_BASE + 0x00020)
1376 #define ISP_HIST_HIST2_SIZE (ISP_HIST_BASE + 0x00024)
1377 #define ISP_HIST_HIST2_OFFS (ISP_HIST_BASE + 0x00028)
1378 #define ISP_HIST_HIST_DBG3 (ISP_HIST_BASE + 0x0002c)
1379 #define ISP_HIST_HIST3_CTRL (ISP_HIST_BASE + 0x00030)
1380 #define ISP_HIST_HIST3_SIZE (ISP_HIST_BASE + 0x00034)
1381 #define ISP_HIST_HIST3_OFFS (ISP_HIST_BASE + 0x00038)
1382 #define ISP_HIST_HIST_WEIGHT_0 (ISP_HIST_BASE + 0x0003c)
1383 #define ISP_HIST_HIST_BIN (ISP_HIST_BASE + 0x00120)
1384 #define ISP_HIST_HIST1_BIN (ISP_HIST_BASE + 0x00160)
1385 #define ISP_HIST_HIST2_BIN (ISP_HIST_BASE + 0x001a0)
1386 #define ISP_HIST_HIST3_BIN (ISP_HIST_BASE + 0x001e0)
1387 #define ISP_HIST_HIST1_DBG1 (ISP_HIST_BASE + 0x00220)
1388 #define ISP_HIST_HIST1_DBG2 (ISP_HIST_BASE + 0x00224)
1389 #define ISP_HIST_HIST2_DBG1 (ISP_HIST_BASE + 0x00228)
1390 #define ISP_HIST_HIST2_DBG2 (ISP_HIST_BASE + 0x0022c)
1391 #define ISP_HIST_HIST3_DBG1 (ISP_HIST_BASE + 0x00230)
1392 #define ISP_HIST_HIST3_DBG2 (ISP_HIST_BASE + 0x00234)
1393
1394 #define RAWAE_BIG1_BASE 0x00004400
1395 #define RAWAE_BIG2_BASE 0x00004600
1396 #define RAWAE_BIG3_BASE 0x00004700
1397 #define RAWAE_BIG_CTRL (0x00000)
1398 #define RAWAE_BIG_BLK_SIZE (0x00004)
1399 #define RAWAE_BIG_OFFSET (0x00008)
1400 #define RAWAE_BIG_RAM_CTRL (0x0000c)
1401 #define RAWAE_BIG_WND1_SIZE (0x00010)
1402 #define RAWAE_BIG_WND1_OFFSET (0x00014)
1403 #define RAWAE_BIG_WND2_SIZE (0x00018)
1404 #define RAWAE_BIG_WND2_OFFSET (0x0001c)
1405 #define RAWAE_BIG_WND3_SIZE (0x00020)
1406 #define RAWAE_BIG_WND3_OFFSET (0x00024)
1407 #define RAWAE_BIG_WND4_SIZE (0x00028)
1408 #define RAWAE_BIG_WND4_OFFSET (0x0002c)
1409 #define RAWAE_BIG_WND1_SUMR (0x00030)
1410 #define RAWAE_BIG_WND2_SUMR (0x00034)
1411 #define RAWAE_BIG_WND3_SUMR (0x00038)
1412 #define RAWAE_BIG_WND4_SUMR (0x0003c)
1413 #define RAWAE_BIG_WND1_SUMG (0x00040)
1414 #define RAWAE_BIG_WND2_SUMG (0x00044)
1415 #define RAWAE_BIG_WND3_SUMG (0x00048)
1416 #define RAWAE_BIG_WND4_SUMG (0x0004c)
1417 #define RAWAE_BIG_WND1_SUMB (0x00050)
1418 #define RAWAE_BIG_WND2_SUMB (0x00054)
1419 #define RAWAE_BIG_WND3_SUMB (0x00058)
1420 #define RAWAE_BIG_WND4_SUMB (0x0005c)
1421 #define RAWAE_BIG_RO_DBG1 (0x00060)
1422 #define RAWAE_BIG_RO_DBG2 (0x00064)
1423 #define RAWAE_BIG_RO_DBG3 (0x00068)
1424 #define RAWAE_BIG_RO_MEAN_BASE_ADDR (0x00080)
1425
1426 #define ISP_RAWAE_LITE_BASE 0x00004500
1427 #define ISP_RAWAE_LITE_CTRL (ISP_RAWAE_LITE_BASE + 0x00000)
1428 #define ISP_RAWAE_LITE_BLK_SIZ (ISP_RAWAE_LITE_BASE + 0x00004)
1429 #define ISP_RAWAE_LITE_OFFSET (ISP_RAWAE_LITE_BASE + 0x00008)
1430 #define ISP_RAWAE_LITE_R2Y_CC (ISP_RAWAE_LITE_BASE + 0x0000c)
1431 #define ISP_RAWAE_LITE_RO_MEAN (ISP_RAWAE_LITE_BASE + 0x00010)
1432 #define ISP_RAWAE_LITE_RO_DBG1 (ISP_RAWAE_LITE_BASE + 0x00074)
1433 #define ISP_RAWAE_LITE_RO_DBG2 (ISP_RAWAE_LITE_BASE + 0x00078)
1434
1435 #define ISP_RAWHIST_LITE_BASE 0x00004900
1436 #define ISP_RAWHIST_LITE_CTRL (ISP_RAWHIST_LITE_BASE + 0x00000)
1437 #define ISP_RAWHIST_LITE_SIZE (ISP_RAWHIST_LITE_BASE + 0x00004)
1438 #define ISP_RAWHIST_LITE_OFFS (ISP_RAWHIST_LITE_BASE + 0x00008)
1439 #define ISP_RAWHIST_LITE_RAM_CTRL (ISP_RAWHIST_LITE_BASE + 0x0000c)
1440 #define ISP_RAWHIST_LITE_RAW2Y_CC (ISP_RAWHIST_LITE_BASE + 0x00010)
1441 #define ISP_RAWHIST_LITE_DBG1 (ISP_RAWHIST_LITE_BASE + 0x00020)
1442 #define ISP_RAWHIST_LITE_DBG2 (ISP_RAWHIST_LITE_BASE + 0x00024)
1443 #define ISP_RAWHIST_LITE_DBG3 (ISP_RAWHIST_LITE_BASE + 0x00028)
1444 #define ISP_RAWHIST_LITE_WEIGHT (ISP_RAWHIST_LITE_BASE + 0x00040)
1445 #define ISP_RAWHIST_LITE_RO_BASE_BIN (ISP_RAWHIST_LITE_BASE + 0x00080)
1446
1447 #define ISP_RAWHIST_BIG1_BASE 0x00004800
1448 #define ISP_RAWHIST_BIG2_BASE 0x00004A00
1449 #define ISP_RAWHIST_BIG3_BASE 0x00004B00
1450 #define ISP_RAWHIST_BIG_CTRL (0x00000)
1451 #define ISP_RAWHIST_BIG_SIZE (0x00004)
1452 #define ISP_RAWHIST_BIG_OFFS (0x00008)
1453 #define ISP_RAWHIST_BIG_HRAM_CTRL (0x0000c)
1454 #define ISP_RAWHIST_BIG_RAW2Y_CC (0x00010)
1455 #define ISP_RAWHIST_BIG_WRAM_CTRL (0x00014)
1456 #define ISP_RAWHIST_BIG_DBG1 (0x00020)
1457 #define ISP_RAWHIST_BIG_DBG2 (0x00024)
1458 #define ISP_RAWHIST_BIG_DBG3 (0x00028)
1459 #define ISP_RAWHIST_BIG_WEIGHT_BASE (0x00040)
1460 #define ISP_RAWHIST_BIG_RO_BASE_BIN (0x00080)
1461
1462 #define ISP_YUVAE_BASE 0x00004C00
1463 #define ISP_YUVAE_CTRL (ISP_YUVAE_BASE + 0x00000)
1464 #define ISP_YUVAE_BLK_SIZE (ISP_YUVAE_BASE + 0x00004)
1465 #define ISP_YUVAE_OFFSET (ISP_YUVAE_BASE + 0x00008)
1466 #define ISP_YUVAE_RAM_CTRL (ISP_YUVAE_BASE + 0x0000c)
1467 #define ISP_YUVAE_WND1_SIZE (ISP_YUVAE_BASE + 0x00010)
1468 #define ISP_YUVAE_WND1_OFFSET (ISP_YUVAE_BASE + 0x00014)
1469 #define ISP_YUVAE_WND2_SIZE (ISP_YUVAE_BASE + 0x00018)
1470 #define ISP_YUVAE_WND2_OFFSET (ISP_YUVAE_BASE + 0x0001c)
1471 #define ISP_YUVAE_WND3_SIZE (ISP_YUVAE_BASE + 0x00020)
1472 #define ISP_YUVAE_WND3_OFFSET (ISP_YUVAE_BASE + 0x00024)
1473 #define ISP_YUVAE_WND4_SIZE (ISP_YUVAE_BASE + 0x00028)
1474 #define ISP_YUVAE_WND4_OFFSET (ISP_YUVAE_BASE + 0x0002c)
1475 #define ISP_YUVAE_WND1_SUMY (ISP_YUVAE_BASE + 0x00030)
1476 #define ISP_YUVAE_WND2_SUMY (ISP_YUVAE_BASE + 0x00034)
1477 #define ISP_YUVAE_WND3_SUMY (ISP_YUVAE_BASE + 0x00038)
1478 #define ISP_YUVAE_WND4_SUMY (ISP_YUVAE_BASE + 0x0003c)
1479 #define ISP_YUVAE_RO_DBG1 (ISP_YUVAE_BASE + 0x00040)
1480 #define ISP_YUVAE_RO_DBG2 (ISP_YUVAE_BASE + 0x00044)
1481 #define ISP_YUVAE_RO_DBG3 (ISP_YUVAE_BASE + 0x00048)
1482 #define ISP_YUVAE_RO_MEAN_BASE_ADDR (ISP_YUVAE_BASE + 0x00080)
1483
1484 #define ISP_RAWAF_BASE 0x00004D00
1485 #define ISP_RAWAF_CTRL (ISP_RAWAF_BASE + 0x00000)
1486 #define ISP_RAWAF_LT_A (ISP_RAWAF_BASE + 0x00004)
1487 #define ISP_RAWAF_RB_A (ISP_RAWAF_BASE + 0x00008)
1488 #define ISP_RAWAF_LT_B (ISP_RAWAF_BASE + 0x0000c)
1489 #define ISP_RAWAF_RB_B (ISP_RAWAF_BASE + 0x00010)
1490 #define ISP_RAWAF_INT_LINE (ISP_RAWAF_BASE + 0x00014)
1491 #define ISP_RAWAF_GAUS_COE (ISP_RAWAF_BASE + 0x00018)
1492 #define ISP_RAWAF_THRES (ISP_RAWAF_BASE + 0x0001c)
1493 #define ISP_RAWAF_VAR_SHIFT (ISP_RAWAF_BASE + 0x00020)
1494 #define ISP_RAWAF_SUM_A (ISP_RAWAF_BASE + 0x00024)
1495 #define ISP_RAWAF_SUM_B (ISP_RAWAF_BASE + 0x00028)
1496 #define ISP_RAWAF_LUM_A (ISP_RAWAF_BASE + 0x0002c)
1497 #define ISP_RAWAF_LUM_B (ISP_RAWAF_BASE + 0x00030)
1498 #define ISP_RAWAF_GAMMA_Y0 (ISP_RAWAF_BASE + 0x00034)
1499 #define ISP_RAWAF_GAMMA_Y1 (ISP_RAWAF_BASE + 0x00038)
1500 #define ISP_RAWAF_GAMMA_Y2 (ISP_RAWAF_BASE + 0x0003c)
1501 #define ISP_RAWAF_GAMMA_Y3 (ISP_RAWAF_BASE + 0x00040)
1502 #define ISP_RAWAF_GAMMA_Y4 (ISP_RAWAF_BASE + 0x00044)
1503 #define ISP_RAWAF_GAMMA_Y5 (ISP_RAWAF_BASE + 0x00048)
1504 #define ISP_RAWAF_GAMMA_Y6 (ISP_RAWAF_BASE + 0x0004c)
1505 #define ISP_RAWAF_GAMMA_Y7 (ISP_RAWAF_BASE + 0x00050)
1506 #define ISP_RAWAF_GAMMA_Y8 (ISP_RAWAF_BASE + 0x00054)
1507 #define ISP_RAWAF_INT_STATE (ISP_RAWAF_BASE + 0x00058)
1508 #define ISP_RAWAF_RAM_DATA (ISP_RAWAF_BASE + 0x0005c)
1509
1510 #define ISP_RAWAWB_BASE 0x00005000
1511 #define ISP_RAWAWB_CTRL (ISP_RAWAWB_BASE + 0x00000)
1512 #define ISP_RAWAWB_BLK_CTRL (ISP_RAWAWB_BASE + 0x00004)
1513 #define ISP_RAWAWB_WIN_OFFS (ISP_RAWAWB_BASE + 0x00008)
1514 #define ISP_RAWAWB_WIN_SIZE (ISP_RAWAWB_BASE + 0x0000c)
1515 #define ISP_RAWAWB_LIMIT_RG_MAX (ISP_RAWAWB_BASE + 0x00010)
1516 #define ISP_RAWAWB_LIMIT_BY_MAX (ISP_RAWAWB_BASE + 0x00014)
1517 #define ISP_RAWAWB_LIMIT_RG_MIN (ISP_RAWAWB_BASE + 0x00018)
1518 #define ISP_RAWAWB_LIMIT_BY_MIN (ISP_RAWAWB_BASE + 0x0001c)
1519 #define ISP_RAWAWB_RGB2Y_0 (ISP_RAWAWB_BASE + 0x00020)
1520 #define ISP_RAWAWB_RGB2Y_1 (ISP_RAWAWB_BASE + 0x00024)
1521 #define ISP_RAWAWB_RGB2U_0 (ISP_RAWAWB_BASE + 0x00028)
1522 #define ISP_RAWAWB_RGB2U_1 (ISP_RAWAWB_BASE + 0x0002c)
1523 #define ISP_RAWAWB_RGB2V_0 (ISP_RAWAWB_BASE + 0x00030)
1524 #define ISP_RAWAWB_RGB2V_1 (ISP_RAWAWB_BASE + 0x00034)
1525 #define ISP_RAWAWB_UV_DETC_VERTEX0_0 (ISP_RAWAWB_BASE + 0x00038)
1526 #define ISP_RAWAWB_UV_DETC_VERTEX1_0 (ISP_RAWAWB_BASE + 0x0003c)
1527 #define ISP_RAWAWB_UV_DETC_VERTEX2_0 (ISP_RAWAWB_BASE + 0x00040)
1528 #define ISP_RAWAWB_UV_DETC_VERTEX3_0 (ISP_RAWAWB_BASE + 0x00044)
1529 #define ISP_RAWAWB_UV_DETC_ISLOPE01_0 (ISP_RAWAWB_BASE + 0x00048)
1530 #define ISP_RAWAWB_UV_DETC_ISLOPE12_0 (ISP_RAWAWB_BASE + 0x0004c)
1531 #define ISP_RAWAWB_UV_DETC_ISLOPE23_0 (ISP_RAWAWB_BASE + 0x00050)
1532 #define ISP_RAWAWB_UV_DETC_ISLOPE30_0 (ISP_RAWAWB_BASE + 0x00054)
1533 #define ISP_RAWAWB_UV_DETC_VERTEX0_1 (ISP_RAWAWB_BASE + 0x00058)
1534 #define ISP_RAWAWB_UV_DETC_VERTEX1_1 (ISP_RAWAWB_BASE + 0x0005c)
1535 #define ISP_RAWAWB_UV_DETC_VERTEX2_1 (ISP_RAWAWB_BASE + 0x00060)
1536 #define ISP_RAWAWB_UV_DETC_VERTEX3_1 (ISP_RAWAWB_BASE + 0x00064)
1537 #define ISP_RAWAWB_UV_DETC_ISLOPE01_1 (ISP_RAWAWB_BASE + 0x00068)
1538 #define ISP_RAWAWB_UV_DETC_ISLOPE12_1 (ISP_RAWAWB_BASE + 0x0006c)
1539 #define ISP_RAWAWB_UV_DETC_ISLOPE23_1 (ISP_RAWAWB_BASE + 0x00070)
1540 #define ISP_RAWAWB_UV_DETC_ISLOPE30_1 (ISP_RAWAWB_BASE + 0x00074)
1541 #define ISP_RAWAWB_UV_DETC_VERTEX0_2 (ISP_RAWAWB_BASE + 0x00078)
1542 #define ISP_RAWAWB_UV_DETC_VERTEX1_2 (ISP_RAWAWB_BASE + 0x0007c)
1543 #define ISP_RAWAWB_UV_DETC_VERTEX2_2 (ISP_RAWAWB_BASE + 0x00080)
1544 #define ISP_RAWAWB_UV_DETC_VERTEX3_2 (ISP_RAWAWB_BASE + 0x00084)
1545 #define ISP_RAWAWB_UV_DETC_ISLOPE01_2 (ISP_RAWAWB_BASE + 0x00088)
1546 #define ISP_RAWAWB_UV_DETC_ISLOPE12_2 (ISP_RAWAWB_BASE + 0x0008c)
1547 #define ISP_RAWAWB_UV_DETC_ISLOPE23_2 (ISP_RAWAWB_BASE + 0x00090)
1548 #define ISP_RAWAWB_UV_DETC_ISLOPE30_2 (ISP_RAWAWB_BASE + 0x00094)
1549 #define ISP_RAWAWB_UV_DETC_VERTEX0_3 (ISP_RAWAWB_BASE + 0x00098)
1550 #define ISP_RAWAWB_UV_DETC_VERTEX1_3 (ISP_RAWAWB_BASE + 0x0009c)
1551 #define ISP_RAWAWB_UV_DETC_VERTEX2_3 (ISP_RAWAWB_BASE + 0x000a0)
1552 #define ISP_RAWAWB_UV_DETC_VERTEX3_3 (ISP_RAWAWB_BASE + 0x000a4)
1553 #define ISP_RAWAWB_UV_DETC_ISLOPE01_3 (ISP_RAWAWB_BASE + 0x000a8)
1554 #define ISP_RAWAWB_UV_DETC_ISLOPE12_3 (ISP_RAWAWB_BASE + 0x000ac)
1555 #define ISP_RAWAWB_UV_DETC_ISLOPE23_3 (ISP_RAWAWB_BASE + 0x000b0)
1556 #define ISP_RAWAWB_UV_DETC_ISLOPE30_3 (ISP_RAWAWB_BASE + 0x000b4)
1557 #define ISP_RAWAWB_UV_DETC_VERTEX0_4 (ISP_RAWAWB_BASE + 0x000b8)
1558 #define ISP_RAWAWB_UV_DETC_VERTEX1_4 (ISP_RAWAWB_BASE + 0x000bc)
1559 #define ISP_RAWAWB_UV_DETC_VERTEX2_4 (ISP_RAWAWB_BASE + 0x000c0)
1560 #define ISP_RAWAWB_UV_DETC_VERTEX3_4 (ISP_RAWAWB_BASE + 0x000c4)
1561 #define ISP_RAWAWB_UV_DETC_ISLOPE01_4 (ISP_RAWAWB_BASE + 0x000c8)
1562 #define ISP_RAWAWB_UV_DETC_ISLOPE12_4 (ISP_RAWAWB_BASE + 0x000cc)
1563 #define ISP_RAWAWB_UV_DETC_ISLOPE23_4 (ISP_RAWAWB_BASE + 0x000d0)
1564 #define ISP_RAWAWB_UV_DETC_ISLOPE30_4 (ISP_RAWAWB_BASE + 0x000d4)
1565 #define ISP_RAWAWB_UV_DETC_VERTEX0_5 (ISP_RAWAWB_BASE + 0x000d8)
1566 #define ISP_RAWAWB_UV_DETC_VERTEX1_5 (ISP_RAWAWB_BASE + 0x000dc)
1567 #define ISP_RAWAWB_UV_DETC_VERTEX2_5 (ISP_RAWAWB_BASE + 0x000e0)
1568 #define ISP_RAWAWB_UV_DETC_VERTEX3_5 (ISP_RAWAWB_BASE + 0x000e4)
1569 #define ISP_RAWAWB_UV_DETC_ISLOPE01_5 (ISP_RAWAWB_BASE + 0x000e8)
1570 #define ISP_RAWAWB_UV_DETC_ISLOPE12_5 (ISP_RAWAWB_BASE + 0x000ec)
1571 #define ISP_RAWAWB_UV_DETC_ISLOPE23_5 (ISP_RAWAWB_BASE + 0x000f0)
1572 #define ISP_RAWAWB_UV_DETC_ISLOPE30_5 (ISP_RAWAWB_BASE + 0x000f4)
1573 #define ISP_RAWAWB_UV_DETC_VERTEX0_6 (ISP_RAWAWB_BASE + 0x000f8)
1574 #define ISP_RAWAWB_UV_DETC_VERTEX1_6 (ISP_RAWAWB_BASE + 0x000fc)
1575 #define ISP_RAWAWB_UV_DETC_VERTEX2_6 (ISP_RAWAWB_BASE + 0x00100)
1576 #define ISP_RAWAWB_UV_DETC_VERTEX3_6 (ISP_RAWAWB_BASE + 0x00104)
1577 #define ISP_RAWAWB_UV_DETC_ISLOPE01_6 (ISP_RAWAWB_BASE + 0x00108)
1578 #define ISP_RAWAWB_UV_DETC_ISLOPE12_6 (ISP_RAWAWB_BASE + 0x0010c)
1579 #define ISP_RAWAWB_UV_DETC_ISLOPE23_6 (ISP_RAWAWB_BASE + 0x00110)
1580 #define ISP_RAWAWB_UV_DETC_ISLOPE30_6 (ISP_RAWAWB_BASE + 0x00114)
1581 #define ISP_RAWAWB_YUV_DETC_B_UV_0 (ISP_RAWAWB_BASE + 0x00118)
1582 #define ISP_RAWAWB_YUV_DETC_SLOPE_VTCUV_0 (ISP_RAWAWB_BASE + 0x0011c)
1583 #define ISP_RAWAWB_YUV_DETC_INV_DSLOPE_0 (ISP_RAWAWB_BASE + 0x00120)
1584 #define ISP_RAWAWB_YUV_DETC_SLOPE_YDIS_0 (ISP_RAWAWB_BASE + 0x00124)
1585 #define ISP_RAWAWB_YUV_DETC_B_YDIS_0 (ISP_RAWAWB_BASE + 0x00128)
1586 #define ISP_RAWAWB_YUV_DETC_B_UV_1 (ISP_RAWAWB_BASE + 0x0012c)
1587 #define ISP_RAWAWB_YUV_DETC_SLOPE_VTCUV_1 (ISP_RAWAWB_BASE + 0x00130)
1588 #define ISP_RAWAWB_YUV_DETC_INV_DSLOPE_1 (ISP_RAWAWB_BASE + 0x00134)
1589 #define ISP_RAWAWB_YUV_DETC_SLOPE_YDIS_1 (ISP_RAWAWB_BASE + 0x00138)
1590 #define ISP_RAWAWB_YUV_DETC_B_YDIS_1 (ISP_RAWAWB_BASE + 0x0013c)
1591 #define ISP_RAWAWB_YUV_DETC_B_UV_2 (ISP_RAWAWB_BASE + 0x00140)
1592 #define ISP_RAWAWB_YUV_DETC_SLOPE_VTCUV_2 (ISP_RAWAWB_BASE + 0x00144)
1593 #define ISP_RAWAWB_YUV_DETC_INV_DSLOPE_2 (ISP_RAWAWB_BASE + 0x00148)
1594 #define ISP_RAWAWB_YUV_DETC_SLOPE_YDIS_2 (ISP_RAWAWB_BASE + 0x0014c)
1595 #define ISP_RAWAWB_YUV_DETC_B_YDIS_2 (ISP_RAWAWB_BASE + 0x00150)
1596 #define ISP_RAWAWB_YUV_DETC_B_UV_3 (ISP_RAWAWB_BASE + 0x00154)
1597 #define ISP_RAWAWB_YUV_DETC_SLOPE_VTCUV_3 (ISP_RAWAWB_BASE + 0x00158)
1598 #define ISP_RAWAWB_YUV_DETC_INV_DSLOPE_3 (ISP_RAWAWB_BASE + 0x0015c)
1599 #define ISP_RAWAWB_YUV_DETC_SLOPE_YDIS_3 (ISP_RAWAWB_BASE + 0x00160)
1600 #define ISP_RAWAWB_YUV_DETC_B_YDIS_3 (ISP_RAWAWB_BASE + 0x00164)
1601 #define ISP_RAWAWB_YUV_DETC_REF_U (ISP_RAWAWB_BASE + 0x00168)
1602 #define ISP_RAWAWB_YUV_DETC_REF_V (ISP_RAWAWB_BASE + 0x0016c)
1603 #define ISP_RAWAWB_YUV_DETC_DIS01_0 (ISP_RAWAWB_BASE + 0x00170)
1604 #define ISP_RAWAWB_YUV_DETC_DIS23_0 (ISP_RAWAWB_BASE + 0x00174)
1605 #define ISP_RAWAWB_YUV_DETC_DIS45_0 (ISP_RAWAWB_BASE + 0x00178)
1606 #define ISP_RAWAWB_YUV_DETC_TH03_0 (ISP_RAWAWB_BASE + 0x0017c)
1607 #define ISP_RAWAWB_YUV_DETC_TH45_0 (ISP_RAWAWB_BASE + 0x00180)
1608 #define ISP_RAWAWB_YUV_DETC_DIS01_1 (ISP_RAWAWB_BASE + 0x00184)
1609 #define ISP_RAWAWB_YUV_DETC_DIS23_1 (ISP_RAWAWB_BASE + 0x00188)
1610 #define ISP_RAWAWB_YUV_DETC_DIS45_1 (ISP_RAWAWB_BASE + 0x0018c)
1611 #define ISP_RAWAWB_YUV_DETC_TH03_1 (ISP_RAWAWB_BASE + 0x00190)
1612 #define ISP_RAWAWB_YUV_DETC_TH45_1 (ISP_RAWAWB_BASE + 0x00194)
1613 #define ISP_RAWAWB_YUV_DETC_DIS01_2 (ISP_RAWAWB_BASE + 0x00198)
1614 #define ISP_RAWAWB_YUV_DETC_DIS23_2 (ISP_RAWAWB_BASE + 0x0019c)
1615 #define ISP_RAWAWB_YUV_DETC_DIS45_2 (ISP_RAWAWB_BASE + 0x001a0)
1616 #define ISP_RAWAWB_YUV_DETC_TH03_2 (ISP_RAWAWB_BASE + 0x001a4)
1617 #define ISP_RAWAWB_YUV_DETC_TH45_2 (ISP_RAWAWB_BASE + 0x001a8)
1618 #define ISP_RAWAWB_YUV_DETC_DIS01_3 (ISP_RAWAWB_BASE + 0x001ac)
1619 #define ISP_RAWAWB_YUV_DETC_DIS23_3 (ISP_RAWAWB_BASE + 0x001b0)
1620 #define ISP_RAWAWB_YUV_DETC_DIS45_3 (ISP_RAWAWB_BASE + 0x001b4)
1621 #define ISP_RAWAWB_YUV_DETC_TH03_3 (ISP_RAWAWB_BASE + 0x001b8)
1622 #define ISP_RAWAWB_YUV_DETC_TH45_3 (ISP_RAWAWB_BASE + 0x001bc)
1623 #define ISP_RAWAWB_RGB2XY_WT01 (ISP_RAWAWB_BASE + 0x001fc)
1624 #define ISP_RAWAWB_RGB2XY_WT2 (ISP_RAWAWB_BASE + 0x00200)
1625 #define ISP_RAWAWB_RGB2XY_MAT0_XY (ISP_RAWAWB_BASE + 0x00204)
1626 #define ISP_RAWAWB_RGB2XY_MAT1_XY (ISP_RAWAWB_BASE + 0x00208)
1627 #define ISP_RAWAWB_RGB2XY_MAT2_XY (ISP_RAWAWB_BASE + 0x0020c)
1628 #define ISP_RAWAWB_XY_DETC_NOR_X_0 (ISP_RAWAWB_BASE + 0x00210)
1629 #define ISP_RAWAWB_XY_DETC_NOR_Y_0 (ISP_RAWAWB_BASE + 0x00214)
1630 #define ISP_RAWAWB_XY_DETC_BIG_X_0 (ISP_RAWAWB_BASE + 0x00218)
1631 #define ISP_RAWAWB_XY_DETC_BIG_Y_0 (ISP_RAWAWB_BASE + 0x0021c)
1632 #define ISP_RAWAWB_XY_DETC_SMA_X_0 (ISP_RAWAWB_BASE + 0x00220)
1633 #define ISP_RAWAWB_XY_DETC_SMA_Y_0 (ISP_RAWAWB_BASE + 0x00224)
1634 #define ISP_RAWAWB_XY_DETC_NOR_X_1 (ISP_RAWAWB_BASE + 0x00228)
1635 #define ISP_RAWAWB_XY_DETC_NOR_Y_1 (ISP_RAWAWB_BASE + 0x0022c)
1636 #define ISP_RAWAWB_XY_DETC_BIG_X_1 (ISP_RAWAWB_BASE + 0x00230)
1637 #define ISP_RAWAWB_XY_DETC_BIG_Y_1 (ISP_RAWAWB_BASE + 0x00234)
1638 #define ISP_RAWAWB_XY_DETC_SMA_X_1 (ISP_RAWAWB_BASE + 0x00238)
1639 #define ISP_RAWAWB_XY_DETC_SMA_Y_1 (ISP_RAWAWB_BASE + 0x0023c)
1640 #define ISP_RAWAWB_XY_DETC_NOR_X_2 (ISP_RAWAWB_BASE + 0x00240)
1641 #define ISP_RAWAWB_XY_DETC_NOR_Y_2 (ISP_RAWAWB_BASE + 0x00244)
1642 #define ISP_RAWAWB_XY_DETC_BIG_X_2 (ISP_RAWAWB_BASE + 0x00248)
1643 #define ISP_RAWAWB_XY_DETC_BIG_Y_2 (ISP_RAWAWB_BASE + 0x0024c)
1644 #define ISP_RAWAWB_XY_DETC_SMA_X_2 (ISP_RAWAWB_BASE + 0x00250)
1645 #define ISP_RAWAWB_XY_DETC_SMA_Y_2 (ISP_RAWAWB_BASE + 0x00254)
1646 #define ISP_RAWAWB_XY_DETC_NOR_X_3 (ISP_RAWAWB_BASE + 0x00258)
1647 #define ISP_RAWAWB_XY_DETC_NOR_Y_3 (ISP_RAWAWB_BASE + 0x0025c)
1648 #define ISP_RAWAWB_XY_DETC_BIG_X_3 (ISP_RAWAWB_BASE + 0x00260)
1649 #define ISP_RAWAWB_XY_DETC_BIG_Y_3 (ISP_RAWAWB_BASE + 0x00264)
1650 #define ISP_RAWAWB_XY_DETC_SMA_X_3 (ISP_RAWAWB_BASE + 0x00268)
1651 #define ISP_RAWAWB_XY_DETC_SMA_Y_3 (ISP_RAWAWB_BASE + 0x0026c)
1652 #define ISP_RAWAWB_XY_DETC_NOR_X_4 (ISP_RAWAWB_BASE + 0x00270)
1653 #define ISP_RAWAWB_XY_DETC_NOR_Y_4 (ISP_RAWAWB_BASE + 0x00274)
1654 #define ISP_RAWAWB_XY_DETC_BIG_X_4 (ISP_RAWAWB_BASE + 0x00278)
1655 #define ISP_RAWAWB_XY_DETC_BIG_Y_4 (ISP_RAWAWB_BASE + 0x0027c)
1656 #define ISP_RAWAWB_XY_DETC_SMA_X_4 (ISP_RAWAWB_BASE + 0x00280)
1657 #define ISP_RAWAWB_XY_DETC_SMA_Y_4 (ISP_RAWAWB_BASE + 0x00284)
1658 #define ISP_RAWAWB_XY_DETC_NOR_X_5 (ISP_RAWAWB_BASE + 0x00288)
1659 #define ISP_RAWAWB_XY_DETC_NOR_Y_5 (ISP_RAWAWB_BASE + 0x0028c)
1660 #define ISP_RAWAWB_XY_DETC_BIG_X_5 (ISP_RAWAWB_BASE + 0x00290)
1661 #define ISP_RAWAWB_XY_DETC_BIG_Y_5 (ISP_RAWAWB_BASE + 0x00294)
1662 #define ISP_RAWAWB_XY_DETC_SMA_X_5 (ISP_RAWAWB_BASE + 0x00298)
1663 #define ISP_RAWAWB_XY_DETC_SMA_Y_5 (ISP_RAWAWB_BASE + 0x0029c)
1664 #define ISP_RAWAWB_XY_DETC_NOR_X_6 (ISP_RAWAWB_BASE + 0x002a0)
1665 #define ISP_RAWAWB_XY_DETC_NOR_Y_6 (ISP_RAWAWB_BASE + 0x002a4)
1666 #define ISP_RAWAWB_XY_DETC_BIG_X_6 (ISP_RAWAWB_BASE + 0x002a8)
1667 #define ISP_RAWAWB_XY_DETC_BIG_Y_6 (ISP_RAWAWB_BASE + 0x002ac)
1668 #define ISP_RAWAWB_XY_DETC_SMA_X_6 (ISP_RAWAWB_BASE + 0x002b0)
1669 #define ISP_RAWAWB_XY_DETC_SMA_Y_6 (ISP_RAWAWB_BASE + 0x002b4)
1670 #define ISP_RAWAWB_MULTIWINDOW_EXC_CTRL (ISP_RAWAWB_BASE + 0x002b8)
1671 #define ISP_RAWAWB_MULTIWINDOW0_OFFS (ISP_RAWAWB_BASE + 0x002bc)
1672 #define ISP_RAWAWB_MULTIWINDOW0_SIZE (ISP_RAWAWB_BASE + 0x002c0)
1673 #define ISP_RAWAWB_MULTIWINDOW1_OFFS (ISP_RAWAWB_BASE + 0x002c4)
1674 #define ISP_RAWAWB_MULTIWINDOW1_SIZE (ISP_RAWAWB_BASE + 0x002c8)
1675 #define ISP_RAWAWB_MULTIWINDOW2_OFFS (ISP_RAWAWB_BASE + 0x002cc)
1676 #define ISP_RAWAWB_MULTIWINDOW2_SIZE (ISP_RAWAWB_BASE + 0x002d0)
1677 #define ISP_RAWAWB_MULTIWINDOW3_OFFS (ISP_RAWAWB_BASE + 0x002d4)
1678 #define ISP_RAWAWB_MULTIWINDOW3_SIZE (ISP_RAWAWB_BASE + 0x002d8)
1679 #define ISP_RAWAWB_MULTIWINDOW4_OFFS (ISP_RAWAWB_BASE + 0x002dc)
1680 #define ISP_RAWAWB_MULTIWINDOW4_SIZE (ISP_RAWAWB_BASE + 0x002e0)
1681 #define ISP_RAWAWB_MULTIWINDOW5_OFFS (ISP_RAWAWB_BASE + 0x002e4)
1682 #define ISP_RAWAWB_MULTIWINDOW5_SIZE (ISP_RAWAWB_BASE + 0x002e8)
1683 #define ISP_RAWAWB_MULTIWINDOW6_OFFS (ISP_RAWAWB_BASE + 0x002ec)
1684 #define ISP_RAWAWB_MULTIWINDOW6_SIZE (ISP_RAWAWB_BASE + 0x002f0)
1685 #define ISP_RAWAWB_MULTIWINDOW7_OFFS (ISP_RAWAWB_BASE + 0x002f4)
1686 #define ISP_RAWAWB_MULTIWINDOW7_SIZE (ISP_RAWAWB_BASE + 0x002f8)
1687 #define ISP_RAWAWB_EXC_WP_REGION0_XU (ISP_RAWAWB_BASE + 0x002fc)
1688 #define ISP_RAWAWB_EXC_WP_REGION0_YV (ISP_RAWAWB_BASE + 0x00300)
1689 #define ISP_RAWAWB_EXC_WP_REGION1_XU (ISP_RAWAWB_BASE + 0x00304)
1690 #define ISP_RAWAWB_EXC_WP_REGION1_YV (ISP_RAWAWB_BASE + 0x00308)
1691 #define ISP_RAWAWB_EXC_WP_REGION2_XU (ISP_RAWAWB_BASE + 0x0030c)
1692 #define ISP_RAWAWB_EXC_WP_REGION2_YV (ISP_RAWAWB_BASE + 0x00310)
1693 #define ISP_RAWAWB_EXC_WP_REGION3_XU (ISP_RAWAWB_BASE + 0x00314)
1694 #define ISP_RAWAWB_EXC_WP_REGION3_YV (ISP_RAWAWB_BASE + 0x00318)
1695 #define ISP_RAWAWB_EXC_WP_REGION4_XU (ISP_RAWAWB_BASE + 0x0031c)
1696 #define ISP_RAWAWB_EXC_WP_REGION4_YV (ISP_RAWAWB_BASE + 0x00320)
1697 #define ISP_RAWAWB_EXC_WP_REGION5_XU (ISP_RAWAWB_BASE + 0x00324)
1698 #define ISP_RAWAWB_EXC_WP_REGION5_YV (ISP_RAWAWB_BASE + 0x00328)
1699 #define ISP_RAWAWB_EXC_WP_REGION6_XU (ISP_RAWAWB_BASE + 0x0032c)
1700 #define ISP_RAWAWB_EXC_WP_REGION6_YV (ISP_RAWAWB_BASE + 0x00330)
1701 #define ISP_RAWAWB_SUM_R_NOR_0 (ISP_RAWAWB_BASE + 0x00340)
1702 #define ISP_RAWAWB_SUM_G_NOR_0 (ISP_RAWAWB_BASE + 0x00344)
1703 #define ISP_RAWAWB_SUM_B_NOR_0 (ISP_RAWAWB_BASE + 0x00348)
1704 #define ISP_RAWAWB_WP_NUM_NOR_0 (ISP_RAWAWB_BASE + 0x0034c)
1705 #define ISP_RAWAWB_SUM_R_BIG_0 (ISP_RAWAWB_BASE + 0x00350)
1706 #define ISP_RAWAWB_SUM_G_BIG_0 (ISP_RAWAWB_BASE + 0x00354)
1707 #define ISP_RAWAWB_SUM_B_BIG_0 (ISP_RAWAWB_BASE + 0x00358)
1708 #define ISP_RAWAWB_WP_NUM_BIG_0 (ISP_RAWAWB_BASE + 0x0035c)
1709 #define ISP_RAWAWB_SUM_R_SMA_0 (ISP_RAWAWB_BASE + 0x00360)
1710 #define ISP_RAWAWB_SUM_G_SMA_0 (ISP_RAWAWB_BASE + 0x00364)
1711 #define ISP_RAWAWB_SUM_B_SMA_0 (ISP_RAWAWB_BASE + 0x00368)
1712 #define ISP_RAWAWB_WP_NUM_SMA_0 (ISP_RAWAWB_BASE + 0x0036c)
1713 #define ISP_RAWAWB_SUM_R_NOR_1 (ISP_RAWAWB_BASE + 0x00370)
1714 #define ISP_RAWAWB_SUM_G_NOR_1 (ISP_RAWAWB_BASE + 0x00374)
1715 #define ISP_RAWAWB_SUM_B_NOR_1 (ISP_RAWAWB_BASE + 0x00378)
1716 #define ISP_RAWAWB_WP_NUM_NOR_1 (ISP_RAWAWB_BASE + 0x0037c)
1717 #define ISP_RAWAWB_SUM_R_BIG_1 (ISP_RAWAWB_BASE + 0x00380)
1718 #define ISP_RAWAWB_SUM_G_BIG_1 (ISP_RAWAWB_BASE + 0x00384)
1719 #define ISP_RAWAWB_SUM_B_BIG_1 (ISP_RAWAWB_BASE + 0x00388)
1720 #define ISP_RAWAWB_WP_NUM_BIG_1 (ISP_RAWAWB_BASE + 0x0038c)
1721 #define ISP_RAWAWB_SUM_R_SMA_1 (ISP_RAWAWB_BASE + 0x00390)
1722 #define ISP_RAWAWB_SUM_G_SMA_1 (ISP_RAWAWB_BASE + 0x00394)
1723 #define ISP_RAWAWB_SUM_B_SMA_1 (ISP_RAWAWB_BASE + 0x00398)
1724 #define ISP_RAWAWB_WP_NUM_SMA_1 (ISP_RAWAWB_BASE + 0x0039c)
1725 #define ISP_RAWAWB_SUM_R_NOR_2 (ISP_RAWAWB_BASE + 0x003a0)
1726 #define ISP_RAWAWB_SUM_G_NOR_2 (ISP_RAWAWB_BASE + 0x003a4)
1727 #define ISP_RAWAWB_SUM_B_NOR_2 (ISP_RAWAWB_BASE + 0x003a8)
1728 #define ISP_RAWAWB_WP_NUM_NOR_2 (ISP_RAWAWB_BASE + 0x003ac)
1729 #define ISP_RAWAWB_SUM_R_BIG_2 (ISP_RAWAWB_BASE + 0x003b0)
1730 #define ISP_RAWAWB_SUM_G_BIG_2 (ISP_RAWAWB_BASE + 0x003b4)
1731 #define ISP_RAWAWB_SUM_B_BIG_2 (ISP_RAWAWB_BASE + 0x003b8)
1732 #define ISP_RAWAWB_WP_NUM_BIG_2 (ISP_RAWAWB_BASE + 0x003bc)
1733 #define ISP_RAWAWB_SUM_R_SMA_2 (ISP_RAWAWB_BASE + 0x003c0)
1734 #define ISP_RAWAWB_SUM_G_SMA_2 (ISP_RAWAWB_BASE + 0x003c4)
1735 #define ISP_RAWAWB_SUM_B_SMA_2 (ISP_RAWAWB_BASE + 0x003c8)
1736 #define ISP_RAWAWB_WP_NUM_SMA_2 (ISP_RAWAWB_BASE + 0x003cc)
1737 #define ISP_RAWAWB_SUM_R_NOR_3 (ISP_RAWAWB_BASE + 0x003d0)
1738 #define ISP_RAWAWB_SUM_G_NOR_3 (ISP_RAWAWB_BASE + 0x003d4)
1739 #define ISP_RAWAWB_SUM_B_NOR_3 (ISP_RAWAWB_BASE + 0x003d8)
1740 #define ISP_RAWAWB_WP_NUM_NOR_3 (ISP_RAWAWB_BASE + 0x003dc)
1741 #define ISP_RAWAWB_SUM_R_BIG_3 (ISP_RAWAWB_BASE + 0x003e0)
1742 #define ISP_RAWAWB_SUM_G_BIG_3 (ISP_RAWAWB_BASE + 0x003e4)
1743 #define ISP_RAWAWB_SUM_B_BIG_3 (ISP_RAWAWB_BASE + 0x003e8)
1744 #define ISP_RAWAWB_WP_NUM_BIG_3 (ISP_RAWAWB_BASE + 0x003ec)
1745 #define ISP_RAWAWB_SUM_R_SMA_3 (ISP_RAWAWB_BASE + 0x003f0)
1746 #define ISP_RAWAWB_SUM_G_SMA_3 (ISP_RAWAWB_BASE + 0x003f4)
1747 #define ISP_RAWAWB_SUM_B_SMA_3 (ISP_RAWAWB_BASE + 0x003f8)
1748 #define ISP_RAWAWB_WP_NUM_SMA_3 (ISP_RAWAWB_BASE + 0x003fc)
1749 #define ISP_RAWAWB_SUM_R_NOR_4 (ISP_RAWAWB_BASE + 0x00400)
1750 #define ISP_RAWAWB_SUM_G_NOR_4 (ISP_RAWAWB_BASE + 0x00404)
1751 #define ISP_RAWAWB_SUM_B_NOR_4 (ISP_RAWAWB_BASE + 0x00408)
1752 #define ISP_RAWAWB_WP_NUM_NOR_4 (ISP_RAWAWB_BASE + 0x0040c)
1753 #define ISP_RAWAWB_SUM_R_BIG_4 (ISP_RAWAWB_BASE + 0x00410)
1754 #define ISP_RAWAWB_SUM_G_BIG_4 (ISP_RAWAWB_BASE + 0x00414)
1755 #define ISP_RAWAWB_SUM_B_BIG_4 (ISP_RAWAWB_BASE + 0x00418)
1756 #define ISP_RAWAWB_WP_NUM_BIG_4 (ISP_RAWAWB_BASE + 0x0041c)
1757 #define ISP_RAWAWB_SUM_R_SMA_4 (ISP_RAWAWB_BASE + 0x00420)
1758 #define ISP_RAWAWB_SUM_G_SMA_4 (ISP_RAWAWB_BASE + 0x00424)
1759 #define ISP_RAWAWB_SUM_B_SMA_4 (ISP_RAWAWB_BASE + 0x00428)
1760 #define ISP_RAWAWB_WP_NUM_SMA_4 (ISP_RAWAWB_BASE + 0x0042c)
1761 #define ISP_RAWAWB_SUM_R_NOR_5 (ISP_RAWAWB_BASE + 0x00430)
1762 #define ISP_RAWAWB_SUM_G_NOR_5 (ISP_RAWAWB_BASE + 0x00434)
1763 #define ISP_RAWAWB_SUM_B_NOR_5 (ISP_RAWAWB_BASE + 0x00438)
1764 #define ISP_RAWAWB_WP_NUM_NOR_5 (ISP_RAWAWB_BASE + 0x0043c)
1765 #define ISP_RAWAWB_SUM_R_BIG_5 (ISP_RAWAWB_BASE + 0x00440)
1766 #define ISP_RAWAWB_SUM_G_BIG_5 (ISP_RAWAWB_BASE + 0x00444)
1767 #define ISP_RAWAWB_SUM_B_BIG_5 (ISP_RAWAWB_BASE + 0x00448)
1768 #define ISP_RAWAWB_WP_NUM_BIG_5 (ISP_RAWAWB_BASE + 0x0044c)
1769 #define ISP_RAWAWB_SUM_R_SMA_5 (ISP_RAWAWB_BASE + 0x00450)
1770 #define ISP_RAWAWB_SUM_G_SMA_5 (ISP_RAWAWB_BASE + 0x00454)
1771 #define ISP_RAWAWB_SUM_B_SMA_5 (ISP_RAWAWB_BASE + 0x00458)
1772 #define ISP_RAWAWB_WP_NUM_SMA_5 (ISP_RAWAWB_BASE + 0x0045c)
1773 #define ISP_RAWAWB_SUM_R_NOR_6 (ISP_RAWAWB_BASE + 0x00460)
1774 #define ISP_RAWAWB_SUM_G_NOR_6 (ISP_RAWAWB_BASE + 0x00464)
1775 #define ISP_RAWAWB_SUM_B_NOR_6 (ISP_RAWAWB_BASE + 0x00468)
1776 #define ISP_RAWAWB_WP_NUM_NOR_6 (ISP_RAWAWB_BASE + 0x0046c)
1777 #define ISP_RAWAWB_SUM_R_BIG_6 (ISP_RAWAWB_BASE + 0x00470)
1778 #define ISP_RAWAWB_SUM_G_BIG_6 (ISP_RAWAWB_BASE + 0x00474)
1779 #define ISP_RAWAWB_SUM_B_BIG_6 (ISP_RAWAWB_BASE + 0x00478)
1780 #define ISP_RAWAWB_WP_NUM_BIG_6 (ISP_RAWAWB_BASE + 0x0047c)
1781 #define ISP_RAWAWB_SUM_R_SMA_6 (ISP_RAWAWB_BASE + 0x00480)
1782 #define ISP_RAWAWB_SUM_G_SMA_6 (ISP_RAWAWB_BASE + 0x00484)
1783 #define ISP_RAWAWB_SUM_B_SMA_6 (ISP_RAWAWB_BASE + 0x00488)
1784 #define ISP_RAWAWB_WP_NUM_SMA_6 (ISP_RAWAWB_BASE + 0x0048c)
1785 #define ISP_RAWAWB_SUM_R_NOR_MULTIWINDOW_0 (ISP_RAWAWB_BASE + 0x00490)
1786 #define ISP_RAWAWB_SUM_G_NOR_MULTIWINDOW_0 (ISP_RAWAWB_BASE + 0x00494)
1787 #define ISP_RAWAWB_SUM_B_NOR_MULTIWINDOW_0 (ISP_RAWAWB_BASE + 0x00498)
1788 #define ISP_RAWAWB_WP_NM_NOR_MULTIWINDOW_0 (ISP_RAWAWB_BASE + 0x0049c)
1789 #define ISP_RAWAWB_SUM_R_BIG_MULTIWINDOW_0 (ISP_RAWAWB_BASE + 0x004a0)
1790 #define ISP_RAWAWB_SUM_G_BIG_MULTIWINDOW_0 (ISP_RAWAWB_BASE + 0x004a4)
1791 #define ISP_RAWAWB_SUM_B_BIG_MULTIWINDOW_0 (ISP_RAWAWB_BASE + 0x004a8)
1792 #define ISP_RAWAWB_WP_NM_BIG_MULTIWINDOW_0 (ISP_RAWAWB_BASE + 0x004ac)
1793 #define ISP_RAWAWB_SUM_R_SMA_MULTIWINDOW_0 (ISP_RAWAWB_BASE + 0x004b0)
1794 #define ISP_RAWAWB_SUM_G_SMA_MULTIWINDOW_0 (ISP_RAWAWB_BASE + 0x004b4)
1795 #define ISP_RAWAWB_SUM_B_SMA_MULTIWINDOW_0 (ISP_RAWAWB_BASE + 0x004b8)
1796 #define ISP_RAWAWB_WP_NM_SMA_MULTIWINDOW_0 (ISP_RAWAWB_BASE + 0x004bc)
1797 #define ISP_RAWAWB_SUM_R_NOR_MULTIWINDOW_1 (ISP_RAWAWB_BASE + 0x004c0)
1798 #define ISP_RAWAWB_SUM_G_NOR_MULTIWINDOW_1 (ISP_RAWAWB_BASE + 0x004c4)
1799 #define ISP_RAWAWB_SUM_B_NOR_MULTIWINDOW_1 (ISP_RAWAWB_BASE + 0x004c8)
1800 #define ISP_RAWAWB_WP_NM_NOR_MULTIWINDOW_1 (ISP_RAWAWB_BASE + 0x004cc)
1801 #define ISP_RAWAWB_SUM_R_BIG_MULTIWINDOW_1 (ISP_RAWAWB_BASE + 0x004d0)
1802 #define ISP_RAWAWB_SUM_G_BIG_MULTIWINDOW_1 (ISP_RAWAWB_BASE + 0x004d4)
1803 #define ISP_RAWAWB_SUM_B_BIG_MULTIWINDOW_1 (ISP_RAWAWB_BASE + 0x004d8)
1804 #define ISP_RAWAWB_WP_NM_BIG_MULTIWINDOW_1 (ISP_RAWAWB_BASE + 0x004dc)
1805 #define ISP_RAWAWB_SUM_R_SMA_MULTIWINDOW_1 (ISP_RAWAWB_BASE + 0x004e0)
1806 #define ISP_RAWAWB_SUM_G_SMA_MULTIWINDOW_1 (ISP_RAWAWB_BASE + 0x004e4)
1807 #define ISP_RAWAWB_SUM_B_SMA_MULTIWINDOW_1 (ISP_RAWAWB_BASE + 0x004e8)
1808 #define ISP_RAWAWB_WP_NM_SMA_MULTIWINDOW_1 (ISP_RAWAWB_BASE + 0x004ec)
1809 #define ISP_RAWAWB_SUM_R_NOR_MULTIWINDOW_2 (ISP_RAWAWB_BASE + 0x004f0)
1810 #define ISP_RAWAWB_SUM_G_NOR_MULTIWINDOW_2 (ISP_RAWAWB_BASE + 0x004f4)
1811 #define ISP_RAWAWB_SUM_B_NOR_MULTIWINDOW_2 (ISP_RAWAWB_BASE + 0x004f8)
1812 #define ISP_RAWAWB_WP_NM_NOR_MULTIWINDOW_2 (ISP_RAWAWB_BASE + 0x004fc)
1813 #define ISP_RAWAWB_SUM_R_BIG_MULTIWINDOW_2 (ISP_RAWAWB_BASE + 0x00500)
1814 #define ISP_RAWAWB_SUM_G_BIG_MULTIWINDOW_2 (ISP_RAWAWB_BASE + 0x00504)
1815 #define ISP_RAWAWB_SUM_B_BIG_MULTIWINDOW_2 (ISP_RAWAWB_BASE + 0x00508)
1816 #define ISP_RAWAWB_WP_NM_BIG_MULTIWINDOW_2 (ISP_RAWAWB_BASE + 0x0050c)
1817 #define ISP_RAWAWB_SUM_R_SMA_MULTIWINDOW_2 (ISP_RAWAWB_BASE + 0x00510)
1818 #define ISP_RAWAWB_SUM_G_SMA_MULTIWINDOW_2 (ISP_RAWAWB_BASE + 0x00514)
1819 #define ISP_RAWAWB_SUM_B_SMA_MULTIWINDOW_2 (ISP_RAWAWB_BASE + 0x00518)
1820 #define ISP_RAWAWB_WP_NM_SMA_MULTIWINDOW_2 (ISP_RAWAWB_BASE + 0x0051c)
1821 #define ISP_RAWAWB_SUM_R_NOR_MULTIWINDOW_3 (ISP_RAWAWB_BASE + 0x00520)
1822 #define ISP_RAWAWB_SUM_G_NOR_MULTIWINDOW_3 (ISP_RAWAWB_BASE + 0x00524)
1823 #define ISP_RAWAWB_SUM_B_NOR_MULTIWINDOW_3 (ISP_RAWAWB_BASE + 0x00528)
1824 #define ISP_RAWAWB_WP_NM_NOR_MULTIWINDOW_3 (ISP_RAWAWB_BASE + 0x0052c)
1825 #define ISP_RAWAWB_SUM_R_BIG_MULTIWINDOW_3 (ISP_RAWAWB_BASE + 0x00530)
1826 #define ISP_RAWAWB_SUM_G_BIG_MULTIWINDOW_3 (ISP_RAWAWB_BASE + 0x00534)
1827 #define ISP_RAWAWB_SUM_B_BIG_MULTIWINDOW_3 (ISP_RAWAWB_BASE + 0x00538)
1828 #define ISP_RAWAWB_WP_NM_BIG_MULTIWINDOW_3 (ISP_RAWAWB_BASE + 0x0053c)
1829 #define ISP_RAWAWB_SUM_R_SMA_MULTIWINDOW_3 (ISP_RAWAWB_BASE + 0x00540)
1830 #define ISP_RAWAWB_SUM_G_SMA_MULTIWINDOW_3 (ISP_RAWAWB_BASE + 0x00544)
1831 #define ISP_RAWAWB_SUM_B_SMA_MULTIWINDOW_3 (ISP_RAWAWB_BASE + 0x00548)
1832 #define ISP_RAWAWB_WP_NM_SMA_MULTIWINDOW_3 (ISP_RAWAWB_BASE + 0x0054c)
1833 #define ISP_RAWAWB_SUM_R_NOR_MULTIWINDOW_4 (ISP_RAWAWB_BASE + 0x00550)
1834 #define ISP_RAWAWB_SUM_G_NOR_MULTIWINDOW_4 (ISP_RAWAWB_BASE + 0x00554)
1835 #define ISP_RAWAWB_SUM_B_NOR_MULTIWINDOW_4 (ISP_RAWAWB_BASE + 0x00558)
1836 #define ISP_RAWAWB_WP_NM_NOR_MULTIWINDOW_4 (ISP_RAWAWB_BASE + 0x0055c)
1837 #define ISP_RAWAWB_SUM_R_BIG_MULTIWINDOW_4 (ISP_RAWAWB_BASE + 0x00560)
1838 #define ISP_RAWAWB_SUM_G_BIG_MULTIWINDOW_4 (ISP_RAWAWB_BASE + 0x00564)
1839 #define ISP_RAWAWB_SUM_B_BIG_MULTIWINDOW_4 (ISP_RAWAWB_BASE + 0x00568)
1840 #define ISP_RAWAWB_WP_NM_BIG_MULTIWINDOW_4 (ISP_RAWAWB_BASE + 0x0056c)
1841 #define ISP_RAWAWB_SUM_R_SMA_MULTIWINDOW_4 (ISP_RAWAWB_BASE + 0x00570)
1842 #define ISP_RAWAWB_SUM_G_SMA_MULTIWINDOW_4 (ISP_RAWAWB_BASE + 0x00574)
1843 #define ISP_RAWAWB_SUM_B_SMA_MULTIWINDOW_4 (ISP_RAWAWB_BASE + 0x00578)
1844 #define ISP_RAWAWB_WP_NM_SMA_MULTIWINDOW_4 (ISP_RAWAWB_BASE + 0x0057c)
1845 #define ISP_RAWAWB_SUM_R_NOR_MULTIWINDOW_5 (ISP_RAWAWB_BASE + 0x00580)
1846 #define ISP_RAWAWB_SUM_G_NOR_MULTIWINDOW_5 (ISP_RAWAWB_BASE + 0x00584)
1847 #define ISP_RAWAWB_SUM_B_NOR_MULTIWINDOW_5 (ISP_RAWAWB_BASE + 0x00588)
1848 #define ISP_RAWAWB_WP_NM_NOR_MULTIWINDOW_5 (ISP_RAWAWB_BASE + 0x0058c)
1849 #define ISP_RAWAWB_SUM_R_BIG_MULTIWINDOW_5 (ISP_RAWAWB_BASE + 0x00590)
1850 #define ISP_RAWAWB_SUM_G_BIG_MULTIWINDOW_5 (ISP_RAWAWB_BASE + 0x00594)
1851 #define ISP_RAWAWB_SUM_B_BIG_MULTIWINDOW_5 (ISP_RAWAWB_BASE + 0x00598)
1852 #define ISP_RAWAWB_WP_NM_BIG_MULTIWINDOW_5 (ISP_RAWAWB_BASE + 0x0059c)
1853 #define ISP_RAWAWB_SUM_R_SMA_MULTIWINDOW_5 (ISP_RAWAWB_BASE + 0x005a0)
1854 #define ISP_RAWAWB_SUM_G_SMA_MULTIWINDOW_5 (ISP_RAWAWB_BASE + 0x005a4)
1855 #define ISP_RAWAWB_SUM_B_SMA_MULTIWINDOW_5 (ISP_RAWAWB_BASE + 0x005a8)
1856 #define ISP_RAWAWB_WP_NM_SMA_MULTIWINDOW_5 (ISP_RAWAWB_BASE + 0x005ac)
1857 #define ISP_RAWAWB_SUM_R_NOR_MULTIWINDOW_6 (ISP_RAWAWB_BASE + 0x005b0)
1858 #define ISP_RAWAWB_SUM_G_NOR_MULTIWINDOW_6 (ISP_RAWAWB_BASE + 0x005b4)
1859 #define ISP_RAWAWB_SUM_B_NOR_MULTIWINDOW_6 (ISP_RAWAWB_BASE + 0x005b8)
1860 #define ISP_RAWAWB_WP_NM_NOR_MULTIWINDOW_6 (ISP_RAWAWB_BASE + 0x005bc)
1861 #define ISP_RAWAWB_SUM_R_BIG_MULTIWINDOW_6 (ISP_RAWAWB_BASE + 0x005c0)
1862 #define ISP_RAWAWB_SUM_G_BIG_MULTIWINDOW_6 (ISP_RAWAWB_BASE + 0x005c4)
1863 #define ISP_RAWAWB_SUM_B_BIG_MULTIWINDOW_6 (ISP_RAWAWB_BASE + 0x005c8)
1864 #define ISP_RAWAWB_WP_NM_BIG_MULTIWINDOW_6 (ISP_RAWAWB_BASE + 0x005cc)
1865 #define ISP_RAWAWB_SUM_R_SMA_MULTIWINDOW_6 (ISP_RAWAWB_BASE + 0x005d0)
1866 #define ISP_RAWAWB_SUM_G_SMA_MULTIWINDOW_6 (ISP_RAWAWB_BASE + 0x005d4)
1867 #define ISP_RAWAWB_SUM_B_SMA_MULTIWINDOW_6 (ISP_RAWAWB_BASE + 0x005d8)
1868 #define ISP_RAWAWB_WP_NM_SMA_MULTIWINDOW_6 (ISP_RAWAWB_BASE + 0x005dc)
1869 #define ISP_RAWAWB_SUM_R_EXC_0 (ISP_RAWAWB_BASE + 0x005e0)
1870 #define ISP_RAWAWB_SUM_G_EXC_0 (ISP_RAWAWB_BASE + 0x005e4)
1871 #define ISP_RAWAWB_SUM_B_EXC_0 (ISP_RAWAWB_BASE + 0x005e8)
1872 #define ISP_RAWAWB_WP_NM_EXC_0 (ISP_RAWAWB_BASE + 0x005ec)
1873 #define ISP_RAWAWB_SUM_R_EXC_1 (ISP_RAWAWB_BASE + 0x005f0)
1874 #define ISP_RAWAWB_SUM_G_EXC_1 (ISP_RAWAWB_BASE + 0x005f4)
1875 #define ISP_RAWAWB_SUM_B_EXC_1 (ISP_RAWAWB_BASE + 0x005f8)
1876 #define ISP_RAWAWB_WP_NM_EXC_1 (ISP_RAWAWB_BASE + 0x005fc)
1877 #define ISP_RAWAWB_SUM_R_EXC_2 (ISP_RAWAWB_BASE + 0x00600)
1878 #define ISP_RAWAWB_SUM_G_EXC_2 (ISP_RAWAWB_BASE + 0x00604)
1879 #define ISP_RAWAWB_SUM_B_EXC_2 (ISP_RAWAWB_BASE + 0x00608)
1880 #define ISP_RAWAWB_WP_NM_EXC_2 (ISP_RAWAWB_BASE + 0x0060c)
1881 #define ISP_RAWAWB_SUM_R_EXC_3 (ISP_RAWAWB_BASE + 0x00610)
1882 #define ISP_RAWAWB_SUM_G_EXC_3 (ISP_RAWAWB_BASE + 0x00614)
1883 #define ISP_RAWAWB_SUM_B_EXC_3 (ISP_RAWAWB_BASE + 0x00618)
1884 #define ISP_RAWAWB_WP_NM_EXC_3 (ISP_RAWAWB_BASE + 0x0061c)
1885 #define ISP_RAWAWB_SUM_R_EXC_4 (ISP_RAWAWB_BASE + 0x00620)
1886 #define ISP_RAWAWB_SUM_G_EXC_4 (ISP_RAWAWB_BASE + 0x00624)
1887 #define ISP_RAWAWB_SUM_B_EXC_4 (ISP_RAWAWB_BASE + 0x00628)
1888 #define ISP_RAWAWB_WP_NM_EXC_4 (ISP_RAWAWB_BASE + 0x0062c)
1889 #define ISP_RAWAWB_SUM_R_EXC_5 (ISP_RAWAWB_BASE + 0x00630)
1890 #define ISP_RAWAWB_SUM_G_EXC_5 (ISP_RAWAWB_BASE + 0x00634)
1891 #define ISP_RAWAWB_SUM_B_EXC_5 (ISP_RAWAWB_BASE + 0x00638)
1892 #define ISP_RAWAWB_WP_NM_EXC_5 (ISP_RAWAWB_BASE + 0x0063c)
1893 #define ISP_RAWAWB_SUM_R_EXC_6 (ISP_RAWAWB_BASE + 0x00640)
1894 #define ISP_RAWAWB_SUM_G_EXC_6 (ISP_RAWAWB_BASE + 0x00644)
1895 #define ISP_RAWAWB_SUM_B_EXC_6 (ISP_RAWAWB_BASE + 0x00648)
1896 #define ISP_RAWAWB_WP_NM_EXC_6 (ISP_RAWAWB_BASE + 0x0064c)
1897 #define ISP_RAWAWB_RAM_CTRL (ISP_RAWAWB_BASE + 0x00650)
1898 #define ISP_RAWAWB_RAM_DATA (ISP_RAWAWB_BASE + 0x00660)
1899
1900 #define ISP21_RAWAWB_BASE 0x00005000
1901 #define ISP21_RAWAWB_CTRL (ISP21_RAWAWB_BASE + 0x0000)
1902 #define ISP21_RAWAWB_BLK_CTRL (ISP21_RAWAWB_BASE + 0x0004)
1903 #define ISP21_RAWAWB_WIN_OFFS (ISP21_RAWAWB_BASE + 0x0008)
1904 #define ISP21_RAWAWB_WIN_SIZE (ISP21_RAWAWB_BASE + 0x000c)
1905 #define ISP21_RAWAWB_LIMIT_RG_MAX (ISP21_RAWAWB_BASE + 0x0010)
1906 #define ISP21_RAWAWB_LIMIT_BY_MAX (ISP21_RAWAWB_BASE + 0x0014)
1907 #define ISP21_RAWAWB_LIMIT_RG_MIN (ISP21_RAWAWB_BASE + 0x0018)
1908 #define ISP21_RAWAWB_LIMIT_BY_MIN (ISP21_RAWAWB_BASE + 0x001c)
1909 #define ISP21_RAWAWB_WEIGHT_CURVE_CTRL (ISP21_RAWAWB_BASE + 0x0020)
1910 #define ISP21_RAWAWB_YWEIGHT_CURVE_XCOOR03 (ISP21_RAWAWB_BASE + 0x0024)
1911 #define ISP21_RAWAWB_YWEIGHT_CURVE_XCOOR47 (ISP21_RAWAWB_BASE + 0x0028)
1912 #define ISP21_RAWAWB_YWEIGHT_CURVE_XCOOR8 (ISP21_RAWAWB_BASE + 0x002c)
1913 #define ISP21_RAWAWB_YWEIGHT_CURVE_YCOOR03 (ISP21_RAWAWB_BASE + 0x0030)
1914 #define ISP21_RAWAWB_YWEIGHT_CURVE_YCOOR47 (ISP21_RAWAWB_BASE + 0x0034)
1915 #define ISP21_RAWAWB_YWEIGHT_CURVE_YCOOR8 (ISP21_RAWAWB_BASE + 0x0038)
1916 #define ISP21_RAWAWB_PRE_WBGAIN_INV (ISP21_RAWAWB_BASE + 0x003c)
1917 #define ISP21_RAWAWB_UV_DETC_VERTEX0_0 (ISP21_RAWAWB_BASE + 0x0040)
1918 #define ISP21_RAWAWB_UV_DETC_VERTEX1_0 (ISP21_RAWAWB_BASE + 0x0044)
1919 #define ISP21_RAWAWB_UV_DETC_VERTEX2_0 (ISP21_RAWAWB_BASE + 0x0048)
1920 #define ISP21_RAWAWB_UV_DETC_VERTEX3_0 (ISP21_RAWAWB_BASE + 0x004c)
1921 #define ISP21_RAWAWB_UV_DETC_ISLOPE01_0 (ISP21_RAWAWB_BASE + 0x0050)
1922 #define ISP21_RAWAWB_UV_DETC_ISLOPE12_0 (ISP21_RAWAWB_BASE + 0x0054)
1923 #define ISP21_RAWAWB_UV_DETC_ISLOPE23_0 (ISP21_RAWAWB_BASE + 0x0058)
1924 #define ISP21_RAWAWB_UV_DETC_ISLOPE30_0 (ISP21_RAWAWB_BASE + 0x005c)
1925 #define ISP21_RAWAWB_UV_DETC_VERTEX0_1 (ISP21_RAWAWB_BASE + 0x0060)
1926 #define ISP21_RAWAWB_UV_DETC_VERTEX1_1 (ISP21_RAWAWB_BASE + 0x0064)
1927 #define ISP21_RAWAWB_UV_DETC_VERTEX2_1 (ISP21_RAWAWB_BASE + 0x0068)
1928 #define ISP21_RAWAWB_UV_DETC_VERTEX3_1 (ISP21_RAWAWB_BASE + 0x006c)
1929 #define ISP21_RAWAWB_UV_DETC_ISLOPE01_1 (ISP21_RAWAWB_BASE + 0x0070)
1930 #define ISP21_RAWAWB_UV_DETC_ISLOPE12_1 (ISP21_RAWAWB_BASE + 0x0074)
1931 #define ISP21_RAWAWB_UV_DETC_ISLOPE23_1 (ISP21_RAWAWB_BASE + 0x0078)
1932 #define ISP21_RAWAWB_UV_DETC_ISLOPE30_1 (ISP21_RAWAWB_BASE + 0x007c)
1933 #define ISP21_RAWAWB_UV_DETC_VERTEX0_2 (ISP21_RAWAWB_BASE + 0x0080)
1934 #define ISP21_RAWAWB_UV_DETC_VERTEX1_2 (ISP21_RAWAWB_BASE + 0x0084)
1935 #define ISP21_RAWAWB_UV_DETC_VERTEX2_2 (ISP21_RAWAWB_BASE + 0x0088)
1936 #define ISP21_RAWAWB_UV_DETC_VERTEX3_2 (ISP21_RAWAWB_BASE + 0x008c)
1937 #define ISP21_RAWAWB_UV_DETC_ISLOPE01_2 (ISP21_RAWAWB_BASE + 0x0090)
1938 #define ISP21_RAWAWB_UV_DETC_ISLOPE12_2 (ISP21_RAWAWB_BASE + 0x0094)
1939 #define ISP21_RAWAWB_UV_DETC_ISLOPE23_2 (ISP21_RAWAWB_BASE + 0x0098)
1940 #define ISP21_RAWAWB_UV_DETC_ISLOPE30_2 (ISP21_RAWAWB_BASE + 0x009c)
1941 #define ISP21_RAWAWB_UV_DETC_VERTEX0_3 (ISP21_RAWAWB_BASE + 0x00a0)
1942 #define ISP21_RAWAWB_UV_DETC_VERTEX1_3 (ISP21_RAWAWB_BASE + 0x00a4)
1943 #define ISP21_RAWAWB_UV_DETC_VERTEX2_3 (ISP21_RAWAWB_BASE + 0x00a8)
1944 #define ISP21_RAWAWB_UV_DETC_VERTEX3_3 (ISP21_RAWAWB_BASE + 0x00ac)
1945 #define ISP21_RAWAWB_UV_DETC_ISLOPE01_3 (ISP21_RAWAWB_BASE + 0x00b0)
1946 #define ISP21_RAWAWB_UV_DETC_ISLOPE12_3 (ISP21_RAWAWB_BASE + 0x00b4)
1947 #define ISP21_RAWAWB_UV_DETC_ISLOPE23_3 (ISP21_RAWAWB_BASE + 0x00b8)
1948 #define ISP21_RAWAWB_UV_DETC_ISLOPE30_3 (ISP21_RAWAWB_BASE + 0x00bc)
1949 #define ISP21_RAWAWB_UV_DETC_VERTEX0_4 (ISP21_RAWAWB_BASE + 0x00c0)
1950 #define ISP21_RAWAWB_UV_DETC_VERTEX1_4 (ISP21_RAWAWB_BASE + 0x00c4)
1951 #define ISP21_RAWAWB_UV_DETC_VERTEX2_4 (ISP21_RAWAWB_BASE + 0x00c8)
1952 #define ISP21_RAWAWB_UV_DETC_VERTEX3_4 (ISP21_RAWAWB_BASE + 0x00cc)
1953 #define ISP21_RAWAWB_UV_DETC_ISLOPE01_4 (ISP21_RAWAWB_BASE + 0x00d0)
1954 #define ISP21_RAWAWB_UV_DETC_ISLOPE12_4 (ISP21_RAWAWB_BASE + 0x00d4)
1955 #define ISP21_RAWAWB_UV_DETC_ISLOPE23_4 (ISP21_RAWAWB_BASE + 0x00d8)
1956 #define ISP21_RAWAWB_UV_DETC_ISLOPE30_4 (ISP21_RAWAWB_BASE + 0x00dc)
1957 #define ISP21_RAWAWB_UV_DETC_VERTEX0_5 (ISP21_RAWAWB_BASE + 0x00e0)
1958 #define ISP21_RAWAWB_UV_DETC_VERTEX1_5 (ISP21_RAWAWB_BASE + 0x00e4)
1959 #define ISP21_RAWAWB_UV_DETC_VERTEX2_5 (ISP21_RAWAWB_BASE + 0x00e8)
1960 #define ISP21_RAWAWB_UV_DETC_VERTEX3_5 (ISP21_RAWAWB_BASE + 0x00ec)
1961 #define ISP21_RAWAWB_UV_DETC_ISLOPE01_5 (ISP21_RAWAWB_BASE + 0x00f0)
1962 #define ISP21_RAWAWB_UV_DETC_ISLOPE10_5 (ISP21_RAWAWB_BASE + 0x00f4)
1963 #define ISP21_RAWAWB_UV_DETC_ISLOPE23_5 (ISP21_RAWAWB_BASE + 0x00f8)
1964 #define ISP21_RAWAWB_UV_DETC_ISLOPE30_5 (ISP21_RAWAWB_BASE + 0x00fc)
1965 #define ISP21_RAWAWB_UV_DETC_VERTEX0_6 (ISP21_RAWAWB_BASE + 0x0100)
1966 #define ISP21_RAWAWB_UV_DETC_VERTEX1_6 (ISP21_RAWAWB_BASE + 0x0104)
1967 #define ISP21_RAWAWB_UV_DETC_VERTEX2_6 (ISP21_RAWAWB_BASE + 0x0108)
1968 #define ISP21_RAWAWB_UV_DETC_VERTEX3_6 (ISP21_RAWAWB_BASE + 0x010c)
1969 #define ISP21_RAWAWB_UV_DETC_ISLOPE01_6 (ISP21_RAWAWB_BASE + 0x0110)
1970 #define ISP21_RAWAWB_UV_DETC_ISLOPE10_6 (ISP21_RAWAWB_BASE + 0x0114)
1971 #define ISP21_RAWAWB_UV_DETC_ISLOPE23_6 (ISP21_RAWAWB_BASE + 0x0118)
1972 #define ISP21_RAWAWB_UV_DETC_ISLOPE30_6 (ISP21_RAWAWB_BASE + 0x011c)
1973 #define ISP21_RAWAWB_YUV_RGB2ROTY_0 (ISP21_RAWAWB_BASE + 0x0120)
1974 #define ISP21_RAWAWB_YUV_RGB2ROTY_1 (ISP21_RAWAWB_BASE + 0x0124)
1975 #define ISP21_RAWAWB_YUV_RGB2ROTU_0 (ISP21_RAWAWB_BASE + 0x0128)
1976 #define ISP21_RAWAWB_YUV_RGB2ROTU_1 (ISP21_RAWAWB_BASE + 0x012c)
1977 #define ISP21_RAWAWB_YUV_RGB2ROTV_0 (ISP21_RAWAWB_BASE + 0x0130)
1978 #define ISP21_RAWAWB_YUV_RGB2ROTV_1 (ISP21_RAWAWB_BASE + 0x0134)
1979 #define ISP21_RAWAWB_YUV_X_COOR_Y_0 (ISP21_RAWAWB_BASE + 0x0140)
1980 #define ISP21_RAWAWB_YUV_X_COOR_U_0 (ISP21_RAWAWB_BASE + 0x0144)
1981 #define ISP21_RAWAWB_YUV_X_COOR_V_0 (ISP21_RAWAWB_BASE + 0x0148)
1982 #define ISP21_RAWAWB_YUV_X1X2_DIS_0 (ISP21_RAWAWB_BASE + 0x014c)
1983 #define ISP21_RAWAWB_YUV_INTERP_CURVE_UCOOR_0 (ISP21_RAWAWB_BASE + 0x0150)
1984 #define ISP21_RAWAWB_YUV_INTERP_CURVE_TH0_0 (ISP21_RAWAWB_BASE + 0x0154)
1985 #define ISP21_RAWAWB_YUV_INTERP_CURVE_TH1_0 (ISP21_RAWAWB_BASE + 0x0158)
1986 #define ISP21_RAWAWB_YUV_INTERP_CURVE_TH2_0 (ISP21_RAWAWB_BASE + 0x015c)
1987 #define ISP21_RAWAWB_YUV_X_COOR_Y_1 (ISP21_RAWAWB_BASE + 0x0160)
1988 #define ISP21_RAWAWB_YUV_X_COOR_U_1 (ISP21_RAWAWB_BASE + 0x0164)
1989 #define ISP21_RAWAWB_YUV_X_COOR_V_1 (ISP21_RAWAWB_BASE + 0x0168)
1990 #define ISP21_RAWAWB_YUV_X1X2_DIS_1 (ISP21_RAWAWB_BASE + 0x016c)
1991 #define ISP21_RAWAWB_YUV_INTERP_CURVE_UCOOR_1 (ISP21_RAWAWB_BASE + 0x0170)
1992 #define ISP21_RAWAWB_YUV_INTERP_CURVE_TH0_1 (ISP21_RAWAWB_BASE + 0x0174)
1993 #define ISP21_RAWAWB_YUV_INTERP_CURVE_TH1_1 (ISP21_RAWAWB_BASE + 0x0178)
1994 #define ISP21_RAWAWB_YUV_INTERP_CURVE_TH2_1 (ISP21_RAWAWB_BASE + 0x017c)
1995 #define ISP21_RAWAWB_YUV_X_COOR_Y_2 (ISP21_RAWAWB_BASE + 0x0180)
1996 #define ISP21_RAWAWB_YUV_X_COOR_U_2 (ISP21_RAWAWB_BASE + 0x0184)
1997 #define ISP21_RAWAWB_YUV_X_COOR_V_2 (ISP21_RAWAWB_BASE + 0x0188)
1998 #define ISP21_RAWAWB_YUV_X1X2_DIS_2 (ISP21_RAWAWB_BASE + 0x018c)
1999 #define ISP21_RAWAWB_YUV_INTERP_CURVE_UCOOR_2 (ISP21_RAWAWB_BASE + 0x0190)
2000 #define ISP21_RAWAWB_YUV_INTERP_CURVE_TH0_2 (ISP21_RAWAWB_BASE + 0x0194)
2001 #define ISP21_RAWAWB_YUV_INTERP_CURVE_TH1_2 (ISP21_RAWAWB_BASE + 0x0198)
2002 #define ISP21_RAWAWB_YUV_INTERP_CURVE_TH2_2 (ISP21_RAWAWB_BASE + 0x019c)
2003 #define ISP21_RAWAWB_YUV_X_COOR_Y_3 (ISP21_RAWAWB_BASE + 0x01a0)
2004 #define ISP21_RAWAWB_YUV_X_COOR_U_3 (ISP21_RAWAWB_BASE + 0x01a4)
2005 #define ISP21_RAWAWB_YUV_X_COOR_V_3 (ISP21_RAWAWB_BASE + 0x01a8)
2006 #define ISP21_RAWAWB_YUV_X1X2_DIS_3 (ISP21_RAWAWB_BASE + 0x01ac)
2007 #define ISP21_RAWAWB_YUV_INTERP_CURVE_UCOOR_3 (ISP21_RAWAWB_BASE + 0x01b0)
2008 #define ISP21_RAWAWB_YUV_INTERP_CURVE_TH0_3 (ISP21_RAWAWB_BASE + 0x01b4)
2009 #define ISP21_RAWAWB_YUV_INTERP_CURVE_TH1_3 (ISP21_RAWAWB_BASE + 0x01b8)
2010 #define ISP21_RAWAWB_YUV_INTERP_CURVE_TH2_3 (ISP21_RAWAWB_BASE + 0x01bc)
2011 #define ISP21_RAWAWB_RGB2XY_WT01 (ISP21_RAWAWB_BASE + 0x01fc)
2012 #define ISP21_RAWAWB_RGB2XY_WT2 (ISP21_RAWAWB_BASE + 0x0200)
2013 #define ISP21_RAWAWB_RGB2XY_MAT0_XY (ISP21_RAWAWB_BASE + 0x0204)
2014 #define ISP21_RAWAWB_RGB2XY_MAT1_XY (ISP21_RAWAWB_BASE + 0x0208)
2015 #define ISP21_RAWAWB_RGB2XY_MAT2_XY (ISP21_RAWAWB_BASE + 0x020c)
2016 #define ISP21_RAWAWB_XY_DETC_NOR_X_0 (ISP21_RAWAWB_BASE + 0x0210)
2017 #define ISP21_RAWAWB_XY_DETC_NOR_Y_0 (ISP21_RAWAWB_BASE + 0x0214)
2018 #define ISP21_RAWAWB_XY_DETC_BIG_X_0 (ISP21_RAWAWB_BASE + 0x0218)
2019 #define ISP21_RAWAWB_XY_DETC_BIG_Y_0 (ISP21_RAWAWB_BASE + 0x021c)
2020 #define ISP21_RAWAWB_XY_DETC_NOR_X_1 (ISP21_RAWAWB_BASE + 0x0228)
2021 #define ISP21_RAWAWB_XY_DETC_NOR_Y_1 (ISP21_RAWAWB_BASE + 0x022c)
2022 #define ISP21_RAWAWB_XY_DETC_BIG_X_1 (ISP21_RAWAWB_BASE + 0x0230)
2023 #define ISP21_RAWAWB_XY_DETC_BIG_Y_1 (ISP21_RAWAWB_BASE + 0x0234)
2024 #define ISP21_RAWAWB_XY_DETC_NOR_X_2 (ISP21_RAWAWB_BASE + 0x0240)
2025 #define ISP21_RAWAWB_XY_DETC_NOR_Y_2 (ISP21_RAWAWB_BASE + 0x0244)
2026 #define ISP21_RAWAWB_XY_DETC_BIG_X_2 (ISP21_RAWAWB_BASE + 0x0248)
2027 #define ISP21_RAWAWB_XY_DETC_BIG_Y_2 (ISP21_RAWAWB_BASE + 0x024c)
2028 #define ISP21_RAWAWB_XY_DETC_NOR_X_3 (ISP21_RAWAWB_BASE + 0x0258)
2029 #define ISP21_RAWAWB_XY_DETC_NOR_Y_3 (ISP21_RAWAWB_BASE + 0x025c)
2030 #define ISP21_RAWAWB_XY_DETC_BIG_X_3 (ISP21_RAWAWB_BASE + 0x0260)
2031 #define ISP21_RAWAWB_XY_DETC_BIG_Y_3 (ISP21_RAWAWB_BASE + 0x0264)
2032 #define ISP21_RAWAWB_XY_DETC_NOR_X_4 (ISP21_RAWAWB_BASE + 0x0270)
2033 #define ISP21_RAWAWB_XY_DETC_NOR_Y_4 (ISP21_RAWAWB_BASE + 0x0274)
2034 #define ISP21_RAWAWB_XY_DETC_BIG_X_4 (ISP21_RAWAWB_BASE + 0x0278)
2035 #define ISP21_RAWAWB_XY_DETC_BIG_Y_4 (ISP21_RAWAWB_BASE + 0x027c)
2036 #define ISP21_RAWAWB_XY_DETC_NOR_X_5 (ISP21_RAWAWB_BASE + 0x0288)
2037 #define ISP21_RAWAWB_XY_DETC_NOR_Y_5 (ISP21_RAWAWB_BASE + 0x028c)
2038 #define ISP21_RAWAWB_XY_DETC_BIG_X_5 (ISP21_RAWAWB_BASE + 0x0290)
2039 #define ISP21_RAWAWB_XY_DETC_BIG_Y_5 (ISP21_RAWAWB_BASE + 0x0294)
2040 #define ISP21_RAWAWB_XY_DETC_NOR_X_6 (ISP21_RAWAWB_BASE + 0x02a0)
2041 #define ISP21_RAWAWB_XY_DETC_NOR_Y_6 (ISP21_RAWAWB_BASE + 0x02a4)
2042 #define ISP21_RAWAWB_XY_DETC_BIG_X_6 (ISP21_RAWAWB_BASE + 0x02a8)
2043 #define ISP21_RAWAWB_XY_DETC_BIG_Y_6 (ISP21_RAWAWB_BASE + 0x02ac)
2044 #define ISP21_RAWAWB_MULTIWINDOW_EXC_CTRL (ISP21_RAWAWB_BASE + 0x02b8)
2045 #define ISP21_RAWAWB_EXC_WP_REGION0_XU (ISP21_RAWAWB_BASE + 0x02fc)
2046 #define ISP21_RAWAWB_EXC_WP_REGION0_YV (ISP21_RAWAWB_BASE + 0x0300)
2047 #define ISP21_RAWAWB_EXC_WP_REGION1_XU (ISP21_RAWAWB_BASE + 0x0304)
2048 #define ISP21_RAWAWB_EXC_WP_REGION1_YV (ISP21_RAWAWB_BASE + 0x0308)
2049 #define ISP21_RAWAWB_EXC_WP_REGION2_XU (ISP21_RAWAWB_BASE + 0x030c)
2050 #define ISP21_RAWAWB_EXC_WP_REGION2_YV (ISP21_RAWAWB_BASE + 0x0310)
2051 #define ISP21_RAWAWB_EXC_WP_REGION3_XU (ISP21_RAWAWB_BASE + 0x0314)
2052 #define ISP21_RAWAWB_EXC_WP_REGION3_YV (ISP21_RAWAWB_BASE + 0x0318)
2053 #define ISP21_RAWAWB_EXC_WP_REGION4_XU (ISP21_RAWAWB_BASE + 0x031c)
2054 #define ISP21_RAWAWB_EXC_WP_REGION4_YV (ISP21_RAWAWB_BASE + 0x0320)
2055 #define ISP21_RAWAWB_EXC_WP_REGION5_XU (ISP21_RAWAWB_BASE + 0x0324)
2056 #define ISP21_RAWAWB_EXC_WP_REGION5_YV (ISP21_RAWAWB_BASE + 0x0328)
2057 #define ISP21_RAWAWB_EXC_WP_REGION6_XU (ISP21_RAWAWB_BASE + 0x032c)
2058 #define ISP21_RAWAWB_EXC_WP_REGION6_YV (ISP21_RAWAWB_BASE + 0x0330)
2059 #define ISP21_RAWAWB_SUM_RGAIN_NOR_0 (ISP21_RAWAWB_BASE + 0x0340)
2060 #define ISP21_RAWAWB_SUM_BGAIN_NOR_0 (ISP21_RAWAWB_BASE + 0x0348)
2061 #define ISP21_RAWAWB_WP_NUM_NOR_0 (ISP21_RAWAWB_BASE + 0x034c)
2062 #define ISP21_RAWAWB_SUM_RGAIN_BIG_0 (ISP21_RAWAWB_BASE + 0x0350)
2063 #define ISP21_RAWAWB_SUM_BGAIN_BIG_0 (ISP21_RAWAWB_BASE + 0x0358)
2064 #define ISP21_RAWAWB_WP_NUM_BIG_0 (ISP21_RAWAWB_BASE + 0x035c)
2065 #define ISP21_RAWAWB_SUM_RGAIN_NOR_1 (ISP21_RAWAWB_BASE + 0x0370)
2066 #define ISP21_RAWAWB_SUM_BGAIN_NOR_1 (ISP21_RAWAWB_BASE + 0x0378)
2067 #define ISP21_RAWAWB_WP_NUM_NOR_1 (ISP21_RAWAWB_BASE + 0x037c)
2068 #define ISP21_RAWAWB_SUM_RGAIN_BIG_1 (ISP21_RAWAWB_BASE + 0x0380)
2069 #define ISP21_RAWAWB_SUM_BGAIN_BIG_1 (ISP21_RAWAWB_BASE + 0x0388)
2070 #define ISP21_RAWAWB_WP_NUM_BIG_1 (ISP21_RAWAWB_BASE + 0x038c)
2071 #define ISP21_RAWAWB_SUM_RGAIN_NOR_2 (ISP21_RAWAWB_BASE + 0x03a0)
2072 #define ISP21_RAWAWB_SUM_BGAIN_NOR_2 (ISP21_RAWAWB_BASE + 0x03a8)
2073 #define ISP21_RAWAWB_WP_NUM_NOR_2 (ISP21_RAWAWB_BASE + 0x03ac)
2074 #define ISP21_RAWAWB_SUM_RGAIN_BIG_2 (ISP21_RAWAWB_BASE + 0x03b0)
2075 #define ISP21_RAWAWB_SUM_BGAIN_BIG_2 (ISP21_RAWAWB_BASE + 0x03b8)
2076 #define ISP21_RAWAWB_WP_NUM_BIG_2 (ISP21_RAWAWB_BASE + 0x03bc)
2077 #define ISP21_RAWAWB_SUM_RGAIN_NOR_3 (ISP21_RAWAWB_BASE + 0x03d0)
2078 #define ISP21_RAWAWB_SUM_BGAIN_NOR_3 (ISP21_RAWAWB_BASE + 0x03d8)
2079 #define ISP21_RAWAWB_WP_NUM_NOR_3 (ISP21_RAWAWB_BASE + 0x03dc)
2080 #define ISP21_RAWAWB_SUM_RGAIN_BIG_3 (ISP21_RAWAWB_BASE + 0x03e0)
2081 #define ISP21_RAWAWB_SUM_BGAIN_BIG_3 (ISP21_RAWAWB_BASE + 0x03e8)
2082 #define ISP21_RAWAWB_WP_NUM_BIG_3 (ISP21_RAWAWB_BASE + 0x03ec)
2083 #define ISP21_RAWAWB_SUM_RGAIN_NOR_4 (ISP21_RAWAWB_BASE + 0x0400)
2084 #define ISP21_RAWAWB_SUM_BGAIN_NOR_4 (ISP21_RAWAWB_BASE + 0x0408)
2085 #define ISP21_RAWAWB_WP_NUM_NOR_4 (ISP21_RAWAWB_BASE + 0x040c)
2086 #define ISP21_RAWAWB_SUM_RGAIN_BIG_4 (ISP21_RAWAWB_BASE + 0x0410)
2087 #define ISP21_RAWAWB_SUM_BGAIN_BIG_4 (ISP21_RAWAWB_BASE + 0x0418)
2088 #define ISP21_RAWAWB_WP_NUM_BIG_4 (ISP21_RAWAWB_BASE + 0x041c)
2089 #define ISP21_RAWAWB_SUM_RGAIN_NOR_5 (ISP21_RAWAWB_BASE + 0x0430)
2090 #define ISP21_RAWAWB_SUM_BGAIN_NOR_5 (ISP21_RAWAWB_BASE + 0x0438)
2091 #define ISP21_RAWAWB_WP_NUM_NOR_5 (ISP21_RAWAWB_BASE + 0x043c)
2092 #define ISP21_RAWAWB_SUM_RGAIN_BIG_5 (ISP21_RAWAWB_BASE + 0x0440)
2093 #define ISP21_RAWAWB_SUM_BGAIN_BIG_5 (ISP21_RAWAWB_BASE + 0x0448)
2094 #define ISP21_RAWAWB_WP_NUM_BIG_5 (ISP21_RAWAWB_BASE + 0x044c)
2095 #define ISP21_RAWAWB_SUM_RGAIN_NOR_6 (ISP21_RAWAWB_BASE + 0x0460)
2096 #define ISP21_RAWAWB_SUM_BGAIN_NOR_6 (ISP21_RAWAWB_BASE + 0x0468)
2097 #define ISP21_RAWAWB_WP_NUM_NOR_6 (ISP21_RAWAWB_BASE + 0x046c)
2098 #define ISP21_RAWAWB_SUM_RGAIN_BIG_6 (ISP21_RAWAWB_BASE + 0x0470)
2099 #define ISP21_RAWAWB_SUM_BGAIN_BIG_6 (ISP21_RAWAWB_BASE + 0x0478)
2100 #define ISP21_RAWAWB_WP_NUM_BIG_6 (ISP21_RAWAWB_BASE + 0x047c)
2101 #define ISP21_RAWAWB_Y_HIST01 (ISP21_RAWAWB_BASE + 0x0620)
2102 #define ISP21_RAWAWB_Y_HIST23 (ISP21_RAWAWB_BASE + 0x0624)
2103 #define ISP21_RAWAWB_Y_HIST45 (ISP21_RAWAWB_BASE + 0x0628)
2104 #define ISP21_RAWAWB_Y_HIST67 (ISP21_RAWAWB_BASE + 0x062c)
2105 #define ISP21_RAWAWB_RAM_CTRL (ISP21_RAWAWB_BASE + 0x0650)
2106 #define ISP21_RAWAWB_WRAM_CTRL (ISP21_RAWAWB_BASE + 0x0654)
2107 #define ISP21_RAWAWB_WRAM_DATA_BASE (ISP21_RAWAWB_BASE + 0x0660)
2108 #define ISP21_RAWAWB_RAM_DATA_BASE (ISP21_RAWAWB_BASE + 0x0700)
2109
2110
2111 /* VI_ISP_EN */
2112 #define VI_CCL_EN BIT(0)
2113 #define VI_ISP_EN_SEL BIT(1)
2114 #define VI_ISP_BLS_EN BIT(5)
2115 #define VI_ISP_GAMMA_IN_EN BIT(6)
2116 #define VI_ISP_HDRMGE_EN BIT(7)
2117 #define VI_ISP_RAWNR_EN BIT(9)
2118 #define VI_ISP_LSC_EN BIT(10)
2119 #define VI_ISP_HDRTMO_EN BIT(11)
2120 #define VI_ISP_GIC_EN BTI(12)
2121 #define VI_ISP_DEBAYER_EN BIT(13)
2122 #define VI_ISP_CCM_EN BIT(14)
2123 #define VI_ISP_GAMMA12_EN BIT(15)
2124 #define VI_ISP_RKWDR_EN BIT(16)
2125 #define VI_ISP_DHAZ_EN BIT(17)
2126 #define VI_ISP_3DLUT_EN BIT(18)
2127 #define VI_ISP_AWB_EN BIT(20)
2128 #define VI_ISP_CP_EN BIT(21)
2129 #define VI_ISP_RSZ_EN BIT(22)
2130 #define VI_ISP_EFF_EN BIT(24)
2131 #define VI_ISP_IMP_EN BIT(25)
2132
2133 /* VI_ISP_PATH */
2134 #define SW_3A_RAWAE_SEL(a) (((a) & 0x3) << 16)
2135 #define SW_3A_RAWAF_SEL(a) (((a) & 0x3) << 18)
2136 #define SW_3A_RAWAWB_SEL(a) (((a) & 0x3) << 20)
2137 #define SW_3A_RAWAE_SWAP(a) (((a) & 0x3) << 22)
2138
2139 /* VI_ISP_CLK_CTRL */
2140 #define CLK_CTRL_ISP_RAW BIT(0)
2141 #define CLK_CTRL_ISP_RGB BIT(1)
2142 #define CLK_CTRL_ISP_YUV BIT(2)
2143 #define CLK_CTRL_ISP_3A BIT(3)
2144 #define CLK_CTRL_MIPI_RAM BIT(4)
2145 #define CLK_CTRL_ISP_FIFO_RAM BIT(5)
2146 #define CLK_CTRL_ISP_DEM_RAM BIT(6)
2147 #define CLK_CTRL_ISP_DPCC_RAM BIT(7)
2148 #define CLK_CTRL_ISP_IE_RAM BIT(8)
2149 #define CLK_CTRL_RSZ_RAM BIT(9)
2150 #define CLK_CTRL_JPEG_RAM BIT(10)
2151 #define CLK_CTRL_ACLK_ISP BIT(11)
2152 #define CLK_CTRL_LDC_RAM BIT(12)
2153 #define CLK_CTRL_MI_LDC BIT(13)
2154 #define CLK_CTRL_MI_MP BIT(14)
2155 #define CLK_CTRL_MI_JPEG BIT(15)
2156 #define CLK_CTRL_MI_DP BIT(16)
2157 #define CLK_CTRL_MI_Y12 BIT(17)
2158 #define CLK_CTRL_MI_SP BIT(18)
2159 #define CLK_CTRL_MI_RAW0 BIT(19)
2160 #define CLK_CTRL_MI_RAW1 BIT(20)
2161 #define CLK_CTRL_MI_READ BIT(21)
2162 #define CLK_CTRL_MI_RAWRD BIT(22)
2163 #define CLK_CTRL_CP BIT(23)
2164 #define CLK_CTRL_IE BIT(24)
2165 #define CLK_CTRL_SI BIT(25)
2166 #define CLK_CTRL_RSZM BIT(26)
2167 #define CLK_CTRL_DPMUX BIT(27)
2168 #define CLK_CTRL_JPEG BIT(28)
2169 #define CLK_CTRL_RSZS BIT(29)
2170 #define CLK_CTRL_MIPI BIT(30)
2171 #define CLK_CTRL_MARVINMI BIT(31)
2172
2173 /* VI_ICCL */
2174 #define ICCL_ISP_CLK BIT(0)
2175 #define ICCL_CP_CLK BIT(1)
2176 #define ICCL_MRSZ_CLK BIT(3)
2177 #define ICCL_SRSZ_CLK BIT(4)
2178 #define ICCL_JPEG_CLK BIT(5)
2179 #define ICCL_MI_CLK BIT(6)
2180 #define ICCL_IE_CLK BIT(8)
2181 #define ICCL_SIMP_CLK BIT(9)
2182 #define ICCL_SMIA_CLK BIT(10)
2183 #define ICCL_MIPI_CLK BIT(11)
2184 #define ICCL_MPFBC_CLK BIT(14)
2185
2186 /* VI_IRCL */
2187 #define IRCL_ISP_SW_RST BIT(0)
2188 #define IRCL_CP_SW_RST BIT(1)
2189 #define IRCL_YCS_SW_RST BIT(2)
2190 #define IRCL_MRSZ_SW_RST BIT(3)
2191 #define IRCL_SRSZ_SW_RST BIT(4)
2192 #define IRCL_JPEG_SW_RST BIT(5)
2193 #define IRCL_MI_SW_RST BIT(6)
2194 #define IRCL_MARVIN_RST BIT(7)
2195 #define IRCL_IE_SW_RST BIT(8)
2196 #define IRCL_SI_SW_RST BIT(9)
2197 #define IRCL_MIPI_SW_RST BIT(11)
2198 #define IRCL_3A_SW_RST BIT(13)
2199
2200 /* VI_DPCL */
2201 #define VI_DPCL_IF_SEL_LVDS BIT(8)
2202
2203 /* SWS_CFG */
2204 #define SW_SWS_EN BIT(0)
2205 #define SW_ISP2PP_PIPE_EN BIT(1)
2206 #define SW_MPIP_DROP_FRM_DIS BIT(2)
2207 #define SW_SENSOR_ID(a) (((a) & 0x3) << 4)
2208 #define SW_SWS_TMO_DDR_RD BIT(8)
2209 #define SW_SWS_WDR_DDR_RD BIT(9)
2210 #define SW_SWS_DHAZ_DDR_RD BIT(10)
2211 #define SW_SWS_ISP_DDRLOAD_DIS BIT(11)
2212 #define SW_SWS_DMA_START_MODE(a) (((a) & 0x3) << 12)
2213 #define SW_ISP2PP_DIFX16(a) (((a) & 0xff) << 16)
2214 #define SW_3A_DDR_WRITE_EN BIT(24)
2215 #define SW_ISP2PP_HOLD BIT(31)
2216
2217 /* LVDS_CTRL */
2218 #define SW_LVDS_EN BIT(0)
2219 #define SW_LVDS_MODE BIT(1)
2220 #define SW_LVDS_WIDTH(a) (((a) & 0x3) << 2)
2221 #define SW_LVDS_LANE_EN(a) (((a) & 0xf) << 4)
2222 #define SW_LVDS_MAIN_LANE(a) (((a) & 0x3) << 8)
2223 #define SW_LVDS_START_X(a) (((a) & 0x7ff) << 10)
2224 #define SW_LVDS_START_Y(a) (((a) & 0x7ff) << 21)
2225
2226 #define SW_LVDS_SAV(a) ((a) & 0xfff)
2227 #define SW_LVDS_EAV(a) (((a) & 0xfff) << 16)
2228
2229 /* ISP CTRL */
2230 #define NOC_HURRY_PRIORITY(a) (((a) & 0x3) << 30)
2231 #define NOC_HURRY_W_MODE(a) (((a) & 0x7) << 21)
2232 #define NOC_HURRY_R_MODE(a) (((a) & 0x7) << 18)
2233
2234 /* ISP CTRL1 */
2235 #define ISP2X_SYS_YNR_FST BIT(23)
2236 #define ISP2X_SYS_ADRC_FST BIT(24)
2237 #define ISP2X_SYS_DHAZ_FST BIT(25)
2238 #define ISP2X_SYS_CNR_FST BIT(26)
2239 #define ISP2X_SYS_BAY3D_FST BIT(27)
2240 #define ISP2X_SYS_BIGMODE_FORCEEN BIT(28)
2241 #define ISP2X_SYS_BIGMODE_MANUAL BIT(29)
2242
2243 /* isp interrupt */
2244 #define ISP2X_OFF BIT(0)
2245 #define ISP2X_FRAME BIT(1)
2246 #define ISP2X_DATA_LOSS BIT(2)
2247 #define ISP2X_PIC_SIZE_ERROR BIT(3)
2248 #define ISP2X_SIAWB_DONE BIT(4)
2249 #define ISP2X_FRAME_IN BIT(5)
2250 #define ISP2X_V_START BIT(6)
2251 #define ISP2X_H_START BIT(7)
2252 #define ISP2X_FLASH_ON BIT(8)
2253 #define ISP2X_FLASH_OFF BIT(9)
2254 #define ISP2X_SHUTTER_ON BIT(10)
2255 #define ISP2X_SHUTTER_OFF BIT(11)
2256 #define ISP2X_AFM_SUM_OF BIT(12)
2257 #define ISP2X_AFM_LUM_OF BIT(13)
2258 #define ISP2X_SIAF_FIN BIT(14)
2259 #define ISP2X_SIHST_RDY BIT(15)
2260 #define ISP2X_LSC_LUT_ERR BIT(16)
2261 #define ISP2X_FLASH_CAP BIT(17)
2262 #define ISP2X_YUVAE_END BIT(18)
2263 #define ISP2X_VSM_END BIT(19)
2264 #define ISP2X_HDR_DONE BIT(20)
2265 #define ISP2X_DHAZ_DONE BIT(21)
2266 #define ISP2X_GAIN_DONE BIT(22)
2267
2268 /* isp3a interrupt */
2269 #define ISP2X_3A_RAWAE_BIG BIT(0)
2270 #define ISP2X_3A_RAWAE_CH0 BIT(1)
2271 #define ISP2X_3A_RAWAE_CH1 BIT(2)
2272 #define ISP2X_3A_RAWAE_CH2 BIT(3)
2273 #define ISP2X_3A_RAWHIST_BIG BIT(4)
2274 #define ISP2X_3A_RAWHIST_CH0 BIT(5)
2275 #define ISP2X_3A_RAWHIST_CH1 BIT(6)
2276 #define ISP2X_3A_RAWHIST_CH2 BIT(7)
2277 #define ISP2X_3A_RAWAF_SUM BIT(8)
2278 #define ISP2X_3A_RAWAF_LUM BIT(9)
2279 #define ISP2X_3A_RAWAF BIT(10)
2280 #define ISP2X_3A_RAWAWB BIT(11)
2281 #define ISP2X_3A_DDR_DONE BIT(12)
2282
2283 /* MI_WR_CTRL */
2284 #define MI_LUM_BURST_MASK GENMASK(17, 16)
2285 #define MI_MIPI_LUM_BURST2 BIT(16)
2286 #define MI_MIPI_LUM_BURST4 BIT(17)
2287 #define MI_MIPI_LUM_BURST8 (3 << 16)
2288 #define MI_MIPI_LUM_BURST16 (0 << 16)
2289
2290 /* mi interrupt */
2291 #define MI_MP_FRAME BIT(0)
2292 #define MI_SP_FRAME BIT(1)
2293 #define MI_MBLK_LINE BIT(2)
2294 #define MI_FILL_MP_Y BIT(3)
2295 #define MI_WRAP_MP_Y BIT(4)
2296 #define MI_WRAP_MP_CB BIT(5)
2297 #define MI_WRAP_MP_CR BIT(6)
2298 #define MI_WRAP_SP_Y BIT(7)
2299 #define MI_WRAP_SP_CB BIT(8)
2300 #define MI_WARP_SP_CR BIT(9)
2301 #define MI_FILL_MP_Y2 BIT(10)
2302 #define MI_DMA_READY BIT(11)
2303 #define MI_Y12Y_FRAME BIT(12)
2304 #define MI_Y12C_FRAME BIT(13)
2305 #define MI_ALL_FRAME BIT(14)
2306 #define MI_RAW0_WR_FRAME BIT(16)
2307 #define MI_RAW1_WR_FRAME BIT(17)
2308 #define MI_RAW2_WR_FRAME BIT(18)
2309 #define MI_RAW3_WR_FRAME BIT(19)
2310 #define MI_DBR_WR_FRAME BIT(20)
2311 #define MI_GAIN_WR_FRAME BIT(21)
2312 #define MI_MPFBC_FRAME BIT(31)
2313
2314 /* MI_CTRL2 */
2315 #define SW_BAY3D_FORCEUPD BIT(22)
2316 #define SW_BAY3D_WR_AUTOUPD BIT(16)
2317 #define SW_GAIN_WR_AUTOUPD BIT(13)
2318 #define SW_GAIN_WR_PINGPONG BIT(12)
2319 #define SW_DBR_WR_AUTOUPD BIT(10)
2320 #define SW_MIMUX_BYTE_SWAP BIT(9)
2321 #define SW_MIMUX_EN BIT(8)
2322 #define SW_RAW3_WR_AUTOUPD BIT(3)
2323 #define SW_RAW2_WR_AUTOUPD BIT(2)
2324 #define SW_RAW1_WR_AUTOUPD BIT(1)
2325 #define SW_RAW0_WR_AUTOUPD BIT(0)
2326
2327 /* MI_RD_CTRL2 */
2328 #define BAY3D_RW_ONEADDR_EN BIT(4)
2329
2330 /* MPFBC */
2331 #define SW_MPFBC_EN BIT(0)
2332 #define SW_MPFBC_MAINISP_MODE BIT(3)
2333 #define SW_MPFBC_YUV_MODE(a) (((a) & 0x3) << 1)
2334 #define SW_MPFBC_PINGPONG_EN BIT(4)
2335
2336 /* CSI2RX */
2337 #define SW_CSI2RX_EN BIT(0)
2338 #define SW_HDR_ESP_MODE(a) (((a) & 0x3) << 2)
2339 #define SW_IBUF_OP_MODE(a) (((a) & 0x0F) << 8)
2340 #define SW_DMA_2FRM_MODE(a) (((a) & 0x3) << 12)
2341
2342 #define SW_CSI_LANE(a) ((a) & 0x3)
2343 #define SW_CSI_CH0_SEL(a) (((a) & 0x7) << 4)
2344 #define SW_CSI_CH1_SEL(a) (((a) & 0x7) << 8)
2345 #define SW_CSI_CH2_SEL(a) (((a) & 0x7) << 12)
2346 #define SW_CSI_CH3_SEL(a) (((a) & 0x7) << 16)
2347 #define SW_LVL0_SEL0_CSI1 BIT(20)
2348 #define SW_LVL0_SEL1_RAW0 BIT(21)
2349 #define SW_LVL0_SEL2_RAW1 BIT(22)
2350 #define SW_LVL0_SEL3_RAW3 BIT(23)
2351 #define SW_LVL1_SEL0(a) (((a) & 0x3) << 24)
2352 #define SW_LVL1_SEL1(a) (((a) & 0x3) << 26)
2353 #define SW_LVL1_SEL2(a) (((a) & 0x3) << 28)
2354
2355 #define SW_CSI_ID0(a) ((a) & 0xff)
2356 #define SW_CSI_ID1(a) (((a) & 0xff) << 8)
2357 #define SW_CSI_ID2(a) (((a) & 0xff) << 16)
2358 #define SW_CSI_ID3(a) (((a) & 0xff) << 24)
2359
2360 #define SW_CSI_ID4(a) ((a) & 0xff)
2361 #define SW_CSI_ID5(a) (((a) & 0xff) << 8)
2362 #define SW_CSI_ID6(a) (((a) & 0xff) << 16)
2363 #define SW_CSI_ID7(a) (((a) & 0xff) << 24)
2364
2365 #define PHY_ERR_SOTHS GENMASK(3, 0)
2366 #define PHY_ERR_SOTSYNCHS GENMASK(7, 4)
2367 #define PHY_ERR_EOTSYNCHS GENMASK(11, 8)
2368 #define PHY_ERR_ESC GENMASK(15, 12)
2369 #define PHY_ERR_CTL GENMASK(23, 20)
2370
2371 #define PACKET_ERR_F_BNDRY_MATCG GENMASK(3, 0)
2372 #define PACKET_ERR_F_SEQ GENMASK(7, 4)
2373 #define PACKET_ERR_FRAME_DATA GENMASK(11, 8)
2374 #define PACKET_ERR_ID GENMASK(15, 12)
2375 #define PACKET_ERR_ECC_1BIT GENMASK(19, 16)
2376 #define PACKET_ERR_ECC_2BIT BIT(20)
2377 #define PACKET_ERR_CHECKSUM GENMASK(27, 24)
2378
2379 #define AFIFO0_OVERFLOW BIT(0)
2380 #define AFIFO1X_OVERFLOW GENMASK(7, 4)
2381 #define LAFIFO1X_OVERFLOW GENMASK(11, 8)
2382 #define AFIFO2X_OVERFLOW GENMASK(14, 12)
2383 #define IBUFX3_OVERFLOW GENMASK(18, 16)
2384 #define IBUF3R_OVERFLOW BIT(19)
2385 #define Y_STAT_AFIFOX3_OVERFLOW GENMASK(22, 20)
2386
2387 #define RAW0_WR_FRAME BIT(0)
2388 #define RAW1_WR_FRAME BIT(1)
2389 #define RAW2_WR_FRAME BIT(2)
2390 #define MIPI_DROP_FRM BIT(3)
2391 #define RAW0_RD_FRAME BIT(4)
2392 #define RAW1_RD_FRAME BIT(5)
2393 #define RAW2_RD_FRAME BIT(6)
2394 #define RAW_WR_SIZE_ERR GENMASK(15, 8)
2395 #define MIPI_LINECNT BIT(16)
2396 #define RAW_RD_SIZE_ERR GENMASK(19, 17)
2397 #define MIPI_FRAME_ST_VC(a) (((a) & 0xf) << 20)
2398 #define MIPI_FRAME_END_VC(a) (((a) & 0xf) << 24)
2399 #define RAW0_Y_STATE BIT(28)
2400 #define RAW1_Y_STATE BIT(29)
2401 #define RAW2_Y_STATE BIT(30)
2402
2403 #define SW_CSI_RAW_WR_EN_ORG BIT(0)
2404 #define SW_CSI_RAW_WR_SIMG_MODE BIT(1)
2405 #define SW_CSI_RWA_WR_SIMG_SWP BIT(2)
2406 #define SW_CSI_RAW_WR_H_OUT BIT(3)
2407 #define SW_CSI_RAW_WR_CRC_OUT BIT(4)
2408 #define SW_CSI_RAW_WR_CH_EN(a) (((a) & 0xff) << 8)
2409 #define SW_CSI_RAW_WR_EN_SHD BIT(31)
2410
2411 #define SW_CSI_RAW_PIC_V_SIZE(a) (((a) & 0x3FFF) << 16)
2412 #define SW_CSI_RAW_PIC_H_SIZE(a) ((a) & 0x3FFF)
2413
2414 #define SW_CSI_RAW_PIC_V_OFF(a) (((a) & 0x3FFF) << 16)
2415 #define SW_CSI_RAW_PIC_H_OFF(a) ((a) & 0x3FFF)
2416
2417 #define SW_CSI_RAW0_RD_EN_ORG BIT(0)
2418 #define SW_CSI_RAW1_RD_EN_ORG BIT(1)
2419 #define SW_CSI_RAW2_RD_EN_ORG BIT(2)
2420 #define SW_CSI_RAW_RD_SIMG_MOD BIT(3)
2421 #define SW_CSI_RAW_RD_SIMG_SWP BIT(4)
2422 #define SW_CSI_RAW_RD_CH_SEL(a) (((a) & 0x7) << 5)
2423
2424 #define SW_RAW_OUT_EN BIT(0)
2425 #define SW_RAWFBC_EN BIT(1)
2426 #define SW_RAWFBC_HEAD_DIFF_EN BIT(4)
2427 #define SW_RAWFBC_HEAD_DIFF_NUM(a) (((a) & 0x3) << 8)
2428
2429 #define SW_CSI_ESP_LCNT_PADPIX(a) ((a) & 0xFFF)
2430 #define SW_CSI_ESP_LCNT_PADNUM(a) (((a) & 0x3F) << 12)
2431
2432 #define SW_CSI_ESP_IDCD_OBPIX(a) ((a) & 0x7F)
2433 #define SW_CSI_ESP_IDCD_EFPIX(a) (((a) & 0x7F) << 16)
2434
2435 #define SW_Y_STAT_INT_MODE_MASK GENMASK(3, 2)
2436 #define SW_Y_STAT_RD_FRM_ID_MASK GENMASK(5, 4)
2437 #define SW_Y_STAT_RD_TILE_ID_MASK GENMASK(7, 6)
2438 #define SW_Y_STAT_EN BIT(0)
2439 #define SW_Y_STAT_RD_EN BIT(1)
2440 #define SW_Y_STAT_INT_MODE(a) (((a) & 0x3) << 2)
2441 #define SW_Y_STAT_RD_FRM_ID(a) (((a) & 0x3) << 4)
2442 #define SW_Y_STAT_RD_TILE_ID(a) (((a) & 0x3) << 6)
2443 #define SW_Y_STAT_BLK_R(a) (((a) & 0x1f) << 8)
2444 #define SW_Y_STAT_BLK_G(a) (((a) & 0x1f) << 16)
2445 #define SW_Y_STAT_BLK_B(a) (((a) & 0x1f) << 24)
2446
2447 /* DEBAYER */
2448 #define SW_DEBAYER_EN BIT(0)
2449 #define SW_DEBAYER_FILTER_G_EN BIT(4)
2450 #define SW_DEBAYER_FILTER_C_EN BIT(8)
2451
2452 #define SW_DEBAYER_CLIP_EN BIT(0)
2453
2454 /* HDRMGE */
2455 #define SW_HDRMGE_EN BIT(0)
2456 #define SW_HDRMGE_MODE_NORMAL (0 << 2)
2457 #define SW_HDRMGE_MODE_FRAMEX2 BIT(2)
2458 #define SW_HDRMGE_MODE_FRAMEX3 (2 << 2)
2459
2460 /* BLS */
2461 /* ISP_BLS_CTRL */
2462 #define ISP_BLS_ENA BIT(0)
2463 #define ISP_BLS_MODE_MEASURED BIT(1)
2464 #define ISP_BLS_MODE_FIXED 0
2465 #define ISP_BLS_WINDOW_1 (1 << 2)
2466 #define ISP_BLS_WINDOW_2 (2 << 2)
2467 #define ISP_BLS_BLS1_EN BIT(4)
2468
2469 /* GIC */
2470 /* ISP_GIC_CTRL */
2471 #define ISP_GIC_ENA BIT(0)
2472 #define ISP_GIC_EDGE_OPEN BIT(1)
2473
2474 /* DHAZ */
2475 /* ISP_DHAZ_CTRL */
2476 #define ISP_DHAZ_ENMUX BIT(0)
2477 #define ISP_DHAZ_NOBIGEN BIT(2)
2478 #define ISP_DHAZ_BIGEN BIT(3)
2479 #define ISP_DHAZ_DCEN BIT(4)
2480 #define ISP_DHAZ_HSTEN BIT(8)
2481 #define ISP_DHAZ_HPARAEN BIT(12)
2482 #define ISP_DHAZ_HSTCHN BIT(16)
2483 #define ISP_DHAZ_ENHANCE BIT(20)
2484
2485 /* HDRTMO */
2486 /* ISP_HDRTMO_CTRL */
2487 #define ISP_HDRTMO_EN BIT(0)
2488
2489 /* HDRDRC */
2490 /* ISP21_DRC_CTRL0 */
2491 #define ISP_DRC_EN BIT(0)
2492
2493 /* HDRMGE */
2494 /* ISP_HDRMGE_CTRL */
2495 #define ISP_HDRMGE_MODE_MASK GENMASK(3, 2)
2496 #define ISP_HDRMGE_EN BIT(0)
2497
2498 /* RAWNR */
2499 /* ISP_RAWNR_CTRL */
2500 #define ISP_RAWNR_EN BIT(0)
2501
2502 /* DPCC */
2503 /* ISP_DPCC_CTRL */
2504 #define ISP_DPCC_EN BIT(0)
2505
2506 /* CCM */
2507 /* ISP_CCM_CTRL */
2508 #define ISP_CCM_EN BIT(0)
2509
2510 /* 3DLUT */
2511 /* ISP_3DLUT_CTRL */
2512 #define ISP_3DLUT_EN BIT(0)
2513 #define ISP_3DLUT_BYPASS BIT(1)
2514
2515 /* DEBAYER */
2516 /* ISP_DEBAYER_CONTROL */
2517 #define ISP_DEBAYER_EN BIT(0)
2518
2519 /* LSC */
2520 /* ISP_LSC_CTRL */
2521 #define ISP_LSC_EN BIT(0)
2522 #define ISP_LSC_LUT_EN BIT(1)
2523 #define ISP_ISP_LSC_TABLE_DATA(v0, v1) \
2524 (((v0) & 0x1FFF) | (((v1) & 0x1FFF) << 16))
2525
2526 #define ISP21_YNR_EN BIT(0)
2527 #define ISP21_CNR_EN BIT(0)
2528 #define ISP21_SHARP_EN BIT(0)
2529 #define ISP21_BAYNR_EN BIT(0)
2530 #define ISP21_BAY3D_EN BIT(0)
2531
2532 /* ISP21 ISP CTRL0 */
2533 #define ISP21_CGC_RATIO_EN BIT(29)
2534 #define ISP21_CGC_YUV_LIMIT BIT(28)
2535 #define ISP21_NOC_HURRY_W1_MODE(a) (((a) & 0x7) << 24)
2536
2537 /* ISP CTRL1 */
2538 #define ISP21_BIGMODE_MODE BIT(29)
2539 #define ISP21_BIGMODE_FORCE_EN BIT(28)
2540 #define ISP21_RAW3D_FST_FRAME BIT(27)
2541 #define ISP21_CNR_FST_FRAME BIT(26)
2542 #define ISP21_DHAZ_FST_FRAME BIT(25)
2543 #define ISP21_ADRC_FST_FRAME BIT(24)
2544 #define ISP21_YNR_FST_FRAME BIT(23)
2545 #define ISP21_BT1120_YC_SWAP BIT(22)
2546 #define ISP21_DUALEDGE_EN BIT(21)
2547 #define ISP21_BI1120_EN BIT(20)
2548 #define ISP21_FIELD_INV BIT(11)
2549
2550 /* ISP21 ACQ_H_OFFS */
2551 #define ISP21_SENSOR_MODE(a) (((a) & 3) << 30)
2552 #define ISP21_SENSOR_INDEX(a) (((a) & 3) << 28)
2553 #define ISP21_ACQ_H_OFFS(a) ((a) & 0x7fff)
2554
2555 /* ISP21 ACQ_H_SIZE */
2556 #define ISP21_ACQ_H_SIZE_BAY3DMI(a) (((a) & 0xffff) << 16)
2557 #define ISP21_ACQ_H_SIZE(a) ((a) & 0x7fff)
2558
2559 /* ISP21 MI_WR_INIT */
2560 #define ISP21_SP_FORCE_UPD BIT(21)
2561 #define ISP21_MP_FORCE_UPD BIT(20)
2562
2563 /* ISP21 MI_WR_CTRL2*/
2564 #define ISP21_BAY3D_FORCE_UPD BIT(22)
2565 #define ISP21_GAIN_FORCE_UPD BIT(21)
2566 #define ISP21_DBR_FORCE_UPD BIT(20)
2567 #define ISP21_BAY3D_WR_AUTO_UPD BIT(16)
2568
2569 /* ISP21 CSI2RX */
2570 #define ISP21_CSI_2PIX_MODE BIT(1)
2571
2572 #define ISP21_MIPI_DROP_FRM BIT(31)
2573
2574 #define ISP21_RAW3_WR_FRAME BIT(3)
2575
2576 #define ISP21_RAW_FORCE_UPD BIT(31)
2577
2578 /* ISP21 DHAZ/DRC/BAY3D */
2579 #define ISP21_SELF_FORCE_UPD BIT(31)
2580
dmatx0_is_stream_stopped(void __iomem * base)2581 static inline bool dmatx0_is_stream_stopped(void __iomem *base)
2582 {
2583 u32 ret = readl(base + CSI2RX_RAW0_WR_CTRL);
2584
2585 return !(ret & SW_CSI_RAW_WR_EN_SHD);
2586 }
2587
dmatx1_is_stream_stopped(void __iomem * base)2588 static inline bool dmatx1_is_stream_stopped(void __iomem *base)
2589 {
2590 u32 ret = readl(base + CSI2RX_RAW1_WR_CTRL);
2591
2592 return !(ret & SW_CSI_RAW_WR_EN_SHD);
2593 }
2594
dmatx2_is_stream_stopped(void __iomem * base)2595 static inline bool dmatx2_is_stream_stopped(void __iomem *base)
2596 {
2597 u32 ret = readl(base + CSI2RX_RAW2_WR_CTRL);
2598
2599 return !(ret & SW_CSI_RAW_WR_EN_SHD);
2600 }
2601
dmatx3_is_stream_stopped(void __iomem * base)2602 static inline bool dmatx3_is_stream_stopped(void __iomem *base)
2603 {
2604 u32 ret = readl(base + CSI2RX_RAW3_WR_CTRL);
2605
2606 return !(ret & SW_CSI_RAW_WR_EN_SHD);
2607 }
2608
is_mpfbc_stopped(void __iomem * base)2609 static inline bool is_mpfbc_stopped(void __iomem *base)
2610 {
2611 u32 ret = readl(base + ISP_MPFBC_CTRL);
2612
2613 return !(ret & SW_MPFBC_EN);
2614 }
2615
mi_wr_ctrl2(void __iomem * base,u32 val)2616 static inline void mi_wr_ctrl2(void __iomem *base, u32 val)
2617 {
2618 void __iomem *addr = base + MI_WR_CTRL2;
2619
2620 writel(val | readl(addr), addr);
2621 }
2622
raw_wr_set_pic_size(struct rkisp_stream * stream,u32 width,u32 height)2623 static inline void raw_wr_set_pic_size(struct rkisp_stream *stream,
2624 u32 width, u32 height)
2625 {
2626 void __iomem *base = stream->ispdev->base_addr;
2627
2628 if (stream->out_isp_fmt.fmt_type == FMT_YUV)
2629 width *= 2;
2630 /* hardware received 16bit embedded data */
2631 else if (stream->out_isp_fmt.fmt_type == FMT_EBD)
2632 width /= 2;
2633 writel(height << 16 | width,
2634 base + stream->config->dma.pic_size);
2635 }
2636
raw_wr_set_pic_offs(struct rkisp_stream * stream,u32 val)2637 static inline void raw_wr_set_pic_offs(struct rkisp_stream *stream, u32 val)
2638 {
2639 void __iomem *base = stream->ispdev->base_addr;
2640
2641 writel(val, base + stream->config->dma.pic_offs);
2642 }
2643
raw_wr_ctrl(struct rkisp_stream * stream,u32 val)2644 static inline void raw_wr_ctrl(struct rkisp_stream *stream, u32 val)
2645 {
2646 void __iomem *base = stream->ispdev->base_addr;
2647
2648 writel(val, base + stream->config->dma.ctrl);
2649 }
2650
raw_wr_enable(struct rkisp_stream * stream)2651 static inline void raw_wr_enable(struct rkisp_stream *stream)
2652 {
2653 void __iomem *base = stream->ispdev->base_addr;
2654 void __iomem *addr = base + stream->config->dma.ctrl;
2655 u32 val = readl(addr);
2656
2657 val |= ISP21_RAW_FORCE_UPD | SW_CSI_RAW_WR_EN_ORG;
2658 writel(val, addr);
2659 }
2660
raw_wr_disable(struct rkisp_stream * stream)2661 static inline void raw_wr_disable(struct rkisp_stream *stream)
2662 {
2663 void __iomem *base = stream->ispdev->base_addr;
2664 void __iomem *addr = base + stream->config->dma.ctrl;
2665 u32 val = readl(addr);
2666
2667 val &= ~(ISP21_RAW_FORCE_UPD | SW_CSI_RAW_WR_EN_ORG);
2668 writel(val, addr);
2669 }
2670
mi_raw0_rd_set_addr(void __iomem * base,u32 val)2671 static inline void mi_raw0_rd_set_addr(void __iomem *base, u32 val)
2672 {
2673 writel(val, base + MI_RAW0_RD_BASE);
2674 }
2675
mi_raw1_rd_set_addr(void __iomem * base,u32 val)2676 static inline void mi_raw1_rd_set_addr(void __iomem *base, u32 val)
2677 {
2678 writel(val, base + MI_RAW1_RD_BASE);
2679 }
2680
mi_raw2_rd_set_addr(void __iomem * base,u32 val)2681 static inline void mi_raw2_rd_set_addr(void __iomem *base, u32 val)
2682 {
2683 writel(val, base + MI_RAW2_RD_BASE);
2684 }
2685
raw_rd_ctrl(void __iomem * base,u32 val)2686 static inline void raw_rd_ctrl(void __iomem *base, u32 val)
2687 {
2688 writel(val, base + CSI2RX_RAW_RD_CTRL);
2689 }
2690
mi_raw_length(struct rkisp_stream * stream)2691 static inline void mi_raw_length(struct rkisp_stream *stream)
2692 {
2693 bool is_direct = true;
2694
2695 if (stream->config->mi.length == MI_RAW0_RD_LENGTH ||
2696 stream->config->mi.length == MI_RAW1_RD_LENGTH ||
2697 stream->config->mi.length == MI_RAW2_RD_LENGTH)
2698 is_direct = false;
2699 rkisp_write(stream->ispdev, stream->config->mi.length,
2700 stream->out_fmt.plane_fmt[0].bytesperline, is_direct);
2701 if (stream->ispdev->isp_ver == ISP_V21 || stream->ispdev->isp_ver == ISP_V30)
2702 rkisp_set_bits(stream->ispdev, MI_RD_CTRL2, 0, BIT(30), false);
2703 if (stream->ispdev->hw_dev->is_unite) {
2704 rkisp_next_write(stream->ispdev, stream->config->mi.length,
2705 stream->out_fmt.plane_fmt[0].bytesperline, is_direct);
2706 rkisp_next_set_bits(stream->ispdev, MI_RD_CTRL2, 0, BIT(30), false);
2707 }
2708 }
2709
rx_force_upd(void __iomem * base)2710 static inline void rx_force_upd(void __iomem *base)
2711 {
2712 void __iomem *addr = base + CSI2RX_RAW_RD_CTRL;
2713
2714 writel(ISP21_RAW_FORCE_UPD | readl(addr), addr);
2715 }
2716
2717 #endif /* _RKISP_REGS_V2X_H */
2718