1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Rockchip MIPI CSI2 DPHY driver
4 *
5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd.
6 */
7
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/io.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/of_graph.h>
14 #include <linux/of_platform.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regmap.h>
18 #include <linux/mfd/syscon.h>
19 #include <media/media-entity.h>
20 #include <media/v4l2-ctrls.h>
21 #include <media/v4l2-fwnode.h>
22 #include <media/v4l2-subdev.h>
23 #include <media/v4l2-device.h>
24 #include <linux/reset.h>
25 #include "phy-rockchip-csi2-dphy-common.h"
26
27 /* GRF REG OFFSET */
28 #define GRF_VI_CON0 (0x0340)
29 #define GRF_VI_CON1 (0x0344)
30
31 /*RK3588 DPHY GRF REG OFFSET */
32 #define GRF_DPHY_CON0 (0x0)
33 #define GRF_SOC_CON2 (0x0308)
34
35 /*GRF REG BIT DEFINE */
36 #define GRF_CSI2PHY_LANE_SEL_SPLIT (0x1)
37 #define GRF_CSI2PHY_SEL_SPLIT_0_1 (0x0)
38 #define GRF_CSI2PHY_SEL_SPLIT_2_3 BIT(0)
39
40 /*RK3588 DCPHY GRF REG OFFSET */
41 #define GRF_DCPHY_CON0 (0x0)
42
43 /* PHY REG OFFSET */
44 #define CSI2_DPHY_CTRL_INVALID_OFFSET (0xffff)
45 #define CSI2_DPHY_CTRL_PWRCTL \
46 CSI2_DPHY_CTRL_INVALID_OFFSET
47 #define CSI2_DPHY_CTRL_LANE_ENABLE (0x00)
48 #define CSI2_DPHY_CLK1_LANE_EN (0x2C)
49 #define CSI2_DPHY_DUAL_CAL_EN (0x80)
50 #define CSI2_DPHY_CLK_WR_THS_SETTLE (0x160)
51 #define CSI2_DPHY_CLK_CALIB_EN (0x168)
52 #define CSI2_DPHY_LANE0_WR_THS_SETTLE (0x1e0)
53 #define CSI2_DPHY_LANE0_CALIB_EN (0x1e8)
54 #define CSI2_DPHY_LANE1_WR_THS_SETTLE (0x260)
55 #define CSI2_DPHY_LANE1_CALIB_EN (0x268)
56 #define CSI2_DPHY_LANE2_WR_THS_SETTLE (0x2e0)
57 #define CSI2_DPHY_LANE2_CALIB_EN (0x2e8)
58 #define CSI2_DPHY_LANE3_WR_THS_SETTLE (0x360)
59 #define CSI2_DPHY_LANE3_CALIB_EN (0x368)
60 #define CSI2_DPHY_CLK1_WR_THS_SETTLE (0x3e0)
61 #define CSI2_DPHY_CLK1_CALIB_EN (0x3e8)
62
63 #define CSI2_DCPHY_CLK_WR_THS_SETTLE (0x030)
64 #define CSI2_DCPHY_LANE0_WR_THS_SETTLE (0x130)
65 #define CSI2_DCPHY_LANE0_WR_ERR_SOT_SYNC (0x134)
66 #define CSI2_DCPHY_LANE1_WR_THS_SETTLE (0x230)
67 #define CSI2_DCPHY_LANE1_WR_ERR_SOT_SYNC (0x234)
68 #define CSI2_DCPHY_LANE2_WR_THS_SETTLE (0x330)
69 #define CSI2_DCPHY_LANE2_WR_ERR_SOT_SYNC (0x334)
70 #define CSI2_DCPHY_LANE3_WR_THS_SETTLE (0x430)
71 #define CSI2_DCPHY_LANE3_WR_ERR_SOT_SYNC (0x434)
72 #define CSI2_DCPHY_CLK_LANE_ENABLE (0x000)
73 #define CSI2_DCPHY_DATA_LANE0_ENABLE (0x100)
74 #define CSI2_DCPHY_DATA_LANE1_ENABLE (0x200)
75 #define CSI2_DCPHY_DATA_LANE2_ENABLE (0x300)
76 #define CSI2_DCPHY_DATA_LANE3_ENABLE (0x400)
77
78 #define CSI2_DCPHY_S0C_GNR_CON1 (0x004)
79 #define CSI2_DCPHY_COMBO_S0D0_GNR_CON1 (0x104)
80 #define CSI2_DCPHY_COMBO_S0D1_GNR_CON1 (0x204)
81 #define CSI2_DCPHY_COMBO_S0D2_GNR_CON1 (0x304)
82 #define CSI2_DCPHY_S0D3_GNR_CON1 (0x304)
83
84 /* PHY REG BIT DEFINE */
85 #define CSI2_DPHY_LANE_MODE_FULL (0x4)
86 #define CSI2_DPHY_LANE_MODE_SPLIT (0x2)
87 #define CSI2_DPHY_LANE_SPLIT_TOP (0x1)
88 #define CSI2_DPHY_LANE_SPLIT_BOT (0x2)
89 #define CSI2_DPHY_LANE_SPLIT_LANE0_1 (0x3 << 2)
90 #define CSI2_DPHY_LANE_SPLIT_LANE2_3 (0x3 << 4)
91 #define CSI2_DPHY_LANE_DUAL_MODE_EN BIT(6)
92 #define CSI2_DPHY_LANE_PARA_ARR_NUM (0x2)
93
94 #define CSI2_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT 2
95 #define CSI2_DPHY_CTRL_DATALANE_SPLIT_LANE2_3_OFFSET_BIT 4
96 #define CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT 6
97
98 enum csi2_dphy_index {
99 DPHY0 = 0x0,
100 DPHY1,
101 DPHY2,
102 };
103
104 enum csi2_dphy_lane {
105 CSI2_DPHY_LANE_CLOCK = 0,
106 CSI2_DPHY_LANE_CLOCK1,
107 CSI2_DPHY_LANE_DATA0,
108 CSI2_DPHY_LANE_DATA1,
109 CSI2_DPHY_LANE_DATA2,
110 CSI2_DPHY_LANE_DATA3
111 };
112
113 enum grf_reg_id {
114 GRF_DPHY_RX0_TURNDISABLE = 0,
115 GRF_DPHY_RX0_FORCERXMODE,
116 GRF_DPHY_RX0_FORCETXSTOPMODE,
117 GRF_DPHY_RX0_ENABLE,
118 GRF_DPHY_RX0_TESTCLR,
119 GRF_DPHY_RX0_TESTCLK,
120 GRF_DPHY_RX0_TESTEN,
121 GRF_DPHY_RX0_TESTDIN,
122 GRF_DPHY_RX0_TURNREQUEST,
123 GRF_DPHY_RX0_TESTDOUT,
124 GRF_DPHY_TX0_TURNDISABLE,
125 GRF_DPHY_TX0_FORCERXMODE,
126 GRF_DPHY_TX0_FORCETXSTOPMODE,
127 GRF_DPHY_TX0_TURNREQUEST,
128 GRF_DPHY_TX1RX1_TURNDISABLE,
129 GRF_DPHY_TX1RX1_FORCERXMODE,
130 GRF_DPHY_TX1RX1_FORCETXSTOPMODE,
131 GRF_DPHY_TX1RX1_ENABLE,
132 GRF_DPHY_TX1RX1_MASTERSLAVEZ,
133 GRF_DPHY_TX1RX1_BASEDIR,
134 GRF_DPHY_TX1RX1_ENABLECLK,
135 GRF_DPHY_TX1RX1_TURNREQUEST,
136 GRF_DPHY_RX1_SRC_SEL,
137 /* rk3288 only */
138 GRF_CON_DISABLE_ISP,
139 GRF_CON_ISP_DPHY_SEL,
140 GRF_DSI_CSI_TESTBUS_SEL,
141 GRF_DVP_V18SEL,
142 /* rk1808 & rk3326 & rv1126 */
143 GRF_DPHY_CSI2PHY_FORCERXMODE,
144 GRF_DPHY_CSI2PHY_CLKLANE_EN,
145 GRF_DPHY_CSI2PHY_DATALANE_EN,
146 /* rv1126 only */
147 GRF_DPHY_CLK_INV_SEL,
148 GRF_DPHY_SEL,
149 /* rk3368 only */
150 GRF_ISP_MIPI_CSI_HOST_SEL,
151 /* below is for rk3399 only */
152 GRF_DPHY_RX0_CLK_INV_SEL,
153 GRF_DPHY_RX1_CLK_INV_SEL,
154 GRF_DPHY_TX1RX1_SRC_SEL,
155 /* below is for rk3568 only */
156 GRF_DPHY_CSI2PHY_CLKLANE1_EN,
157 GRF_DPHY_CLK1_INV_SEL,
158 GRF_DPHY_ISP_CSI2PHY_SEL,
159 GRF_DPHY_CIF_CSI2PHY_SEL,
160 GRF_DPHY_CSI2PHY_LANE_SEL,
161 GRF_DPHY_CSI2PHY1_LANE_SEL,
162 GRF_DPHY_CSI2PHY_DATALANE_EN0,
163 GRF_DPHY_CSI2PHY_DATALANE_EN1,
164 GRF_CPHY_MODE,
165 GRF_DPHY_CSIHOST2_SEL,
166 GRF_DPHY_CSIHOST3_SEL,
167 GRF_DPHY_CSIHOST4_SEL,
168 GRF_DPHY_CSIHOST5_SEL,
169 };
170
171 enum csi2dphy_reg_id {
172 CSI2PHY_REG_CTRL_LANE_ENABLE = 0,
173 CSI2PHY_CTRL_PWRCTL,
174 CSI2PHY_CTRL_DIG_RST,
175 CSI2PHY_CLK_THS_SETTLE,
176 CSI2PHY_LANE0_THS_SETTLE,
177 CSI2PHY_LANE1_THS_SETTLE,
178 CSI2PHY_LANE2_THS_SETTLE,
179 CSI2PHY_LANE3_THS_SETTLE,
180 CSI2PHY_CLK_CALIB_ENABLE,
181 CSI2PHY_LANE0_CALIB_ENABLE,
182 CSI2PHY_LANE1_CALIB_ENABLE,
183 CSI2PHY_LANE2_CALIB_ENABLE,
184 CSI2PHY_LANE3_CALIB_ENABLE,
185 //rv1126 only
186 CSI2PHY_MIPI_LVDS_MODEL,
187 CSI2PHY_LVDS_MODE,
188 //rk3568 only
189 CSI2PHY_DUAL_CLK_EN,
190 CSI2PHY_CLK1_THS_SETTLE,
191 CSI2PHY_CLK1_CALIB_ENABLE,
192 //rk3588
193 CSI2PHY_CLK_LANE_ENABLE,
194 CSI2PHY_CLK1_LANE_ENABLE,
195 CSI2PHY_DATA_LANE0_ENABLE,
196 CSI2PHY_DATA_LANE1_ENABLE,
197 CSI2PHY_DATA_LANE2_ENABLE,
198 CSI2PHY_DATA_LANE3_ENABLE,
199 CSI2PHY_LANE0_ERR_SOT_SYNC,
200 CSI2PHY_LANE1_ERR_SOT_SYNC,
201 CSI2PHY_LANE2_ERR_SOT_SYNC,
202 CSI2PHY_LANE3_ERR_SOT_SYNC,
203 CSI2PHY_S0C_GNR_CON1,
204 CSI2PHY_COMBO_S0D0_GNR_CON1,
205 CSI2PHY_COMBO_S0D1_GNR_CON1,
206 CSI2PHY_COMBO_S0D2_GNR_CON1,
207 CSI2PHY_S0D3_GNR_CON1,
208 };
209
210 #define HIWORD_UPDATE(val, mask, shift) \
211 ((val) << (shift) | (mask) << ((shift) + 16))
212
213 #define GRF_REG(_offset, _width, _shift) \
214 { .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, }
215
216 #define CSI2PHY_REG(_offset) \
217 { .offset = _offset, }
218
219 struct hsfreq_range {
220 u32 range_h;
221 u16 cfg_bit;
222 };
223
write_sys_grf_reg(struct csi2_dphy_hw * hw,int index,u8 value)224 static inline void write_sys_grf_reg(struct csi2_dphy_hw *hw,
225 int index, u8 value)
226 {
227 const struct grf_reg *reg = &hw->grf_regs[index];
228 unsigned int val = HIWORD_UPDATE(value, reg->mask, reg->shift);
229
230 if (reg->shift)
231 regmap_write(hw->regmap_sys_grf, reg->offset, val);
232 }
233
write_grf_reg(struct csi2_dphy_hw * hw,int index,u8 value)234 static inline void write_grf_reg(struct csi2_dphy_hw *hw,
235 int index, u8 value)
236 {
237 const struct grf_reg *reg = &hw->grf_regs[index];
238 unsigned int val = HIWORD_UPDATE(value, reg->mask, reg->shift);
239
240 if (reg->shift)
241 regmap_write(hw->regmap_grf, reg->offset, val);
242 }
243
read_grf_reg(struct csi2_dphy_hw * hw,int index)244 static inline u32 read_grf_reg(struct csi2_dphy_hw *hw, int index)
245 {
246 const struct grf_reg *reg = &hw->grf_regs[index];
247 unsigned int val = 0;
248
249 if (reg->shift) {
250 regmap_read(hw->regmap_grf, reg->offset, &val);
251 val = (val >> reg->shift) & reg->mask;
252 }
253
254 return val;
255 }
256
write_csi2_dphy_reg(struct csi2_dphy_hw * hw,int index,u32 value)257 static inline void write_csi2_dphy_reg(struct csi2_dphy_hw *hw,
258 int index, u32 value)
259 {
260 const struct csi2dphy_reg *reg = &hw->csi2dphy_regs[index];
261
262 if ((index == CSI2PHY_REG_CTRL_LANE_ENABLE) ||
263 (index == CSI2PHY_CLK_LANE_ENABLE) ||
264 (index != CSI2PHY_REG_CTRL_LANE_ENABLE &&
265 reg->offset != 0x0))
266 writel(value, hw->hw_base_addr + reg->offset);
267 }
268
write_csi2_dphy_reg_mask(struct csi2_dphy_hw * hw,int index,u32 value,u32 mask)269 static inline void write_csi2_dphy_reg_mask(struct csi2_dphy_hw *hw,
270 int index, u32 value, u32 mask)
271 {
272 const struct csi2dphy_reg *reg = &hw->csi2dphy_regs[index];
273 u32 read_val = 0;
274
275 read_val = readl(hw->hw_base_addr + reg->offset);
276 read_val &= ~mask;
277 read_val |= value;
278 writel(read_val, hw->hw_base_addr + reg->offset);
279 }
280
read_csi2_dphy_reg(struct csi2_dphy_hw * hw,int index,u32 * value)281 static inline void read_csi2_dphy_reg(struct csi2_dphy_hw *hw,
282 int index, u32 *value)
283 {
284 const struct csi2dphy_reg *reg = &hw->csi2dphy_regs[index];
285
286 if ((index == CSI2PHY_REG_CTRL_LANE_ENABLE) ||
287 (index == CSI2PHY_CLK_LANE_ENABLE) ||
288 (index != CSI2PHY_REG_CTRL_LANE_ENABLE &&
289 reg->offset != 0x0))
290 *value = readl(hw->hw_base_addr + reg->offset);
291 }
292
csi_mipidphy_wr_ths_settle(struct csi2_dphy_hw * hw,int hsfreq,enum csi2_dphy_lane lane)293 static void csi_mipidphy_wr_ths_settle(struct csi2_dphy_hw *hw,
294 int hsfreq,
295 enum csi2_dphy_lane lane)
296 {
297 unsigned int val = 0;
298 unsigned int offset;
299
300 switch (lane) {
301 case CSI2_DPHY_LANE_CLOCK:
302 offset = CSI2PHY_CLK_THS_SETTLE;
303 break;
304 case CSI2_DPHY_LANE_CLOCK1:
305 offset = CSI2PHY_CLK1_THS_SETTLE;
306 break;
307 case CSI2_DPHY_LANE_DATA0:
308 offset = CSI2PHY_LANE0_THS_SETTLE;
309 break;
310 case CSI2_DPHY_LANE_DATA1:
311 offset = CSI2PHY_LANE1_THS_SETTLE;
312 break;
313 case CSI2_DPHY_LANE_DATA2:
314 offset = CSI2PHY_LANE2_THS_SETTLE;
315 break;
316 case CSI2_DPHY_LANE_DATA3:
317 offset = CSI2PHY_LANE3_THS_SETTLE;
318 break;
319 default:
320 return;
321 }
322
323 read_csi2_dphy_reg(hw, offset, &val);
324 val = (val & ~0x7f) | hsfreq;
325 write_csi2_dphy_reg(hw, offset, val);
326 }
327
328 static const struct grf_reg rk3568_grf_dphy_regs[] = {
329 [GRF_DPHY_CSI2PHY_FORCERXMODE] = GRF_REG(GRF_VI_CON0, 4, 0),
330 [GRF_DPHY_CSI2PHY_DATALANE_EN] = GRF_REG(GRF_VI_CON0, 4, 4),
331 [GRF_DPHY_CSI2PHY_DATALANE_EN0] = GRF_REG(GRF_VI_CON0, 2, 4),
332 [GRF_DPHY_CSI2PHY_DATALANE_EN1] = GRF_REG(GRF_VI_CON0, 2, 6),
333 [GRF_DPHY_CSI2PHY_CLKLANE_EN] = GRF_REG(GRF_VI_CON0, 1, 8),
334 [GRF_DPHY_CLK_INV_SEL] = GRF_REG(GRF_VI_CON0, 1, 9),
335 [GRF_DPHY_CSI2PHY_CLKLANE1_EN] = GRF_REG(GRF_VI_CON0, 1, 10),
336 [GRF_DPHY_CLK1_INV_SEL] = GRF_REG(GRF_VI_CON0, 1, 11),
337 [GRF_DPHY_ISP_CSI2PHY_SEL] = GRF_REG(GRF_VI_CON1, 1, 12),
338 [GRF_DPHY_CIF_CSI2PHY_SEL] = GRF_REG(GRF_VI_CON1, 1, 11),
339 [GRF_DPHY_CSI2PHY_LANE_SEL] = GRF_REG(GRF_VI_CON1, 1, 7),
340 };
341
342 static const struct csi2dphy_reg rk3568_csi2dphy_regs[] = {
343 [CSI2PHY_REG_CTRL_LANE_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CTRL_LANE_ENABLE),
344 [CSI2PHY_DUAL_CLK_EN] = CSI2PHY_REG(CSI2_DPHY_DUAL_CAL_EN),
345 [CSI2PHY_CLK_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_CLK_WR_THS_SETTLE),
346 [CSI2PHY_CLK_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK_CALIB_EN),
347 [CSI2PHY_LANE0_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE0_WR_THS_SETTLE),
348 [CSI2PHY_LANE0_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE0_CALIB_EN),
349 [CSI2PHY_LANE1_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE1_WR_THS_SETTLE),
350 [CSI2PHY_LANE1_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE1_CALIB_EN),
351 [CSI2PHY_LANE2_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE2_WR_THS_SETTLE),
352 [CSI2PHY_LANE2_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE2_CALIB_EN),
353 [CSI2PHY_LANE3_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE3_WR_THS_SETTLE),
354 [CSI2PHY_LANE3_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE3_CALIB_EN),
355 [CSI2PHY_CLK1_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_WR_THS_SETTLE),
356 [CSI2PHY_CLK1_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_CALIB_EN),
357 };
358
359 static const struct grf_reg rk3588_grf_dphy_regs[] = {
360 [GRF_DPHY_CSI2PHY_FORCERXMODE] = GRF_REG(GRF_DPHY_CON0, 4, 0),
361 [GRF_DPHY_CSI2PHY_DATALANE_EN] = GRF_REG(GRF_DPHY_CON0, 4, 4),
362 [GRF_DPHY_CSI2PHY_DATALANE_EN0] = GRF_REG(GRF_DPHY_CON0, 2, 4),
363 [GRF_DPHY_CSI2PHY_DATALANE_EN1] = GRF_REG(GRF_DPHY_CON0, 2, 6),
364 [GRF_DPHY_CSI2PHY_CLKLANE_EN] = GRF_REG(GRF_DPHY_CON0, 1, 8),
365 [GRF_DPHY_CLK_INV_SEL] = GRF_REG(GRF_DPHY_CON0, 1, 9),
366 [GRF_DPHY_CSI2PHY_CLKLANE1_EN] = GRF_REG(GRF_DPHY_CON0, 1, 10),
367 [GRF_DPHY_CLK1_INV_SEL] = GRF_REG(GRF_DPHY_CON0, 1, 11),
368 [GRF_DPHY_CSI2PHY_LANE_SEL] = GRF_REG(GRF_SOC_CON2, 1, 6),
369 [GRF_DPHY_CSI2PHY1_LANE_SEL] = GRF_REG(GRF_SOC_CON2, 1, 7),
370 [GRF_DPHY_CSIHOST2_SEL] = GRF_REG(GRF_SOC_CON2, 1, 8),
371 [GRF_DPHY_CSIHOST3_SEL] = GRF_REG(GRF_SOC_CON2, 1, 9),
372 [GRF_DPHY_CSIHOST4_SEL] = GRF_REG(GRF_SOC_CON2, 1, 10),
373 [GRF_DPHY_CSIHOST5_SEL] = GRF_REG(GRF_SOC_CON2, 1, 11),
374 };
375
376 static const struct csi2dphy_reg rk3588_csi2dphy_regs[] = {
377 [CSI2PHY_REG_CTRL_LANE_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CTRL_LANE_ENABLE),
378 [CSI2PHY_DUAL_CLK_EN] = CSI2PHY_REG(CSI2_DPHY_DUAL_CAL_EN),
379 [CSI2PHY_CLK_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_CLK_WR_THS_SETTLE),
380 [CSI2PHY_CLK_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK_CALIB_EN),
381 [CSI2PHY_LANE0_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE0_WR_THS_SETTLE),
382 [CSI2PHY_LANE0_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE0_CALIB_EN),
383 [CSI2PHY_LANE1_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE1_WR_THS_SETTLE),
384 [CSI2PHY_LANE1_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE1_CALIB_EN),
385 [CSI2PHY_LANE2_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE2_WR_THS_SETTLE),
386 [CSI2PHY_LANE2_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE2_CALIB_EN),
387 [CSI2PHY_LANE3_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_LANE3_WR_THS_SETTLE),
388 [CSI2PHY_LANE3_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_LANE3_CALIB_EN),
389 [CSI2PHY_CLK1_THS_SETTLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_WR_THS_SETTLE),
390 [CSI2PHY_CLK1_CALIB_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_CALIB_EN),
391 [CSI2PHY_CLK1_LANE_ENABLE] = CSI2PHY_REG(CSI2_DPHY_CLK1_LANE_EN),
392 };
393
394 static const struct grf_reg rk3588_grf_dcphy_regs[] = {
395 [GRF_CPHY_MODE] = GRF_REG(GRF_DCPHY_CON0, 9, 0),
396 };
397
398 static const struct csi2dphy_reg rk3588_csi2dcphy_regs[] = {
399 [CSI2PHY_CLK_THS_SETTLE] = CSI2PHY_REG(CSI2_DCPHY_CLK_WR_THS_SETTLE),
400 [CSI2PHY_LANE0_THS_SETTLE] = CSI2PHY_REG(CSI2_DCPHY_LANE0_WR_THS_SETTLE),
401 [CSI2PHY_LANE0_ERR_SOT_SYNC] = CSI2PHY_REG(CSI2_DCPHY_LANE0_WR_ERR_SOT_SYNC),
402 [CSI2PHY_LANE1_THS_SETTLE] = CSI2PHY_REG(CSI2_DCPHY_LANE1_WR_THS_SETTLE),
403 [CSI2PHY_LANE1_ERR_SOT_SYNC] = CSI2PHY_REG(CSI2_DCPHY_LANE1_WR_ERR_SOT_SYNC),
404 [CSI2PHY_LANE2_THS_SETTLE] = CSI2PHY_REG(CSI2_DCPHY_LANE2_WR_THS_SETTLE),
405 [CSI2PHY_LANE2_ERR_SOT_SYNC] = CSI2PHY_REG(CSI2_DCPHY_LANE2_WR_ERR_SOT_SYNC),
406 [CSI2PHY_LANE3_THS_SETTLE] = CSI2PHY_REG(CSI2_DCPHY_LANE3_WR_THS_SETTLE),
407 [CSI2PHY_LANE3_ERR_SOT_SYNC] = CSI2PHY_REG(CSI2_DCPHY_LANE3_WR_ERR_SOT_SYNC),
408 [CSI2PHY_CLK_LANE_ENABLE] = CSI2PHY_REG(CSI2_DCPHY_CLK_LANE_ENABLE),
409 [CSI2PHY_DATA_LANE0_ENABLE] = CSI2PHY_REG(CSI2_DCPHY_DATA_LANE0_ENABLE),
410 [CSI2PHY_DATA_LANE1_ENABLE] = CSI2PHY_REG(CSI2_DCPHY_DATA_LANE1_ENABLE),
411 [CSI2PHY_DATA_LANE2_ENABLE] = CSI2PHY_REG(CSI2_DCPHY_DATA_LANE2_ENABLE),
412 [CSI2PHY_DATA_LANE3_ENABLE] = CSI2PHY_REG(CSI2_DCPHY_DATA_LANE3_ENABLE),
413 [CSI2PHY_S0C_GNR_CON1] = CSI2PHY_REG(CSI2_DCPHY_S0C_GNR_CON1),
414 [CSI2PHY_COMBO_S0D0_GNR_CON1] = CSI2PHY_REG(CSI2_DCPHY_COMBO_S0D0_GNR_CON1),
415 [CSI2PHY_COMBO_S0D1_GNR_CON1] = CSI2PHY_REG(CSI2_DCPHY_COMBO_S0D1_GNR_CON1),
416 [CSI2PHY_COMBO_S0D2_GNR_CON1] = CSI2PHY_REG(CSI2_DCPHY_COMBO_S0D2_GNR_CON1),
417 [CSI2PHY_S0D3_GNR_CON1] = CSI2PHY_REG(CSI2_DCPHY_S0D3_GNR_CON1),
418 };
419
420 /* These tables must be sorted by .range_h ascending. */
421 static const struct hsfreq_range rk3568_csi2_dphy_hw_hsfreq_ranges[] = {
422 { 109, 0x02}, { 149, 0x03}, { 199, 0x06}, { 249, 0x06},
423 { 299, 0x06}, { 399, 0x08}, { 499, 0x0b}, { 599, 0x0e},
424 { 699, 0x10}, { 799, 0x12}, { 999, 0x16}, {1199, 0x1e},
425 {1399, 0x23}, {1599, 0x2d}, {1799, 0x32}, {1999, 0x37},
426 {2199, 0x3c}, {2399, 0x41}, {2499, 0x46}
427 };
428
429 /* These tables must be sorted by .range_h ascending. */
430 static const struct hsfreq_range rk3588_csi2_dcphy_d_hw_hsfreq_ranges[] = {
431 { 80, 0x105}, { 100, 0x106}, { 120, 0x107}, { 140, 0x108},
432 { 160, 0x109}, { 180, 0x10a}, { 200, 0x10b}, { 220, 0x10c},
433 { 240, 0x10d}, { 270, 0x10e}, { 290, 0x10f}, { 310, 0x110},
434 { 330, 0x111}, { 350, 0x112}, { 370, 0x113}, { 390, 0x114},
435 { 410, 0x115}, { 430, 0x116}, { 450, 0x117}, { 470, 0x118},
436 { 490, 0x119}, { 510, 0x11a}, { 540, 0x11b}, { 560, 0x11c},
437 { 580, 0x11d}, { 600, 0x11e}, { 620, 0x11f}, { 640, 0x120},
438 { 660, 0x121}, { 680, 0x122}, { 700, 0x123}, { 720, 0x124},
439 { 740, 0x125}, { 760, 0x126}, { 790, 0x127}, { 810, 0x128},
440 { 830, 0x129}, { 850, 0x12a}, { 870, 0x12b}, { 890, 0x12c},
441 { 910, 0x12d}, { 930, 0x12e}, { 950, 0x12f}, { 970, 0x130},
442 { 990, 0x131}, {1010, 0x132}, {1030, 0x133}, {1060, 0x134},
443 {1080, 0x135}, {1100, 0x136}, {1120, 0x137}, {1140, 0x138},
444 {1160, 0x139}, {1180, 0x13a}, {1200, 0x13b}, {1220, 0x13c},
445 {1240, 0x13d}, {1260, 0x13e}, {1280, 0x13f}, {1310, 0x140},
446 {1330, 0x141}, {1350, 0x142}, {1370, 0x143}, {1390, 0x144},
447 {1410, 0x145}, {1430, 0x146}, {1450, 0x147}, {1470, 0x148},
448 {1490, 0x149}, {1580, 0x007}, {1740, 0x008}, {1910, 0x009},
449 {2070, 0x00a}, {2240, 0x00b}, {2410, 0x00c}, {2570, 0x00d},
450 {2740, 0x00e}, {2910, 0x00f}, {3070, 0x010}, {3240, 0x011},
451 {3410, 0x012}, {3570, 0x013}, {3740, 0x014}, {3890, 0x015},
452 {4070, 0x016}, {4240, 0x017}, {4400, 0x018}, {4500, 0x019},
453 };
454
455 /* These tables must be sorted by .range_h ascending. */
456 static const struct hsfreq_range rk3588_csi2_dcphy_c_hw_hsfreq_ranges[] = {
457 { 500, 0x102}, { 990, 0x002}, { 2500, 0x001},
458 };
459
get_remote_sensor(struct v4l2_subdev * sd)460 static struct v4l2_subdev *get_remote_sensor(struct v4l2_subdev *sd)
461 {
462 struct media_pad *local, *remote;
463 struct media_entity *sensor_me;
464
465 local = &sd->entity.pads[CSI2_DPHY_RX_PAD_SINK];
466 remote = media_entity_remote_pad(local);
467 if (!remote) {
468 v4l2_warn(sd, "No link between dphy and sensor\n");
469 return NULL;
470 }
471
472 sensor_me = media_entity_remote_pad(local)->entity;
473 return media_entity_to_v4l2_subdev(sensor_me);
474 }
475
sd_to_sensor(struct csi2_dphy * dphy,struct v4l2_subdev * sd)476 static struct csi2_sensor *sd_to_sensor(struct csi2_dphy *dphy,
477 struct v4l2_subdev *sd)
478 {
479 int i;
480
481 for (i = 0; i < dphy->num_sensors; ++i)
482 if (dphy->sensors[i].sd == sd)
483 return &dphy->sensors[i];
484
485 return NULL;
486 }
487
csi2_dphy_hw_do_reset(struct csi2_dphy_hw * hw)488 static void csi2_dphy_hw_do_reset(struct csi2_dphy_hw *hw)
489 {
490 if (hw->rsts_bulk)
491 reset_control_assert(hw->rsts_bulk);
492
493 udelay(5);
494
495 if (hw->rsts_bulk)
496 reset_control_deassert(hw->rsts_bulk);
497 }
498
csi2_dphy_config_dual_mode(struct csi2_dphy * dphy,struct csi2_sensor * sensor)499 static void csi2_dphy_config_dual_mode(struct csi2_dphy *dphy,
500 struct csi2_sensor *sensor)
501 {
502 struct csi2_dphy_hw *hw = dphy->dphy_hw;
503 struct v4l2_subdev *sd = &dphy->sd;
504 bool is_cif = false;
505 char *model;
506 u32 val;
507
508 model = sd->v4l2_dev->mdev->model;
509 if (!strncmp(model, "rkcif_mipi_lvds", sizeof("rkcif_mipi_lvds") - 1))
510 is_cif = true;
511 else
512 is_cif = false;
513
514 if (hw->lane_mode == LANE_MODE_FULL) {
515 val = ~GRF_CSI2PHY_LANE_SEL_SPLIT;
516 if (dphy->phy_index < 3) {
517 write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN,
518 GENMASK(sensor->lanes - 1, 0));
519 write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE_EN, 0x1);
520 if (hw->drv_data->chip_id < CHIP_ID_RK3588)
521 write_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
522 else
523 write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
524 } else {
525 write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN,
526 GENMASK(sensor->lanes - 1, 0));
527 write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE_EN, 0x1);
528 if (hw->drv_data->chip_id < CHIP_ID_RK3588)
529 write_grf_reg(hw, GRF_DPHY_CSI2PHY1_LANE_SEL, val);
530 else
531 write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY1_LANE_SEL, val);
532 }
533 } else {
534 val = GRF_CSI2PHY_LANE_SEL_SPLIT;
535
536 switch (dphy->phy_index) {
537 case 1:
538 write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN0,
539 GENMASK(sensor->lanes - 1, 0));
540 write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE_EN, 0x1);
541 if (hw->drv_data->chip_id < CHIP_ID_RK3588) {
542 write_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
543 if (is_cif)
544 write_grf_reg(hw, GRF_DPHY_CIF_CSI2PHY_SEL,
545 GRF_CSI2PHY_SEL_SPLIT_0_1);
546 else
547 write_grf_reg(hw, GRF_DPHY_ISP_CSI2PHY_SEL,
548 GRF_CSI2PHY_SEL_SPLIT_0_1);
549 } else {
550 write_sys_grf_reg(hw, GRF_DPHY_CSIHOST2_SEL, 0x0);
551 write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
552 }
553 break;
554 case 2:
555 write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN1,
556 GENMASK(sensor->lanes - 1, 0));
557 write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE1_EN, 0x1);
558 if (hw->drv_data->chip_id < CHIP_ID_RK3588) {
559 write_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
560 if (is_cif)
561 write_grf_reg(hw, GRF_DPHY_CIF_CSI2PHY_SEL,
562 GRF_CSI2PHY_SEL_SPLIT_2_3);
563 else
564 write_grf_reg(hw, GRF_DPHY_ISP_CSI2PHY_SEL,
565 GRF_CSI2PHY_SEL_SPLIT_2_3);
566 } else {
567 write_sys_grf_reg(hw, GRF_DPHY_CSIHOST3_SEL, 0x1);
568 write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY_LANE_SEL, val);
569 }
570 break;
571 case 4:
572 write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY1_LANE_SEL, val);
573 write_sys_grf_reg(hw, GRF_DPHY_CSIHOST4_SEL, 0x0);
574 write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN0,
575 GENMASK(sensor->lanes - 1, 0));
576 write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE_EN, 0x1);
577 break;
578 case 5:
579 write_sys_grf_reg(hw, GRF_DPHY_CSI2PHY1_LANE_SEL, val);
580 write_sys_grf_reg(hw, GRF_DPHY_CSIHOST5_SEL, 0x1);
581 write_grf_reg(hw, GRF_DPHY_CSI2PHY_DATALANE_EN1,
582 GENMASK(sensor->lanes - 1, 0));
583 write_grf_reg(hw, GRF_DPHY_CSI2PHY_CLKLANE1_EN, 0x1);
584 break;
585 default:
586 break;
587 };
588 }
589 }
590
csi2_dphy_hw_stream_on(struct csi2_dphy * dphy,struct v4l2_subdev * sd)591 static int csi2_dphy_hw_stream_on(struct csi2_dphy *dphy,
592 struct v4l2_subdev *sd)
593 {
594 struct v4l2_subdev *sensor_sd = get_remote_sensor(sd);
595 struct csi2_sensor *sensor = sd_to_sensor(dphy, sensor_sd);
596 struct csi2_dphy_hw *hw = dphy->dphy_hw;
597 const struct dphy_hw_drv_data *drv_data = hw->drv_data;
598 const struct hsfreq_range *hsfreq_ranges = drv_data->hsfreq_ranges;
599 int num_hsfreq_ranges = drv_data->num_hsfreq_ranges;
600 int i, hsfreq = 0;
601 u32 val = 0, pre_val;
602
603 mutex_lock(&hw->mutex);
604
605 /* set data lane num and enable clock lane */
606 /*
607 * for rk356x: dphy0 is used just for full mode,
608 * dphy1 is used just for split mode,uses lane0_1,
609 * dphy2 is used just for split mode,uses lane2_3
610 */
611 read_csi2_dphy_reg(hw, CSI2PHY_REG_CTRL_LANE_ENABLE, &pre_val);
612 if (hw->lane_mode == LANE_MODE_FULL) {
613 val |= (GENMASK(sensor->lanes - 1, 0) <<
614 CSI2_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT) |
615 (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT);
616 } else {
617 if (!(pre_val & (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT)))
618 val |= (0x1 << CSI2_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT);
619
620 if (dphy->phy_index % 3 == DPHY1)
621 val |= (GENMASK(sensor->lanes - 1, 0) <<
622 CSI2_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT);
623
624 if (dphy->phy_index % 3 == DPHY2) {
625 val |= (GENMASK(sensor->lanes - 1, 0) <<
626 CSI2_DPHY_CTRL_DATALANE_SPLIT_LANE2_3_OFFSET_BIT);
627 write_csi2_dphy_reg(hw, CSI2PHY_CLK1_LANE_ENABLE, BIT(6));
628 }
629 }
630 val |= pre_val;
631 write_csi2_dphy_reg(hw, CSI2PHY_REG_CTRL_LANE_ENABLE, val);
632
633 if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY) {
634 /* Reset dphy digital part */
635 if (hw->lane_mode == LANE_MODE_FULL) {
636 write_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, 0x1e);
637 write_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, 0x1f);
638 } else {
639 read_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, &val);
640 if (!(val & CSI2_DPHY_LANE_DUAL_MODE_EN)) {
641 write_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, 0x5e);
642 write_csi2_dphy_reg(hw, CSI2PHY_DUAL_CLK_EN, 0x5f);
643 }
644 }
645 csi2_dphy_config_dual_mode(dphy, sensor);
646 }
647
648 /* not into receive mode/wait stopstate */
649 write_grf_reg(hw, GRF_DPHY_CSI2PHY_FORCERXMODE, 0x0);
650
651 /* enable calibration */
652 if (dphy->data_rate_mbps > 1500) {
653 if (hw->lane_mode == LANE_MODE_FULL) {
654 write_csi2_dphy_reg(hw, CSI2PHY_CLK_CALIB_ENABLE, 0x80);
655 if (sensor->lanes > 0x00)
656 write_csi2_dphy_reg(hw, CSI2PHY_LANE0_CALIB_ENABLE, 0x80);
657 if (sensor->lanes > 0x01)
658 write_csi2_dphy_reg(hw, CSI2PHY_LANE1_CALIB_ENABLE, 0x80);
659 if (sensor->lanes > 0x02)
660 write_csi2_dphy_reg(hw, CSI2PHY_LANE2_CALIB_ENABLE, 0x80);
661 if (sensor->lanes > 0x03)
662 write_csi2_dphy_reg(hw, CSI2PHY_LANE3_CALIB_ENABLE, 0x80);
663 } else {
664 if (dphy->phy_index % 3 == DPHY1) {
665 write_csi2_dphy_reg(hw, CSI2PHY_CLK_CALIB_ENABLE, 0x80);
666 if (sensor->lanes > 0x00)
667 write_csi2_dphy_reg(hw, CSI2PHY_LANE0_CALIB_ENABLE, 0x80);
668 if (sensor->lanes > 0x01)
669 write_csi2_dphy_reg(hw, CSI2PHY_LANE1_CALIB_ENABLE, 0x80);
670 }
671
672 if (dphy->phy_index % 3 == DPHY2) {
673 write_csi2_dphy_reg(hw, CSI2PHY_CLK1_CALIB_ENABLE, 0x80);
674 if (sensor->lanes > 0x00)
675 write_csi2_dphy_reg(hw, CSI2PHY_LANE2_CALIB_ENABLE, 0x80);
676 if (sensor->lanes > 0x01)
677 write_csi2_dphy_reg(hw, CSI2PHY_LANE3_CALIB_ENABLE, 0x80);
678 }
679 }
680 }
681
682 /* set clock lane and data lane */
683 for (i = 0; i < num_hsfreq_ranges; i++) {
684 if (hsfreq_ranges[i].range_h >= dphy->data_rate_mbps) {
685 hsfreq = hsfreq_ranges[i].cfg_bit;
686 break;
687 }
688 }
689
690 if (i == num_hsfreq_ranges) {
691 i = num_hsfreq_ranges - 1;
692 dev_warn(dphy->dev, "data rate: %lld mbps, max support %d mbps",
693 dphy->data_rate_mbps, hsfreq_ranges[i].range_h + 1);
694 hsfreq = hsfreq_ranges[i].cfg_bit;
695 }
696
697 if (hw->lane_mode == LANE_MODE_FULL) {
698 csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_CLOCK);
699 if (sensor->lanes > 0x00)
700 csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA0);
701 if (sensor->lanes > 0x01)
702 csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA1);
703 if (sensor->lanes > 0x02)
704 csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA2);
705 if (sensor->lanes > 0x03)
706 csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA3);
707 } else {
708 if (dphy->phy_index % 3 == DPHY1) {
709 csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_CLOCK);
710 csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA0);
711 csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA1);
712 }
713
714 if (dphy->phy_index % 3 == DPHY2) {
715 csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_CLOCK1);
716 csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA2);
717 csi_mipidphy_wr_ths_settle(hw, hsfreq, CSI2_DPHY_LANE_DATA3);
718 }
719 }
720
721 atomic_inc(&hw->stream_cnt);
722
723 mutex_unlock(&hw->mutex);
724
725 return 0;
726 }
727
csi2_dphy_hw_stream_off(struct csi2_dphy * dphy,struct v4l2_subdev * sd)728 static int csi2_dphy_hw_stream_off(struct csi2_dphy *dphy,
729 struct v4l2_subdev *sd)
730 {
731 struct csi2_dphy_hw *hw = dphy->dphy_hw;
732
733 if (atomic_dec_return(&hw->stream_cnt))
734 return 0;
735
736 mutex_lock(&hw->mutex);
737
738 write_csi2_dphy_reg(hw, CSI2PHY_REG_CTRL_LANE_ENABLE, 0x01);
739 csi2_dphy_hw_do_reset(hw);
740 usleep_range(500, 1000);
741
742 mutex_unlock(&hw->mutex);
743
744 return 0;
745 }
746
csi_dcphy_wait_lane_prepare(struct csi2_dphy_hw * hw,int index)747 static int csi_dcphy_wait_lane_prepare(struct csi2_dphy_hw *hw, int index)
748 {
749 int count = 0;
750 u32 val = 0;
751
752 read_csi2_dphy_reg(hw, index, &val);
753 while (!(val & BIT(1))) {
754 usleep_range(10, 20);
755 read_csi2_dphy_reg(hw, index, &val);
756 count++;
757 if (count > 2000)
758 return -EINVAL;
759 }
760 return 0;
761 }
762
csi2_dcphy_hw_stream_on(struct csi2_dphy * dphy,struct v4l2_subdev * sd)763 static int csi2_dcphy_hw_stream_on(struct csi2_dphy *dphy,
764 struct v4l2_subdev *sd)
765 {
766 struct v4l2_subdev *sensor_sd = get_remote_sensor(sd);
767 struct csi2_sensor *sensor = sd_to_sensor(dphy, sensor_sd);
768 struct csi2_dphy_hw *hw = dphy->dphy_hw;
769 const struct dphy_hw_drv_data *drv_data = hw->drv_data;
770 const struct hsfreq_range *hsfreq_ranges = drv_data->hsfreq_ranges;
771 int num_hsfreq_ranges = drv_data->num_hsfreq_ranges;
772 int i, hsfreq = 0;
773 u32 sot_sync = 0;
774
775 if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY) {
776 hsfreq_ranges = drv_data->hsfreq_ranges;
777 num_hsfreq_ranges = drv_data->num_hsfreq_ranges;
778 sot_sync = 0x03;
779 } else if (sensor->mbus.type == V4L2_MBUS_CSI2_CPHY) {
780 hsfreq_ranges = drv_data->hsfreq_ranges_cphy;
781 num_hsfreq_ranges = drv_data->num_hsfreq_ranges_cphy;
782 sot_sync = 0x32;
783 }
784
785 mutex_lock(&hw->mutex);
786 if (sensor->mbus.type == V4L2_MBUS_CSI2_CPHY)
787 write_grf_reg(hw, GRF_CPHY_MODE, 0x9);
788
789 if (hw->rsts_bulk)
790 reset_control_assert(hw->rsts_bulk);
791
792 /*clk settle fix to 0x301*/
793 if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY) {
794 write_csi2_dphy_reg(hw, CSI2PHY_CLK_THS_SETTLE, 0x301);
795 write_csi2_dphy_reg(hw, CSI2PHY_S0C_GNR_CON1, 0x1450);
796 write_csi2_dphy_reg(hw, CSI2PHY_COMBO_S0D0_GNR_CON1, 0x1450);
797 write_csi2_dphy_reg(hw, CSI2PHY_COMBO_S0D1_GNR_CON1, 0x1450);
798 write_csi2_dphy_reg(hw, CSI2PHY_COMBO_S0D2_GNR_CON1, 0x1450);
799 write_csi2_dphy_reg(hw, CSI2PHY_S0D3_GNR_CON1, 0x1450);
800 }
801 /* set data lane */
802 for (i = 0; i < num_hsfreq_ranges; i++) {
803 if (hsfreq_ranges[i].range_h >= dphy->data_rate_mbps) {
804 hsfreq = hsfreq_ranges[i].cfg_bit;
805 break;
806 }
807 }
808
809 if (i == num_hsfreq_ranges) {
810 i = num_hsfreq_ranges - 1;
811 dev_warn(dphy->dev, "data rate: %lld mbps, max support %d mbps",
812 dphy->data_rate_mbps, hsfreq_ranges[i].range_h + 1);
813 hsfreq = hsfreq_ranges[i].cfg_bit;
814 }
815 if (sensor->lanes > 0x00) {
816 write_csi2_dphy_reg_mask(hw, CSI2PHY_LANE0_THS_SETTLE, hsfreq, 0x1ff);
817 write_csi2_dphy_reg_mask(hw, CSI2PHY_LANE0_ERR_SOT_SYNC, sot_sync, 0xff);
818 }
819 if (sensor->lanes > 0x01) {
820 write_csi2_dphy_reg_mask(hw, CSI2PHY_LANE1_THS_SETTLE, hsfreq, 0x1ff);
821 write_csi2_dphy_reg_mask(hw, CSI2PHY_LANE1_ERR_SOT_SYNC, sot_sync, 0xff);
822 }
823 if (sensor->lanes > 0x02) {
824 write_csi2_dphy_reg_mask(hw, CSI2PHY_LANE2_THS_SETTLE, hsfreq, 0x1ff);
825 write_csi2_dphy_reg_mask(hw, CSI2PHY_LANE2_ERR_SOT_SYNC, sot_sync, 0xff);
826 }
827 if (sensor->lanes > 0x03) {
828 write_csi2_dphy_reg_mask(hw, CSI2PHY_LANE3_THS_SETTLE, hsfreq, 0x1ff);
829 write_csi2_dphy_reg_mask(hw, CSI2PHY_LANE3_ERR_SOT_SYNC, sot_sync, 0xff);
830 }
831
832 if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY)
833 write_csi2_dphy_reg(hw, CSI2PHY_CLK_LANE_ENABLE, BIT(0));
834
835 if (sensor->lanes > 0x00)
836 write_csi2_dphy_reg(hw, CSI2PHY_DATA_LANE0_ENABLE, BIT(0));
837 if (sensor->lanes > 0x01)
838 write_csi2_dphy_reg(hw, CSI2PHY_DATA_LANE1_ENABLE, BIT(0));
839 if (sensor->lanes > 0x02)
840 write_csi2_dphy_reg(hw, CSI2PHY_DATA_LANE2_ENABLE, BIT(0));
841 if (sensor->lanes > 0x03)
842 write_csi2_dphy_reg(hw, CSI2PHY_DATA_LANE3_ENABLE, BIT(0));
843
844 /*wait for clk lane ready*/
845 if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY)
846 if (csi_dcphy_wait_lane_prepare(hw, CSI2PHY_CLK_LANE_ENABLE))
847 goto out_streamon;
848
849 /*wait for data lane ready*/
850 if (sensor->lanes > 0x00)
851 if (csi_dcphy_wait_lane_prepare(hw, CSI2PHY_DATA_LANE0_ENABLE))
852 goto out_streamon;
853 if (sensor->lanes > 0x01)
854 if (csi_dcphy_wait_lane_prepare(hw, CSI2PHY_DATA_LANE1_ENABLE))
855 goto out_streamon;
856 if (sensor->lanes > 0x02)
857 if (csi_dcphy_wait_lane_prepare(hw, CSI2PHY_DATA_LANE2_ENABLE))
858 goto out_streamon;
859 if (sensor->lanes > 0x03)
860 if (csi_dcphy_wait_lane_prepare(hw, CSI2PHY_DATA_LANE3_ENABLE))
861 goto out_streamon;
862
863 if (hw->rsts_bulk)
864 reset_control_deassert(hw->rsts_bulk);
865 atomic_inc(&hw->stream_cnt);
866
867 mutex_unlock(&hw->mutex);
868
869 return 0;
870 out_streamon:
871 if (hw->rsts_bulk)
872 reset_control_deassert(hw->rsts_bulk);
873 mutex_unlock(&hw->mutex);
874 dev_err(dphy->dev, "stream on error\n");
875 return -EINVAL;
876
877 }
878
csi2_dcphy_hw_stream_off(struct csi2_dphy * dphy,struct v4l2_subdev * sd)879 static int csi2_dcphy_hw_stream_off(struct csi2_dphy *dphy,
880 struct v4l2_subdev *sd)
881 {
882 struct csi2_dphy_hw *hw = dphy->dphy_hw;
883 struct v4l2_subdev *sensor_sd = get_remote_sensor(sd);
884 struct csi2_sensor *sensor = sd_to_sensor(dphy, sensor_sd);
885
886 if (atomic_dec_return(&hw->stream_cnt))
887 return 0;
888
889 mutex_lock(&hw->mutex);
890 if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY)
891 write_csi2_dphy_reg(hw, CSI2PHY_CLK_LANE_ENABLE, 0);
892 if (sensor->lanes > 0x00)
893 write_csi2_dphy_reg(hw, CSI2PHY_DATA_LANE0_ENABLE, 0);
894 if (sensor->lanes > 0x01)
895 write_csi2_dphy_reg(hw, CSI2PHY_DATA_LANE1_ENABLE, 0);
896 if (sensor->lanes > 0x02)
897 write_csi2_dphy_reg(hw, CSI2PHY_DATA_LANE2_ENABLE, 0);
898 if (sensor->lanes > 0x03)
899 write_csi2_dphy_reg(hw, CSI2PHY_DATA_LANE3_ENABLE, 0);
900
901 usleep_range(500, 1000);
902
903 mutex_unlock(&hw->mutex);
904
905 return 0;
906 }
907
rk3568_csi2_dphy_hw_individual_init(struct csi2_dphy_hw * hw)908 static void rk3568_csi2_dphy_hw_individual_init(struct csi2_dphy_hw *hw)
909 {
910 hw->grf_regs = rk3568_grf_dphy_regs;
911 }
912
rk3588_csi2_dphy_hw_individual_init(struct csi2_dphy_hw * hw)913 static void rk3588_csi2_dphy_hw_individual_init(struct csi2_dphy_hw *hw)
914 {
915 hw->grf_regs = rk3588_grf_dphy_regs;
916 }
917
rk3588_csi2_dcphy_hw_individual_init(struct csi2_dphy_hw * hw)918 static void rk3588_csi2_dcphy_hw_individual_init(struct csi2_dphy_hw *hw)
919 {
920 hw->grf_regs = rk3588_grf_dcphy_regs;
921 }
922
923 static const struct dphy_hw_drv_data rk3568_csi2_dphy_hw_drv_data = {
924 .hsfreq_ranges = rk3568_csi2_dphy_hw_hsfreq_ranges,
925 .num_hsfreq_ranges = ARRAY_SIZE(rk3568_csi2_dphy_hw_hsfreq_ranges),
926 .csi2dphy_regs = rk3568_csi2dphy_regs,
927 .grf_regs = rk3568_grf_dphy_regs,
928 .individual_init = rk3568_csi2_dphy_hw_individual_init,
929 .chip_id = CHIP_ID_RK3568,
930 .stream_on = csi2_dphy_hw_stream_on,
931 .stream_off = csi2_dphy_hw_stream_off,
932 };
933
934 static const struct dphy_hw_drv_data rk3588_csi2_dphy_hw_drv_data = {
935 .hsfreq_ranges = rk3568_csi2_dphy_hw_hsfreq_ranges,
936 .num_hsfreq_ranges = ARRAY_SIZE(rk3568_csi2_dphy_hw_hsfreq_ranges),
937 .csi2dphy_regs = rk3588_csi2dphy_regs,
938 .grf_regs = rk3588_grf_dphy_regs,
939 .individual_init = rk3588_csi2_dphy_hw_individual_init,
940 .chip_id = CHIP_ID_RK3588,
941 .stream_on = csi2_dphy_hw_stream_on,
942 .stream_off = csi2_dphy_hw_stream_off,
943 };
944
945 static const struct dphy_hw_drv_data rk3588_csi2_dcphy_hw_drv_data = {
946 .hsfreq_ranges = rk3588_csi2_dcphy_d_hw_hsfreq_ranges,
947 .num_hsfreq_ranges = ARRAY_SIZE(rk3588_csi2_dcphy_d_hw_hsfreq_ranges),
948 .hsfreq_ranges_cphy = rk3588_csi2_dcphy_c_hw_hsfreq_ranges,
949 .num_hsfreq_ranges_cphy = ARRAY_SIZE(rk3588_csi2_dcphy_c_hw_hsfreq_ranges),
950 .csi2dphy_regs = rk3588_csi2dcphy_regs,
951 .grf_regs = rk3588_grf_dcphy_regs,
952 .individual_init = rk3588_csi2_dcphy_hw_individual_init,
953 .chip_id = CHIP_ID_RK3588_DCPHY,
954 .stream_on = csi2_dcphy_hw_stream_on,
955 .stream_off = csi2_dcphy_hw_stream_off,
956 };
957
958 static const struct of_device_id rockchip_csi2_dphy_hw_match_id[] = {
959 {
960 .compatible = "rockchip,rk3568-csi2-dphy-hw",
961 .data = &rk3568_csi2_dphy_hw_drv_data,
962 },
963 {
964 .compatible = "rockchip,rk3588-csi2-dphy-hw",
965 .data = &rk3588_csi2_dphy_hw_drv_data,
966 },
967 {
968 .compatible = "rockchip,rk3588-csi2-dcphy-hw",
969 .data = &rk3588_csi2_dcphy_hw_drv_data,
970 },
971 {}
972 };
973 MODULE_DEVICE_TABLE(of, rockchip_csi2_dphy_hw_match_id);
974
rockchip_csi2_dphy_hw_probe(struct platform_device * pdev)975 static int rockchip_csi2_dphy_hw_probe(struct platform_device *pdev)
976 {
977 struct device *dev = &pdev->dev;
978 struct csi2_dphy_hw *dphy_hw;
979 struct regmap *grf;
980 struct resource *res;
981 const struct of_device_id *of_id;
982 const struct dphy_hw_drv_data *drv_data;
983
984 dphy_hw = devm_kzalloc(dev, sizeof(*dphy_hw), GFP_KERNEL);
985 if (!dphy_hw)
986 return -ENOMEM;
987 dphy_hw->dev = dev;
988
989 of_id = of_match_device(rockchip_csi2_dphy_hw_match_id, dev);
990 if (!of_id)
991 return -EINVAL;
992
993 drv_data = of_id->data;
994
995 grf = syscon_regmap_lookup_by_phandle(dev->of_node,
996 "rockchip,grf");
997 if (IS_ERR(grf)) {
998 dev_err(dev, "Can't find GRF syscon\n");
999 return -ENODEV;
1000 }
1001 dphy_hw->regmap_grf = grf;
1002
1003 if (drv_data->chip_id == CHIP_ID_RK3588) {
1004 grf = syscon_regmap_lookup_by_phandle(dev->of_node,
1005 "rockchip,sys_grf");
1006 if (IS_ERR(grf)) {
1007 dev_err(dev, "Can't find SYS GRF syscon\n");
1008 return -ENODEV;
1009 }
1010 dphy_hw->regmap_sys_grf = grf;
1011 }
1012
1013 dphy_hw->num_clks = devm_clk_bulk_get_all(dev, &dphy_hw->clks_bulk);
1014 if (dphy_hw->num_clks < 0)
1015 dev_err(dev, "failed to get csi2 clks\n");
1016
1017 dphy_hw->rsts_bulk = devm_reset_control_array_get_optional_exclusive(dev);
1018 if (IS_ERR(dphy_hw->rsts_bulk))
1019 dev_err_probe(dev, PTR_ERR(dphy_hw->rsts_bulk), "failed to get dphy reset\n");
1020
1021 dphy_hw->dphy_dev_num = 0;
1022 dphy_hw->drv_data = drv_data;
1023 dphy_hw->lane_mode = LANE_MODE_UNDEF;
1024 dphy_hw->grf_regs = drv_data->grf_regs;
1025 dphy_hw->txrx_regs = drv_data->txrx_regs;
1026 dphy_hw->csi2dphy_regs = drv_data->csi2dphy_regs;
1027
1028 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1029 dphy_hw->hw_base_addr = devm_ioremap_resource(dev, res);
1030 if (IS_ERR(dphy_hw->hw_base_addr)) {
1031 resource_size_t offset = res->start;
1032 resource_size_t size = resource_size(res);
1033
1034 dphy_hw->hw_base_addr = devm_ioremap(dev, offset, size);
1035 if (IS_ERR(dphy_hw->hw_base_addr)) {
1036 dev_err(dev, "Can't find csi2 dphy hw addr!\n");
1037 return -ENODEV;
1038 }
1039 }
1040 dphy_hw->stream_on = drv_data->stream_on;
1041 dphy_hw->stream_off = drv_data->stream_off;
1042
1043 atomic_set(&dphy_hw->stream_cnt, 0);
1044
1045 mutex_init(&dphy_hw->mutex);
1046
1047 platform_set_drvdata(pdev, dphy_hw);
1048
1049 pm_runtime_enable(&pdev->dev);
1050
1051 dev_info(dev, "csi2 dphy hw probe successfully!\n");
1052
1053 return 0;
1054 }
1055
rockchip_csi2_dphy_hw_remove(struct platform_device * pdev)1056 static int rockchip_csi2_dphy_hw_remove(struct platform_device *pdev)
1057 {
1058 struct csi2_dphy_hw *hw = platform_get_drvdata(pdev);
1059
1060 pm_runtime_disable(&pdev->dev);
1061 mutex_destroy(&hw->mutex);
1062
1063 return 0;
1064 }
1065
1066 static struct platform_driver rockchip_csi2_dphy_hw_driver = {
1067 .probe = rockchip_csi2_dphy_hw_probe,
1068 .remove = rockchip_csi2_dphy_hw_remove,
1069 .driver = {
1070 .name = "rockchip-csi2-dphy-hw",
1071 .of_match_table = rockchip_csi2_dphy_hw_match_id,
1072 },
1073 };
1074 module_platform_driver(rockchip_csi2_dphy_hw_driver);
1075
1076 MODULE_AUTHOR("Rockchip Camera/ISP team");
1077 MODULE_DESCRIPTION("Rockchip MIPI CSI2 DPHY HW driver");
1078 MODULE_LICENSE("GPL v2");
1079