1 /*
2 * Copyright (c) 2017 Rockchip Electronics Co. Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
17 #include <linux/delay.h>
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
20 #include <linux/io.h>
21 #include <linux/iopoll.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/nvmem-consumer.h>
25 #include <linux/of.h>
26 #include <linux/phy/phy.h>
27 #include <linux/platform_device.h>
28 #include <linux/regmap.h>
29 #include <linux/rockchip/cpu.h>
30 #include <linux/slab.h>
31
32 #define INNO_HDMI_PHY_TIMEOUT_LOOP_COUNT 1000
33
34 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l)))
35
36 /* REG: 0x00 */
37 #define PRE_PLL_REFCLK_SEL_MASK BIT(0)
38 #define PRE_PLL_REFCLK_SEL_PCLK BIT(0)
39 #define PRE_PLL_REFCLK_SEL_OSCCLK 0
40 /* REG: 0x01 */
41 #define BYPASS_RXSENSE_EN_MASK BIT(2)
42 #define BYPASS_RXSENSE_EN BIT(2)
43 #define BYPASS_PWRON_EN_MASK BIT(1)
44 #define BYPASS_PWRON_EN BIT(1)
45 #define BYPASS_PLLPD_EN_MASK BIT(0)
46 #define BYPASS_PLLPD_EN BIT(0)
47 /* REG: 0x02 */
48 #define BYPASS_PDATA_EN_MASK BIT(4)
49 #define BYPASS_PDATA_EN BIT(4)
50 #define PDATAEN_MASK BIT(0)
51 #define PDATAEN_DISABLE BIT(0)
52 #define PDATAEN_ENABLE 0
53 /* REG: 0x03 */
54 #define BYPASS_AUTO_TERM_RES_CAL BIT(7)
55 #define AUDO_TERM_RES_CAL_SPEED_14_8(x) UPDATE(x, 6, 0)
56 /* REG: 0x04 */
57 #define AUDO_TERM_RES_CAL_SPEED_7_0(x) UPDATE(x, 7, 0)
58 /* REG: 0xaa */
59 #define POST_PLL_CTRL_MASK BIT(0)
60 #define POST_PLL_CTRL_MANUAL BIT(0)
61 /* REG: 0xe0 */
62 #define POST_PLL_POWER_MASK BIT(5)
63 #define POST_PLL_POWER_DOWN BIT(5)
64 #define POST_PLL_POWER_UP 0
65 #define PRE_PLL_POWER_MASK BIT(4)
66 #define PRE_PLL_POWER_DOWN BIT(4)
67 #define PRE_PLL_POWER_UP 0
68 #define RXSENSE_CLK_CH_MASK BIT(3)
69 #define RXSENSE_CLK_CH_ENABLE BIT(3)
70 #define RXSENSE_DATA_CH2_MASK BIT(2)
71 #define RXSENSE_DATA_CH2_ENABLE BIT(2)
72 #define RXSENSE_DATA_CH1_MASK BIT(1)
73 #define RXSENSE_DATA_CH1_ENABLE BIT(1)
74 #define RXSENSE_DATA_CH0_MASK BIT(0)
75 #define RXSENSE_DATA_CH0_ENABLE BIT(0)
76 /* REG: 0xe1 */
77 #define BANDGAP_MASK BIT(4)
78 #define BANDGAP_ENABLE BIT(4)
79 #define BANDGAP_DISABLE 0
80 #define TMDS_DRIVER_MASK GENMASK(3, 0)
81 #define TMDS_DRIVER_ENABLE UPDATE(0xf, 3, 0)
82 #define TMDS_DRIVER_DISABLE 0
83 /* REG: 0xe2 */
84 #define PRE_PLL_FB_DIV_8_MASK BIT(7)
85 #define PRE_PLL_FB_DIV_8_SHIFT 7
86 #define PRE_PLL_FB_DIV_8(x) UPDATE(x, 7, 7)
87 #define PCLK_VCO_DIV_5_MASK BIT(5)
88 #define PCLK_VCO_DIV_5_SHIFT 5
89 #define PCLK_VCO_DIV_5(x) UPDATE(x, 5, 5)
90 #define PRE_PLL_PRE_DIV_MASK GENMASK(4, 0)
91 #define PRE_PLL_PRE_DIV(x) UPDATE(x, 4, 0)
92 /* REG: 0xe3 */
93 #define PRE_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0)
94 /* REG: 0xe4 */
95 #define PRE_PLL_PCLK_DIV_B_MASK GENMASK(6, 5)
96 #define PRE_PLL_PCLK_DIV_B_SHIFT 5
97 #define PRE_PLL_PCLK_DIV_B(x) UPDATE(x, 6, 5)
98 #define PRE_PLL_PCLK_DIV_A_MASK GENMASK(4, 0)
99 #define PRE_PLL_PCLK_DIV_A_SHIFT 0
100 #define PRE_PLL_PCLK_DIV_A(x) UPDATE(x, 4, 0)
101 /* REG: 0xe5 */
102 #define PRE_PLL_PCLK_DIV_C_MASK GENMASK(6, 5)
103 #define PRE_PLL_PCLK_DIV_C_SHIFT 5
104 #define PRE_PLL_PCLK_DIV_C(x) UPDATE(x, 6, 5)
105 #define PRE_PLL_PCLK_DIV_D_MASK GENMASK(4, 0)
106 #define PRE_PLL_PCLK_DIV_D_SHIFT 0
107 #define PRE_PLL_PCLK_DIV_D(x) UPDATE(x, 4, 0)
108 /* REG: 0xe6 */
109 #define PRE_PLL_TMDSCLK_DIV_C_MASK GENMASK(5, 4)
110 #define PRE_PLL_TMDSCLK_DIV_C(x) UPDATE(x, 5, 4)
111 #define PRE_PLL_TMDSCLK_DIV_A_MASK GENMASK(3, 2)
112 #define PRE_PLL_TMDSCLK_DIV_A(x) UPDATE(x, 3, 2)
113 #define PRE_PLL_TMDSCLK_DIV_B_MASK GENMASK(1, 0)
114 #define PRE_PLL_TMDSCLK_DIV_B(x) UPDATE(x, 1, 0)
115 /* REG: 0xe8 */
116 #define PRE_PLL_LOCK_STATUS BIT(0)
117 /* REG: 0xe9 */
118 #define POST_PLL_POST_DIV_EN_MASK GENMASK(7, 6)
119 #define POST_PLL_POST_DIV_ENABLE UPDATE(3, 7, 6)
120 #define POST_PLL_POST_DIV_DISABLE 0
121 #define POST_PLL_PRE_DIV_MASK GENMASK(4, 0)
122 #define POST_PLL_PRE_DIV(x) UPDATE(x, 4, 0)
123 /* REG: 0xea */
124 #define POST_PLL_FB_DIV_7_0(x) UPDATE(x, 7, 0)
125 /* REG: 0xeb */
126 #define POST_PLL_FB_DIV_8_MASK BIT(7)
127 #define POST_PLL_FB_DIV_8(x) UPDATE(x, 7, 7)
128 #define POST_PLL_POST_DIV_MASK GENMASK(5, 4)
129 #define POST_PLL_POST_DIV(x) UPDATE(x, 5, 4)
130 #define POST_PLL_LOCK_STATUS BIT(0)
131 /* REG: 0xee */
132 #define TMDS_CH_TA_MASK GENMASK(7, 4)
133 #define TMDS_CH_TA_ENABLE UPDATE(0xf, 7, 4)
134 #define TMDS_CH_TA_DISABLE 0
135 /* REG: 0xef */
136 #define TMDS_CLK_CH_TA(x) UPDATE(x, 7, 6)
137 #define TMDS_DATA_CH2_TA(x) UPDATE(x, 5, 4)
138 #define TMDS_DATA_CH1_TA(x) UPDATE(x, 3, 2)
139 #define TMDS_DATA_CH0_TA(x) UPDATE(x, 1, 0)
140 /* REG: 0xf0 */
141 #define TMDS_DATA_CH2_PRE_EMPHASIS_MASK GENMASK(5, 4)
142 #define TMDS_DATA_CH2_PRE_EMPHASIS(x) UPDATE(x, 5, 4)
143 #define TMDS_DATA_CH1_PRE_EMPHASIS_MASK GENMASK(3, 2)
144 #define TMDS_DATA_CH1_PRE_EMPHASIS(x) UPDATE(x, 3, 2)
145 #define TMDS_DATA_CH0_PRE_EMPHASIS_MASK GENMASK(1, 0)
146 #define TMDS_DATA_CH0_PRE_EMPHASIS(x) UPDATE(x, 1, 0)
147 /* REG: 0xf1 */
148 #define TMDS_CLK_CH_OUTPUT_SWING(x) UPDATE(x, 7, 4)
149 #define TMDS_DATA_CH2_OUTPUT_SWING(x) UPDATE(x, 3, 0)
150 /* REG: 0xf2 */
151 #define TMDS_DATA_CH1_OUTPUT_SWING(x) UPDATE(x, 7, 4)
152 #define TMDS_DATA_CH0_OUTPUT_SWING(x) UPDATE(x, 3, 0)
153
154 enum inno_hdmi_phy_type {
155 INNO_HDMI_PHY_RK3228,
156 INNO_HDMI_PHY_RK3328
157 };
158
159 struct phy_config {
160 unsigned long tmdsclock;
161 u8 regs[14];
162 };
163
164 struct inno_hdmi_phy_drv_data;
165
166 struct inno_hdmi_phy {
167 struct device *dev;
168 struct regmap *regmap;
169
170 int irq;
171
172 struct phy *phy;
173 struct clk *sysclk;
174 struct phy_config *phy_cfg;
175
176 /* platform data */
177 struct inno_hdmi_phy_drv_data *plat_data;
178
179 /* efuse flag */
180 bool efuse_flag;
181
182 /* clk provider */
183 struct clk_hw hw;
184 struct clk *pclk;
185 unsigned long pixclock;
186 unsigned long tmdsclock;
187 };
188
189 struct pre_pll_config {
190 unsigned long pixclock;
191 unsigned long tmdsclock;
192 u8 prediv;
193 u16 fbdiv;
194 u8 tmds_div_a;
195 u8 tmds_div_b;
196 u8 tmds_div_c;
197 u8 pclk_div_a;
198 u8 pclk_div_b;
199 u8 pclk_div_c;
200 u8 pclk_div_d;
201 u8 vco_div_5_en;
202 u32 fracdiv;
203 };
204
205 struct post_pll_config {
206 unsigned long tmdsclock;
207 u8 prediv;
208 u16 fbdiv;
209 u8 postdiv;
210 u8 version;
211 };
212
213 struct inno_hdmi_phy_ops {
214 void (*init)(struct inno_hdmi_phy *inno);
215 int (*power_on)(struct inno_hdmi_phy *inno,
216 const struct post_pll_config *cfg,
217 const struct phy_config *phy_cfg);
218 void (*power_off)(struct inno_hdmi_phy *inno);
219 int (*pre_pll_update)(struct inno_hdmi_phy *inno,
220 const struct pre_pll_config *cfg);
221 unsigned long (*recalc_rate)(struct inno_hdmi_phy *inno,
222 unsigned long parent_rate);
223 };
224
225 struct inno_hdmi_phy_drv_data {
226 enum inno_hdmi_phy_type dev_type;
227 const struct inno_hdmi_phy_ops *ops;
228 const struct phy_config *phy_cfg_table;
229 };
230
231 /*
232 * If only using integer freq div can't get frequency we want, frac
233 * freq div is needed. For example, pclk 88.75 Mhz and tmdsclk
234 * 110.9375 Mhz must use frac div 0xF00000. The actual frequency is different
235 * from the target frequency. Such as the tmds clock 110.9375 Mhz,
236 * the actual tmds clock we get is 110.93719 Mhz. It is important
237 * to note that RK322X platforms do not support frac div.
238 */
239 static const struct pre_pll_config pre_pll_cfg_table[] = {
240 { 27000000, 27000000, 1, 90, 3, 2, 2, 10, 3, 3, 4, 0, 0},
241 { 27000000, 33750000, 1, 90, 1, 3, 3, 10, 3, 3, 4, 0, 0},
242 { 40000000, 40000000, 1, 80, 2, 2, 2, 12, 2, 2, 2, 0, 0},
243 { 40000000, 50000000, 1, 100, 2, 2, 2, 1, 0, 0, 15, 0, 0},
244 { 59341000, 59341000, 1, 98, 3, 1, 2, 1, 3, 3, 4, 0, 0xE6AE6B},
245 { 59400000, 59400000, 1, 99, 3, 1, 1, 1, 3, 3, 4, 0, 0},
246 { 59341000, 74176250, 1, 98, 0, 3, 3, 1, 3, 3, 4, 0, 0xE6AE6B},
247 { 59400000, 74250000, 1, 99, 1, 2, 2, 1, 3, 3, 4, 0, 0},
248 { 65000000, 65000000, 1, 130, 2, 2, 2, 1, 0, 0, 12, 0, 0},
249 { 65000000, 81250000, 3, 325, 0, 3, 3, 1, 0, 0, 10, 0, 0},
250 { 71000000, 71000000, 3, 284, 0, 3, 3, 1, 0, 0, 8, 0, 0},
251 { 71000000, 88750000, 3, 355, 0, 3, 3, 1, 0, 0, 10, 0, 0},
252 { 74176000, 74176000, 1, 98, 1, 2, 2, 1, 2, 3, 4, 0, 0xE6AE6B},
253 { 74250000, 74250000, 1, 99, 1, 2, 2, 1, 2, 3, 4, 0, 0},
254 { 74176000, 92720000, 4, 494, 1, 2, 2, 1, 3, 3, 4, 0, 0x816817},
255 { 74250000, 92812500, 4, 495, 1, 2, 2, 1, 3, 3, 4, 0, 0},
256 { 83500000, 83500000, 2, 167, 2, 1, 1, 1, 0, 0, 6, 0, 0},
257 { 83500000, 104375000, 1, 104, 2, 1, 1, 1, 1, 0, 5, 0, 0x600000},
258 { 85750000, 85750000, 3, 343, 0, 3, 3, 1, 0, 0, 8, 0, 0},
259 { 88750000, 88750000, 3, 355, 0, 3, 3, 1, 0, 0, 8, 0, 0},
260 { 88750000, 110937500, 1, 110, 2, 1, 1, 1, 1, 0, 5, 0, 0xF00000},
261 {108000000, 108000000, 1, 90, 3, 0, 0, 1, 0, 0, 5, 0, 0},
262 {108000000, 135000000, 1, 90, 0, 2, 2, 1, 0, 0, 5, 0, 0},
263 {119000000, 119000000, 1, 119, 2, 1, 1, 1, 0, 0, 6, 0, 0},
264 {119000000, 148750000, 1, 99, 0, 2, 2, 1, 0, 0, 5, 0, 0x2AAAAA},
265 {148352000, 148352000, 1, 98, 1, 1, 1, 1, 2, 2, 2, 0, 0xE6AE6B},
266 {148500000, 148500000, 1, 99, 1, 1, 1, 1, 2, 2, 2, 0, 0},
267 {148352000, 185440000, 4, 494, 0, 2, 2, 1, 3, 2, 2, 0, 0x816817},
268 {148500000, 185625000, 4, 495, 0, 2, 2, 1, 3, 2, 2, 0, 0},
269 {162000000, 162000000, 1, 108, 0, 2, 2, 1, 0, 0, 4, 0, 0},
270 {162000000, 202500000, 1, 135, 0, 2, 2, 1, 0, 0, 5, 0, 0},
271 {296703000, 296703000, 1, 98, 0, 1, 1, 1, 0, 2, 2, 0, 0xE6AE6B},
272 {297000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 2, 2, 0, 0},
273 {296703000, 370878750, 4, 494, 1, 2, 0, 1, 3, 1, 1, 0, 0x816817},
274 {297000000, 371250000, 4, 495, 1, 2, 0, 1, 3, 1, 1, 0, 0},
275 {593407000, 296703500, 1, 98, 0, 1, 1, 1, 0, 2, 1, 0, 0xE6AE6B},
276 {594000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 2, 1, 0, 0},
277 {593407000, 370879375, 4, 494, 1, 2, 0, 1, 3, 1, 1, 1, 0x816817},
278 {594000000, 371250000, 4, 495, 1, 2, 0, 1, 3, 1, 1, 1, 0},
279 {593407000, 593407000, 1, 98, 0, 2, 0, 1, 0, 1, 1, 0, 0xE6AE6B},
280 {594000000, 594000000, 1, 99, 0, 2, 0, 1, 0, 1, 1, 0, 0},
281 { ~0UL, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
282 };
283
284 static const struct post_pll_config post_pll_cfg_table[] = {
285 {33750000, 1, 40, 8, 1},
286 {33750000, 1, 80, 8, 2},
287 {33750000, 1, 10, 2, 4},
288 {74250000, 1, 40, 8, 1},
289 {74250000, 18, 80, 8, 2},
290 {148500000, 2, 40, 4, 3},
291 {297000000, 4, 40, 2, 3},
292 {594000000, 8, 40, 1, 3},
293 { ~0UL, 0, 0, 0, 0}
294 };
295
296 static const struct phy_config rk3228_phy_cfg[] = {
297 { 165000000, {
298 0xaa, 0x00, 0x44, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00,
299 0x00, 0x00, 0x00, 0x00, 0x00,
300 },
301 }, {
302 340000000, {
303 0xaa, 0x15, 0x6a, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00,
304 0x00, 0x00, 0x00, 0x00, 0x00,
305 },
306 }, {
307 594000000, {
308 0xaa, 0x15, 0x7a, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00,
309 0x00, 0x00, 0x00, 0x00, 0x00,
310 },
311 }, {
312 ~0UL, {
313 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
314 0x00, 0x00, 0x00, 0x00, 0x00,
315 },
316 }
317 };
318
319 static const struct phy_config rk3328_phy_cfg[] = {
320 { 165000000, {
321 0x07, 0x0a, 0x0a, 0x0a, 0x00, 0x00, 0x08, 0x08, 0x08,
322 0x00, 0xac, 0xcc, 0xcc, 0xcc,
323 },
324 }, {
325 340000000, {
326 0x0b, 0x0d, 0x0d, 0x0d, 0x07, 0x15, 0x08, 0x08, 0x08,
327 0x3f, 0xac, 0xcc, 0xcd, 0xdd,
328 },
329 }, {
330 594000000, {
331 0x10, 0x1a, 0x1a, 0x1a, 0x07, 0x15, 0x08, 0x08, 0x08,
332 0x00, 0xac, 0xcc, 0xcc, 0xcc,
333 },
334 }, {
335 ~0UL, {
336 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
337 0x00, 0x00, 0x00, 0x00, 0x00,
338 },
339 }
340 };
341
to_inno_hdmi_phy(struct clk_hw * hw)342 static inline struct inno_hdmi_phy *to_inno_hdmi_phy(struct clk_hw *hw)
343 {
344 return container_of(hw, struct inno_hdmi_phy, hw);
345 }
346
inno_write(struct inno_hdmi_phy * inno,u32 reg,u8 val)347 static inline void inno_write(struct inno_hdmi_phy *inno, u32 reg, u8 val)
348 {
349 regmap_write(inno->regmap, reg * 4, val);
350 }
351
inno_read(struct inno_hdmi_phy * inno,u32 reg)352 static inline u8 inno_read(struct inno_hdmi_phy *inno, u32 reg)
353 {
354 u32 val;
355
356 regmap_read(inno->regmap, reg * 4, &val);
357
358 return val;
359 }
360
inno_update_bits(struct inno_hdmi_phy * inno,u8 reg,u8 mask,u8 val)361 static inline void inno_update_bits(struct inno_hdmi_phy *inno, u8 reg,
362 u8 mask, u8 val)
363 {
364 regmap_update_bits(inno->regmap, reg * 4, mask, val);
365 }
366
inno_hdmi_phy_get_tmdsclk(struct inno_hdmi_phy * inno,int rate)367 static u32 inno_hdmi_phy_get_tmdsclk(struct inno_hdmi_phy *inno, int rate)
368 {
369 int bus_width = phy_get_bus_width(inno->phy);
370 u32 tmdsclk;
371
372 switch (bus_width) {
373 case 4:
374 tmdsclk = (u32)rate / 2;
375 break;
376 case 5:
377 tmdsclk = (u32)rate * 5 / 8;
378 break;
379 case 6:
380 tmdsclk = (u32)rate * 3 / 4;
381 break;
382 case 10:
383 tmdsclk = (u32)rate * 5 / 4;
384 break;
385 case 12:
386 tmdsclk = (u32)rate * 3 / 2;
387 break;
388 case 16:
389 tmdsclk = (u32)rate * 2;
390 break;
391 default:
392 tmdsclk = rate;
393 }
394
395 return tmdsclk;
396 }
397
inno_hdmi_phy_hardirq(int irq,void * dev_id)398 static irqreturn_t inno_hdmi_phy_hardirq(int irq, void *dev_id)
399 {
400 struct inno_hdmi_phy *inno = dev_id;
401 int intr_stat1, intr_stat2, intr_stat3;
402
403 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228)
404 return IRQ_NONE;
405
406 intr_stat1 = inno_read(inno, 0x04);
407 intr_stat2 = inno_read(inno, 0x06);
408 intr_stat3 = inno_read(inno, 0x08);
409
410 if (intr_stat1)
411 inno_write(inno, 0x04, intr_stat1);
412 if (intr_stat2)
413 inno_write(inno, 0x06, intr_stat2);
414 if (intr_stat3)
415 inno_write(inno, 0x08, intr_stat3);
416
417 if (intr_stat1 || intr_stat2 || intr_stat3)
418 return IRQ_WAKE_THREAD;
419
420 return IRQ_HANDLED;
421 }
422
inno_hdmi_phy_irq(int irq,void * dev_id)423 static irqreturn_t inno_hdmi_phy_irq(int irq, void *dev_id)
424 {
425 struct inno_hdmi_phy *inno = dev_id;
426
427 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228)
428 return IRQ_NONE;
429 /* set pdata_en to 0 */
430 inno_update_bits(inno, 0x02, 1, 0);
431
432 udelay(10);
433
434 /* set pdata_en to 1 */
435 inno_update_bits(inno, 0x02, 1, 1);
436
437 return IRQ_HANDLED;
438 }
439
440 static int inno_hdmi_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate,
441 unsigned long parent_rate);
442
inno_hdmi_phy_power_on(struct phy * phy)443 static int inno_hdmi_phy_power_on(struct phy *phy)
444 {
445 struct inno_hdmi_phy *inno = phy_get_drvdata(phy);
446 const struct post_pll_config *cfg = post_pll_cfg_table;
447 const struct phy_config *phy_cfg = inno->plat_data->phy_cfg_table;
448 u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, inno->pixclock);
449 u32 chipversion = 1;
450
451 if (inno->phy_cfg)
452 phy_cfg = inno->phy_cfg;
453
454 if (!tmdsclock) {
455 dev_err(inno->dev, "TMDS clock is zero!\n");
456 return -EINVAL;
457 }
458
459 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3328 &&
460 rockchip_get_cpu_version())
461 chipversion = 2;
462 else if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228 &&
463 tmdsclock <= 33750000 && inno->efuse_flag)
464 chipversion = 4;
465
466 for (; cfg->tmdsclock != ~0UL; cfg++)
467 if (tmdsclock <= cfg->tmdsclock &&
468 cfg->version & chipversion)
469 break;
470
471 for (; phy_cfg->tmdsclock != ~0UL; phy_cfg++)
472 if (tmdsclock <= phy_cfg->tmdsclock)
473 break;
474
475 if (cfg->tmdsclock == ~0UL || phy_cfg->tmdsclock == ~0UL)
476 return -EINVAL;
477
478 dev_dbg(inno->dev, "Inno HDMI PHY Power On\n");
479 inno_hdmi_phy_clk_set_rate(&inno->hw, inno->pixclock, 0);
480
481 if (inno->plat_data->ops->power_on)
482 return inno->plat_data->ops->power_on(inno, cfg, phy_cfg);
483 else
484 return -EINVAL;
485 }
486
inno_hdmi_phy_power_off(struct phy * phy)487 static int inno_hdmi_phy_power_off(struct phy *phy)
488 {
489 struct inno_hdmi_phy *inno = phy_get_drvdata(phy);
490
491 if (inno->plat_data->ops->power_off)
492 inno->plat_data->ops->power_off(inno);
493
494 inno->tmdsclock = 0;
495 dev_dbg(inno->dev, "Inno HDMI PHY Power Off\n");
496
497 return 0;
498 }
499
500 static const struct phy_ops inno_hdmi_phy_ops = {
501 .owner = THIS_MODULE,
502 .power_on = inno_hdmi_phy_power_on,
503 .power_off = inno_hdmi_phy_power_off,
504 };
505
inno_hdmi_phy_clk_is_prepared(struct clk_hw * hw)506 static int inno_hdmi_phy_clk_is_prepared(struct clk_hw *hw)
507 {
508 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
509 u8 status;
510
511 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228)
512 status = inno_read(inno, 0xe0) & PRE_PLL_POWER_MASK;
513 else
514 status = inno_read(inno, 0xa0) & 1;
515
516 return status ? 0 : 1;
517 }
518
inno_hdmi_phy_clk_prepare(struct clk_hw * hw)519 static int inno_hdmi_phy_clk_prepare(struct clk_hw *hw)
520 {
521 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
522
523 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228)
524 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK,
525 PRE_PLL_POWER_UP);
526 else
527 inno_update_bits(inno, 0xa0, 1, 0);
528
529 return 0;
530 }
531
inno_hdmi_phy_clk_unprepare(struct clk_hw * hw)532 static void inno_hdmi_phy_clk_unprepare(struct clk_hw *hw)
533 {
534 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
535
536 if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228)
537 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK,
538 PRE_PLL_POWER_DOWN);
539 else
540 inno_update_bits(inno, 0xa0, 1, 1);
541 }
542
inno_hdmi_phy_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)543 static unsigned long inno_hdmi_phy_clk_recalc_rate(struct clk_hw *hw,
544 unsigned long parent_rate)
545 {
546 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
547
548 if (inno->plat_data->ops->recalc_rate)
549 return inno->plat_data->ops->recalc_rate(inno, parent_rate);
550 else
551 return inno->pixclock;
552 }
553
inno_hdmi_phy_clk_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)554 static long inno_hdmi_phy_clk_round_rate(struct clk_hw *hw, unsigned long rate,
555 unsigned long *parent_rate)
556 {
557 int i;
558 const struct pre_pll_config *cfg = pre_pll_cfg_table;
559 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
560 u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate);
561
562 for (; cfg->pixclock != ~0UL; cfg++)
563 if (cfg->pixclock == rate)
564 break;
565
566 /* XXX: Limit pixel clock under 600MHz */
567 if (cfg->pixclock > 600000000)
568 return -EINVAL;
569
570 /*
571 * If there is no dts phy cfg table, use default phy cfg table.
572 * The tmds clock maximum is 594MHz. So there is no need to check
573 * whether tmds clock is out of range.
574 */
575 if (!inno->phy_cfg)
576 return cfg->pixclock;
577
578 /* Check if tmds clock is out of dts phy config's range. */
579 for (i = 0; inno->phy_cfg[i].tmdsclock != ~0UL; i++) {
580 if (inno->phy_cfg[i].tmdsclock >= tmdsclock)
581 break;
582 }
583
584 if (inno->phy_cfg[i].tmdsclock == ~0UL)
585 return -EINVAL;
586
587 return cfg->pixclock;
588 }
589
inno_hdmi_phy_clk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)590 static int inno_hdmi_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate,
591 unsigned long parent_rate)
592 {
593 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
594 const struct pre_pll_config *cfg = pre_pll_cfg_table;
595 u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate);
596
597 dev_dbg(inno->dev, "%s rate %lu tmdsclk %u\n",
598 __func__, rate, tmdsclock);
599
600 if (inno->tmdsclock == tmdsclock)
601 return 0;
602
603 for (; cfg->pixclock != ~0UL; cfg++)
604 if (cfg->pixclock == rate && cfg->tmdsclock == tmdsclock)
605 break;
606
607 if (cfg->pixclock == ~0UL) {
608 dev_err(inno->dev, "unsupported rate %lu\n", rate);
609 return -EINVAL;
610 }
611
612 if (inno->plat_data->ops->pre_pll_update)
613 inno->plat_data->ops->pre_pll_update(inno, cfg);
614
615 inno->pixclock = rate;
616 inno->tmdsclock = tmdsclock;
617
618 return 0;
619 }
620
621 static const struct clk_ops inno_hdmi_phy_clk_ops = {
622 .prepare = inno_hdmi_phy_clk_prepare,
623 .unprepare = inno_hdmi_phy_clk_unprepare,
624 .is_prepared = inno_hdmi_phy_clk_is_prepared,
625 .recalc_rate = inno_hdmi_phy_clk_recalc_rate,
626 .round_rate = inno_hdmi_phy_clk_round_rate,
627 .set_rate = inno_hdmi_phy_clk_set_rate,
628 };
629
inno_hdmi_phy_clk_register(struct inno_hdmi_phy * inno)630 static int inno_hdmi_phy_clk_register(struct inno_hdmi_phy *inno)
631 {
632 struct device *dev = inno->dev;
633 struct device_node *np = dev->of_node;
634 struct clk_init_data init = {};
635 struct clk *refclk;
636 const char *parent_name;
637 int ret;
638
639 refclk = devm_clk_get(dev, "refclk");
640 if (IS_ERR(refclk)) {
641 dev_err(dev, "failed to get ref clock\n");
642 return PTR_ERR(refclk);
643 }
644
645 parent_name = __clk_get_name(refclk);
646
647 init.parent_names = &parent_name;
648 init.num_parents = 1;
649 init.flags = 0;
650 init.name = "pin_hd20_pclk";
651 init.ops = &inno_hdmi_phy_clk_ops;
652
653 /* optional override of the clock name */
654 of_property_read_string(np, "clock-output-names", &init.name);
655
656 inno->hw.init = &init;
657
658 inno->pclk = devm_clk_register(dev, &inno->hw);
659 if (IS_ERR(inno->pclk)) {
660 ret = PTR_ERR(inno->pclk);
661 dev_err(dev, "failed to register clock: %d\n", ret);
662 return ret;
663 }
664
665 ret = of_clk_add_provider(np, of_clk_src_simple_get, inno->pclk);
666 if (ret) {
667 dev_err(dev, "failed to register OF clock provider: %d\n", ret);
668 return ret;
669 }
670
671 return 0;
672 }
673
674 static int
inno_hdmi_phy_rk3228_power_on(struct inno_hdmi_phy * inno,const struct post_pll_config * cfg,const struct phy_config * phy_cfg)675 inno_hdmi_phy_rk3228_power_on(struct inno_hdmi_phy *inno,
676 const struct post_pll_config *cfg,
677 const struct phy_config *phy_cfg)
678 {
679 int pll_tries;
680 u32 m, v;
681
682 /* pdata_en disable */
683 inno_update_bits(inno, 0x02, PDATAEN_MASK, PDATAEN_DISABLE);
684
685 /* Power down Post-PLL */
686 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_DOWN);
687 inno_update_bits(inno, 0xe0, POST_PLL_POWER_MASK, POST_PLL_POWER_DOWN);
688
689 /* Post-PLL update */
690 m = POST_PLL_PRE_DIV_MASK;
691 v = POST_PLL_PRE_DIV(cfg->prediv);
692 inno_update_bits(inno, 0xe9, m, v);
693
694 m = POST_PLL_FB_DIV_8_MASK;
695 v = POST_PLL_FB_DIV_8(cfg->fbdiv >> 8);
696 inno_update_bits(inno, 0xeb, m, v);
697 inno_write(inno, 0xea, POST_PLL_FB_DIV_7_0(cfg->fbdiv));
698
699 if (cfg->postdiv == 1) {
700 /* Disable Post-PLL post divider */
701 m = POST_PLL_POST_DIV_EN_MASK;
702 v = POST_PLL_POST_DIV_DISABLE;
703 inno_update_bits(inno, 0xe9, m, v);
704 } else {
705 /* Enable Post-PLL post divider */
706 m = POST_PLL_POST_DIV_EN_MASK;
707 v = POST_PLL_POST_DIV_ENABLE;
708 inno_update_bits(inno, 0xe9, m, v);
709
710 m = POST_PLL_POST_DIV_MASK;
711 v = POST_PLL_POST_DIV(cfg->postdiv / 2 - 1);
712 inno_update_bits(inno, 0xeb, m, v);
713 }
714
715 for (v = 0; v < 4; v++)
716 inno_write(inno, 0xef + v, phy_cfg->regs[v]);
717
718 /* Power up Post-PLL */
719 inno_update_bits(inno, 0xe0, POST_PLL_POWER_MASK, POST_PLL_POWER_UP);
720 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_UP);
721
722 /* BandGap enable */
723 inno_update_bits(inno, 0xe1, BANDGAP_MASK, BANDGAP_ENABLE);
724
725 /* TMDS driver enable */
726 inno_update_bits(inno, 0xe1, TMDS_DRIVER_MASK, TMDS_DRIVER_ENABLE);
727
728 /* Wait for post PLL lock */
729 pll_tries = 0;
730 while (!(inno_read(inno, 0xeb) & POST_PLL_LOCK_STATUS)) {
731 if (pll_tries == INNO_HDMI_PHY_TIMEOUT_LOOP_COUNT) {
732 dev_err(inno->dev, "Post-PLL unlock\n");
733 return -ETIMEDOUT;
734 }
735
736 pll_tries++;
737 usleep_range(100, 110);
738 }
739
740 if (cfg->tmdsclock > 340000000)
741 msleep(100);
742
743 /* pdata_en enable */
744 inno_update_bits(inno, 0x02, PDATAEN_MASK, PDATAEN_ENABLE);
745 return 0;
746 }
747
inno_hdmi_phy_rk3228_power_off(struct inno_hdmi_phy * inno)748 static void inno_hdmi_phy_rk3228_power_off(struct inno_hdmi_phy *inno)
749 {
750 /* TMDS driver Disable */
751 inno_update_bits(inno, 0xe1, TMDS_DRIVER_MASK, TMDS_DRIVER_DISABLE);
752
753 /* BandGap Disable */
754 inno_update_bits(inno, 0xe1, BANDGAP_MASK, BANDGAP_DISABLE);
755
756 /* Post-PLL power down */
757 inno_update_bits(inno, 0xe0, POST_PLL_POWER_MASK, POST_PLL_POWER_DOWN);
758 }
759
inno_hdmi_phy_rk3228_init(struct inno_hdmi_phy * inno)760 static void inno_hdmi_phy_rk3228_init(struct inno_hdmi_phy *inno)
761 {
762 u32 m, v;
763 struct nvmem_cell *cell;
764 unsigned char *efuse_buf;
765 size_t len;
766
767 /*
768 * Use phy internal register control
769 * rxsense/poweron/pllpd/pdataen signal.
770 */
771 m = BYPASS_RXSENSE_EN_MASK | BYPASS_PWRON_EN_MASK |
772 BYPASS_PLLPD_EN_MASK;
773 v = BYPASS_RXSENSE_EN | BYPASS_PWRON_EN | BYPASS_PLLPD_EN;
774 inno_update_bits(inno, 0x01, m, v);
775 inno_update_bits(inno, 0x02, BYPASS_PDATA_EN_MASK, BYPASS_PDATA_EN);
776
777 /*
778 * reg0xe9 default value is 0xe4, reg0xea is 0x50.
779 * if phy had been set in uboot, one of them will be different.
780 */
781 if ((inno_read(inno, 0xe9) != 0xe4 || inno_read(inno, 0xea) != 0x50)) {
782 dev_info(inno->dev, "phy had been powered up\n");
783 inno->phy->power_count = 1;
784 } else {
785 inno_hdmi_phy_rk3228_power_off(inno);
786 /* manual power down post-PLL */
787 inno_update_bits(inno, 0xaa,
788 POST_PLL_CTRL_MASK, POST_PLL_CTRL_MANUAL);
789 }
790
791 cell = nvmem_cell_get(inno->dev, "hdmi_phy_flag");
792 if (IS_ERR(cell)) {
793 dev_err(inno->dev,
794 "failed to get id cell: %ld\n", PTR_ERR(cell));
795 return;
796 }
797 efuse_buf = nvmem_cell_read(cell, &len);
798 nvmem_cell_put(cell);
799 if (len == 1)
800 inno->efuse_flag = efuse_buf[0] ? true : false;
801 kfree(efuse_buf);
802 }
803
804 static int
inno_hdmi_phy_rk3228_pre_pll_update(struct inno_hdmi_phy * inno,const struct pre_pll_config * cfg)805 inno_hdmi_phy_rk3228_pre_pll_update(struct inno_hdmi_phy *inno,
806 const struct pre_pll_config *cfg)
807 {
808 int pll_tries;
809 u32 m, v;
810
811 /* Power down PRE-PLL */
812 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_DOWN);
813
814 m = PRE_PLL_FB_DIV_8_MASK | PCLK_VCO_DIV_5_MASK | PRE_PLL_PRE_DIV_MASK;
815 v = PRE_PLL_FB_DIV_8(cfg->fbdiv >> 8) |
816 PCLK_VCO_DIV_5(cfg->vco_div_5_en) | PRE_PLL_PRE_DIV(cfg->prediv);
817 inno_update_bits(inno, 0xe2, m, v);
818
819 inno_write(inno, 0xe3, PRE_PLL_FB_DIV_7_0(cfg->fbdiv));
820
821 m = PRE_PLL_PCLK_DIV_B_MASK | PRE_PLL_PCLK_DIV_A_MASK;
822 v = PRE_PLL_PCLK_DIV_B(cfg->pclk_div_b) |
823 PRE_PLL_PCLK_DIV_A(cfg->pclk_div_a);
824 inno_update_bits(inno, 0xe4, m, v);
825
826 m = PRE_PLL_PCLK_DIV_C_MASK | PRE_PLL_PCLK_DIV_D_MASK;
827 v = PRE_PLL_PCLK_DIV_C(cfg->pclk_div_c) |
828 PRE_PLL_PCLK_DIV_D(cfg->pclk_div_d);
829 inno_update_bits(inno, 0xe5, m, v);
830
831 m = PRE_PLL_TMDSCLK_DIV_C_MASK | PRE_PLL_TMDSCLK_DIV_A_MASK |
832 PRE_PLL_TMDSCLK_DIV_B_MASK;
833 v = PRE_PLL_TMDSCLK_DIV_C(cfg->tmds_div_c) |
834 PRE_PLL_TMDSCLK_DIV_A(cfg->tmds_div_a) |
835 PRE_PLL_TMDSCLK_DIV_B(cfg->tmds_div_b);
836 inno_update_bits(inno, 0xe6, m, v);
837
838 /* Power up PRE-PLL */
839 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_UP);
840
841 /* Wait for Pre-PLL lock */
842 pll_tries = 0;
843 while (!(inno_read(inno, 0xe8) & PRE_PLL_LOCK_STATUS)) {
844 if (pll_tries == INNO_HDMI_PHY_TIMEOUT_LOOP_COUNT) {
845 dev_err(inno->dev, "Pre-PLL unlock\n");
846 return -ETIMEDOUT;
847 }
848
849 pll_tries++;
850 usleep_range(100, 110);
851 }
852
853 return 0;
854 }
855
856 static int
inno_hdmi_phy_rk3328_power_on(struct inno_hdmi_phy * inno,const struct post_pll_config * cfg,const struct phy_config * phy_cfg)857 inno_hdmi_phy_rk3328_power_on(struct inno_hdmi_phy *inno,
858 const struct post_pll_config *cfg,
859 const struct phy_config *phy_cfg)
860 {
861 u32 val;
862 u64 temp;
863
864 /* set pdata_en to 0 */
865 inno_update_bits(inno, 0x02, 1, 0);
866 /* Power off post PLL */
867 inno_update_bits(inno, 0xaa, 1, 1);
868
869 val = cfg->fbdiv & 0xff;
870 inno_write(inno, 0xac, val);
871 if (cfg->postdiv == 1) {
872 inno_write(inno, 0xaa, 2);
873 val = (cfg->fbdiv >> 8) | cfg->prediv;
874 inno_write(inno, 0xab, val);
875 } else {
876 val = (cfg->postdiv / 2) - 1;
877 inno_write(inno, 0xad, val);
878 val = (cfg->fbdiv >> 8) | cfg->prediv;
879 inno_write(inno, 0xab, val);
880 inno_write(inno, 0xaa, 0x0e);
881 }
882
883 for (val = 0; val < 14; val++)
884 inno_write(inno, 0xb5 + val, phy_cfg->regs[val]);
885
886 /* bit[7:6] of reg c8/c9/ca/c8 is ESD detect threshold:
887 * 00 - 340mV
888 * 01 - 280mV
889 * 10 - 260mV
890 * 11 - 240mV
891 * default is 240mV, now we set it to 340mV
892 */
893 inno_write(inno, 0xc8, 0);
894 inno_write(inno, 0xc9, 0);
895 inno_write(inno, 0xca, 0);
896 inno_write(inno, 0xcb, 0);
897
898 if (phy_cfg->tmdsclock > 340000000) {
899 /* Set termination resistor to 100ohm */
900 val = clk_get_rate(inno->sysclk) / 100000;
901 inno_write(inno, 0xc5, ((val >> 8) & 0xff) | 0x80);
902 inno_write(inno, 0xc6, val & 0xff);
903 inno_write(inno, 0xc7, 3 << 1);
904 inno_write(inno, 0xc5, ((val >> 8) & 0xff));
905 } else {
906 inno_write(inno, 0xc5, 0x81);
907 /* clk termination resistor is 50ohm */
908 if (phy_cfg->tmdsclock > 165000000)
909 inno_write(inno, 0xc8, 0x30);
910 /* data termination resistor is 150ohm */
911 inno_write(inno, 0xc9, 0x10);
912 inno_write(inno, 0xca, 0x10);
913 inno_write(inno, 0xcb, 0x10);
914 }
915
916 /* set TMDS sync detection counter length */
917 temp = 47520000000;
918 do_div(temp, inno->tmdsclock);
919 inno_write(inno, 0xd8, (temp >> 8) & 0xff);
920 inno_write(inno, 0xd9, temp & 0xff);
921
922 /* Power up post PLL */
923 inno_update_bits(inno, 0xaa, 1, 0);
924 /* Power up tmds driver */
925 inno_update_bits(inno, 0xb0, 4, 4);
926 inno_write(inno, 0xb2, 0x0f);
927
928 /* Wait for post PLL lock */
929 for (val = 0; val < 5; val++) {
930 if (inno_read(inno, 0xaf) & 1)
931 break;
932 usleep_range(1000, 2000);
933 }
934 if (!(inno_read(inno, 0xaf) & 1)) {
935 dev_err(inno->dev, "HDMI PHY Post PLL unlock\n");
936 return -ETIMEDOUT;
937 }
938 if (phy_cfg->tmdsclock > 340000000)
939 msleep(100);
940 /* set pdata_en to 1 */
941 inno_update_bits(inno, 0x02, 1, 1);
942
943 /* Enable PHY IRQ */
944 inno_write(inno, 0x05, 0x22);
945 inno_write(inno, 0x07, 0x22);
946 return 0;
947 }
948
inno_hdmi_phy_rk3328_power_off(struct inno_hdmi_phy * inno)949 static void inno_hdmi_phy_rk3328_power_off(struct inno_hdmi_phy *inno)
950 {
951 /* Power off driver */
952 inno_write(inno, 0xb2, 0);
953 /* Power off band gap */
954 inno_update_bits(inno, 0xb0, 4, 0);
955 /* Power off post pll */
956 inno_update_bits(inno, 0xaa, 1, 1);
957
958 /* Disable PHY IRQ */
959 inno_write(inno, 0x05, 0);
960 inno_write(inno, 0x07, 0);
961 }
962
inno_hdmi_phy_rk3328_init(struct inno_hdmi_phy * inno)963 static void inno_hdmi_phy_rk3328_init(struct inno_hdmi_phy *inno)
964 {
965 /*
966 * Use phy internal register control
967 * rxsense/poweron/pllpd/pdataen signal.
968 */
969 inno_write(inno, 0x01, 0x07);
970 inno_write(inno, 0x02, 0x91);
971
972 /*
973 * reg0xc8 default value is 0xc0, if phy had been set in uboot,
974 * the value of bit[7:6] will be zero.
975 */
976 if ((inno_read(inno, 0xc8) & 0xc0) == 0) {
977 dev_info(inno->dev, "phy had been powered up\n");
978 inno->phy->power_count = 1;
979 } else {
980 /* manual power down post-PLL */
981 inno_hdmi_phy_rk3328_power_off(inno);
982 }
983 }
984
985 static int
inno_hdmi_phy_rk3328_pre_pll_update(struct inno_hdmi_phy * inno,const struct pre_pll_config * cfg)986 inno_hdmi_phy_rk3328_pre_pll_update(struct inno_hdmi_phy *inno,
987 const struct pre_pll_config *cfg)
988 {
989 u32 val;
990
991 /* Power off PLL */
992 inno_update_bits(inno, 0xa0, 1, 1);
993 /* Configure pre-pll */
994 inno_update_bits(inno, 0xa0, 2, (cfg->vco_div_5_en & 1) << 1);
995 inno_write(inno, 0xa1, cfg->prediv);
996 if (cfg->fracdiv)
997 val = ((cfg->fbdiv >> 8) & 0x0f) | 0xc0;
998 else
999 val = ((cfg->fbdiv >> 8) & 0x0f) | 0xf0;
1000 inno_write(inno, 0xa2, val);
1001 inno_write(inno, 0xa3, cfg->fbdiv & 0xff);
1002 val = (cfg->pclk_div_a & 0x1f) |
1003 ((cfg->pclk_div_b & 3) << 5);
1004 inno_write(inno, 0xa5, val);
1005 val = (cfg->pclk_div_d & 0x1f) |
1006 ((cfg->pclk_div_c & 3) << 5);
1007 inno_write(inno, 0xa6, val);
1008 val = ((cfg->tmds_div_a & 3) << 4) |
1009 ((cfg->tmds_div_b & 3) << 2) |
1010 (cfg->tmds_div_c & 3);
1011 inno_write(inno, 0xa4, val);
1012
1013 if (cfg->fracdiv) {
1014 val = cfg->fracdiv & 0xff;
1015 inno_write(inno, 0xd3, val);
1016 val = (cfg->fracdiv >> 8) & 0xff;
1017 inno_write(inno, 0xd2, val);
1018 val = (cfg->fracdiv >> 16) & 0xff;
1019 inno_write(inno, 0xd1, val);
1020 } else {
1021 inno_write(inno, 0xd3, 0);
1022 inno_write(inno, 0xd2, 0);
1023 inno_write(inno, 0xd1, 0);
1024 }
1025
1026 /* Power up PLL */
1027 inno_update_bits(inno, 0xa0, 1, 0);
1028
1029 /* Wait for PLL lock */
1030 for (val = 0; val < 5; val++) {
1031 if (inno_read(inno, 0xa9) & 1)
1032 break;
1033 usleep_range(1000, 2000);
1034 }
1035 if (val == 5) {
1036 dev_err(inno->dev, "Pre-PLL unlock\n");
1037 return -ETIMEDOUT;
1038 }
1039
1040 return 0;
1041 }
1042
1043 static unsigned long
inno_hdmi_rk3328_phy_pll_recalc_rate(struct inno_hdmi_phy * inno,unsigned long parent_rate)1044 inno_hdmi_rk3328_phy_pll_recalc_rate(struct inno_hdmi_phy *inno,
1045 unsigned long parent_rate)
1046 {
1047 unsigned long frac;
1048 u8 nd, no_a, no_b, no_d;
1049 u16 nf;
1050 u64 vco = parent_rate;
1051
1052 nd = inno_read(inno, 0xa1) & 0x3f;
1053 nf = ((inno_read(inno, 0xa2) & 0x0f) << 8) | inno_read(inno, 0xa3);
1054 vco *= nf;
1055 if ((inno_read(inno, 0xa2) & 0x30) == 0) {
1056 frac = inno_read(inno, 0xd3) |
1057 (inno_read(inno, 0xd2) << 8) |
1058 (inno_read(inno, 0xd1) << 16);
1059 vco += DIV_ROUND_CLOSEST(parent_rate * frac, (1 << 24));
1060 }
1061 if (inno_read(inno, 0xa0) & 2) {
1062 do_div(vco, nd * 5);
1063 } else {
1064 no_a = inno_read(inno, 0xa5) & 0x1f;
1065 no_b = ((inno_read(inno, 0xa5) >> 5) & 7) + 2;
1066 no_d = inno_read(inno, 0xa6) & 0x1f;
1067 if (no_a == 1)
1068 do_div(vco, nd * no_b * no_d * 2);
1069 else
1070 do_div(vco, nd * no_a * no_d * 2);
1071 }
1072
1073 frac = vco;
1074 inno->pixclock = DIV_ROUND_CLOSEST(frac, 1000) * 1000;
1075
1076 dev_dbg(inno->dev, "%s rate %lu\n", __func__, inno->pixclock);
1077
1078 return frac;
1079 }
1080
1081 static unsigned long
inno_hdmi_rk3228_phy_pll_recalc_rate(struct inno_hdmi_phy * inno,unsigned long parent_rate)1082 inno_hdmi_rk3228_phy_pll_recalc_rate(struct inno_hdmi_phy *inno,
1083 unsigned long parent_rate)
1084 {
1085 u8 nd, no_a, no_b, no_d;
1086 u16 nf;
1087 u64 vco = parent_rate;
1088
1089 nd = inno_read(inno, 0xe2) & 0x1f;
1090 nf = ((inno_read(inno, 0xe2) & 0x80) << 1) | inno_read(inno, 0xe3);
1091 vco *= nf;
1092
1093 if ((inno_read(inno, 0xe2) >> 5) & 0x1) {
1094 do_div(vco, nd * 5);
1095 } else {
1096 no_a = inno_read(inno, 0xe4) & 0x1f;
1097 if (!no_a)
1098 no_a = 1;
1099 no_b = ((inno_read(inno, 0xe4) >> 5) & 0x3) + 2;
1100 no_d = inno_read(inno, 0xe5) & 0x1f;
1101
1102 if (no_a == 1)
1103 do_div(vco, nd * no_b * no_d * 2);
1104 else
1105 do_div(vco, nd * no_a * no_d * 2);
1106 }
1107
1108 inno->pixclock = vco;
1109
1110 dev_dbg(inno->dev, "%s rate %lu\n", __func__, inno->pixclock);
1111
1112 return inno->pixclock;
1113 }
1114
1115 static const struct inno_hdmi_phy_ops rk3228_hdmi_phy_ops = {
1116 .init = inno_hdmi_phy_rk3228_init,
1117 .power_on = inno_hdmi_phy_rk3228_power_on,
1118 .power_off = inno_hdmi_phy_rk3228_power_off,
1119 .pre_pll_update = inno_hdmi_phy_rk3228_pre_pll_update,
1120 .recalc_rate = inno_hdmi_rk3228_phy_pll_recalc_rate,
1121 };
1122
1123 static const struct inno_hdmi_phy_ops rk3328_hdmi_phy_ops = {
1124 .init = inno_hdmi_phy_rk3328_init,
1125 .power_on = inno_hdmi_phy_rk3328_power_on,
1126 .power_off = inno_hdmi_phy_rk3328_power_off,
1127 .pre_pll_update = inno_hdmi_phy_rk3328_pre_pll_update,
1128 .recalc_rate = inno_hdmi_rk3328_phy_pll_recalc_rate,
1129 };
1130
1131 static const struct inno_hdmi_phy_drv_data rk3228_hdmi_phy_drv_data = {
1132 .dev_type = INNO_HDMI_PHY_RK3228,
1133 .ops = &rk3228_hdmi_phy_ops,
1134 .phy_cfg_table = rk3228_phy_cfg,
1135 };
1136
1137 static const struct inno_hdmi_phy_drv_data rk3328_hdmi_phy_drv_data = {
1138 .dev_type = INNO_HDMI_PHY_RK3328,
1139 .ops = &rk3328_hdmi_phy_ops,
1140 .phy_cfg_table = rk3328_phy_cfg,
1141 };
1142
1143 static const struct of_device_id inno_hdmi_phy_of_match[] = {
1144 { .compatible = "rockchip,rk3228-hdmi-phy",
1145 .data = &rk3228_hdmi_phy_drv_data
1146 },
1147 { .compatible = "rockchip,rk3328-hdmi-phy",
1148 .data = &rk3328_hdmi_phy_drv_data
1149 },
1150 {}
1151 };
1152 MODULE_DEVICE_TABLE(of, inno_hdmi_phy_of_match);
1153
1154 static const struct regmap_config inno_hdmi_phy_regmap_config = {
1155 .reg_bits = 32,
1156 .val_bits = 32,
1157 .reg_stride = 4,
1158 .max_register = 0x400,
1159 };
1160
1161 static
inno_hdmi_update_phy_table(struct inno_hdmi_phy * inno,u32 * config,struct phy_config * phy_cfg,int phy_table_size)1162 int inno_hdmi_update_phy_table(struct inno_hdmi_phy *inno, u32 *config,
1163 struct phy_config *phy_cfg,
1164 int phy_table_size)
1165 {
1166 int i, j;
1167
1168 for (i = 0; i < phy_table_size; i++) {
1169 phy_cfg[i].tmdsclock =
1170 (unsigned long)config[i * 15];
1171
1172 for (j = 0; j < 14; j++)
1173 phy_cfg[i].regs[j] = (u8)config[i * 15 + 1 + j];
1174 }
1175
1176 /*
1177 * The last set of phy cfg is used to indicate whether
1178 * there is no more phy cfg data.
1179 */
1180 phy_cfg[i].tmdsclock = ~0UL;
1181 for (j = 0; j < 14; j++)
1182 phy_cfg[i].regs[j] = 0;
1183
1184 return 0;
1185 }
1186
1187 #define PHY_TAB_LEN 60
1188
inno_hdmi_phy_probe(struct platform_device * pdev)1189 static int inno_hdmi_phy_probe(struct platform_device *pdev)
1190 {
1191 struct device *dev = &pdev->dev;
1192 struct device_node *np = dev->of_node;
1193 struct inno_hdmi_phy *inno;
1194 const struct of_device_id *match;
1195 struct phy_provider *phy_provider;
1196 struct resource *res;
1197 void __iomem *regs;
1198 u32 *phy_config;
1199 int ret, val, phy_table_size;
1200
1201 inno = devm_kzalloc(dev, sizeof(*inno), GFP_KERNEL);
1202 if (!inno)
1203 return -ENOMEM;
1204
1205 inno->dev = dev;
1206
1207 match = of_match_node(inno_hdmi_phy_of_match, pdev->dev.of_node);
1208 inno->plat_data = (struct inno_hdmi_phy_drv_data *)match->data;
1209 if (!inno->plat_data || !inno->plat_data->ops)
1210 return -EINVAL;
1211
1212 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1213 regs = devm_ioremap_resource(dev, res);
1214 if (IS_ERR(regs))
1215 return PTR_ERR(regs);
1216
1217 inno->sysclk = devm_clk_get(inno->dev, "sysclk");
1218 if (IS_ERR(inno->sysclk)) {
1219 ret = PTR_ERR(inno->sysclk);
1220 dev_err(inno->dev, "Unable to get inno phy sysclk: %d\n", ret);
1221 return ret;
1222 }
1223 ret = clk_prepare_enable(inno->sysclk);
1224 if (ret) {
1225 dev_err(inno->dev, "Cannot enable inno phy sysclk: %d\n", ret);
1226 return ret;
1227 }
1228
1229 inno->regmap = devm_regmap_init_mmio(dev, regs,
1230 &inno_hdmi_phy_regmap_config);
1231 if (IS_ERR(inno->regmap)) {
1232 ret = PTR_ERR(inno->regmap);
1233 dev_err(dev, "failed to init regmap: %d\n", ret);
1234 goto err_regsmap;
1235 }
1236
1237 inno->phy = devm_phy_create(dev, NULL, &inno_hdmi_phy_ops);
1238 if (IS_ERR(inno->phy)) {
1239 dev_err(dev, "failed to create HDMI PHY\n");
1240 ret = PTR_ERR(inno->phy);
1241 goto err_regsmap;
1242 }
1243
1244 if (of_get_property(np, "rockchip,phy-table", &val)) {
1245 if (val % PHY_TAB_LEN || !val) {
1246 dev_err(dev, "Invalid phy cfg table format!\n");
1247 return -EINVAL;
1248 }
1249
1250 phy_config = kmalloc(val, GFP_KERNEL);
1251 if (!phy_config) {
1252 dev_err(dev, "kmalloc phy table failed\n");
1253 return -ENOMEM;
1254 }
1255
1256 phy_table_size = val / PHY_TAB_LEN;
1257 /* Effective phy cfg data and the end of phy cfg table */
1258 inno->phy_cfg = devm_kzalloc(dev, val + PHY_TAB_LEN,
1259 GFP_KERNEL);
1260 if (!inno->phy_cfg) {
1261 kfree(phy_config);
1262 return -ENOMEM;
1263 }
1264 of_property_read_u32_array(np, "rockchip,phy-table",
1265 phy_config, val / sizeof(u32));
1266 ret = inno_hdmi_update_phy_table(inno, phy_config,
1267 inno->phy_cfg,
1268 phy_table_size);
1269 if (ret) {
1270 kfree(phy_config);
1271 return ret;
1272 }
1273 kfree(phy_config);
1274 } else {
1275 dev_dbg(dev, "use default hdmi phy table\n");
1276 }
1277
1278 phy_set_drvdata(inno->phy, inno);
1279 phy_set_bus_width(inno->phy, 8);
1280
1281 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1282 if (IS_ERR(phy_provider)) {
1283 dev_err(dev, "failed to register PHY provider\n");
1284 ret = PTR_ERR(phy_provider);
1285 goto err_regsmap;
1286 }
1287
1288 if (inno->plat_data->ops->init)
1289 inno->plat_data->ops->init(inno);
1290
1291 ret = inno_hdmi_phy_clk_register(inno);
1292 if (ret)
1293 goto err_regsmap;
1294
1295 inno->irq = platform_get_irq(pdev, 0);
1296 if (inno->irq > 0) {
1297 ret = devm_request_threaded_irq(inno->dev, inno->irq,
1298 inno_hdmi_phy_hardirq,
1299 inno_hdmi_phy_irq, IRQF_SHARED,
1300 dev_name(inno->dev), inno);
1301 if (ret)
1302 goto err_irq;
1303 }
1304 platform_set_drvdata(pdev, inno);
1305 return 0;
1306
1307 err_irq:
1308 of_clk_del_provider(pdev->dev.of_node);
1309 err_regsmap:
1310 clk_disable_unprepare(inno->sysclk);
1311 return ret;
1312 }
1313
inno_hdmi_phy_remove(struct platform_device * pdev)1314 static int inno_hdmi_phy_remove(struct platform_device *pdev)
1315 {
1316 struct inno_hdmi_phy *inno = platform_get_drvdata(pdev);
1317
1318 of_clk_del_provider(pdev->dev.of_node);
1319 clk_disable_unprepare(inno->sysclk);
1320 return 0;
1321 }
1322
1323 static struct platform_driver inno_hdmi_phy_driver = {
1324 .probe = inno_hdmi_phy_probe,
1325 .remove = inno_hdmi_phy_remove,
1326 .driver = {
1327 .name = "inno-hdmi-phy",
1328 .of_match_table = of_match_ptr(inno_hdmi_phy_of_match),
1329 },
1330 };
1331
1332 module_platform_driver(inno_hdmi_phy_driver);
1333
1334 MODULE_DESCRIPTION("Innosilion HDMI 2.0 Transmitter PHY Driver");
1335 MODULE_LICENSE("GPL v2");
1336