1 /*
2 * Rockchip USB 3.0 PHY with Innosilicon IP block driver
3 *
4 * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/debugfs.h>
20 #include <linux/gpio/consumer.h>
21 #include <linux/interrupt.h>
22 #include <linux/io.h>
23 #include <linux/kernel.h>
24 #include <linux/mfd/syscon.h>
25 #include <linux/module.h>
26 #include <linux/of.h>
27 #include <linux/of_address.h>
28 #include <linux/of_irq.h>
29 #include <linux/of_platform.h>
30 #include <linux/phy/phy.h>
31 #include <linux/platform_device.h>
32 #include <linux/regmap.h>
33 #include <linux/reset.h>
34 #include <linux/usb/phy.h>
35 #include <linux/uaccess.h>
36
37 #define U3PHY_PORT_NUM 2
38 #define U3PHY_MAX_CLKS 4
39 #define BIT_WRITEABLE_SHIFT 16
40 #define SCHEDULE_DELAY (60 * HZ)
41
42 #define U3PHY_APB_RST BIT(0)
43 #define U3PHY_POR_RST BIT(1)
44 #define U3PHY_MAC_RST BIT(2)
45
46 struct rockchip_u3phy;
47 struct rockchip_u3phy_port;
48
49 enum rockchip_u3phy_type {
50 U3PHY_TYPE_PIPE,
51 U3PHY_TYPE_UTMI,
52 };
53
54 enum rockchip_u3phy_pipe_pwr {
55 PIPE_PWR_P0 = 0,
56 PIPE_PWR_P1 = 1,
57 PIPE_PWR_P2 = 2,
58 PIPE_PWR_P3 = 3,
59 PIPE_PWR_MAX = 4,
60 };
61
62 enum rockchip_u3phy_rest_req {
63 U3_POR_RSTN = 0,
64 U2_POR_RSTN = 1,
65 PIPE_MAC_RSTN = 2,
66 UTMI_MAC_RSTN = 3,
67 PIPE_APB_RSTN = 4,
68 UTMI_APB_RSTN = 5,
69 U3PHY_RESET_MAX = 6,
70 };
71
72 enum rockchip_u3phy_utmi_state {
73 PHY_UTMI_HS_ONLINE = 0,
74 PHY_UTMI_DISCONNECT = 1,
75 PHY_UTMI_CONNECT = 2,
76 PHY_UTMI_FS_LS_ONLINE = 4,
77 };
78
79 /*
80 * @rvalue: reset value
81 * @dvalue: desired value
82 */
83 struct u3phy_reg {
84 unsigned int offset;
85 unsigned int bitend;
86 unsigned int bitstart;
87 unsigned int rvalue;
88 unsigned int dvalue;
89 };
90
91 struct rockchip_u3phy_grfcfg {
92 struct u3phy_reg um_suspend;
93 struct u3phy_reg ls_det_en;
94 struct u3phy_reg ls_det_st;
95 struct u3phy_reg um_ls;
96 struct u3phy_reg um_hstdct;
97 struct u3phy_reg u2_only_ctrl;
98 struct u3phy_reg u3_disable;
99 struct u3phy_reg pp_pwr_st;
100 struct u3phy_reg pp_pwr_en[PIPE_PWR_MAX];
101 };
102
103 /**
104 * struct rockchip_u3phy_apbcfg: usb3-phy apb configuration.
105 * @u2_pre_emp: usb2-phy pre-emphasis tuning.
106 * @u2_pre_emp_sth: usb2-phy pre-emphasis strength tuning.
107 * @u2_odt_tuning: usb2-phy odt 45ohm tuning.
108 */
109 struct rockchip_u3phy_apbcfg {
110 unsigned int u2_pre_emp;
111 unsigned int u2_pre_emp_sth;
112 unsigned int u2_odt_tuning;
113 };
114
115 struct rockchip_u3phy_cfg {
116 unsigned int reg;
117 const struct rockchip_u3phy_grfcfg grfcfg;
118
119 int (*phy_pipe_power)(struct rockchip_u3phy *,
120 struct rockchip_u3phy_port *,
121 bool on);
122 int (*phy_tuning)(struct rockchip_u3phy *,
123 struct rockchip_u3phy_port *,
124 struct device_node *);
125 };
126
127 struct rockchip_u3phy_port {
128 struct phy *phy;
129 void __iomem *base;
130 unsigned int index;
131 unsigned char type;
132 bool suspended;
133 bool refclk_25m_quirk;
134 struct mutex mutex; /* mutex for updating register */
135 struct delayed_work um_sm_work;
136 };
137
138 struct rockchip_u3phy {
139 struct device *dev;
140 struct regmap *u3phy_grf;
141 struct regmap *grf;
142 int um_ls_irq;
143 struct clk *clks[U3PHY_MAX_CLKS];
144 struct dentry *root;
145 struct regulator *vbus;
146 struct reset_control *rsts[U3PHY_RESET_MAX];
147 struct rockchip_u3phy_apbcfg apbcfg;
148 const struct rockchip_u3phy_cfg *cfgs;
149 struct rockchip_u3phy_port ports[U3PHY_PORT_NUM];
150 struct usb_phy usb_phy;
151 bool vbus_enabled;
152 };
153
param_write(void __iomem * base,const struct u3phy_reg * reg,bool desired)154 static inline int param_write(void __iomem *base,
155 const struct u3phy_reg *reg, bool desired)
156 {
157 unsigned int val, mask;
158 unsigned int tmp = desired ? reg->dvalue : reg->rvalue;
159 int ret = 0;
160
161 mask = GENMASK(reg->bitend, reg->bitstart);
162 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
163 ret = regmap_write(base, reg->offset, val);
164
165 return ret;
166 }
167
param_exped(void __iomem * base,const struct u3phy_reg * reg,unsigned int value)168 static inline bool param_exped(void __iomem *base,
169 const struct u3phy_reg *reg,
170 unsigned int value)
171 {
172 int ret;
173 unsigned int tmp, orig;
174 unsigned int mask = GENMASK(reg->bitend, reg->bitstart);
175
176 ret = regmap_read(base, reg->offset, &orig);
177 if (ret)
178 return false;
179
180 tmp = (orig & mask) >> reg->bitstart;
181 return tmp == value;
182 }
183
rockchip_set_vbus_power(struct rockchip_u3phy * u3phy,bool en)184 static int rockchip_set_vbus_power(struct rockchip_u3phy *u3phy, bool en)
185 {
186 int ret = 0;
187
188 if (!u3phy->vbus)
189 return 0;
190
191 if (en && !u3phy->vbus_enabled) {
192 ret = regulator_enable(u3phy->vbus);
193 if (ret)
194 dev_err(u3phy->dev,
195 "Failed to enable VBUS supply\n");
196 } else if (!en && u3phy->vbus_enabled) {
197 ret = regulator_disable(u3phy->vbus);
198 }
199
200 if (ret == 0)
201 u3phy->vbus_enabled = en;
202
203 return ret;
204 }
205
rockchip_u3phy_usb2_only_show(struct seq_file * s,void * unused)206 static int rockchip_u3phy_usb2_only_show(struct seq_file *s, void *unused)
207 {
208 struct rockchip_u3phy *u3phy = s->private;
209
210 if (param_exped(u3phy->u3phy_grf, &u3phy->cfgs->grfcfg.u2_only_ctrl, 1))
211 dev_info(u3phy->dev, "u2\n");
212 else
213 dev_info(u3phy->dev, "u3\n");
214
215 return 0;
216 }
217
rockchip_u3phy_usb2_only_open(struct inode * inode,struct file * file)218 static int rockchip_u3phy_usb2_only_open(struct inode *inode,
219 struct file *file)
220 {
221 return single_open(file, rockchip_u3phy_usb2_only_show,
222 inode->i_private);
223 }
224
rockchip_u3phy_usb2_only_write(struct file * file,const char __user * ubuf,size_t count,loff_t * ppos)225 static ssize_t rockchip_u3phy_usb2_only_write(struct file *file,
226 const char __user *ubuf,
227 size_t count, loff_t *ppos)
228 {
229 struct seq_file *s = file->private_data;
230 struct rockchip_u3phy *u3phy = s->private;
231 struct rockchip_u3phy_port *u3phy_port;
232 char buf[32];
233 u8 index;
234
235 if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count)))
236 return -EFAULT;
237
238 if (!strncmp(buf, "u3", 2) &&
239 param_exped(u3phy->u3phy_grf,
240 &u3phy->cfgs->grfcfg.u2_only_ctrl, 1)) {
241 dev_info(u3phy->dev, "Set usb3.0 and usb2.0 mode successfully\n");
242
243 rockchip_set_vbus_power(u3phy, false);
244
245 param_write(u3phy->grf,
246 &u3phy->cfgs->grfcfg.u3_disable, false);
247 param_write(u3phy->u3phy_grf,
248 &u3phy->cfgs->grfcfg.u2_only_ctrl, false);
249
250 for (index = 0; index < U3PHY_PORT_NUM; index++) {
251 u3phy_port = &u3phy->ports[index];
252 /* enable u3 rx termimation */
253 if (u3phy_port->type == U3PHY_TYPE_PIPE)
254 writel(0x30, u3phy_port->base + 0xd8);
255 }
256
257 atomic_notifier_call_chain(&u3phy->usb_phy.notifier, 0, NULL);
258
259 rockchip_set_vbus_power(u3phy, true);
260 } else if (!strncmp(buf, "u2", 2) &&
261 param_exped(u3phy->u3phy_grf,
262 &u3phy->cfgs->grfcfg.u2_only_ctrl, 0)) {
263 dev_info(u3phy->dev, "Set usb2.0 only mode successfully\n");
264
265 rockchip_set_vbus_power(u3phy, false);
266
267 param_write(u3phy->grf,
268 &u3phy->cfgs->grfcfg.u3_disable, true);
269 param_write(u3phy->u3phy_grf,
270 &u3phy->cfgs->grfcfg.u2_only_ctrl, true);
271
272 for (index = 0; index < U3PHY_PORT_NUM; index++) {
273 u3phy_port = &u3phy->ports[index];
274 /* disable u3 rx termimation */
275 if (u3phy_port->type == U3PHY_TYPE_PIPE)
276 writel(0x20, u3phy_port->base + 0xd8);
277 }
278
279 atomic_notifier_call_chain(&u3phy->usb_phy.notifier, 0, NULL);
280
281 rockchip_set_vbus_power(u3phy, true);
282 } else {
283 dev_info(u3phy->dev, "Same or illegal mode\n");
284 }
285
286 return count;
287 }
288
289 static const struct file_operations rockchip_u3phy_usb2_only_fops = {
290 .open = rockchip_u3phy_usb2_only_open,
291 .write = rockchip_u3phy_usb2_only_write,
292 .read = seq_read,
293 .llseek = seq_lseek,
294 .release = single_release,
295 };
296
rockchip_u3phy_debugfs_init(struct rockchip_u3phy * u3phy)297 int rockchip_u3phy_debugfs_init(struct rockchip_u3phy *u3phy)
298 {
299 struct dentry *root;
300 struct dentry *file;
301 int ret;
302
303 root = debugfs_create_dir(dev_name(u3phy->dev), NULL);
304 if (!root) {
305 ret = -ENOMEM;
306 goto err0;
307 }
308
309 u3phy->root = root;
310
311 file = debugfs_create_file("u3phy_mode", 0644, root,
312 u3phy, &rockchip_u3phy_usb2_only_fops);
313 if (!file) {
314 ret = -ENOMEM;
315 goto err1;
316 }
317 return 0;
318
319 err1:
320 debugfs_remove_recursive(root);
321 err0:
322 return ret;
323 }
324
get_rest_name(enum rockchip_u3phy_rest_req rst)325 static const char *get_rest_name(enum rockchip_u3phy_rest_req rst)
326 {
327 switch (rst) {
328 case U2_POR_RSTN:
329 return "u3phy-u2-por";
330 case U3_POR_RSTN:
331 return "u3phy-u3-por";
332 case PIPE_MAC_RSTN:
333 return "u3phy-pipe-mac";
334 case UTMI_MAC_RSTN:
335 return "u3phy-utmi-mac";
336 case UTMI_APB_RSTN:
337 return "u3phy-utmi-apb";
338 case PIPE_APB_RSTN:
339 return "u3phy-pipe-apb";
340 default:
341 return "invalid";
342 }
343 }
344
rockchip_u3phy_rest_deassert(struct rockchip_u3phy * u3phy,unsigned int flag)345 static void rockchip_u3phy_rest_deassert(struct rockchip_u3phy *u3phy,
346 unsigned int flag)
347 {
348 int rst;
349
350 if (flag & U3PHY_APB_RST) {
351 dev_dbg(u3phy->dev, "deassert APB bus interface reset\n");
352 for (rst = PIPE_APB_RSTN; rst <= UTMI_APB_RSTN; rst++) {
353 if (u3phy->rsts[rst])
354 reset_control_deassert(u3phy->rsts[rst]);
355 }
356 }
357
358 if (flag & U3PHY_POR_RST) {
359 usleep_range(12, 15);
360 dev_dbg(u3phy->dev, "deassert u2 and u3 phy power on reset\n");
361 for (rst = U3_POR_RSTN; rst <= U2_POR_RSTN; rst++) {
362 if (u3phy->rsts[rst])
363 reset_control_deassert(u3phy->rsts[rst]);
364 }
365 }
366
367 if (flag & U3PHY_MAC_RST) {
368 usleep_range(1200, 1500);
369 dev_dbg(u3phy->dev, "deassert pipe and utmi MAC reset\n");
370 for (rst = PIPE_MAC_RSTN; rst <= UTMI_MAC_RSTN; rst++)
371 if (u3phy->rsts[rst])
372 reset_control_deassert(u3phy->rsts[rst]);
373 }
374 }
375
rockchip_u3phy_rest_assert(struct rockchip_u3phy * u3phy)376 static void rockchip_u3phy_rest_assert(struct rockchip_u3phy *u3phy)
377 {
378 int rst;
379
380 dev_dbg(u3phy->dev, "assert u3phy reset\n");
381 for (rst = 0; rst < U3PHY_RESET_MAX; rst++)
382 if (u3phy->rsts[rst])
383 reset_control_assert(u3phy->rsts[rst]);
384 }
385
rockchip_u3phy_clk_enable(struct rockchip_u3phy * u3phy)386 static int rockchip_u3phy_clk_enable(struct rockchip_u3phy *u3phy)
387 {
388 int ret, clk;
389
390 for (clk = 0; clk < U3PHY_MAX_CLKS && u3phy->clks[clk]; clk++) {
391 ret = clk_prepare_enable(u3phy->clks[clk]);
392 if (ret)
393 goto err_disable_clks;
394 }
395 return 0;
396
397 err_disable_clks:
398 while (--clk >= 0)
399 clk_disable_unprepare(u3phy->clks[clk]);
400 return ret;
401 }
402
rockchip_u3phy_clk_disable(struct rockchip_u3phy * u3phy)403 static void rockchip_u3phy_clk_disable(struct rockchip_u3phy *u3phy)
404 {
405 int clk;
406
407 for (clk = U3PHY_MAX_CLKS - 1; clk >= 0; clk--)
408 if (u3phy->clks[clk])
409 clk_disable_unprepare(u3phy->clks[clk]);
410 }
411
rockchip_u3phy_init(struct phy * phy)412 static int rockchip_u3phy_init(struct phy *phy)
413 {
414 return 0;
415 }
416
rockchip_u3phy_exit(struct phy * phy)417 static int rockchip_u3phy_exit(struct phy *phy)
418 {
419 return 0;
420 }
421
rockchip_u3phy_power_on(struct phy * phy)422 static int rockchip_u3phy_power_on(struct phy *phy)
423 {
424 struct rockchip_u3phy_port *u3phy_port = phy_get_drvdata(phy);
425 struct rockchip_u3phy *u3phy = dev_get_drvdata(phy->dev.parent);
426 int ret;
427
428 dev_info(&u3phy_port->phy->dev, "u3phy %s power on\n",
429 (u3phy_port->type == U3PHY_TYPE_UTMI) ? "u2" : "u3");
430
431 if (!u3phy_port->suspended)
432 return 0;
433
434 ret = rockchip_u3phy_clk_enable(u3phy);
435 if (ret)
436 return ret;
437
438 if (u3phy_port->type == U3PHY_TYPE_UTMI) {
439 param_write(u3phy->u3phy_grf,
440 &u3phy->cfgs->grfcfg.um_suspend, false);
441 } else {
442 /* current in p2 ? */
443 if (param_exped(u3phy->u3phy_grf,
444 &u3phy->cfgs->grfcfg.pp_pwr_st, PIPE_PWR_P2))
445 goto done;
446
447 if (u3phy->cfgs->phy_pipe_power) {
448 dev_dbg(u3phy->dev, "do pipe power up\n");
449 u3phy->cfgs->phy_pipe_power(u3phy, u3phy_port, true);
450 }
451
452 /* exit to p0 */
453 param_write(u3phy->u3phy_grf,
454 &u3phy->cfgs->grfcfg.pp_pwr_en[PIPE_PWR_P0], true);
455 usleep_range(90, 100);
456
457 /* enter to p2 from p0 */
458 param_write(u3phy->u3phy_grf,
459 &u3phy->cfgs->grfcfg.pp_pwr_en[PIPE_PWR_P2],
460 false);
461 udelay(3);
462 }
463
464 done:
465 rockchip_set_vbus_power(u3phy, true);
466 u3phy_port->suspended = false;
467 return 0;
468 }
469
rockchip_u3phy_power_off(struct phy * phy)470 static int rockchip_u3phy_power_off(struct phy *phy)
471 {
472 struct rockchip_u3phy_port *u3phy_port = phy_get_drvdata(phy);
473 struct rockchip_u3phy *u3phy = dev_get_drvdata(phy->dev.parent);
474
475 dev_info(&u3phy_port->phy->dev, "u3phy %s power off\n",
476 (u3phy_port->type == U3PHY_TYPE_UTMI) ? "u2" : "u3");
477
478 if (u3phy_port->suspended)
479 return 0;
480
481 if (u3phy_port->type == U3PHY_TYPE_UTMI) {
482 param_write(u3phy->u3phy_grf,
483 &u3phy->cfgs->grfcfg.um_suspend, true);
484 } else {
485 /* current in p3 ? */
486 if (param_exped(u3phy->u3phy_grf,
487 &u3phy->cfgs->grfcfg.pp_pwr_st, PIPE_PWR_P3))
488 goto done;
489
490 /* exit to p0 */
491 param_write(u3phy->u3phy_grf,
492 &u3phy->cfgs->grfcfg.pp_pwr_en[PIPE_PWR_P0], true);
493 udelay(2);
494
495 /* enter to p3 from p0 */
496 param_write(u3phy->u3phy_grf,
497 &u3phy->cfgs->grfcfg.pp_pwr_en[PIPE_PWR_P3], true);
498 udelay(6);
499
500 if (u3phy->cfgs->phy_pipe_power) {
501 dev_dbg(u3phy->dev, "do pipe power down\n");
502 u3phy->cfgs->phy_pipe_power(u3phy, u3phy_port, false);
503 }
504 }
505
506 done:
507 rockchip_u3phy_clk_disable(u3phy);
508 u3phy_port->suspended = true;
509 return 0;
510 }
511
512 static __maybe_unused
rockchip_u3phy_xlate(struct device * dev,struct of_phandle_args * args)513 struct phy *rockchip_u3phy_xlate(struct device *dev,
514 struct of_phandle_args *args)
515 {
516 struct rockchip_u3phy *u3phy = dev_get_drvdata(dev);
517 struct rockchip_u3phy_port *u3phy_port = NULL;
518 struct device_node *phy_np = args->np;
519 int index;
520
521 if (args->args_count != 1) {
522 dev_err(dev, "invalid number of cells in 'phy' property\n");
523 return ERR_PTR(-EINVAL);
524 }
525
526 for (index = 0; index < U3PHY_PORT_NUM; index++) {
527 if (phy_np == u3phy->ports[index].phy->dev.of_node) {
528 u3phy_port = &u3phy->ports[index];
529 break;
530 }
531 }
532
533 if (!u3phy_port) {
534 dev_err(dev, "failed to find appropriate phy\n");
535 return ERR_PTR(-EINVAL);
536 }
537
538 return u3phy_port->phy;
539 }
540
541 static struct phy_ops rockchip_u3phy_ops = {
542 .init = rockchip_u3phy_init,
543 .exit = rockchip_u3phy_exit,
544 .power_on = rockchip_u3phy_power_on,
545 .power_off = rockchip_u3phy_power_off,
546 .owner = THIS_MODULE,
547 };
548
549 /*
550 * The function manage host-phy port state and suspend/resume phy port
551 * to save power automatically.
552 *
553 * we rely on utmi_linestate and utmi_hostdisconnect to identify whether
554 * devices is disconnect or not. Besides, we do not need care it is FS/LS
555 * disconnected or HS disconnected, actually, we just only need get the
556 * device is disconnected at last through rearm the delayed work,
557 * to suspend the phy port in _PHY_STATE_DISCONNECT_ case.
558 */
rockchip_u3phy_um_sm_work(struct work_struct * work)559 static void rockchip_u3phy_um_sm_work(struct work_struct *work)
560 {
561 struct rockchip_u3phy_port *u3phy_port =
562 container_of(work, struct rockchip_u3phy_port, um_sm_work.work);
563 struct rockchip_u3phy *u3phy =
564 dev_get_drvdata(u3phy_port->phy->dev.parent);
565 unsigned int sh = u3phy->cfgs->grfcfg.um_hstdct.bitend -
566 u3phy->cfgs->grfcfg.um_hstdct.bitstart + 1;
567 unsigned int ul, uhd, state;
568 unsigned int ul_mask, uhd_mask;
569 int ret;
570
571 mutex_lock(&u3phy_port->mutex);
572
573 ret = regmap_read(u3phy->u3phy_grf,
574 u3phy->cfgs->grfcfg.um_ls.offset, &ul);
575 if (ret < 0)
576 goto next_schedule;
577
578 ret = regmap_read(u3phy->u3phy_grf,
579 u3phy->cfgs->grfcfg.um_hstdct.offset, &uhd);
580 if (ret < 0)
581 goto next_schedule;
582
583 uhd_mask = GENMASK(u3phy->cfgs->grfcfg.um_hstdct.bitend,
584 u3phy->cfgs->grfcfg.um_hstdct.bitstart);
585 ul_mask = GENMASK(u3phy->cfgs->grfcfg.um_ls.bitend,
586 u3phy->cfgs->grfcfg.um_ls.bitstart);
587
588 /* stitch on um_ls and um_hstdct as phy state */
589 state = ((uhd & uhd_mask) >> u3phy->cfgs->grfcfg.um_hstdct.bitstart) |
590 (((ul & ul_mask) >> u3phy->cfgs->grfcfg.um_ls.bitstart) << sh);
591
592 switch (state) {
593 case PHY_UTMI_HS_ONLINE:
594 dev_dbg(&u3phy_port->phy->dev, "HS online\n");
595 break;
596 case PHY_UTMI_FS_LS_ONLINE:
597 /*
598 * For FS/LS device, the online state share with connect state
599 * from um_ls and um_hstdct register, so we distinguish
600 * them via suspended flag.
601 *
602 * Plus, there are two cases, one is D- Line pull-up, and D+
603 * line pull-down, the state is 4; another is D+ line pull-up,
604 * and D- line pull-down, the state is 2.
605 */
606 if (!u3phy_port->suspended) {
607 /* D- line pull-up, D+ line pull-down */
608 dev_dbg(&u3phy_port->phy->dev, "FS/LS online\n");
609 break;
610 }
611 /* fall through */
612 case PHY_UTMI_CONNECT:
613 if (u3phy_port->suspended) {
614 dev_dbg(&u3phy_port->phy->dev, "Connected\n");
615 rockchip_u3phy_power_on(u3phy_port->phy);
616 u3phy_port->suspended = false;
617 } else {
618 /* D+ line pull-up, D- line pull-down */
619 dev_dbg(&u3phy_port->phy->dev, "FS/LS online\n");
620 }
621 break;
622 case PHY_UTMI_DISCONNECT:
623 if (!u3phy_port->suspended) {
624 dev_dbg(&u3phy_port->phy->dev, "Disconnected\n");
625 rockchip_u3phy_power_off(u3phy_port->phy);
626 u3phy_port->suspended = true;
627 }
628
629 /*
630 * activate the linestate detection to get the next device
631 * plug-in irq.
632 */
633 param_write(u3phy->u3phy_grf,
634 &u3phy->cfgs->grfcfg.ls_det_st, true);
635 param_write(u3phy->u3phy_grf,
636 &u3phy->cfgs->grfcfg.ls_det_en, true);
637
638 /*
639 * we don't need to rearm the delayed work when the phy port
640 * is suspended.
641 */
642 mutex_unlock(&u3phy_port->mutex);
643 return;
644 default:
645 dev_dbg(&u3phy_port->phy->dev, "unknown phy state\n");
646 break;
647 }
648
649 next_schedule:
650 mutex_unlock(&u3phy_port->mutex);
651 schedule_delayed_work(&u3phy_port->um_sm_work, SCHEDULE_DELAY);
652 }
653
rockchip_u3phy_um_ls_irq(int irq,void * data)654 static irqreturn_t rockchip_u3phy_um_ls_irq(int irq, void *data)
655 {
656 struct rockchip_u3phy_port *u3phy_port = data;
657 struct rockchip_u3phy *u3phy =
658 dev_get_drvdata(u3phy_port->phy->dev.parent);
659
660 if (!param_exped(u3phy->u3phy_grf,
661 &u3phy->cfgs->grfcfg.ls_det_st,
662 u3phy->cfgs->grfcfg.ls_det_st.dvalue))
663 return IRQ_NONE;
664
665 dev_dbg(u3phy->dev, "utmi linestate interrupt\n");
666 mutex_lock(&u3phy_port->mutex);
667
668 /* disable linestate detect irq and clear its status */
669 param_write(u3phy->u3phy_grf, &u3phy->cfgs->grfcfg.ls_det_en, false);
670 param_write(u3phy->u3phy_grf, &u3phy->cfgs->grfcfg.ls_det_st, true);
671
672 mutex_unlock(&u3phy_port->mutex);
673
674 /*
675 * In this case for host phy, a new device is plugged in, meanwhile,
676 * if the phy port is suspended, we need rearm the work to resume it
677 * and mange its states; otherwise, we just return irq handled.
678 */
679 if (u3phy_port->suspended) {
680 dev_dbg(u3phy->dev, "schedule utmi sm work\n");
681 rockchip_u3phy_um_sm_work(&u3phy_port->um_sm_work.work);
682 }
683
684 return IRQ_HANDLED;
685 }
686
rockchip_u3phy_parse_dt(struct rockchip_u3phy * u3phy,struct platform_device * pdev)687 static int rockchip_u3phy_parse_dt(struct rockchip_u3phy *u3phy,
688 struct platform_device *pdev)
689
690 {
691 struct device *dev = &pdev->dev;
692 struct device_node *np = dev->of_node;
693 int ret, i, clk;
694
695 u3phy->um_ls_irq = platform_get_irq_byname(pdev, "linestate");
696 if (u3phy->um_ls_irq < 0) {
697 dev_err(dev, "get utmi linestate irq failed\n");
698 return -ENXIO;
699 }
700
701 /* Get Vbus regulators */
702 u3phy->vbus = devm_regulator_get_optional(dev, "vbus");
703 if (IS_ERR(u3phy->vbus)) {
704 ret = PTR_ERR(u3phy->vbus);
705 if (ret == -EPROBE_DEFER)
706 return ret;
707
708 dev_warn(dev, "Failed to get VBUS supply regulator\n");
709 u3phy->vbus = NULL;
710 }
711
712 for (clk = 0; clk < U3PHY_MAX_CLKS; clk++) {
713 u3phy->clks[clk] = of_clk_get(np, clk);
714 if (IS_ERR(u3phy->clks[clk])) {
715 ret = PTR_ERR(u3phy->clks[clk]);
716 if (ret == -EPROBE_DEFER)
717 goto err_put_clks;
718 u3phy->clks[clk] = NULL;
719 break;
720 }
721 }
722
723 for (i = 0; i < U3PHY_RESET_MAX; i++) {
724 u3phy->rsts[i] = devm_reset_control_get(dev, get_rest_name(i));
725 if (IS_ERR(u3phy->rsts[i])) {
726 dev_info(dev, "no %s reset control specified\n",
727 get_rest_name(i));
728 u3phy->rsts[i] = NULL;
729 }
730 }
731
732 return 0;
733
734 err_put_clks:
735 while (--clk >= 0)
736 clk_put(u3phy->clks[clk]);
737 return ret;
738 }
739
rockchip_u3phy_port_init(struct rockchip_u3phy * u3phy,struct rockchip_u3phy_port * u3phy_port,struct device_node * child_np)740 static int rockchip_u3phy_port_init(struct rockchip_u3phy *u3phy,
741 struct rockchip_u3phy_port *u3phy_port,
742 struct device_node *child_np)
743 {
744 struct resource res;
745 struct phy *phy;
746 int ret;
747
748 dev_dbg(u3phy->dev, "u3phy port initialize\n");
749
750 mutex_init(&u3phy_port->mutex);
751 u3phy_port->suspended = true; /* initial status */
752
753 phy = devm_phy_create(u3phy->dev, child_np, &rockchip_u3phy_ops);
754 if (IS_ERR(phy)) {
755 dev_err(u3phy->dev, "failed to create phy\n");
756 return PTR_ERR(phy);
757 }
758
759 u3phy_port->phy = phy;
760
761 ret = of_address_to_resource(child_np, 0, &res);
762 if (ret) {
763 dev_err(u3phy->dev, "failed to get address resource(np-%s)\n",
764 child_np->name);
765 return ret;
766 }
767
768 u3phy_port->base = devm_ioremap_resource(&u3phy_port->phy->dev, &res);
769 if (IS_ERR(u3phy_port->base)) {
770 dev_err(u3phy->dev, "failed to remap phy regs\n");
771 return PTR_ERR(u3phy_port->base);
772 }
773
774 if (!of_node_cmp(child_np->name, "pipe")) {
775 u3phy_port->type = U3PHY_TYPE_PIPE;
776 u3phy_port->refclk_25m_quirk =
777 of_property_read_bool(child_np,
778 "rockchip,refclk-25m-quirk");
779 } else {
780 u3phy_port->type = U3PHY_TYPE_UTMI;
781 INIT_DELAYED_WORK(&u3phy_port->um_sm_work,
782 rockchip_u3phy_um_sm_work);
783
784 ret = devm_request_threaded_irq(u3phy->dev, u3phy->um_ls_irq,
785 NULL, rockchip_u3phy_um_ls_irq,
786 IRQF_ONESHOT, "rockchip_u3phy",
787 u3phy_port);
788 if (ret) {
789 dev_err(u3phy->dev, "failed to request utmi linestate irq handle\n");
790 return ret;
791 }
792 }
793
794 if (u3phy->cfgs->phy_tuning) {
795 dev_dbg(u3phy->dev, "do u3phy tuning\n");
796 ret = u3phy->cfgs->phy_tuning(u3phy, u3phy_port, child_np);
797 if (ret)
798 return ret;
799 }
800
801 phy_set_drvdata(u3phy_port->phy, u3phy_port);
802 return 0;
803 }
804
rockchip_u3phy_on_init(struct usb_phy * usb_phy)805 static int rockchip_u3phy_on_init(struct usb_phy *usb_phy)
806 {
807 struct rockchip_u3phy *u3phy =
808 container_of(usb_phy, struct rockchip_u3phy, usb_phy);
809
810 rockchip_u3phy_rest_deassert(u3phy, U3PHY_POR_RST | U3PHY_MAC_RST);
811 return 0;
812 }
813
rockchip_u3phy_on_shutdown(struct usb_phy * usb_phy)814 static void rockchip_u3phy_on_shutdown(struct usb_phy *usb_phy)
815 {
816 struct rockchip_u3phy *u3phy =
817 container_of(usb_phy, struct rockchip_u3phy, usb_phy);
818 int rst;
819
820 for (rst = 0; rst < U3PHY_RESET_MAX; rst++)
821 if (u3phy->rsts[rst] && rst != UTMI_APB_RSTN &&
822 rst != PIPE_APB_RSTN)
823 reset_control_assert(u3phy->rsts[rst]);
824 udelay(1);
825 }
826
rockchip_u3phy_on_disconnect(struct usb_phy * usb_phy,enum usb_device_speed speed)827 static int rockchip_u3phy_on_disconnect(struct usb_phy *usb_phy,
828 enum usb_device_speed speed)
829 {
830 struct rockchip_u3phy *u3phy =
831 container_of(usb_phy, struct rockchip_u3phy, usb_phy);
832
833 dev_info(u3phy->dev, "%s device has disconnected\n",
834 (speed == USB_SPEED_SUPER) ? "U3" : "UW/U2/U1.1/U1");
835
836 if (speed == USB_SPEED_SUPER)
837 atomic_notifier_call_chain(&usb_phy->notifier, 0, NULL);
838
839 return 0;
840 }
841
rockchip_u3phy_probe(struct platform_device * pdev)842 static int rockchip_u3phy_probe(struct platform_device *pdev)
843 {
844 struct device *dev = &pdev->dev;
845 struct device_node *np = dev->of_node;
846 struct device_node *child_np;
847 struct phy_provider *provider;
848 struct rockchip_u3phy *u3phy;
849 const struct rockchip_u3phy_cfg *phy_cfgs;
850 const struct of_device_id *match;
851 unsigned int reg[2];
852 int index, ret;
853
854 match = of_match_device(dev->driver->of_match_table, dev);
855 if (!match || !match->data) {
856 dev_err(dev, "phy-cfgs are not assigned!\n");
857 return -EINVAL;
858 }
859
860 u3phy = devm_kzalloc(dev, sizeof(*u3phy), GFP_KERNEL);
861 if (!u3phy)
862 return -ENOMEM;
863
864 u3phy->u3phy_grf =
865 syscon_regmap_lookup_by_phandle(np, "rockchip,u3phygrf");
866 if (IS_ERR(u3phy->u3phy_grf))
867 return PTR_ERR(u3phy->u3phy_grf);
868
869 u3phy->grf =
870 syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
871 if (IS_ERR(u3phy->grf)) {
872 dev_err(dev, "Missing rockchip,grf property\n");
873 return PTR_ERR(u3phy->grf);
874 }
875
876 if (of_property_read_u32_array(np, "reg", reg, 2)) {
877 dev_err(dev, "the reg property is not assigned in %s node\n",
878 np->name);
879 return -EINVAL;
880 }
881
882 u3phy->dev = dev;
883 u3phy->vbus_enabled = false;
884 phy_cfgs = match->data;
885 platform_set_drvdata(pdev, u3phy);
886
887 /* find out a proper config which can be matched with dt. */
888 index = 0;
889 while (phy_cfgs[index].reg) {
890 if (phy_cfgs[index].reg == reg[1]) {
891 u3phy->cfgs = &phy_cfgs[index];
892 break;
893 }
894
895 ++index;
896 }
897
898 if (!u3phy->cfgs) {
899 dev_err(dev, "no phy-cfgs can be matched with %s node\n",
900 np->name);
901 return -EINVAL;
902 }
903
904 ret = rockchip_u3phy_parse_dt(u3phy, pdev);
905 if (ret) {
906 dev_err(dev, "parse dt failed, ret(%d)\n", ret);
907 return ret;
908 }
909
910 ret = rockchip_u3phy_clk_enable(u3phy);
911 if (ret) {
912 dev_err(dev, "clk enable failed, ret(%d)\n", ret);
913 return ret;
914 }
915
916 rockchip_u3phy_rest_assert(u3phy);
917 rockchip_u3phy_rest_deassert(u3phy, U3PHY_APB_RST | U3PHY_POR_RST);
918
919 index = 0;
920 for_each_available_child_of_node(np, child_np) {
921 struct rockchip_u3phy_port *u3phy_port = &u3phy->ports[index];
922
923 u3phy_port->index = index;
924 ret = rockchip_u3phy_port_init(u3phy, u3phy_port, child_np);
925 if (ret) {
926 dev_err(dev, "u3phy port init failed,ret(%d)\n", ret);
927 goto put_child;
928 }
929
930 /* to prevent out of boundary */
931 if (++index >= U3PHY_PORT_NUM)
932 break;
933 }
934
935 provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
936 if (IS_ERR_OR_NULL(provider))
937 goto put_child;
938
939 rockchip_u3phy_rest_deassert(u3phy, U3PHY_MAC_RST);
940 rockchip_u3phy_clk_disable(u3phy);
941
942 u3phy->usb_phy.dev = dev;
943 u3phy->usb_phy.init = rockchip_u3phy_on_init;
944 u3phy->usb_phy.shutdown = rockchip_u3phy_on_shutdown;
945 u3phy->usb_phy.notify_disconnect = rockchip_u3phy_on_disconnect;
946 usb_add_phy(&u3phy->usb_phy, USB_PHY_TYPE_USB3);
947 ATOMIC_INIT_NOTIFIER_HEAD(&u3phy->usb_phy.notifier);
948
949 rockchip_u3phy_debugfs_init(u3phy);
950
951 dev_info(dev, "Rockchip u3phy initialized successfully\n");
952 return 0;
953
954 put_child:
955 of_node_put(child_np);
956 return ret;
957 }
958
rk3328_u3phy_pipe_power(struct rockchip_u3phy * u3phy,struct rockchip_u3phy_port * u3phy_port,bool on)959 static int rk3328_u3phy_pipe_power(struct rockchip_u3phy *u3phy,
960 struct rockchip_u3phy_port *u3phy_port,
961 bool on)
962 {
963 unsigned int reg;
964
965 if (on) {
966 reg = readl(u3phy_port->base + 0x1a8);
967 reg &= ~BIT(4); /* ldo power up */
968 writel(reg, u3phy_port->base + 0x1a8);
969
970 reg = readl(u3phy_port->base + 0x044);
971 reg &= ~BIT(4); /* bg power on */
972 writel(reg, u3phy_port->base + 0x044);
973
974 reg = readl(u3phy_port->base + 0x150);
975 reg |= BIT(6); /* tx bias enable */
976 writel(reg, u3phy_port->base + 0x150);
977
978 reg = readl(u3phy_port->base + 0x080);
979 reg &= ~BIT(2); /* tx cm power up */
980 writel(reg, u3phy_port->base + 0x080);
981
982 reg = readl(u3phy_port->base + 0x0c0);
983 /* tx obs enable and rx cm enable */
984 reg |= (BIT(3) | BIT(4));
985 writel(reg, u3phy_port->base + 0x0c0);
986
987 udelay(1);
988 } else {
989 reg = readl(u3phy_port->base + 0x1a8);
990 reg |= BIT(4); /* ldo power down */
991 writel(reg, u3phy_port->base + 0x1a8);
992
993 reg = readl(u3phy_port->base + 0x044);
994 reg |= BIT(4); /* bg power down */
995 writel(reg, u3phy_port->base + 0x044);
996
997 reg = readl(u3phy_port->base + 0x150);
998 reg &= ~BIT(6); /* tx bias disable */
999 writel(reg, u3phy_port->base + 0x150);
1000
1001 reg = readl(u3phy_port->base + 0x080);
1002 reg |= BIT(2); /* tx cm power down */
1003 writel(reg, u3phy_port->base + 0x080);
1004
1005 reg = readl(u3phy_port->base + 0x0c0);
1006 /* tx obs disable and rx cm disable */
1007 reg &= ~(BIT(3) | BIT(4));
1008 writel(reg, u3phy_port->base + 0x0c0);
1009 }
1010
1011 return 0;
1012 }
1013
rk3328_u3phy_tuning(struct rockchip_u3phy * u3phy,struct rockchip_u3phy_port * u3phy_port,struct device_node * child_np)1014 static int rk3328_u3phy_tuning(struct rockchip_u3phy *u3phy,
1015 struct rockchip_u3phy_port *u3phy_port,
1016 struct device_node *child_np)
1017 {
1018 if (u3phy_port->type == U3PHY_TYPE_UTMI) {
1019 /*
1020 * For rk3328 SoC, pre-emphasis and pre-emphasis strength must
1021 * be written as one fixed value as below.
1022 *
1023 * Dissimilarly, the odt 45ohm value should be flexibly tuninged
1024 * for the different boards to adjust HS eye height, so its
1025 * value can be assigned in DT in code design.
1026 */
1027
1028 /* {bits[2:0]=111}: always enable pre-emphasis */
1029 u3phy->apbcfg.u2_pre_emp = 0x0f;
1030
1031 /* {bits[5:3]=000}: pre-emphasis strength as the weakest */
1032 u3phy->apbcfg.u2_pre_emp_sth = 0x41;
1033
1034 /* {bits[4:0]=10101}: odt 45ohm tuning */
1035 u3phy->apbcfg.u2_odt_tuning = 0xb5;
1036 /* optional override of the odt 45ohm tuning */
1037 of_property_read_u32(child_np, "rockchip,odt-val-tuning",
1038 &u3phy->apbcfg.u2_odt_tuning);
1039
1040 writel(u3phy->apbcfg.u2_pre_emp, u3phy_port->base + 0x030);
1041 writel(u3phy->apbcfg.u2_pre_emp_sth, u3phy_port->base + 0x040);
1042 writel(u3phy->apbcfg.u2_odt_tuning, u3phy_port->base + 0x11c);
1043 } else if (u3phy_port->type == U3PHY_TYPE_PIPE) {
1044 if (u3phy_port->refclk_25m_quirk) {
1045 dev_dbg(u3phy->dev, "switch to 25m refclk\n");
1046 /* ref clk switch to 25M */
1047 writel(0x64, u3phy_port->base + 0x11c);
1048 writel(0x64, u3phy_port->base + 0x028);
1049 writel(0x01, u3phy_port->base + 0x020);
1050 writel(0x21, u3phy_port->base + 0x030);
1051 writel(0x06, u3phy_port->base + 0x108);
1052 writel(0x00, u3phy_port->base + 0x118);
1053 } else {
1054 /* configure for 24M ref clk */
1055 writel(0x80, u3phy_port->base + 0x10c);
1056 writel(0x01, u3phy_port->base + 0x118);
1057 writel(0x38, u3phy_port->base + 0x11c);
1058 writel(0x83, u3phy_port->base + 0x020);
1059 writel(0x02, u3phy_port->base + 0x108);
1060 }
1061
1062 /* Enable SSC */
1063 udelay(3);
1064 writel(0x08, u3phy_port->base + 0x000);
1065 writel(0x0c, u3phy_port->base + 0x120);
1066
1067 /* Tuning Rx for compliance RJTL test */
1068 writel(0x70, u3phy_port->base + 0x150);
1069 writel(0x12, u3phy_port->base + 0x0c8);
1070 writel(0x05, u3phy_port->base + 0x148);
1071 writel(0x08, u3phy_port->base + 0x068);
1072 writel(0xf0, u3phy_port->base + 0x1c4);
1073 writel(0xff, u3phy_port->base + 0x070);
1074 writel(0x0f, u3phy_port->base + 0x06c);
1075 writel(0xe0, u3phy_port->base + 0x060);
1076
1077 /*
1078 * Tuning Tx to increase the bias current
1079 * used in TX driver and RX EQ, it can
1080 * also increase the voltage of LFPS.
1081 */
1082 writel(0x08, u3phy_port->base + 0x180);
1083 } else {
1084 dev_err(u3phy->dev, "invalid u3phy port type\n");
1085 return -EINVAL;
1086 }
1087
1088 return 0;
1089 }
1090
1091 static const struct rockchip_u3phy_cfg rk3328_u3phy_cfgs[] = {
1092 {
1093 .reg = 0xff470000,
1094 .grfcfg = {
1095 .um_suspend = { 0x0004, 15, 0, 0x1452, 0x15d1 },
1096 .u2_only_ctrl = { 0x0020, 15, 15, 0, 1 },
1097 .um_ls = { 0x0030, 5, 4, 0, 1 },
1098 .um_hstdct = { 0x0030, 7, 7, 0, 1 },
1099 .ls_det_en = { 0x0040, 0, 0, 0, 1 },
1100 .ls_det_st = { 0x0044, 0, 0, 0, 1 },
1101 .pp_pwr_st = { 0x0034, 14, 13, 0, 0},
1102 .pp_pwr_en = { {0x0020, 14, 0, 0x0014, 0x0005},
1103 {0x0020, 14, 0, 0x0014, 0x000d},
1104 {0x0020, 14, 0, 0x0014, 0x0015},
1105 {0x0020, 14, 0, 0x0014, 0x001d} },
1106 .u3_disable = { 0x04c4, 15, 0, 0x1100, 0x101},
1107 },
1108 .phy_pipe_power = rk3328_u3phy_pipe_power,
1109 .phy_tuning = rk3328_u3phy_tuning,
1110 },
1111 { /* sentinel */ }
1112 };
1113
1114 static const struct of_device_id rockchip_u3phy_dt_match[] = {
1115 { .compatible = "rockchip,rk3328-u3phy", .data = &rk3328_u3phy_cfgs },
1116 {}
1117 };
1118 MODULE_DEVICE_TABLE(of, rockchip_u3phy_dt_match);
1119
1120 static struct platform_driver rockchip_u3phy_driver = {
1121 .probe = rockchip_u3phy_probe,
1122 .driver = {
1123 .name = "rockchip-u3phy",
1124 .of_match_table = rockchip_u3phy_dt_match,
1125 },
1126 };
1127 module_platform_driver(rockchip_u3phy_driver);
1128
1129 MODULE_AUTHOR("Frank Wang <frank.wang@rock-chips.com>");
1130 MODULE_AUTHOR("William Wu <william.wu@rock-chips.com>");
1131 MODULE_DESCRIPTION("Rockchip USB 3.0 PHY driver");
1132 MODULE_LICENSE("GPL v2");
1133