1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Rockchip USB2.0 PHY with Naneng IP block driver
4 *
5 * Copyright (C) 2020 Fuzhou Rockchip Electronics Co., Ltd
6 */
7
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
10 #include <linux/delay.h>
11 #include <linux/extcon-provider.h>
12 #include <linux/interrupt.h>
13 #include <linux/io.h>
14 #include <linux/iopoll.h>
15 #include <linux/gpio/consumer.h>
16 #include <linux/jiffies.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/mutex.h>
20 #include <linux/of.h>
21 #include <linux/of_address.h>
22 #include <linux/of_irq.h>
23 #include <linux/of_platform.h>
24 #include <linux/phy/phy.h>
25 #include <linux/platform_device.h>
26 #include <linux/power_supply.h>
27 #include <linux/regmap.h>
28 #include <linux/reset.h>
29 #include <linux/mfd/syscon.h>
30 #include <linux/usb/of.h>
31 #include <linux/usb/otg.h>
32 #include <linux/wakelock.h>
33
34 struct rockchip_usb2phy;
35
36 #define BIT_WRITEABLE_SHIFT 16
37 #define OTG_SCHEDULE_DELAY (1 * HZ)
38
39 enum rockchip_usb2phy_port_id {
40 USB2PHY_PORT_OTG,
41 USB2PHY_PORT_HOST,
42 USB2PHY_NUM_PORTS,
43 };
44
45 enum calibrate_state {
46 SWING_CALIBRATION,
47 CURRENT_COMPENSATION,
48 CALIBRATION_DONE,
49 };
50
51 static const unsigned int rockchip_usb2phy_extcon_cable[] = {
52 EXTCON_USB,
53 EXTCON_USB_HOST,
54 EXTCON_USB_VBUS_EN,
55 EXTCON_CHG_USB_SDP,
56 EXTCON_CHG_USB_CDP,
57 EXTCON_CHG_USB_DCP,
58 EXTCON_NONE,
59 };
60
61 struct usb2phy_reg {
62 unsigned int offset;
63 unsigned int bitend;
64 unsigned int bitstart;
65 unsigned int disable;
66 unsigned int enable;
67 };
68
69 /**
70 * struct rockchip_chg_det_reg: usb charger detect registers
71 * @chg_en: charge detector enable signal.
72 * @chg_rst: charge detector reset signal, active high.
73 * @chg_valid: charge valid signal.
74 * @phy_connect: PHY start handshake signal.
75 */
76 struct rockchip_chg_det_reg {
77 struct usb2phy_reg chg_en;
78 struct usb2phy_reg chg_rst;
79 struct usb2phy_reg chg_valid;
80 struct usb2phy_reg phy_connect;
81 };
82
83 /**
84 * struct rockchip_usb2phy_port_cfg: usb phy port configuration.
85 * @bypass_otgsuspendm: otg-suspendm bypass control register.
86 * 0: iddig; 1: grf.
87 * @bvalidfall_det_en: vbus valid fall detection enable register.
88 * @bvalidfall_det_st: vbus valid fall detection status register.
89 * @bvalidfall_det_clr: vbus valid fall detection clear register.
90 * @bvalidrise_det_en: vbus valid rise detection enable register.
91 * @bvalidrise_det_st: vbus valid rise detection status register.
92 * @bvalidrise_det_clr: vbus valid rise detection clear register.
93 * @disconfall_det_en: host connect detection enable register.
94 * @disconfall_det_st: host connect detection status register.
95 * @disconfall_det_clr: host connect detection clear register.
96 * @disconrise_det_en: host disconnect detection enable register.
97 * @disconrise_det_st: host disconnect detection status register.
98 * @disconrise_det_clr: host disconnect detection clear register.
99 * @idfall_det_en: id fall detection enable register.
100 * @idfall_det_st: id fall detection state register.
101 * @idfall_det_clr: id fall detection clear register.
102 * @idpullup: id pin pullup or pulldown control register.
103 * @iddig_output: utmi iddig value from grf output.
104 * @iddig_en: select utmi iddig output from grf or phy,
105 * 0: from phy output; 1: from grf output
106 * @idrise_det_en: id rise detection enable register.
107 * @idrise_det_st: id rise detection state register.
108 * @idrise_det_clr: id rise detection clear register.
109 * @ls_det_en: linestate detection enable register.
110 * @ls_det_st: linestate detection state register.
111 * @ls_det_clr: linestate detection clear register.
112 * @phy_sus: phy suspend register.
113 * @utmi_bvalid: utmi vbus bvalid status register.
114 * @utmi_iddig: otg port id pin status register.
115 * @utmi_hostdet: utmi host disconnect status register.
116 */
117 struct rockchip_usb2phy_port_cfg {
118 struct usb2phy_reg bypass_otgsuspendm;
119 struct usb2phy_reg bvalidfall_det_en;
120 struct usb2phy_reg bvalidfall_det_st;
121 struct usb2phy_reg bvalidfall_det_clr;
122 struct usb2phy_reg bvalidrise_det_en;
123 struct usb2phy_reg bvalidrise_det_st;
124 struct usb2phy_reg bvalidrise_det_clr;
125 struct usb2phy_reg disconfall_det_en;
126 struct usb2phy_reg disconfall_det_st;
127 struct usb2phy_reg disconfall_det_clr;
128 struct usb2phy_reg disconrise_det_en;
129 struct usb2phy_reg disconrise_det_st;
130 struct usb2phy_reg disconrise_det_clr;
131 struct usb2phy_reg idfall_det_en;
132 struct usb2phy_reg idfall_det_st;
133 struct usb2phy_reg idfall_det_clr;
134 struct usb2phy_reg idpullup;
135 struct usb2phy_reg iddig_output;
136 struct usb2phy_reg iddig_en;
137 struct usb2phy_reg idrise_det_en;
138 struct usb2phy_reg idrise_det_st;
139 struct usb2phy_reg idrise_det_clr;
140 struct usb2phy_reg ls_det_en;
141 struct usb2phy_reg ls_det_st;
142 struct usb2phy_reg ls_det_clr;
143 struct usb2phy_reg phy_sus;
144 struct usb2phy_reg utmi_bvalid;
145 struct usb2phy_reg utmi_iddig;
146 struct usb2phy_reg utmi_hostdet;
147 };
148
149 /**
150 * struct rockchip_usb2phy_cfg: usb phy configuration.
151 * @reg: the address offset of grf for usb-phy config.
152 * @num_ports: specify how many ports that the phy has.
153 * @clks: array of input clocks
154 * @num_clks: number of input clocks.
155 * @phy_tuning: phy default parameters tuning.
156 * @phy_lowpower: phy low power mode.
157 * @clkout_ctl: keep on/turn off output clk of phy.
158 * @port_cfgs: ports register configuration, assigned by driver data.
159 * @chg_det: charger detection registers.
160 * @last: indicate the last one.
161 */
162 struct rockchip_usb2phy_cfg {
163 unsigned int reg;
164 unsigned int num_ports;
165 const struct clk_bulk_data *clks;
166 int num_clks;
167 int (*phy_tuning)(struct rockchip_usb2phy *rphy);
168 int (*phy_lowpower)(struct rockchip_usb2phy *rphy, bool en);
169 struct usb2phy_reg clkout_ctl;
170 const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS];
171 const struct rockchip_chg_det_reg chg_det;
172 bool last;
173 };
174
175 /**
176 * struct rockchip_usb2phy_port: usb phy port data.
177 * @phy: the struct phy of this port.
178 * @port_id: flag for otg port or host port.
179 * @perip_connected: flag for periphyeral connect status.
180 * @prev_iddig: previous otg port id pin status.
181 * @suspended: phy suspended flag.
182 * @vbus_attached: otg device vbus status.
183 * @vbus_always_on: otg vbus is always powered on.
184 * @vbus_enabled: vbus regulator status.
185 * @bvalid_irq: IRQ number assigned for vbus valid rise detection.
186 * @ls_irq: IRQ number assigned for linestate detection.
187 * @disconnect_irq: IRQ number assigned for host disconnect detection.
188 * @id_irq: IRQ number assigned for id fall or rise detection.
189 * @mutex: for register updating in interrupt thread.
190 * @otg_sm_work: OTG periphreal connect or disconnect judgement.
191 * @vbus: vbus regulator supply on few rockchip boards.
192 * @port_cfg: port register configuration, assigned by driver data.
193 * @wakelock: wakeup source for otg-port.
194 * @mode: the dr_mode of the controller.
195 */
196 struct rockchip_usb2phy_port {
197 struct phy *phy;
198 unsigned int port_id;
199 bool perip_connected;
200 bool prev_iddig;
201 bool suspended;
202 bool vbus_attached;
203 bool vbus_always_on;
204 bool vbus_enabled;
205 int bvalid_irq;
206 int ls_irq;
207 int disconnect_irq;
208 int id_irq;
209 struct mutex mutex; /* protects register of phy */
210 struct delayed_work otg_sm_work;
211 struct regulator *vbus;
212 const struct rockchip_usb2phy_port_cfg *port_cfg;
213 struct wake_lock wakelock;
214 enum usb_dr_mode mode;
215 };
216
217 /**
218 * struct rockchip_usb2phy: usb2.0 phy driver data.
219 * @dev: pointer to our struct device.
220 * @grf: General Register Files regmap.
221 * @base: the base address of APB interface.
222 * @reset: power reset signal for phy.
223 * @clks: array of input clocks.
224 * @num_clks: number of input clocks.
225 * @clk480m: clock struct of phy output clk.
226 * @clk480m_hw: clock struct of phy output clk management.
227 * @chg_type: USB charger types.
228 * @edev_self: represent the source of extcon.
229 * @edev: extcon device for notification registration.
230 * @vup_gpio: gpio switch for pull-up register on DM.
231 * @wait_timer: hrtimer for phy calibration delay.
232 * @cal_state: state of phy calibration.
233 * @phy_cfg: phy register configuration, assigned by driver data.
234 * @ports: phy port instance.
235 */
236 struct rockchip_usb2phy {
237 struct device *dev;
238 struct regmap *grf;
239 void __iomem *base;
240 struct reset_control *reset;
241 struct clk_bulk_data *clks;
242 int num_clks;
243 struct clk *clk480m;
244 struct clk_hw clk480m_hw;
245 enum power_supply_type chg_type;
246 bool edev_self;
247 struct extcon_dev *edev;
248 struct gpio_desc *vup_gpio;
249 struct hrtimer wait_timer;
250 enum calibrate_state cal_state;
251 const struct rockchip_usb2phy_cfg *phy_cfg;
252 struct rockchip_usb2phy_port ports[USB2PHY_NUM_PORTS];
253 };
254
property_enable(struct regmap * base,const struct usb2phy_reg * reg,bool en)255 static inline int property_enable(struct regmap *base,
256 const struct usb2phy_reg *reg, bool en)
257 {
258 unsigned int val, mask, tmp;
259
260 tmp = en ? reg->enable : reg->disable;
261 mask = GENMASK(reg->bitend, reg->bitstart);
262 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
263
264 return regmap_write(base, reg->offset, val);
265 }
266
property_enabled(struct regmap * base,const struct usb2phy_reg * reg)267 static inline bool property_enabled(struct regmap *base,
268 const struct usb2phy_reg *reg)
269 {
270 int ret;
271 unsigned int tmp, orig;
272 unsigned int mask = GENMASK(reg->bitend, reg->bitstart);
273
274 ret = regmap_read(base, reg->offset, &orig);
275 if (ret)
276 return false;
277
278 tmp = (orig & mask) >> reg->bitstart;
279 return tmp == reg->enable;
280 }
281
rockchip_usb2phy_clk480m_prepare(struct clk_hw * hw)282 static int rockchip_usb2phy_clk480m_prepare(struct clk_hw *hw)
283 {
284 struct rockchip_usb2phy *rphy =
285 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
286 int ret;
287
288 /* turn on 480m clk output if it is off */
289 if (!property_enabled(rphy->grf, &rphy->phy_cfg->clkout_ctl)) {
290 ret = property_enable(rphy->grf, &rphy->phy_cfg->clkout_ctl,
291 true);
292 if (ret)
293 return ret;
294
295 /* waiting for the clk become stable */
296 usleep_range(500, 600);
297 }
298
299 return 0;
300 }
301
rockchip_usb2phy_clk480m_unprepare(struct clk_hw * hw)302 static void rockchip_usb2phy_clk480m_unprepare(struct clk_hw *hw)
303 {
304 struct rockchip_usb2phy *rphy =
305 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
306
307 /* turn off 480m clk output */
308 property_enable(rphy->grf, &rphy->phy_cfg->clkout_ctl, false);
309 }
310
rockchip_usb2phy_clk480m_prepared(struct clk_hw * hw)311 static int rockchip_usb2phy_clk480m_prepared(struct clk_hw *hw)
312 {
313 struct rockchip_usb2phy *rphy =
314 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
315
316 return property_enabled(rphy->grf, &rphy->phy_cfg->clkout_ctl);
317 }
318
319 static unsigned long
rockchip_usb2phy_clk480m_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)320 rockchip_usb2phy_clk480m_recalc_rate(struct clk_hw *hw,
321 unsigned long parent_rate)
322 {
323 return 480000000;
324 }
325
326 static const struct clk_ops rockchip_usb2phy_clkout_ops = {
327 .prepare = rockchip_usb2phy_clk480m_prepare,
328 .unprepare = rockchip_usb2phy_clk480m_unprepare,
329 .is_prepared = rockchip_usb2phy_clk480m_prepared,
330 .recalc_rate = rockchip_usb2phy_clk480m_recalc_rate,
331 };
332
rockchip_usb2phy_clk480m_unregister(void * data)333 static void rockchip_usb2phy_clk480m_unregister(void *data)
334 {
335 struct rockchip_usb2phy *rphy = data;
336
337 of_clk_del_provider(rphy->dev->of_node);
338 clk_unregister(rphy->clk480m);
339 }
340
341 static int
rockchip_usb2phy_clk480m_register(struct rockchip_usb2phy * rphy)342 rockchip_usb2phy_clk480m_register(struct rockchip_usb2phy *rphy)
343 {
344 struct device_node *node = rphy->dev->of_node;
345 struct clk_init_data init = {};
346 struct clk *refclk = of_clk_get_by_name(node, "phyclk");
347 const char *clk_name;
348 int ret;
349
350 init.flags = 0;
351 init.name = "clk_usbphy_480m";
352 init.ops = &rockchip_usb2phy_clkout_ops;
353
354 /* optional override of the clockname */
355 of_property_read_string(node, "clock-output-names", &init.name);
356
357 if (refclk) {
358 clk_name = __clk_get_name(refclk);
359 init.parent_names = &clk_name;
360 init.num_parents = 1;
361 } else {
362 init.parent_names = NULL;
363 init.num_parents = 0;
364 }
365
366 rphy->clk480m_hw.init = &init;
367
368 /* register the clock */
369 rphy->clk480m = clk_register(rphy->dev, &rphy->clk480m_hw);
370 if (IS_ERR(rphy->clk480m)) {
371 ret = PTR_ERR(rphy->clk480m);
372 goto err_ret;
373 }
374
375 ret = of_clk_add_provider(node, of_clk_src_simple_get, rphy->clk480m);
376 if (ret < 0)
377 goto err_clk_provider;
378
379 ret = devm_add_action(rphy->dev, rockchip_usb2phy_clk480m_unregister,
380 rphy);
381 if (ret < 0)
382 goto err_unreg_action;
383
384 return 0;
385
386 err_unreg_action:
387 of_clk_del_provider(node);
388 err_clk_provider:
389 clk_unregister(rphy->clk480m);
390 err_ret:
391 return ret;
392 }
393
394 /* The caller must hold rport->mutex lock */
rockchip_usb2phy_enable_id_irq(struct rockchip_usb2phy * rphy,struct rockchip_usb2phy_port * rport,bool en)395 static int rockchip_usb2phy_enable_id_irq(struct rockchip_usb2phy *rphy,
396 struct rockchip_usb2phy_port *rport,
397 bool en)
398 {
399 int ret;
400
401 ret = property_enable(rphy->grf,
402 &rport->port_cfg->idfall_det_clr, true);
403 if (ret)
404 goto out;
405
406 ret = property_enable(rphy->grf, &rport->port_cfg->idfall_det_en, en);
407 if (ret)
408 goto out;
409
410 ret = property_enable(rphy->grf,
411 &rport->port_cfg->idrise_det_clr, true);
412 if (ret)
413 goto out;
414
415 ret = property_enable(rphy->grf, &rport->port_cfg->idrise_det_en, en);
416 out:
417 return ret;
418 }
419
420 /* The caller must hold rport->mutex lock */
rockchip_usb2phy_enable_vbus_irq(struct rockchip_usb2phy * rphy,struct rockchip_usb2phy_port * rport,bool en)421 static int rockchip_usb2phy_enable_vbus_irq(struct rockchip_usb2phy *rphy,
422 struct rockchip_usb2phy_port *rport,
423 bool en)
424 {
425 int ret;
426
427 ret = property_enable(rphy->grf,
428 &rport->port_cfg->bvalidfall_det_clr, true);
429 if (ret)
430 goto out;
431
432 ret = property_enable(rphy->grf,
433 &rport->port_cfg->bvalidfall_det_en, en);
434 if (ret)
435 goto out;
436
437 ret = property_enable(rphy->grf,
438 &rport->port_cfg->bvalidrise_det_clr, true);
439 if (ret)
440 goto out;
441
442 ret = property_enable(rphy->grf,
443 &rport->port_cfg->bvalidrise_det_en, en);
444 out:
445 return ret;
446 }
447
rockchip_usb2phy_enable_line_irq(struct rockchip_usb2phy * rphy,struct rockchip_usb2phy_port * rport,bool en)448 static int rockchip_usb2phy_enable_line_irq(struct rockchip_usb2phy *rphy,
449 struct rockchip_usb2phy_port *rport,
450 bool en)
451 {
452 int ret;
453
454 ret = property_enable(rphy->grf, &rport->port_cfg->ls_det_clr, true);
455 if (ret)
456 goto out;
457
458 ret = property_enable(rphy->grf, &rport->port_cfg->ls_det_en, en);
459 out:
460 return ret;
461 }
462
463 static int
rockchip_usb2phy_enable_disconn_irq(struct rockchip_usb2phy * rphy,struct rockchip_usb2phy_port * rport,bool en)464 rockchip_usb2phy_enable_disconn_irq(struct rockchip_usb2phy *rphy,
465 struct rockchip_usb2phy_port *rport,
466 bool en)
467 {
468 int ret;
469
470 ret = property_enable(rphy->grf,
471 &rport->port_cfg->disconrise_det_clr, true);
472 if (ret)
473 goto out;
474
475 ret = property_enable(rphy->grf,
476 &rport->port_cfg->disconrise_det_en, en);
477 out:
478 return ret;
479 }
480
rockchip_usb2phy_extcon_register(struct rockchip_usb2phy * rphy)481 static int rockchip_usb2phy_extcon_register(struct rockchip_usb2phy *rphy)
482 {
483 int ret;
484 struct device_node *node = rphy->dev->of_node;
485 struct extcon_dev *edev;
486
487 if (of_property_read_bool(node, "extcon")) {
488 edev = extcon_get_edev_by_phandle(rphy->dev, 0);
489 if (IS_ERR(edev)) {
490 if (PTR_ERR(edev) != -EPROBE_DEFER)
491 dev_err(rphy->dev,
492 "Invalid or missing extcon\n");
493 return PTR_ERR(edev);
494 }
495 } else {
496 /* Initialize extcon device */
497 edev = devm_extcon_dev_allocate(rphy->dev,
498 rockchip_usb2phy_extcon_cable);
499
500 if (IS_ERR(edev))
501 return -ENOMEM;
502
503 ret = devm_extcon_dev_register(rphy->dev, edev);
504 if (ret) {
505 dev_err(rphy->dev,
506 "failed to register extcon device\n");
507 return ret;
508 }
509
510 rphy->edev_self = true;
511 }
512
513 rphy->edev = edev;
514
515 return 0;
516 }
517
rockchip_usb2phy_init(struct phy * phy)518 static int rockchip_usb2phy_init(struct phy *phy)
519 {
520 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
521 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
522 int ret = 0;
523
524 mutex_lock(&rport->mutex);
525
526 /* clear disconnect status and enable disconnect detect irq */
527 if (rport->disconnect_irq > 0) {
528 ret = rockchip_usb2phy_enable_disconn_irq(rphy, rport, true);
529 if (ret) {
530 dev_err(rphy->dev, "failed to enable disconnect irq\n");
531 goto out;
532 }
533 }
534
535 /* clear linstate status and enable linestate detect irq */
536 if (rport->ls_irq > 0 &&
537 (rport->port_id == USB2PHY_PORT_HOST ||
538 rport->mode == USB_DR_MODE_HOST)) {
539 ret = rockchip_usb2phy_enable_line_irq(rphy, rport, true);
540 if (ret) {
541 dev_err(rphy->dev, "failed to enable linestate irq\n");
542 goto out;
543 }
544 }
545
546 /* clear bvalid status and enable bvalid detect irq */
547 if (rport->bvalid_irq > 0) {
548 ret = rockchip_usb2phy_enable_vbus_irq(rphy, rport, true);
549 if (ret) {
550 dev_err(rphy->dev,
551 "failed to enable bvalid irq\n");
552 goto out;
553 }
554
555 rport->vbus_attached =
556 property_enabled(rphy->grf,
557 &rport->port_cfg->utmi_bvalid);
558 schedule_delayed_work(&rport->otg_sm_work, OTG_SCHEDULE_DELAY);
559 }
560
561 /* clear id status and enable id detect irq */
562 if (rport->id_irq > 0) {
563 ret = rockchip_usb2phy_enable_id_irq(rphy, rport,
564 true);
565 if (ret) {
566 dev_err(rphy->dev,
567 "failed to enable id irq\n");
568 goto out;
569 }
570 }
571
572 out:
573 mutex_unlock(&rport->mutex);
574 return ret;
575 }
576
rockchip_usb2phy_power_on(struct phy * phy)577 static int rockchip_usb2phy_power_on(struct phy *phy)
578 {
579 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
580 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
581 int ret;
582
583 dev_dbg(&rport->phy->dev, "port power on\n");
584
585 mutex_lock(&rport->mutex);
586
587 if (!rport->suspended) {
588 ret = 0;
589 goto unlock;
590 }
591
592 ret = property_enable(rphy->grf, &rport->port_cfg->phy_sus, false);
593 if (ret)
594 goto unlock;
595
596 /* waiting for the utmi_clk to become stable */
597 usleep_range(2500, 3000);
598
599 rport->suspended = false;
600
601 unlock:
602 mutex_unlock(&rport->mutex);
603
604 return ret;
605 }
606
rockchip_usb2phy_power_off(struct phy * phy)607 static int rockchip_usb2phy_power_off(struct phy *phy)
608 {
609 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
610 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
611 int ret;
612
613 dev_dbg(&rport->phy->dev, "port power off\n");
614
615 mutex_lock(&rport->mutex);
616
617 if (rport->suspended) {
618 ret = 0;
619 goto unlock;
620 }
621
622 ret = property_enable(rphy->grf, &rport->port_cfg->phy_sus, true);
623 if (ret)
624 goto unlock;
625
626 rport->suspended = true;
627
628 unlock:
629 mutex_unlock(&rport->mutex);
630
631 return ret;
632 }
633
rockchip_usb2phy_exit(struct phy * phy)634 static int rockchip_usb2phy_exit(struct phy *phy)
635 {
636 return 0;
637 }
638
rockchip_set_vbus_power(struct rockchip_usb2phy_port * rport,bool en)639 static int rockchip_set_vbus_power(struct rockchip_usb2phy_port *rport,
640 bool en)
641 {
642 int ret = 0;
643
644 if (!rport->vbus)
645 return 0;
646
647 if (en && !rport->vbus_enabled) {
648 ret = regulator_enable(rport->vbus);
649 if (ret)
650 dev_err(&rport->phy->dev,
651 "Failed to enable VBUS supply\n");
652 } else if (!en && rport->vbus_enabled) {
653 ret = regulator_disable(rport->vbus);
654 }
655
656 if (ret == 0)
657 rport->vbus_enabled = en;
658
659 return ret;
660 }
661
rockchip_usb2phy_set_mode(struct phy * phy,enum phy_mode mode,int submode)662 static int rockchip_usb2phy_set_mode(struct phy *phy,
663 enum phy_mode mode, int submode)
664 {
665 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
666 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
667 int ret = 0;
668
669 if (rport->port_id != USB2PHY_PORT_OTG)
670 return ret;
671
672 switch (mode) {
673 case PHY_MODE_USB_OTG:
674 /* fallthrough */
675 case PHY_MODE_USB_DEVICE:
676 /* Disable VBUS supply */
677 rockchip_set_vbus_power(rport, false);
678 extcon_set_state_sync(rphy->edev, EXTCON_USB_VBUS_EN, false);
679 break;
680 case PHY_MODE_USB_HOST:
681 /* Enable VBUS supply */
682 ret = rockchip_set_vbus_power(rport, true);
683 if (ret) {
684 dev_err(&rport->phy->dev,
685 "Failed to set host mode\n");
686 return ret;
687 }
688
689 extcon_set_state_sync(rphy->edev, EXTCON_USB_VBUS_EN, true);
690 break;
691 default:
692 dev_info(&rport->phy->dev, "illegal mode\n");
693 return ret;
694 }
695
696 return ret;
697 }
698
rv1126_wait_timer_fn(struct hrtimer * t)699 static enum hrtimer_restart rv1126_wait_timer_fn(struct hrtimer *t)
700 {
701 enum hrtimer_restart ret;
702 ktime_t delay;
703 static u32 reg;
704 struct rockchip_usb2phy *rphy = container_of(t, struct rockchip_usb2phy,
705 wait_timer);
706
707 switch (rphy->cal_state) {
708 case SWING_CALIBRATION:
709 /* disable tx swing calibrate */
710 writel(0x5d, rphy->base + 0x20);
711 /* read the value of rsistance calibration */
712 reg = readl(rphy->base + 0x10);
713
714 /* open the pull-up resistor */
715 gpiod_set_value(rphy->vup_gpio, 1);
716 /* set cfg_hs_strg 0 to increase chirpk amplitude */
717 writel(0x08, rphy->base + 0x00);
718 /*
719 * set internal 45 Ohm resistance minimal to
720 * increase chirpk amplitude
721 */
722 writel(0x7c, rphy->base + 0x10);
723
724 delay = ktime_set(0, 1200000);
725 hrtimer_forward_now(&rphy->wait_timer, delay);
726 rphy->cal_state = CURRENT_COMPENSATION;
727 ret = HRTIMER_RESTART;
728 break;
729 case CURRENT_COMPENSATION:
730 /* close the pull-up resistor */
731 gpiod_set_value(rphy->vup_gpio, 0);
732 /*
733 * set cfg_sel_strength and cfg_sel_pw 1 to
734 * correct the effect of pull-up resistor
735 */
736 writel(0xe8, rphy->base + 0x00);
737 /* write the value of rsistance calibration */
738 writel(reg, rphy->base + 0x10);
739
740 delay = ktime_set(0, 1000000);
741 hrtimer_forward_now(&rphy->wait_timer, delay);
742 rphy->cal_state = CALIBRATION_DONE;
743 ret = HRTIMER_RESTART;
744 break;
745 case CALIBRATION_DONE:
746 /* enable tx swing calibrate */
747 writel(0x4d, rphy->base + 0x20);
748 /* fall through */
749 default:
750 ret = HRTIMER_NORESTART;
751 break;
752 }
753
754 return ret;
755 }
756
rv1126_usb2phy_calibrate(struct phy * phy)757 static int rv1126_usb2phy_calibrate(struct phy *phy)
758 {
759 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
760 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
761 ktime_t delay;
762
763 if (rport->port_id != USB2PHY_PORT_OTG)
764 return 0;
765
766 delay = ktime_set(0, 500000);
767 rphy->cal_state = SWING_CALIBRATION;
768 hrtimer_start(&rphy->wait_timer, delay, HRTIMER_MODE_REL);
769
770 return 0;
771 }
772
773 static struct phy_ops rockchip_usb2phy_ops = {
774 .init = rockchip_usb2phy_init,
775 .exit = rockchip_usb2phy_exit,
776 .power_on = rockchip_usb2phy_power_on,
777 .power_off = rockchip_usb2phy_power_off,
778 .set_mode = rockchip_usb2phy_set_mode,
779 .owner = THIS_MODULE,
780 };
781
chg_to_string(enum power_supply_type chg_type)782 static const char *chg_to_string(enum power_supply_type chg_type)
783 {
784 switch (chg_type) {
785 case POWER_SUPPLY_TYPE_USB:
786 return "USB_SDP_CHARGER";
787 case POWER_SUPPLY_TYPE_USB_DCP:
788 return "USB_DCP_CHARGER";
789 case POWER_SUPPLY_TYPE_USB_CDP:
790 return "USB_CDP_CHARGER";
791 default:
792 return "INVALID_CHARGER";
793 }
794 }
795
rockchip_chg_detect(struct rockchip_usb2phy * rphy,struct rockchip_usb2phy_port * rport)796 static void rockchip_chg_detect(struct rockchip_usb2phy *rphy,
797 struct rockchip_usb2phy_port *rport)
798 {
799 bool chg_valid, phy_connect;
800 int result;
801 int cnt;
802
803 mutex_lock(&rport->mutex);
804
805 reset_control_assert(rphy->reset);
806
807 /* CHG_RST is set to 1'b0 to start charge detection */
808 property_enable(rphy->grf, &rphy->phy_cfg->chg_det.chg_en, true);
809 property_enable(rphy->grf, &rphy->phy_cfg->chg_det.chg_rst, false);
810
811 for (cnt = 0; cnt < 12; cnt++) {
812 msleep(100);
813
814 chg_valid = property_enabled(rphy->grf,
815 &rphy->phy_cfg->chg_det.chg_valid);
816 phy_connect =
817 property_enabled(rphy->grf,
818 &rphy->phy_cfg->chg_det.phy_connect);
819 result = (chg_valid << 1) | phy_connect;
820
821 if (result)
822 break;
823 }
824
825 switch (result) {
826 case 1:
827 rphy->chg_type = POWER_SUPPLY_TYPE_USB;
828 break;
829 case 2:
830 rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP;
831 break;
832 case 3:
833 rphy->chg_type = POWER_SUPPLY_TYPE_USB_CDP;
834 break;
835 case 0:
836 /* fall through */
837 default:
838 rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
839 break;
840 }
841
842 dev_info(&rport->phy->dev, "charger = %s\n",
843 chg_to_string(rphy->chg_type));
844
845 usleep_range(1000, 1100);
846 reset_control_deassert(rphy->reset);
847 /* waiting for the utmi_clk to become stable */
848 usleep_range(2500, 3000);
849
850 /* disable the chg detection module */
851 property_enable(rphy->grf, &rphy->phy_cfg->chg_det.chg_rst, true);
852 property_enable(rphy->grf, &rphy->phy_cfg->chg_det.chg_en, false);
853
854 mutex_unlock(&rport->mutex);
855 }
856
rockchip_usb2phy_disconnect_irq(int irq,void * data)857 static irqreturn_t rockchip_usb2phy_disconnect_irq(int irq, void *data)
858 {
859 struct rockchip_usb2phy_port *rport = data;
860 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
861
862 if (!property_enabled(rphy->grf, &rport->port_cfg->disconrise_det_st))
863 return IRQ_NONE;
864
865 mutex_lock(&rport->mutex);
866
867 /* clear disconnect rise detect irq pending status */
868 property_enable(rphy->grf, &rport->port_cfg->disconrise_det_clr, true);
869
870 mutex_unlock(&rport->mutex);
871
872 /* prevent fs/ls device disconnect before enumeration */
873 msleep(200);
874 if (!property_enabled(rphy->grf, &rport->port_cfg->utmi_hostdet))
875 return IRQ_HANDLED;
876
877 mutex_lock(&rport->mutex);
878
879 /* enable linestate detect irq to detect next host connect */
880 rockchip_usb2phy_enable_line_irq(rphy, rport, true);
881
882 mutex_unlock(&rport->mutex);
883
884 dev_dbg(&rport->phy->dev, "host disconnected\n");
885 rockchip_usb2phy_power_off(rport->phy);
886
887 return IRQ_HANDLED;
888 }
889
rockchip_usb2phy_linestate_irq(int irq,void * data)890 static irqreturn_t rockchip_usb2phy_linestate_irq(int irq, void *data)
891 {
892 struct rockchip_usb2phy_port *rport = data;
893 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
894
895 if (!property_enabled(rphy->grf, &rport->port_cfg->ls_det_st))
896 return IRQ_NONE;
897
898 dev_dbg(&rport->phy->dev, "linestate interrupt\n");
899
900 mutex_lock(&rport->mutex);
901
902 /* disable linestate detect irq and clear its status */
903 rockchip_usb2phy_enable_line_irq(rphy, rport, false);
904
905 mutex_unlock(&rport->mutex);
906
907 if (!rport->suspended)
908 return IRQ_HANDLED;
909
910 if (rport->port_id != USB2PHY_PORT_HOST &&
911 rport->mode != USB_DR_MODE_HOST)
912 return IRQ_HANDLED;
913
914 dev_dbg(&rport->phy->dev, "host connected\n");
915 rockchip_usb2phy_power_on(rport->phy);
916
917 return IRQ_HANDLED;
918 }
919
rockchip_usb2phy_otg_sm_work(struct work_struct * work)920 static void rockchip_usb2phy_otg_sm_work(struct work_struct *work)
921 {
922 static unsigned int cable;
923 struct rockchip_usb2phy_port *rport =
924 container_of(work, struct rockchip_usb2phy_port,
925 otg_sm_work.work);
926 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
927
928 if (rport->vbus_attached) {
929 if (extcon_get_state(rphy->edev, EXTCON_USB_HOST) ||
930 extcon_get_state(rphy->edev, EXTCON_USB_VBUS_EN) ||
931 !property_enabled(rphy->grf, &rport->port_cfg->utmi_iddig))
932 return;
933
934 if (rport->perip_connected)
935 return;
936
937 rockchip_chg_detect(rphy, rport);
938
939 switch (rphy->chg_type) {
940 case POWER_SUPPLY_TYPE_USB:
941 dev_dbg(&rport->phy->dev, "sdp cable is connected\n");
942 wake_lock(&rport->wakelock);
943 cable = EXTCON_CHG_USB_SDP;
944 rport->perip_connected = true;
945 break;
946 case POWER_SUPPLY_TYPE_USB_DCP:
947 dev_dbg(&rport->phy->dev, "dcp cable is connected\n");
948 cable = EXTCON_CHG_USB_DCP;
949 break;
950 case POWER_SUPPLY_TYPE_USB_CDP:
951 dev_dbg(&rport->phy->dev, "cdp cable is connected\n");
952 wake_lock(&rport->wakelock);
953 cable = EXTCON_CHG_USB_CDP;
954 rport->perip_connected = true;
955 break;
956 default:
957 break;
958 }
959 } else {
960 if (!rport->perip_connected) {
961 if (extcon_get_state(rphy->edev, EXTCON_CHG_USB_DCP) > 0)
962 extcon_set_state_sync(rphy->edev, EXTCON_CHG_USB_DCP, 0);
963 return;
964 }
965
966 dev_dbg(&rport->phy->dev, "usb peripheral disconnect\n");
967 wake_unlock(&rport->wakelock);
968 rport->perip_connected = false;
969 rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
970 }
971
972 if (extcon_get_state(rphy->edev, cable) != rport->vbus_attached) {
973 extcon_set_state(rphy->edev, cable, rport->vbus_attached);
974 extcon_sync(rphy->edev, cable);
975 }
976
977 if (rphy->edev_self && (extcon_get_state(rphy->edev, EXTCON_USB) !=
978 rport->perip_connected)) {
979 extcon_set_state(rphy->edev, EXTCON_USB,
980 rport->perip_connected);
981
982 extcon_sync(rphy->edev, EXTCON_USB);
983 extcon_sync(rphy->edev, EXTCON_USB_HOST);
984 }
985 }
986
987 /* Show & store the current value of otg mode for otg port */
otg_mode_show(struct device * device,struct device_attribute * attr,char * buf)988 static ssize_t otg_mode_show(struct device *device,
989 struct device_attribute *attr,
990 char *buf)
991 {
992 struct rockchip_usb2phy *rphy = dev_get_drvdata(device);
993 struct rockchip_usb2phy_port *rport = NULL;
994 unsigned int index;
995
996 for (index = 0; index < rphy->phy_cfg->num_ports; index++) {
997 rport = &rphy->ports[index];
998 if (rport->port_id == USB2PHY_PORT_OTG)
999 break;
1000 }
1001
1002 if (!rport) {
1003 dev_err(rphy->dev, "Fail to get otg port\n");
1004 return -EINVAL;
1005 } else if (rport->port_id != USB2PHY_PORT_OTG) {
1006 dev_err(rphy->dev, "No support otg\n");
1007 return -EINVAL;
1008 }
1009
1010 switch (rport->mode) {
1011 case USB_DR_MODE_HOST:
1012 return sprintf(buf, "host\n");
1013 case USB_DR_MODE_PERIPHERAL:
1014 return sprintf(buf, "peripheral\n");
1015 case USB_DR_MODE_OTG:
1016 return sprintf(buf, "otg\n");
1017 case USB_DR_MODE_UNKNOWN:
1018 return sprintf(buf, "UNKNOWN\n");
1019 default:
1020 break;
1021 }
1022
1023 return -EINVAL;
1024 }
1025
otg_mode_store(struct device * device,struct device_attribute * attr,const char * buf,size_t count)1026 static ssize_t otg_mode_store(struct device *device,
1027 struct device_attribute *attr,
1028 const char *buf, size_t count)
1029 {
1030 struct rockchip_usb2phy *rphy = dev_get_drvdata(device);
1031 struct rockchip_usb2phy_port *rport = NULL;
1032 enum usb_dr_mode new_dr_mode;
1033 unsigned int index;
1034 int rc = count;
1035
1036 for (index = 0; index < rphy->phy_cfg->num_ports; index++) {
1037 rport = &rphy->ports[index];
1038 if (rport->port_id == USB2PHY_PORT_OTG)
1039 break;
1040 }
1041
1042 if (!rport) {
1043 dev_err(rphy->dev, "Fail to get otg port!\n");
1044 rc = -EINVAL;
1045 goto exit;
1046 } else if (rport->port_id != USB2PHY_PORT_OTG ||
1047 rport->mode == USB_DR_MODE_UNKNOWN) {
1048 dev_err(rphy->dev, "No support otg!\n");
1049 rc = -EINVAL;
1050 goto exit;
1051 }
1052
1053 mutex_lock(&rport->mutex);
1054
1055 if (!strncmp(buf, "0", 1) || !strncmp(buf, "otg", 3)) {
1056 new_dr_mode = USB_DR_MODE_OTG;
1057 } else if (!strncmp(buf, "1", 1) || !strncmp(buf, "host", 4)) {
1058 new_dr_mode = USB_DR_MODE_HOST;
1059 } else if (!strncmp(buf, "2", 1) || !strncmp(buf, "peripheral", 10)) {
1060 new_dr_mode = USB_DR_MODE_PERIPHERAL;
1061 } else {
1062 dev_err(rphy->dev, "Error mode! Input 'otg' or 'host' or 'peripheral'\n");
1063 rc = -EINVAL;
1064 goto unlock;
1065 }
1066
1067 if (rport->mode == new_dr_mode) {
1068 dev_warn(rphy->dev, "Same as current mode\n");
1069 goto unlock;
1070 }
1071
1072 rport->mode = new_dr_mode;
1073
1074 switch (rport->mode) {
1075 case USB_DR_MODE_HOST:
1076 rport->perip_connected = false;
1077 extcon_set_state(rphy->edev, EXTCON_USB, false);
1078 extcon_set_state(rphy->edev, EXTCON_USB_HOST, true);
1079 extcon_sync(rphy->edev, EXTCON_USB);
1080 extcon_sync(rphy->edev, EXTCON_USB_HOST);
1081 rockchip_usb2phy_set_mode(rport->phy, PHY_MODE_USB_HOST, 0);
1082 property_enable(rphy->grf, &rport->port_cfg->idpullup,
1083 false);
1084 property_enable(rphy->grf, &rport->port_cfg->iddig_output,
1085 false);
1086 property_enable(rphy->grf, &rport->port_cfg->iddig_en,
1087 true);
1088 break;
1089 case USB_DR_MODE_PERIPHERAL:
1090 rockchip_usb2phy_set_mode(rport->phy, PHY_MODE_USB_DEVICE, 0);
1091 property_enable(rphy->grf, &rport->port_cfg->idpullup,
1092 true);
1093 property_enable(rphy->grf, &rport->port_cfg->iddig_output,
1094 true);
1095 property_enable(rphy->grf, &rport->port_cfg->iddig_en,
1096 true);
1097 break;
1098 case USB_DR_MODE_OTG:
1099 rockchip_usb2phy_set_mode(rport->phy, PHY_MODE_USB_OTG, 0);
1100 property_enable(rphy->grf, &rport->port_cfg->iddig_output,
1101 false);
1102 property_enable(rphy->grf, &rport->port_cfg->iddig_en,
1103 false);
1104 break;
1105 default:
1106 break;
1107 }
1108
1109
1110 if ((rport->mode == USB_DR_MODE_PERIPHERAL ||
1111 rport->mode == USB_DR_MODE_OTG) && property_enabled(rphy->grf,
1112 &rport->port_cfg->utmi_bvalid)) {
1113 rport->vbus_attached = true;
1114 cancel_delayed_work_sync(&rport->otg_sm_work);
1115 schedule_delayed_work(&rport->otg_sm_work, OTG_SCHEDULE_DELAY);
1116 }
1117 unlock:
1118 mutex_unlock(&rport->mutex);
1119
1120 exit:
1121 return rc;
1122 }
1123 static DEVICE_ATTR_RW(otg_mode);
1124
1125 /* Group all the usb2 phy attributes */
1126 static struct attribute *usb2_phy_attrs[] = {
1127 &dev_attr_otg_mode.attr,
1128 NULL,
1129 };
1130
1131 static struct attribute_group usb2_phy_attr_group = {
1132 .name = NULL, /* we want them in the same directory */
1133 .attrs = usb2_phy_attrs,
1134 };
1135
rockchip_usb2phy_bvalid_irq(int irq,void * data)1136 static irqreturn_t rockchip_usb2phy_bvalid_irq(int irq, void *data)
1137 {
1138 struct rockchip_usb2phy_port *rport = data;
1139 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
1140
1141 if (!property_enabled(rphy->grf, &rport->port_cfg->bvalidfall_det_st) &&
1142 !property_enabled(rphy->grf, &rport->port_cfg->bvalidrise_det_st))
1143 return IRQ_NONE;
1144
1145 mutex_lock(&rport->mutex);
1146
1147 /* clear bvalid fall or rise detect irq pending status */
1148 if (property_enabled(rphy->grf, &rport->port_cfg->bvalidfall_det_st)) {
1149 property_enable(rphy->grf, &rport->port_cfg->bvalidfall_det_clr,
1150 true);
1151 rport->vbus_attached = false;
1152 } else if (property_enabled(rphy->grf,
1153 &rport->port_cfg->bvalidrise_det_st)) {
1154 property_enable(rphy->grf, &rport->port_cfg->bvalidrise_det_clr,
1155 true);
1156 rport->vbus_attached = true;
1157 }
1158
1159 mutex_unlock(&rport->mutex);
1160
1161 cancel_delayed_work_sync(&rport->otg_sm_work);
1162 rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
1163
1164 return IRQ_HANDLED;
1165 }
1166
rockchip_usb2phy_id_irq(int irq,void * data)1167 static irqreturn_t rockchip_usb2phy_id_irq(int irq, void *data)
1168 {
1169 struct rockchip_usb2phy_port *rport = data;
1170 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
1171 bool cable_vbus_state = false;
1172
1173 if (!property_enabled(rphy->grf, &rport->port_cfg->idfall_det_st) &&
1174 !property_enabled(rphy->grf, &rport->port_cfg->idrise_det_st))
1175 return IRQ_NONE;
1176
1177 mutex_lock(&rport->mutex);
1178
1179 /* clear id fall or rise detect irq pending status */
1180 if (property_enabled(rphy->grf, &rport->port_cfg->idfall_det_st)) {
1181 property_enable(rphy->grf, &rport->port_cfg->idfall_det_clr,
1182 true);
1183 cable_vbus_state = true;
1184 } else if (property_enabled(rphy->grf,
1185 &rport->port_cfg->idrise_det_st)) {
1186 property_enable(rphy->grf, &rport->port_cfg->idrise_det_clr,
1187 true);
1188 cable_vbus_state = false;
1189 }
1190
1191 dev_dbg(&rport->phy->dev, "id %s interrupt\n",
1192 cable_vbus_state ? "fall" : "rise");
1193 extcon_set_state(rphy->edev, EXTCON_USB_HOST, cable_vbus_state);
1194 extcon_set_state(rphy->edev, EXTCON_USB_VBUS_EN, cable_vbus_state);
1195
1196 extcon_sync(rphy->edev, EXTCON_USB_HOST);
1197 extcon_sync(rphy->edev, EXTCON_USB_VBUS_EN);
1198
1199 rockchip_set_vbus_power(rport, cable_vbus_state);
1200
1201 mutex_unlock(&rport->mutex);
1202
1203 return IRQ_HANDLED;
1204 }
1205
rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy * rphy,struct rockchip_usb2phy_port * rport,struct device_node * child_np)1206 static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy,
1207 struct rockchip_usb2phy_port *rport,
1208 struct device_node *child_np)
1209 {
1210 int ret = 0;
1211 int iddig;
1212
1213 mutex_init(&rport->mutex);
1214
1215 rport->port_id = USB2PHY_PORT_OTG;
1216 rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
1217 rport->vbus_attached = false;
1218 rport->vbus_enabled = false;
1219 rport->prev_iddig = true;
1220
1221 rport->vbus_always_on =
1222 of_property_read_bool(child_np, "rockchip,vbus-always-on");
1223
1224 ret = rockchip_usb2phy_extcon_register(rphy);
1225 if (ret)
1226 return ret;
1227
1228 /* Get Vbus regulators */
1229 rport->vbus = devm_regulator_get_optional(&rport->phy->dev, "vbus");
1230 if (IS_ERR(rport->vbus)) {
1231 if (PTR_ERR(rport->vbus) == -EPROBE_DEFER)
1232 return -EPROBE_DEFER;
1233
1234 dev_warn(&rport->phy->dev,
1235 "Failed to get VBUS supply regulator\n");
1236 rport->vbus = NULL;
1237 }
1238
1239 /*
1240 * The default value of bypass_otgsuspendm is 1 that we must set
1241 * otg_suspendm and LS_PAR_EN by software when switching drd role.
1242 * So we disable the otg_suspend_bypass to let hardware auto-switch
1243 * device mode or host mode.
1244 */
1245 property_enable(rphy->grf, &rport->port_cfg->bypass_otgsuspendm,
1246 false);
1247
1248 /* Request linstate interrupt */
1249 rport->ls_irq = of_irq_get_byname(child_np, "linestate");
1250 if (rport->ls_irq <= 0) {
1251 dev_err(rphy->dev, "no linestate irq provided\n");
1252 return -EINVAL;
1253 }
1254
1255 ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL,
1256 rockchip_usb2phy_linestate_irq,
1257 IRQF_ONESHOT,
1258 "rockchip_usb2phy", rport);
1259 if (ret) {
1260 dev_err(rphy->dev, "failed to request linestate irq handle\n");
1261 return ret;
1262 }
1263
1264 rport->mode = of_usb_get_dr_mode_by_phy(child_np, -1);
1265 if (rport->mode == USB_DR_MODE_HOST) {
1266 if (rphy->edev_self) {
1267 extcon_set_state(rphy->edev, EXTCON_USB, false);
1268 extcon_set_state(rphy->edev, EXTCON_USB_HOST, true);
1269 }
1270 rockchip_usb2phy_set_mode(rport->phy, PHY_MODE_USB_HOST, 0);
1271 /*
1272 * Here set iddig to 0 by disable idpullup, the otg_suspendm
1273 * will be set to 1 to enable the disconnect detection module,
1274 * and the LS_PAR_EN will be set to 1 to enable low speed device
1275 * enumerate.
1276 */
1277 property_enable(rphy->grf, &rport->port_cfg->idpullup, false);
1278
1279 /* Request disconnect interrupt */
1280 rport->disconnect_irq = of_irq_get_byname(child_np,
1281 "disconnect");
1282 if (rport->disconnect_irq <= 0) {
1283 dev_err(rphy->dev, "no disconnect irq provided\n");
1284 return -EINVAL;
1285 }
1286
1287 ret = devm_request_threaded_irq(rphy->dev,
1288 rport->disconnect_irq, NULL,
1289 rockchip_usb2phy_disconnect_irq,
1290 IRQF_ONESHOT,
1291 "rockchip_usb2phy", rport);
1292 if (ret) {
1293 dev_err(rphy->dev,
1294 "failed to request disconnect irq handle\n");
1295 return ret;
1296 }
1297 goto out;
1298 }
1299
1300 /* Request otg iddig interrupt only if there is no extcon property */
1301 if (rphy->edev_self) {
1302 rport->id_irq = of_irq_get_byname(child_np, "otg-id");
1303 if (rport->id_irq <= 0) {
1304 dev_err(rphy->dev, "no otg id irq provided\n");
1305 return -EINVAL;
1306 }
1307
1308 ret = devm_request_threaded_irq(rphy->dev,
1309 rport->id_irq, NULL,
1310 rockchip_usb2phy_id_irq,
1311 IRQF_ONESHOT,
1312 "rockchip_usb2phy_id",
1313 rport);
1314 if (ret) {
1315 dev_err(rphy->dev,
1316 "failed to request otg-id irq handle\n");
1317 return ret;
1318 }
1319
1320 iddig = property_enabled(rphy->grf,
1321 &rport->port_cfg->utmi_iddig);
1322 if (!iddig) {
1323 extcon_set_state(rphy->edev, EXTCON_USB, false);
1324 extcon_set_state(rphy->edev, EXTCON_USB_HOST, true);
1325 extcon_set_state(rphy->edev, EXTCON_USB_VBUS_EN, true);
1326 /* Enable VBUS supply */
1327 ret = rockchip_set_vbus_power(rport, true);
1328 if (ret)
1329 return ret;
1330 }
1331 }
1332
1333 if (rport->vbus_always_on)
1334 goto out;
1335
1336 /* Request otg bvalid interrupt */
1337 rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid");
1338 if (rport->bvalid_irq <= 0) {
1339 dev_err(rphy->dev, "no vbus valid irq provided\n");
1340 return -EINVAL;
1341 }
1342
1343 ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq,
1344 NULL,
1345 rockchip_usb2phy_bvalid_irq,
1346 IRQF_ONESHOT,
1347 "rockchip_usb2phy_bvalid",
1348 rport);
1349 if (ret) {
1350 dev_err(rphy->dev,
1351 "failed to request otg-bvalid irq handle\n");
1352 return ret;
1353 }
1354
1355 INIT_DELAYED_WORK(&rport->otg_sm_work, rockchip_usb2phy_otg_sm_work);
1356
1357 out:
1358 /*
1359 * Let us put phy-port into suspend mode here for saving power
1360 * consumption, and usb controller will resume it during probe
1361 * time if needed.
1362 */
1363 ret = property_enable(rphy->grf, &rport->port_cfg->phy_sus, true);
1364 if (ret)
1365 return ret;
1366
1367 rport->suspended = true;
1368
1369 wake_lock_init(&rport->wakelock, WAKE_LOCK_SUSPEND, "rockchip_otg");
1370
1371 return ret;
1372 }
1373
rockchip_usb2phy_host_port_init(struct rockchip_usb2phy * rphy,struct rockchip_usb2phy_port * rport,struct device_node * child_np)1374 static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy,
1375 struct rockchip_usb2phy_port *rport,
1376 struct device_node *child_np)
1377 {
1378 int ret = 0;
1379
1380 mutex_init(&rport->mutex);
1381
1382 rport->port_id = USB2PHY_PORT_HOST;
1383 rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST];
1384
1385 /* Request disconnect interrupt */
1386 rport->disconnect_irq = of_irq_get_byname(child_np, "disconnect");
1387 if (rport->disconnect_irq <= 0) {
1388 dev_err(rphy->dev, "no disconnect irq provided\n");
1389 return -EINVAL;
1390 }
1391
1392 ret = devm_request_threaded_irq(rphy->dev, rport->disconnect_irq, NULL,
1393 rockchip_usb2phy_disconnect_irq,
1394 IRQF_ONESHOT,
1395 "rockchip_usb2phy", rport);
1396 if (ret) {
1397 dev_err(rphy->dev, "failed to request disconnect irq handle\n");
1398 return ret;
1399 }
1400
1401 /* Request linstate interrupt */
1402 rport->ls_irq = of_irq_get_byname(child_np, "linestate");
1403 if (rport->ls_irq <= 0) {
1404 dev_err(rphy->dev, "no linestate irq provided\n");
1405 return -EINVAL;
1406 }
1407
1408 ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL,
1409 rockchip_usb2phy_linestate_irq,
1410 IRQF_ONESHOT,
1411 "rockchip_usb2phy", rport);
1412 if (ret) {
1413 dev_err(rphy->dev, "failed to request linestate irq handle\n");
1414 return ret;
1415 }
1416
1417 /*
1418 * Let us put phy-port into suspend mode here for saving power
1419 * consumption, and usb controller will resume it during probe
1420 * time if needed.
1421 */
1422 ret = property_enable(rphy->grf, &rport->port_cfg->phy_sus, true);
1423 if (ret)
1424 return ret;
1425
1426 rport->suspended = true;
1427
1428 return ret;
1429 }
1430
rockchip_usb2phy_probe(struct platform_device * pdev)1431 static int rockchip_usb2phy_probe(struct platform_device *pdev)
1432 {
1433 struct device *dev = &pdev->dev;
1434 struct device_node *np = dev->of_node;
1435 struct device_node *child_np;
1436 struct phy_provider *provider;
1437 struct rockchip_usb2phy *rphy;
1438 const struct rockchip_usb2phy_cfg *phy_cfgs;
1439 const struct of_device_id *match;
1440 unsigned int reg;
1441 unsigned int index;
1442 struct resource *res;
1443 int ret = 0;
1444
1445 rphy = devm_kzalloc(dev, sizeof(*rphy), GFP_KERNEL);
1446 if (!rphy)
1447 return -ENOMEM;
1448
1449 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1450 if (!res) {
1451 dev_err(dev, "missing memory resource\n");
1452 return -ENODEV;
1453 }
1454
1455 rphy->base = devm_ioremap_resource(dev, res);
1456 if (IS_ERR(rphy->base)) {
1457 dev_err(dev, "failed to remap phy regs\n");
1458 return PTR_ERR(rphy->base);
1459 }
1460
1461 rphy->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1462 if (IS_ERR(rphy->grf))
1463 return PTR_ERR(rphy->grf);
1464
1465 /* Get PHY power reset */
1466 rphy->reset = devm_reset_control_get(dev, "u2phy");
1467 if (IS_ERR(rphy->reset))
1468 return PTR_ERR(rphy->reset);
1469
1470 rphy->vup_gpio = devm_gpiod_get_optional(dev, "vup", GPIOD_OUT_LOW);
1471 if (IS_ERR(rphy->vup_gpio)) {
1472 ret = PTR_ERR(rphy->vup_gpio);
1473 dev_err(dev, "failed to get vup gpio (%d)\n", ret);
1474 return ret;
1475 }
1476
1477 reset_control_assert(rphy->reset);
1478 udelay(1);
1479 reset_control_deassert(rphy->reset);
1480
1481 match = of_match_device(dev->driver->of_match_table, dev);
1482 if (!match || !match->data) {
1483 dev_err(dev, "phy configs are not assigned!\n");
1484 return -EINVAL;
1485 }
1486
1487 if (of_property_read_u32(np, "reg", ®)) {
1488 dev_err(dev, "the reg property is not assigned in %s node\n",
1489 np->name);
1490 return -EINVAL;
1491 }
1492
1493 rphy->dev = dev;
1494 phy_cfgs = match->data;
1495
1496 /* find out a proper config which can be matched with dt. */
1497 index = 0;
1498 do {
1499 if (phy_cfgs[index].reg == reg) {
1500 rphy->phy_cfg = &phy_cfgs[index];
1501 break;
1502 }
1503 } while (!phy_cfgs[index++].last);
1504
1505 if (!rphy->phy_cfg) {
1506 dev_err(dev, "no phy-config can be matched with %s node\n",
1507 np->name);
1508 return -EINVAL;
1509 }
1510
1511 rphy->num_clks = rphy->phy_cfg->num_clks;
1512
1513 rphy->clks = devm_kmemdup(dev, rphy->phy_cfg->clks,
1514 rphy->num_clks * sizeof(struct clk_bulk_data),
1515 GFP_KERNEL);
1516
1517 if (!rphy->clks)
1518 return -ENOMEM;
1519
1520 ret = devm_clk_bulk_get(dev, rphy->num_clks, rphy->clks);
1521 if (ret == -EPROBE_DEFER)
1522 return -EPROBE_DEFER;
1523 if (ret)
1524 rphy->num_clks = 0;
1525
1526 ret = clk_bulk_prepare_enable(rphy->num_clks, rphy->clks);
1527 if (ret)
1528 return ret;
1529
1530 platform_set_drvdata(pdev, rphy);
1531
1532 if (rphy->phy_cfg->phy_tuning) {
1533 ret = rphy->phy_cfg->phy_tuning(rphy);
1534 if (ret)
1535 goto disable_clks;
1536 }
1537
1538 index = 0;
1539 for_each_available_child_of_node(np, child_np) {
1540 struct rockchip_usb2phy_port *rport = &rphy->ports[index];
1541 struct phy *phy;
1542
1543 /* This driver aims to support both otg-port and host-port */
1544 if (of_node_cmp(child_np->name, "host-port") &&
1545 of_node_cmp(child_np->name, "otg-port"))
1546 goto next_child;
1547
1548 if (rphy->vup_gpio &&
1549 of_device_is_compatible(np, "rockchip,rv1126-usb2phy")) {
1550 rockchip_usb2phy_ops.calibrate =
1551 rv1126_usb2phy_calibrate;
1552 hrtimer_init(&rphy->wait_timer, CLOCK_MONOTONIC,
1553 HRTIMER_MODE_REL);
1554 rphy->wait_timer.function = &rv1126_wait_timer_fn;
1555 }
1556
1557 phy = devm_phy_create(dev, child_np, &rockchip_usb2phy_ops);
1558 if (IS_ERR(phy)) {
1559 dev_err(dev, "failed to create phy\n");
1560 ret = PTR_ERR(phy);
1561 goto put_child;
1562 }
1563
1564 rport->phy = phy;
1565 phy_set_drvdata(rport->phy, rport);
1566
1567 /* initialize otg/host port separately */
1568 if (!of_node_cmp(child_np->name, "host-port")) {
1569 ret = rockchip_usb2phy_host_port_init(rphy, rport,
1570 child_np);
1571 if (ret)
1572 goto put_child;
1573 } else {
1574 ret = rockchip_usb2phy_otg_port_init(rphy, rport,
1575 child_np);
1576 if (ret)
1577 goto put_child;
1578 }
1579
1580 next_child:
1581 /* to prevent out of boundary */
1582 if (++index >= rphy->phy_cfg->num_ports)
1583 break;
1584 }
1585
1586 provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1587 if (IS_ERR_OR_NULL(provider))
1588 goto put_child;
1589
1590 /* Attributes */
1591 ret = sysfs_create_group(&dev->kobj, &usb2_phy_attr_group);
1592 if (ret) {
1593 dev_err(dev, "Cannot create sysfs group: %d\n", ret);
1594 goto put_child;
1595 }
1596
1597 ret = rockchip_usb2phy_clk480m_register(rphy);
1598 if (ret) {
1599 dev_err(dev, "failed to register 480m output clock\n");
1600 goto put_child;
1601 }
1602
1603 if (of_property_read_bool(np, "wakeup-source"))
1604 device_init_wakeup(rphy->dev, true);
1605 else
1606 device_init_wakeup(rphy->dev, false);
1607
1608 return 0;
1609
1610 put_child:
1611 of_node_put(child_np);
1612 disable_clks:
1613 clk_bulk_disable_unprepare(rphy->num_clks, rphy->clks);
1614
1615 return ret;
1616 }
1617
rockchip_usb2phy_remove(struct platform_device * pdev)1618 static int rockchip_usb2phy_remove(struct platform_device *pdev)
1619 {
1620 struct device_node *np = pdev->dev.of_node;
1621 struct rockchip_usb2phy *rphy = platform_get_drvdata(pdev);
1622
1623 if (rphy->vup_gpio &&
1624 of_device_is_compatible(np, "rockchip,rv1126-usb2phy"))
1625 hrtimer_cancel(&rphy->wait_timer);
1626
1627 return 0;
1628 }
1629
rv1126_usb2phy_tuning(struct rockchip_usb2phy * rphy)1630 static int rv1126_usb2phy_tuning(struct rockchip_usb2phy *rphy)
1631 {
1632 int ret = 0;
1633 u32 rcal, reg;
1634
1635 if (rphy->phy_cfg->reg == 0xff4c0000) {
1636 /* set iddig interrupt filter time to 10ms */
1637 ret = regmap_write(rphy->grf, 0x1031c, 0x000f4240);
1638 if (ret)
1639 goto out;
1640
1641 /* set pready_cnt to 1 and rden_cnt to 0 */
1642 ret = regmap_write(rphy->grf, 0x1027c, 0x0f0f0100);
1643 if (ret)
1644 goto out;
1645
1646 reg = readl(rphy->base + 0x10);
1647 /* Enable Rterm self calibration and wait for rcal trim done */
1648 writel(reg & ~BIT(2), rphy->base + 0x10);
1649 /*
1650 * If Rterm is disconnected, self calibration will fail and
1651 * rcal trim done will be set in about 3.5 us
1652 */
1653 udelay(10);
1654 if (readl(rphy->base + 0x34) & BIT(4)) {
1655 dev_dbg(rphy->dev, "Rterm disconnected");
1656 } else {
1657 ret = readl_poll_timeout(rphy->base + 0x34, rcal,
1658 rcal & BIT(4),
1659 100, 600);
1660 if (ret == -ETIMEDOUT)
1661 dev_err(rphy->dev, "Rterm calibration timeout");
1662 else
1663 /* Use rcal out calibration code */
1664 reg = (reg & ~(0x0f << 3)) |
1665 ((rcal & 0x0f) << 3);
1666 }
1667 /* Disable Rterm self calibration */
1668 writel(reg | BIT(2), rphy->base + 0x10);
1669 }
1670
1671 if (rphy->phy_cfg->reg == 0xff4c8000) {
1672 /* set pready_cnt to 1 and rden_cnt to 0 */
1673 ret = regmap_write(rphy->grf, 0x1028c, 0x0f0f0100);
1674 if (ret)
1675 goto out;
1676 }
1677
1678 out:
1679 return ret;
1680 }
1681
rv1126_usb2phy_low_power(struct rockchip_usb2phy * rphy,bool en)1682 static int rv1126_usb2phy_low_power(struct rockchip_usb2phy *rphy, bool en)
1683 {
1684 unsigned int reg;
1685
1686 reg = readl(rphy->base + 0x20);
1687 /* bypass or enable bc detect */
1688 reg = en ? reg | BIT(5) : reg & ~BIT(5);
1689 writel(reg, rphy->base + 0x20);
1690
1691 return 0;
1692 }
1693
1694 static const struct clk_bulk_data rv1126_clks[] = {
1695 { .id = "phyclk" },
1696 { .id = "pclk" },
1697 };
1698
1699 #ifdef CONFIG_PM_SLEEP
rockchip_usb2phy_pm_suspend(struct device * dev)1700 static int rockchip_usb2phy_pm_suspend(struct device *dev)
1701 {
1702 int ret = 0;
1703 struct rockchip_usb2phy *rphy = dev_get_drvdata(dev);
1704 struct rockchip_usb2phy_port *rport;
1705 unsigned int index;
1706 bool wakeup_enable = false;
1707
1708 if (device_may_wakeup(rphy->dev))
1709 wakeup_enable = true;
1710
1711 for (index = 0; index < rphy->phy_cfg->num_ports; index++) {
1712 rport = &rphy->ports[index];
1713 if (!rport->phy)
1714 continue;
1715
1716 if (rport->port_id == USB2PHY_PORT_OTG &&
1717 rport->id_irq > 0) {
1718 mutex_lock(&rport->mutex);
1719 rport->prev_iddig =
1720 property_enabled(rphy->grf,
1721 &rport->port_cfg->utmi_iddig);
1722 ret = rockchip_usb2phy_enable_id_irq(rphy, rport,
1723 false);
1724 mutex_unlock(&rport->mutex);
1725 if (ret) {
1726 dev_err(rphy->dev,
1727 "failed to disable id irq\n");
1728 return ret;
1729 }
1730 }
1731
1732 if (rport->port_id == USB2PHY_PORT_OTG && wakeup_enable &&
1733 rport->bvalid_irq > 0)
1734 enable_irq_wake(rport->bvalid_irq);
1735
1736 /* activate the linestate to detect the remove wakeup. */
1737 mutex_lock(&rport->mutex);
1738 ret = rockchip_usb2phy_enable_line_irq(rphy, rport, true);
1739 mutex_unlock(&rport->mutex);
1740 if (ret) {
1741 dev_err(rphy->dev, "failed to enable linestate irq\n");
1742 return ret;
1743 }
1744
1745 if (wakeup_enable && rport->ls_irq > 0)
1746 enable_irq_wake(rport->ls_irq);
1747 }
1748
1749 /* enter low power state */
1750 if (rphy->phy_cfg->phy_lowpower)
1751 ret = rphy->phy_cfg->phy_lowpower(rphy, true);
1752
1753 return ret;
1754 }
1755
rockchip_usb2phy_pm_resume(struct device * dev)1756 static int rockchip_usb2phy_pm_resume(struct device *dev)
1757 {
1758 int ret = 0;
1759 struct rockchip_usb2phy *rphy = dev_get_drvdata(dev);
1760 struct rockchip_usb2phy_port *rport;
1761 unsigned int index;
1762 bool iddig;
1763 bool wakeup_enable = false;
1764
1765 if (device_may_wakeup(rphy->dev))
1766 wakeup_enable = true;
1767
1768 /* exit low power state */
1769 if (rphy->phy_cfg->phy_lowpower)
1770 ret = rphy->phy_cfg->phy_lowpower(rphy, false);
1771
1772 for (index = 0; index < rphy->phy_cfg->num_ports; index++) {
1773 rport = &rphy->ports[index];
1774 if (!rport->phy)
1775 continue;
1776
1777 if (rport->port_id == USB2PHY_PORT_OTG &&
1778 rport->id_irq > 0) {
1779 mutex_lock(&rport->mutex);
1780 iddig = property_enabled(rphy->grf,
1781 &rport->port_cfg->utmi_iddig);
1782 ret = rockchip_usb2phy_enable_id_irq(rphy, rport,
1783 true);
1784 mutex_unlock(&rport->mutex);
1785 if (ret) {
1786 dev_err(rphy->dev,
1787 "failed to enable id irq\n");
1788 return ret;
1789 }
1790
1791 if (iddig != rport->prev_iddig) {
1792 dev_dbg(&rport->phy->dev,
1793 "iddig changed during resume\n");
1794 rport->prev_iddig = iddig;
1795 extcon_set_state_sync(rphy->edev,
1796 EXTCON_USB_HOST,
1797 !iddig);
1798 extcon_set_state_sync(rphy->edev,
1799 EXTCON_USB_VBUS_EN,
1800 !iddig);
1801 ret = rockchip_set_vbus_power(rport, !iddig);
1802 if (ret)
1803 return ret;
1804 }
1805 }
1806
1807 if (rport->port_id == USB2PHY_PORT_OTG && wakeup_enable &&
1808 rport->bvalid_irq > 0)
1809 disable_irq_wake(rport->bvalid_irq);
1810
1811 if (wakeup_enable && rport->ls_irq > 0)
1812 disable_irq_wake(rport->ls_irq);
1813 }
1814
1815 return ret;
1816 }
1817
1818 static const struct dev_pm_ops rockchip_usb2phy_dev_pm_ops = {
1819 SET_SYSTEM_SLEEP_PM_OPS(rockchip_usb2phy_pm_suspend,
1820 rockchip_usb2phy_pm_resume)
1821 };
1822
1823 #define ROCKCHIP_USB2PHY_DEV_PM (&rockchip_usb2phy_dev_pm_ops)
1824 #else
1825 #define ROCKCHIP_USB2PHY_DEV_PM NULL
1826 #endif
1827
1828 static const struct rockchip_usb2phy_cfg rv1126_phy_cfgs[] = {
1829 {
1830 .reg = 0xff4c0000,
1831 .num_ports = 1,
1832 .phy_tuning = rv1126_usb2phy_tuning,
1833 .phy_lowpower = rv1126_usb2phy_low_power,
1834 .num_clks = 2,
1835 .clks = rv1126_clks,
1836 .clkout_ctl = { 0x10230, 14, 14, 0, 1 },
1837 .port_cfgs = {
1838 [USB2PHY_PORT_OTG] = {
1839 .bypass_otgsuspendm = { 0x10234, 12, 12, 0, 1 },
1840 .bvalidfall_det_en = { 0x10300, 3, 3, 0, 1 },
1841 .bvalidfall_det_st = { 0x10304, 3, 3, 0, 1 },
1842 .bvalidfall_det_clr = { 0x10308, 3, 3, 0, 1 },
1843 .bvalidrise_det_en = { 0x10300, 2, 2, 0, 1 },
1844 .bvalidrise_det_st = { 0x10304, 2, 2, 0, 1 },
1845 .bvalidrise_det_clr = { 0x10308, 2, 2, 0, 1 },
1846 .disconfall_det_en = { 0x10300, 7, 7, 0, 1 },
1847 .disconfall_det_st = { 0x10304, 7, 7, 0, 1 },
1848 .disconfall_det_clr = { 0x10308, 7, 7, 0, 1 },
1849 .disconrise_det_en = { 0x10300, 6, 6, 0, 1 },
1850 .disconrise_det_st = { 0x10304, 6, 6, 0, 1 },
1851 .disconrise_det_clr = { 0x10308, 6, 6, 0, 1 },
1852 .idfall_det_en = { 0x10300, 5, 5, 0, 1 },
1853 .idfall_det_st = { 0x10304, 5, 5, 0, 1 },
1854 .idfall_det_clr = { 0x10308, 5, 5, 0, 1 },
1855 .idpullup = { 0x10230, 11, 11, 0, 1 },
1856 .iddig_output = { 0x10230, 10, 10, 0, 1 },
1857 .iddig_en = { 0x10230, 9, 9, 0, 1 },
1858 .idrise_det_en = { 0x10300, 4, 4, 0, 1 },
1859 .idrise_det_st = { 0x10304, 4, 4, 0, 1 },
1860 .idrise_det_clr = { 0x10308, 4, 4, 0, 1 },
1861 .ls_det_en = { 0x10300, 0, 0, 0, 1 },
1862 .ls_det_st = { 0x10304, 0, 0, 0, 1 },
1863 .ls_det_clr = { 0x10308, 0, 0, 0, 1 },
1864 .phy_sus = { 0x10230, 8, 0, 0x052, 0x1d5 },
1865 .utmi_bvalid = { 0x10248, 9, 9, 0, 1 },
1866 .utmi_iddig = { 0x10248, 6, 6, 0, 1 },
1867 .utmi_hostdet = { 0x10248, 7, 7, 0, 1 },
1868 }
1869 },
1870 .chg_det = {
1871 .chg_en = { 0x10234, 14, 14, 0, 1 },
1872 .chg_rst = { 0x10234, 15, 15, 0, 1 },
1873 .chg_valid = { 0x10248, 12, 12, 0, 1 },
1874 .phy_connect = { 0x10248, 13, 13, 0, 1 },
1875 },
1876 },
1877 {
1878 .reg = 0xff4c8000,
1879 .num_ports = 1,
1880 .phy_tuning = rv1126_usb2phy_tuning,
1881 .phy_lowpower = rv1126_usb2phy_low_power,
1882 .num_clks = 2,
1883 .clks = rv1126_clks,
1884 .clkout_ctl = { 0x10238, 9, 9, 0, 1 },
1885 .port_cfgs = {
1886 [USB2PHY_PORT_HOST] = {
1887 .disconfall_det_en = { 0x10300, 9, 9, 0, 1 },
1888 .disconfall_det_st = { 0x10304, 9, 9, 0, 1 },
1889 .disconfall_det_clr = { 0x10308, 9, 9, 0, 1 },
1890 .disconrise_det_en = { 0x10300, 8, 8, 0, 1 },
1891 .disconrise_det_st = { 0x10304, 8, 8, 0, 1 },
1892 .disconrise_det_clr = { 0x10308, 8, 8, 0, 1 },
1893 .ls_det_en = { 0x10300, 1, 1, 0, 1 },
1894 .ls_det_st = { 0x10304, 1, 1, 0, 1 },
1895 .ls_det_clr = { 0x10308, 1, 1, 0, 1 },
1896 .phy_sus = { 0x10238, 3, 0, 0x2, 0x5 },
1897 .utmi_hostdet = { 0x10248, 23, 23, 0, 1 },
1898 }
1899 },
1900 .chg_det = {
1901 .chg_en = { 0x10238, 7, 7, 0, 1 },
1902 .chg_rst = { 0x10238, 8, 8, 0, 1 },
1903 .chg_valid = { 0x10248, 28, 28, 0, 1 },
1904 .phy_connect = { 0x10248, 29, 29, 0, 1 },
1905 },
1906 .last = true,
1907 },
1908 };
1909
1910 static const struct of_device_id rockchip_usb2phy_dt_match[] = {
1911 { .compatible = "rockchip,rv1126-usb2phy", .data = &rv1126_phy_cfgs },
1912 {}
1913 };
1914 MODULE_DEVICE_TABLE(of, rockchip_usb2phy_dt_match);
1915
1916 static struct platform_driver rockchip_usb2phy_driver = {
1917 .probe = rockchip_usb2phy_probe,
1918 .remove = rockchip_usb2phy_remove,
1919 .driver = {
1920 .name = "rockchip-usb2phy-naneng",
1921 .pm = ROCKCHIP_USB2PHY_DEV_PM,
1922 .of_match_table = rockchip_usb2phy_dt_match,
1923 },
1924 };
1925 module_platform_driver(rockchip_usb2phy_driver);
1926
1927 MODULE_AUTHOR("Jianing Ren <jianing.ren@rock-chips.com>");
1928 MODULE_DESCRIPTION("Rockchip USB2.0 Naneng PHY driver");
1929 MODULE_LICENSE("GPL v2");
1930