1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2020 Rockchip Electronics Co., Ltd
4 */
5 #include <linux/clk.h>
6 #include <linux/delay.h>
7 #include <linux/initramfs.h>
8 #include <linux/interrupt.h>
9 #include <linux/kernel.h>
10 #include <linux/mm.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/of_address.h>
14 #include <linux/of_device.h>
15 #include <linux/platform_device.h>
16 #include <linux/reset.h>
17 #include <linux/soc/rockchip/rockchip_decompress.h>
18
19 #define DECOM_CTRL 0x0
20 #define DECOM_ENR 0x4
21 #define DECOM_RADDR 0x8
22 #define DECOM_WADDR 0xc
23 #define DECOM_UDDSL 0x10
24 #define DECOM_UDDSH 0x14
25 #define DECOM_TXTHR 0x18
26 #define DECOM_RXTHR 0x1c
27 #define DECOM_SLEN 0x20
28 #define DECOM_STAT 0x24
29 #define DECOM_ISR 0x28
30 #define DECOM_IEN 0x2c
31 #define DECOM_AXI_STAT 0x30
32 #define DECOM_TSIZEL 0x34
33 #define DECOM_TSIZEH 0x38
34 #define DECOM_MGNUM 0x3c
35 #define DECOM_FRAME 0x40
36 #define DECOM_DICTID 0x44
37 #define DECOM_CSL 0x48
38 #define DECOM_CSH 0x4c
39 #define DECOM_LMTSL 0x50
40 #define DECOM_LMTSH 0x54
41
42 #define LZ4_HEAD_CSUM_CHECK_EN BIT(1)
43 #define LZ4_BLOCK_CSUM_CHECK_EN BIT(2)
44 #define LZ4_CONT_CSUM_CHECK_EN BIT(3)
45
46 #define DSOLIEN BIT(19)
47 #define ZDICTEIEN BIT(18)
48 #define GCMEIEN BIT(17)
49 #define GIDEIEN BIT(16)
50 #define CCCEIEN BIT(15)
51 #define BCCEIEN BIT(14)
52 #define HCCEIEN BIT(13)
53 #define CSEIEN BIT(12)
54 #define DICTEIEN BIT(11)
55 #define VNEIEN BIT(10)
56 #define WNEIEN BIT(9)
57 #define RDCEIEN BIT(8)
58 #define WRCEIEN BIT(7)
59 #define DISEIEN BIT(6)
60 #define LENEIEN BIT(5)
61 #define LITEIEN BIT(4)
62 #define SQMEIEN BIT(3)
63 #define SLCIEN BIT(2)
64 #define HDEIEN BIT(1)
65 #define DSIEN BIT(0)
66
67 #define DECOM_STOP BIT(0)
68 #define DECOM_COMPLETE BIT(0)
69 #define DECOM_GZIP_MODE BIT(4)
70 #define DECOM_ZLIB_MODE BIT(5)
71 #define DECOM_DEFLATE_MODE BIT(0)
72
73 #define DECOM_ENABLE 0x1
74 #define DECOM_DISABLE 0x0
75
76 #define DECOM_INT_MASK \
77 (DSOLIEN | ZDICTEIEN | GCMEIEN | GIDEIEN | \
78 CCCEIEN | BCCEIEN | HCCEIEN | CSEIEN | \
79 DICTEIEN | VNEIEN | WNEIEN | RDCEIEN | WRCEIEN | \
80 DISEIEN | LENEIEN | LITEIEN | SQMEIEN | SLCIEN | \
81 HDEIEN | DSIEN)
82
83 struct rk_decom {
84 struct device *dev;
85 int irq;
86 int num_clocks;
87 struct clk_bulk_data *clocks;
88 void __iomem *regs;
89 phys_addr_t mem_start;
90 size_t mem_size;
91 struct reset_control *reset;
92 };
93
94 static struct rk_decom *g_decom;
95
96 static DECLARE_WAIT_QUEUE_HEAD(initrd_decom_done);
97 static bool initrd_continue;
98
wait_initrd_hw_decom_done(void)99 void __init wait_initrd_hw_decom_done(void)
100 {
101 wait_event(initrd_decom_done, initrd_continue);
102 }
103
104 static DECLARE_WAIT_QUEUE_HEAD(decom_init_done);
105
rk_decom_start(u32 mode,phys_addr_t src,phys_addr_t dst,u32 dst_max_size)106 int rk_decom_start(u32 mode, phys_addr_t src, phys_addr_t dst, u32 dst_max_size)
107 {
108 u32 irq_status;
109 u32 decom_enr;
110
111 pr_info("%s: mode %u src %pa dst %pa max_size %u\n",
112 __func__, mode, &src, &dst, dst_max_size);
113
114 wait_event_timeout(decom_init_done, g_decom, HZ);
115 if (!g_decom)
116 return -EINVAL;
117
118 decom_enr = readl(g_decom->regs + DECOM_ENR);
119 if (decom_enr & 0x1) {
120 pr_err("decompress busy\n");
121 return -EBUSY;
122 }
123
124 if (g_decom->reset) {
125 reset_control_assert(g_decom->reset);
126 udelay(10);
127 reset_control_deassert(g_decom->reset);
128 }
129
130 irq_status = readl(g_decom->regs + DECOM_ISR);
131 /* clear interrupts */
132 if (irq_status)
133 writel(irq_status, g_decom->regs + DECOM_ISR);
134
135 switch (mode) {
136 case LZ4_MOD:
137 writel(LZ4_CONT_CSUM_CHECK_EN |
138 LZ4_HEAD_CSUM_CHECK_EN |
139 LZ4_BLOCK_CSUM_CHECK_EN |
140 LZ4_MOD, g_decom->regs + DECOM_CTRL);
141 break;
142 case GZIP_MOD:
143 writel(DECOM_DEFLATE_MODE | DECOM_GZIP_MODE,
144 g_decom->regs + DECOM_CTRL);
145 break;
146 case ZLIB_MOD:
147 writel(DECOM_DEFLATE_MODE | DECOM_ZLIB_MODE,
148 g_decom->regs + DECOM_CTRL);
149 break;
150 default:
151 pr_err("undefined mode : %d\n", mode);
152 return -EINVAL;
153 }
154
155 writel(src, g_decom->regs + DECOM_RADDR);
156 writel(dst, g_decom->regs + DECOM_WADDR);
157
158 writel(dst_max_size, g_decom->regs + DECOM_LMTSL);
159 writel(0x0, g_decom->regs + DECOM_LMTSH);
160
161 writel(DECOM_INT_MASK, g_decom->regs + DECOM_IEN);
162 writel(DECOM_ENABLE, g_decom->regs + DECOM_ENR);
163
164 pr_info("%s: started\n", __func__);
165
166 return 0;
167 }
168 EXPORT_SYMBOL(rk_decom_start);
169
rk_decom_irq_handler(int irq,void * priv)170 static irqreturn_t rk_decom_irq_handler(int irq, void *priv)
171 {
172 struct rk_decom *rk_dec = priv;
173 u32 irq_status;
174 u32 decom_status;
175
176 irq_status = readl(rk_dec->regs + DECOM_ISR);
177 /* clear interrupts */
178 writel(irq_status, rk_dec->regs + DECOM_ISR);
179 if (irq_status & DECOM_STOP) {
180 decom_status = readl(rk_dec->regs + DECOM_STAT);
181 if (decom_status & DECOM_COMPLETE) {
182 initrd_continue = true;
183 wake_up(&initrd_decom_done);
184 dev_info(rk_dec->dev, "decom completed\n");
185 } else {
186 dev_info(rk_dec->dev,
187 "decom failed, irq_status = 0x%x, decom_status = 0x%x, try again !\n",
188 irq_status, decom_status);
189
190 print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET,
191 32, 4, rk_dec->regs, 0x128, false);
192
193 writel(DECOM_ENABLE, rk_dec->regs + DECOM_ENR);
194 }
195 }
196
197 return IRQ_WAKE_THREAD;
198 }
199
rk_decom_irq_thread(int irq,void * priv)200 static irqreturn_t rk_decom_irq_thread(int irq, void *priv)
201 {
202 struct rk_decom *rk_dec = priv;
203
204 if (initrd_continue) {
205 void *start, *end;
206
207 /*
208 * Now it is safe to free reserve memory that
209 * store the origin ramdisk file
210 */
211 start = phys_to_virt(rk_dec->mem_start);
212 end = start + rk_dec->mem_size;
213 free_reserved_area(start, end, -1, "ramdisk gzip archive");
214 clk_bulk_disable_unprepare(rk_dec->num_clocks, rk_dec->clocks);
215 }
216
217 return IRQ_HANDLED;
218 }
219
rockchip_decom_probe(struct platform_device * pdev)220 static int __init rockchip_decom_probe(struct platform_device *pdev)
221 {
222 struct rk_decom *rk_dec;
223 struct resource *res = NULL;
224 struct device *dev = &pdev->dev;
225 struct device_node *np = dev->of_node;
226 struct device_node *mem;
227 struct resource reg;
228 int ret = 0;
229
230 rk_dec = devm_kzalloc(dev, sizeof(*rk_dec), GFP_KERNEL);
231 if (!rk_dec)
232 return -ENOMEM;
233
234 rk_dec->dev = dev;
235 rk_dec->irq = platform_get_irq(pdev, 0);
236 if (rk_dec->irq < 0) {
237 dev_err(dev, "failed to get rk_dec irq\n");
238 return -ENOENT;
239 }
240
241 mem = of_parse_phandle(np, "memory-region", 0);
242 if (!mem) {
243 dev_err(dev, "missing \"memory-region\" property\n");
244 return -ENODEV;
245 }
246
247 ret = of_address_to_resource(mem, 0, ®);
248 of_node_put(mem);
249 if (ret) {
250 dev_err(dev, "missing \"reg\" property\n");
251 return -ENODEV;
252 }
253
254 rk_dec->mem_start = reg.start;
255 rk_dec->mem_size = resource_size(®);
256
257 rk_dec->num_clocks = devm_clk_bulk_get_all(dev, &rk_dec->clocks);
258 if (rk_dec->num_clocks < 0) {
259 dev_err(dev, "failed to get decompress clock\n");
260 return -ENODEV;
261 }
262
263 ret = clk_bulk_prepare_enable(rk_dec->num_clocks, rk_dec->clocks);
264 if (ret)
265 return ret;
266
267 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
268 rk_dec->regs = devm_ioremap_resource(dev, res);
269 if (IS_ERR(rk_dec->regs)) {
270 ret = PTR_ERR(rk_dec->regs);
271 goto disable_clk;
272 }
273
274 dev_set_drvdata(dev, rk_dec);
275
276 rk_dec->reset = devm_reset_control_get_exclusive(dev, "dresetn");
277 if (IS_ERR(rk_dec->reset)) {
278 ret = PTR_ERR(rk_dec->reset);
279 if (ret != -ENOENT)
280 return ret;
281
282 dev_dbg(dev, "no reset control found\n");
283 rk_dec->reset = NULL;
284 }
285
286 ret = devm_request_threaded_irq(dev, rk_dec->irq, rk_decom_irq_handler,
287 rk_decom_irq_thread, IRQF_ONESHOT,
288 dev_name(dev), rk_dec);
289 if (ret < 0) {
290 dev_err(dev, "failed to attach decompress irq\n");
291 goto disable_clk;
292 }
293
294 g_decom = rk_dec;
295 wake_up(&decom_init_done);
296
297 return 0;
298
299 disable_clk:
300 clk_bulk_disable_unprepare(rk_dec->num_clocks, rk_dec->clocks);
301
302 return ret;
303 }
304
305 #ifdef CONFIG_OF
306 static const struct of_device_id rockchip_decom_dt_match[] = {
307 { .compatible = "rockchip,hw-decompress" },
308 {},
309 };
310 #endif
311
312 static struct platform_driver rk_decom_driver = {
313 .driver = {
314 .name = "rockchip_hw_decompress",
315 .of_match_table = rockchip_decom_dt_match,
316 },
317 };
318
rockchip_hw_decompress_init(void)319 static int __init rockchip_hw_decompress_init(void)
320 {
321 struct device_node *node;
322
323 node = of_find_matching_node(NULL, rockchip_decom_dt_match);
324 if (node) {
325 of_platform_device_create(node, NULL, NULL);
326 of_node_put(node);
327 return platform_driver_probe(&rk_decom_driver, rockchip_decom_probe);
328 }
329
330 return 0;
331 }
332
333 pure_initcall(rockchip_hw_decompress_init);
334