1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 /* 3 * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6 #ifndef _DT_BINDINGS_DRAM_ROCKCHIP_H 7 #define _DT_BINDINGS_DRAM_ROCKCHIP_H 8 9 #define DDR2_DS_FULL (0x0) 10 #define DDR2_DS_REDUCE (0x1 << 1) 11 #define DDR2_DS_MASK (0x1 << 1) 12 13 #define DDR2_ODT_DIS (0x0) 14 #define DDR2_ODT_75ohm (0x1 << 2) 15 #define DDR2_ODT_150ohm (0x1 << 6) 16 #define DDR2_ODT_50ohm ((0x1 << 6) | (0x1 << 2)) /* optional */ 17 #define DDR2_ODT_MASK ((0x1 << 2) | (0x1 << 6)) 18 19 #define DDR3_DS_40ohm (0x0) 20 #define DDR3_DS_34ohm (0x1 << 1) 21 #define DDR3_DS_MASK ((1 << 1) | (1 << 5)) 22 23 #define DDR3_ODT_DIS (0x0) 24 #define DDR3_ODT_60ohm (0x1 << 2) 25 #define DDR3_ODT_120ohm (0x1 << 6) 26 #define DDR3_ODT_40ohm ((0x1 << 6) | (0x1 << 2)) 27 #define DDR3_ODT_MASK ((0x1 << 2) | (0x1 << 6) | (0x1 << 9)) 28 29 #define DDR4_DS_34ohm (0x0) 30 #define DDR4_DS_48ohm (0x1 << 1) 31 #define DDR4_DS_MASK (0x3 << 1) 32 33 #define DDR4_ODT_DIS (0x0) 34 #define DDR4_ODT_60ohm (0x1 << 8) 35 #define DDR4_ODT_120ohm (0x2 << 8) 36 #define DDR4_ODT_40ohm (0x3 << 8) 37 #define DDR4_ODT_240ohm (0x4 << 8) 38 #define DDR4_ODT_48ohm (0x5 << 8) 39 #define DDR4_ODT_80ohm (0x6 << 8) 40 #define DDR4_ODT_34ohm (0x7 << 8) 41 #define DDR4_ODT_MASK (0x7 << 8) 42 43 #define LP2_DS_34ohm (0x1) 44 #define LP2_DS_40ohm (0x2) 45 #define LP2_DS_48ohm (0x3) 46 #define LP2_DS_60ohm (0x4) 47 #define LP2_DS_68_6ohm (0x5) /* optional */ 48 #define LP2_DS_80ohm (0x6) 49 #define LP2_DS_120ohm (0x7) /* optional */ 50 #define LP2_DS_MASK (0xf) 51 52 #define LP3_DS_34ohm (0x1) 53 #define LP3_DS_40ohm (0x2) 54 #define LP3_DS_48ohm (0x3) 55 #define LP3_DS_60ohm (0x4) 56 #define LP3_DS_80ohm (0x6) 57 #define LP3_DS_34D_40U (0x9) 58 #define LP3_DS_40D_48U (0xa) 59 #define LP3_DS_34D_48U (0xb) 60 #define LP3_DS_MASK (0xf) 61 62 #define LP3_ODT_DIS (0) 63 #define LP3_ODT_60ohm (0x1) 64 #define LP3_ODT_120ohm (0x2) 65 #define LP3_ODT_240ohm (0x3) 66 #define LP3_ODT_MASK (0x3) 67 68 #define LP4_PDDS_240ohm (0x1 << 3) 69 #define LP4_PDDS_120ohm (0x2 << 3) 70 #define LP4_PDDS_80ohm (0x3 << 3) 71 #define LP4_PDDS_60ohm (0x4 << 3) 72 #define LP4_PDDS_48ohm (0x5 << 3) 73 #define LP4_PDDS_40ohm (0x6 << 3) 74 #define LP4_PDDS_MASK (0x7 << 3) 75 76 #define LP4_DQ_ODT_DIS (0x0) 77 #define LP4_DQ_ODT_240ohm (0x1) 78 #define LP4_DQ_ODT_120ohm (0x2) 79 #define LP4_DQ_ODT_80ohm (0x3) 80 #define LP4_DQ_ODT_60ohm (0x4) 81 #define LP4_DQ_ODT_48ohm (0x5) 82 #define LP4_DQ_ODT_40ohm (0x6) 83 #define LP4_DQ_ODT_MASK (0x7) 84 85 #define LP4_CA_ODT_DIS (0x0) 86 #define LP4_CA_ODT_240ohm (0x1 << 4) 87 #define LP4_CA_ODT_120ohm (0x2 << 4) 88 #define LP4_CA_ODT_80ohm (0x3 << 4) 89 #define LP4_CA_ODT_60ohm (0x4 << 4) 90 #define LP4_CA_ODT_48ohm (0x5 << 4) 91 #define LP4_CA_ODT_40ohm (0x6 << 4) 92 #define LP4_CA_ODT_MASK (0x7 << 4) 93 94 #endif /* _DT_BINDINGS_DRAM_ROCKCHIP_H */ 95