1// SPDX-License-Identifier: (GPL-2.0+ or MIT) 2/* 3 * Copyright (C) 2020 frank@allwinnertech.com 4 */ 5 6#include <dt-bindings/clock/sun50iw9-ccu.h> 7#include <dt-bindings/clock/sun50iw9-ccu-rtc.h> 8#include <dt-bindings/clock/sun50iw9-r-ccu.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/gpio/sun4i-gpio.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/reset/sun50iw9-ccu.h> 13#include <dt-bindings/reset/sun50iw9-r-ccu.h> 14#include <dt-bindings/thermal/thermal.h> 15 16/ { 17 interrupt-parent = <&wakeupgen>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases: aliases { 22 serial0 = &uart0; 23 serial1 = &uart1; 24 serial2 = &uart2; 25 serial3 = &uart3; 26 serial4 = &uart4; 27 serial5 = &uart5; 28 pwm = &pwm; 29 pwm0 = &pwm0; 30 pwm1 = &pwm1; 31 pwm2 = &pwm2; 32 pwm3 = &pwm3; 33 pwm4 = &pwm4; 34 pwm5 = &pwm5; 35 ir0 = &s_cir0; 36 /*mmc0 = &sdc0; 37 mmc2 = &sdc2;*/ 38 sunxi-mmc0 = &sdc0; 39 sunxi-mmc2 = &sdc2; 40 tv0 = &tv0; 41 gmac0 = &gmac0; 42 ac200 = &ac200; 43 nand0 = &nand0; 44 ve0 = &ve; 45 ve1 = &ve1; 46 drm = &drm; 47 }; 48 49 reserved-memory { 50 #address-cells = <2>; 51 #size-cells = <2>; 52 ranges; 53 54 bl31 { 55 reg = <0x0 0x48000000 0x0 0x01000000>; 56 }; 57 }; 58 59 firmware { 60 android { 61 compatible = "android,firmware"; 62 name = "android"; 63 boot_devices = "soc@3000000/4020000.sdmmc,soc@3000000/4022000.sdmmc,soc@3000000"; 64 vbmeta { 65 compatible = "android,vbmeta"; 66 parts = "vbmeta,vbmeta_system,vbmeta_vendor,boot"; 67 }; 68 }; 69 optee { 70 compatible = "linaro,optee-tz"; 71 method = "smc"; 72 }; 73 }; 74 75 cpus { 76 #address-cells = <1>; 77 #size-cells = <0>; 78 79 cpu0: cpu@0 { 80 device_type = "cpu"; 81 compatible = "arm,cortex-a53"; 82 reg = <0x0>; 83 enable-method = "psci"; 84 clocks = <&ccu CLK_CPUX>; 85 operating-points-v2 = <&cpu_opp_table>; 86 cpu-idle-states = <&CPU_SLEEP>; 87 dynamic-power-coefficient = <202>; 88 #cooling-cells = <2>; 89 }; 90 91 cpu@1 { 92 device_type = "cpu"; 93 compatible = "arm,cortex-a53"; 94 reg = <0x1>; 95 enable-method = "psci"; 96 clocks = <&ccu CLK_CPUX>; 97 operating-points-v2 = <&cpu_opp_table>; 98 cpu-idle-states = <&CPU_SLEEP>; 99 dynamic-power-coefficient = <202>; 100 #cooling-cells = <2>; 101 }; 102 103 cpu@2 { 104 device_type = "cpu"; 105 compatible = "arm,cortex-a53"; 106 reg = <0x2>; 107 enable-method = "psci"; 108 clocks = <&ccu CLK_CPUX>; 109 operating-points-v2 = <&cpu_opp_table>; 110 cpu-idle-states = <&CPU_SLEEP>; 111 dynamic-power-coefficient = <202>; 112 #cooling-cells = <2>; 113 }; 114 115 cpu@3 { 116 device_type = "cpu"; 117 compatible = "arm,cortex-a53"; 118 reg = <0x3>; 119 enable-method = "psci"; 120 clocks = <&ccu CLK_CPUX>; 121 operating-points-v2 = <&cpu_opp_table>; 122 cpu-idle-states = <&CPU_SLEEP>; 123 dynamic-power-coefficient = <202>; 124 #cooling-cells = <2>; 125 }; 126 127 idle-states { 128 entry-method = "psci"; 129 130 CPU_SLEEP: cpu-sleep { 131 compatible = "arm,idle-state"; 132 local-timer-stop; 133 arm,psci-suspend-param = <0x0010000>; 134 entry-latency-us = <46>; 135 exit-latency-us = <59>; 136 min-residency-us = <3570>; 137 }; 138 }; 139 }; 140 141 cpu_opp_table: cpu-opp-table { 142 compatible = "allwinner,sun50i-operating-points"; 143 nvmem-cells = <&speedbin_efuse>; 144 nvmem-cell-names = "speed"; 145 opp-shared; 146 147 opp@480000000 { 148 opp-hz = /bits/ 64 <480000000>; 149 opp-microvolt-a0 = <900000>; 150 opp-microvolt-a1 = <900000>; 151 clock-latency-ns = <244144>; /* 8 32k periods */ 152 opp-supported-hw = <0x11>; 153 }; 154 155 opp@600000000 { 156 opp-hz = /bits/ 64 <600000000>; 157 opp-microvolt-a1 = <900000>; 158 clock-latency-ns = <244144>; /* 8 32k periods */ 159 opp-supported-hw = <0x1>; 160 }; 161 162 opp@720000000 { 163 opp-hz = /bits/ 64 <720000000>; 164 opp-microvolt-a0 = <900000>; 165 clock-latency-ns = <244144>; /* 8 32k periods */ 166 opp-supported-hw = <0x10>; 167 }; 168 169 opp@792000000 { 170 opp-hz = /bits/ 64 <792000000>; 171 opp-microvolt-a1 = <900000>; 172 clock-latency-ns = <244144>; /* 8 32k periods */ 173 opp-supported-hw = <0x1>; 174 }; 175 176 opp@936000000 { 177 opp-hz = /bits/ 64 <936000000>; 178 opp-microvolt-a0 = <900000>; 179 clock-latency-ns = <244144>; /* 8 32k periods */ 180 opp-supported-hw = <0x10>; 181 }; 182 183 opp@1008000000 { 184 opp-hz = /bits/ 64 <1008000000>; 185 opp-microvolt-a0 = <950000>; 186 opp-microvolt-a1 = <900000>; 187 clock-latency-ns = <244144>; /* 8 32k periods */ 188 opp-supported-hw = <0x11>; 189 }; 190 191 opp@1104000000 { 192 opp-hz = /bits/ 64 <1104000000>; 193 opp-microvolt-a0 = <1000000>; 194 clock-latency-ns = <244144>; /* 8 32k periods */ 195 opp-supported-hw = <0x10>; 196 }; 197 198 opp@1200000000 { 199 opp-hz = /bits/ 64 <1200000000>; 200 opp-microvolt-a0 = <1050000>; 201 opp-microvolt-a1 = <960000>; 202 clock-latency-ns = <244144>; /* 8 32k periods */ 203 opp-supported-hw = <0x11>; 204 }; 205 206 opp@1320000000 { 207 opp-hz = /bits/ 64 <1320000000>; 208 opp-microvolt-a0 = <1100000>; 209 clock-latency-ns = <244144>; /* 8 32k periods */ 210 opp-supported-hw = <0x10>; 211 }; 212 213 opp@1416000000 { 214 opp-hz = /bits/ 64 <1416000000>; 215 opp-microvolt-a0 = <1150000>; 216 clock-latency-ns = <244144>; /* 8 32k periods */ 217 opp-supported-hw = <0x10>; 218 }; 219 220 opp@1512000000 { 221 opp-hz = /bits/ 64 <1512000000>; 222 opp-microvolt-a1 = <1100000>; 223 clock-latency-ns = <244144>; /* 8 32k periods */ 224 opp-supported-hw = <0x1>; 225 }; 226 }; 227 228 dump_reg: dump-reg@20000 { 229 compatible = "allwinner,sunxi-dump-reg"; 230 reg = <0x0 0x00020000 0x0 0x0004>; 231 }; 232 233 psci { 234 compatible = "arm,psci-1.0"; 235 method = "smc"; 236 }; 237 238 iosc: internal-osc-clk { 239 #clock-cells = <0>; 240 compatible = "fixed-clock"; 241 clock-frequency = <16000000>; 242 clock-accuracy = <300000000>; 243 clock-output-names = "iosc"; 244 }; 245 246 dcxo24M: dcxo24M-clk { 247 #clock-cells = <0>; 248 compatible = "fixed-clock"; 249 clock-frequency = <24000000>; 250 clock-output-names = "dcxo24M"; 251 }; 252 253 osc32k: osc32k-clk { 254 #clock-cells = <0>; 255 compatible = "fixed-clock"; 256 clock-frequency = <32768>; 257 clock-output-names = "osc32k"; 258 }; 259 260 gic: interrupt-controller@3021000 { 261 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; 262 #interrupt-cells = <3>; 263 #address-cells = <0>; 264 interrupt-controller; 265 reg = <0x0 0x03021000 0 0x1000>, /* GIC Dist */ 266 <0x0 0x03022000 0 0x2000>, /* GIC CPU */ 267 <0x0 0x03024000 0 0x2000>, /* GIC VCPU Control */ 268 <0x0 0x03026000 0 0x2000>; /* GIC VCPU */ 269 interrupts = <GIC_PPI 9 0xf04>; /* GIC Maintenence IRQ */ 270 interrupt-parent = <&gic>; 271 }; 272 273 wakeupgen: interrupt-controller@0 { 274 compatible = "allwinner,sunxi-wakeupgen"; 275 interrupt-controller; 276 #interrupt-cells = <3>; 277 interrupt-parent = <&gic>; 278 }; 279 280 timer_arch { 281 compatible = "arm,armv8-timer"; 282 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 283 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 284 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 285 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 286 clock-frequency = <24000000>; 287 interrupt-parent = <&gic>; 288 arm,no-tick-in-suspend; 289 }; 290 291 reg_pio1_8: pio-18 { 292 compatible = "regulator-fixed"; 293 regulator-name = "pio-18"; 294 regulator-min-microvolt = <1800000>; 295 regulator-max-microvolt = <1800000>; 296 }; 297 298 reg_pio3_3: pio-33 { 299 compatible = "regulator-fixed"; 300 regulator-name = "pio-33"; 301 regulator-min-microvolt = <3300000>; 302 regulator-max-microvolt = <3300000>; 303 }; 304 305 soc: soc@3000000 { 306 compatible = "simple-bus"; 307 #address-cells = <2>; 308 #size-cells = <2>; 309 ranges; 310 311 vind0:vind@6600800 { 312 compatible = "allwinner,sunxi-vin-media", "simple-bus"; 313 #address-cells = <2>; 314 #size-cells = <2>; 315 ranges; 316 device_id = <0>; 317 csi_top = <324000000>; 318 reg = <0x0 0x06600800 0x0 0x200>, 319 <0x0 0x06600000 0x0 0x800>; 320 clocks = <&ccu CLK_CSI_TOP>, <&ccu CLK_PLL_CSI>, 321 <&ccu CLK_CSI0_MCLK>, <&dcxo24M>, <&ccu CLK_PLL_CSI>, 322 <&ccu CLK_CSI1_MCLK>, <&dcxo24M>, <&ccu CLK_PLL_CSI>, 323 <&ccu CLK_BUS_CSI>, <&ccu CLK_MBUS_CSI>; 324 clock-names = "csi_top", "csi_top_src", 325 "csi_mclk0", "csi_mclk0_24m", "csi_mclk0_pll", 326 "csi_mclk1", "csi_mclk1_24m", "csi_mclk1_pll", 327 "csi_bus", "csi_mbus"; 328 resets = <&ccu RST_BUS_CSI>; 329 reset-names = "csi_ret"; 330 pinctrl-names = "mclk0-default","mclk0-sleep","mclk1-default","mclk1-sleep"; 331 pinctrl-0 = <&csi_mclk0_pins_a>; 332 pinctrl-1 = <&csi_mclk0_pins_b>; 333 pinctrl-2 = <&csi_mclk1_pins_a>; 334 pinctrl-3 = <&csi_mclk1_pins_b>; 335 status = "okay"; 336 337 csi_cci0:cci@6614000 { 338 compatible = "allwinner,sunxi-csi_cci"; 339 reg = <0x0 0x06614000 0x0 0x400>; 340 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 341 pinctrl-names = "default","sleep"; 342 pinctrl-0 = <&csi_cci0_pins_a>; 343 pinctrl-1 = <&csi_cci0_pins_b>; 344 device_id = <0>; 345 status = "okay"; 346 }; 347 csi_cci1:cci@6614400 { 348 compatible = "allwinner,sunxi-csi_cci"; 349 reg = <0x0 0x06614400 0x0 0x400>; 350 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 351 pinctrl-names = "default","sleep"; 352 pinctrl-0 = <&csi_cci1_pins_a>; 353 pinctrl-1 = <&csi_cci1_pins_b>; 354 device_id = <1>; 355 status = "okay"; 356 }; 357 csi0:csi@6601000 { 358 device_type = "csi0"; 359 compatible = "allwinner,sunxi-csi"; 360 reg = <0x0 0x06601000 0x0 0x1000>; 361 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 362 device_id = <0>; 363 iommus = <&mmu_aw 4 1>; 364 status = "okay"; 365 }; 366 csi1:csi@6602000 { 367 device_type = "csi1"; 368 compatible = "allwinner,sunxi-csi"; 369 reg = <0x0 0x06602000 0x0 0x1000>; 370 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 371 pinctrl-names = "default","sleep"; 372 pinctrl-0 = <&csi1_pins_a>; 373 pinctrl-1 = <&csi1_pins_b>; 374 device_id = <1>; 375 iommus = <&mmu_aw 4 1>; 376 status = "disabled"; 377 }; 378 mipi0:mipi@660c000 { 379 compatible = "allwinner,sunxi-mipi"; 380 reg = <0x0 0x0660C000 0x0 0x1000>; 381 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 382 device_id = <0>; 383 status = "okay"; 384 }; 385 isp0:isp@6614810 { 386 compatible = "allwinner,sunxi-isp"; 387 reg = <0x0 0x06614810 0x0 0x10>; 388 device_id = <0xfe>; 389 status = "okay"; 390 }; 391 isp1:isp@6614820 { 392 compatible = "allwinner,sunxi-isp"; 393 reg = <0x0 0x06614820 0x0 0x10>; 394 device_id = <0xff>; 395 status = "okay"; 396 }; 397 scaler0:scaler@6614830 { 398 compatible = "allwinner,sunxi-scaler"; 399 reg = <0x0 0x06614830 0x0 0x10>; 400 device_id = <0xfa>; 401 iommus = <&mmu_aw 4 1>; 402 status = "okay"; 403 }; 404 scaler1:scaler@6614840 { 405 compatible = "allwinner,sunxi-scaler"; 406 reg = <0x0 0x06614840 0x0 0x10>; 407 device_id = <0xfb>; 408 iommus = <&mmu_aw 4 1>; 409 status = "okay"; 410 }; 411 scaler2:scaler@6614850 { 412 compatible = "allwinner,sunxi-scaler"; 413 reg = <0x0 0x06614850 0x0 0x10>; 414 device_id = <0xfc>; 415 iommus = <&mmu_aw 4 1>; 416 status = "okay"; 417 }; 418 scaler3:scaler@6614860 { 419 compatible = "allwinner,sunxi-scaler"; 420 reg = <0x0 0x06614860 0x0 0x10>; 421 device_id = <0xfd>; 422 iommus = <&mmu_aw 4 1>; 423 status = "okay"; 424 }; 425 scaler4:scaler@6614870 { 426 compatible = "allwinner,sunxi-scaler"; 427 reg = <0x0 0x06614870 0x0 0x10>; 428 device_id = <0xfe>; 429 iommus = <&mmu_aw 4 1>; 430 status = "okay"; 431 }; 432 scaler5:scaler@6614880 { 433 compatible = "allwinner,sunxi-scaler"; 434 reg = <0x0 0x06614880 0x0 0x10>; 435 device_id = <0xff>; 436 iommus = <&mmu_aw 4 1>; 437 status = "okay"; 438 }; 439 actuator0:actuator@6614890 { 440 reg = <0x0 0x06614890 0x0 0x10>; 441 device_type = "actuator0"; 442 compatible = "allwinner,sunxi-actuator"; 443 actuator0_name = "ad5820_act"; 444 actuator0_slave = <0x18>; 445 actuator0_af_pwdn = <>; 446 actuator0_afvdd = "afvcc-csi"; 447 actuator0_afvdd_vol = <2800000>; 448 status = "disabled"; 449 }; 450 flash0:flash@66148a0 { 451 reg = <0x0 0x066148a0 0x0 0x10>; 452 device_type = "flash0"; 453 compatible = "allwinner,sunxi-flash"; 454 flash0_type = <2>; 455 flash0_en = <>; 456 flash0_mode = <>; 457 flash0_flvdd = ""; 458 flash0_flvdd_vol = <>; 459 device_id = <0>; 460 status = "disabled"; 461 }; 462 sensor0:sensor@66148b0 { 463 reg = <0x0 0x066148b0 0x0 0x10>; 464 device_type = "sensor0"; 465 compatible = "allwinner,sunxi-sensor"; 466 sensor0_mname = "rn6854m_mipi"; 467 sensor0_twi_cci_id = <0>; 468 sensor0_twi_addr = <0x58>; 469 sensor0_mclk_id = <0>; 470 sensor0_pos = "rear"; 471 sensor0_isp_used = <0>; 472 sensor0_fmt = <0>; 473 sensor0_stby_mode = <0>; 474 sensor0_vflip = <0>; 475 sensor0_hflip = <0>; 476 sensor0_cameravdd-supply = <>; 477 sensor0_cameravdd_vol = <>; 478 sensor0_reservevdd-supply = <>; 479 sensor0_reservevdd_vol = <>; 480 sensor0_iovdd-supply = <>; 481 sensor0_iovdd_vol = <>; 482 sensor0_avdd-supply = <>; 483 sensor0_avdd_vol = <>; 484 sensor0_dvdd-supply = <>; 485 sensor0_dvdd_vol = <>; 486 sensor0_power_en = <>; 487 sensor0_reset = <&pio PI 13 GPIO_ACTIVE_LOW>; 488 sensor0_pwdn = <&pio PI 14 GPIO_ACTIVE_LOW>; 489 sensor0_sm_vs = <>; 490 flash_handle = <&flash0>; 491 act_handle = <&actuator0>; 492 device_id = <0>; 493 status = "okay"; 494 }; 495 sensor1:sensor@66148c0 { 496 reg = <0x0 0x066148c0 0x0 0x10>; 497 device_type = "sensor1"; 498 compatible = "allwinner,sunxi-sensor"; 499 sensor1_mname = "nvp6158"; 500 sensor1_twi_cci_id = <1>; 501 sensor1_twi_addr = <0x64>; 502 sensor1_mclk_id = <1>; 503 sensor1_pos = "front"; 504 sensor1_isp_used = <0>; 505 sensor1_fmt = <0>; 506 sensor1_stby_mode = <0>; 507 sensor1_vflip = <0>; 508 sensor1_hflip = <0>; 509 sensor1_cameravdd-supply = <>; 510 sensor1_cameravdd_vol = <>; 511 sensor1_reservevdd-supply = <>; 512 sensor1_reservevdd_vol = <>; 513 sensor1_iovdd-supply = <>; 514 sensor1_iovdd_vol = <>; 515 sensor1_avdd-supply = <>; 516 sensor1_avdd_vol = <>; 517 sensor1_dvdd-supply = <>; 518 sensor1_dvdd_vol = <>; 519 sensor1_power_en = <>; 520 sensor1_reset = <&pio PI 12 GPIO_ACTIVE_LOW>; 521 sensor1_pwdn = <&pio PI 14 GPIO_ACTIVE_LOW>; 522 sensor1_sm_vs = <>; 523 flash_handle = <>; 524 act_handle = <>; 525 device_id = <1>; 526 status = "okay"; 527 }; 528 vinc0:vinc@6609000 { 529 device_type = "vinc0"; 530 compatible = "allwinner,sunxi-vin-core"; 531 reg = <0x0 0x06609000 0x0 0x200>; 532 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 533 vinc0_csi_sel = <0>; 534 vinc0_mipi_sel = <0>; 535 vinc0_isp_sel = <0>; 536 vinc0_isp_tx_ch = <0>; 537 vinc0_rear_sensor_sel = <0>; 538 vinc0_front_sensor_sel = <0>; 539 vinc0_sensor_list = <0>; 540 device_id = <0>; 541 iommus = <&mmu_aw 4 1>; 542 status = "okay"; 543 }; 544 vinc1:vinc@6609200 { 545 device_type = "vinc1"; 546 compatible = "allwinner,sunxi-vin-core"; 547 reg = <0x0 0x06609200 0x0 0x200>; 548 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 549 vinc1_csi_sel = <0>; 550 vinc1_mipi_sel = <0>; 551 vinc1_isp_sel = <0>; 552 vinc1_isp_tx_ch = <1>; 553 vinc1_rear_sensor_sel = <0>; 554 vinc1_front_sensor_sel = <0>; 555 vinc1_sensor_list = <0>; 556 device_id = <1>; 557 iommus = <&mmu_aw 4 1>; 558 status = "okay"; 559 }; 560 vinc2:vinc@6609400 { 561 device_type = "vinc2"; 562 compatible = "allwinner,sunxi-vin-core"; 563 reg = <0x0 0x06609400 0x0 0x200>; 564 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 565 vinc2_csi_sel = <1>; 566 vinc2_mipi_sel = <0xff>; 567 vinc2_isp_sel = <1>; 568 vinc2_isp_tx_ch = <0>; 569 vinc2_rear_sensor_sel = <1>; 570 vinc2_front_sensor_sel = <1>; 571 vinc2_sensor_list = <0>; 572 device_id = <2>; 573 iommus = <&mmu_aw 4 1>; 574 status = "okay"; 575 }; 576 vinc3:vinc@6609600 { 577 device_type = "vinc3"; 578 compatible = "allwinner,sunxi-vin-core"; 579 reg = <0x0 0x06609600 0x0 0x200>; 580 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 581 vinc3_csi_sel = <1>; 582 vinc3_mipi_sel = <0xff>; 583 vinc3_isp_sel = <1>; 584 vinc3_isp_tx_ch = <1>; 585 vinc3_rear_sensor_sel = <1>; 586 vinc3_front_sensor_sel = <1>; 587 vinc3_sensor_list = <0>; 588 device_id = <3>; 589 iommus = <&mmu_aw 4 1>; 590 status = "okay"; 591 }; 592 vinc4:vinc@6609800 { 593 device_type = "vinc4"; 594 compatible = "allwinner,sunxi-vin-core"; 595 reg = <0x0 0x06609800 0x0 0x200>; 596 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 597 vinc4_csi_sel = <1>; 598 vinc4_mipi_sel = <0xff>; 599 vinc4_isp_sel = <1>; 600 vinc4_isp_tx_ch = <2>; 601 vinc4_rear_sensor_sel = <1>; 602 vinc4_front_sensor_sel = <1>; 603 vinc4_sensor_list = <0>; 604 device_id = <4>; 605 iommus = <&mmu_aw 5 1>; 606 status = "okay"; 607 }; 608 vinc5:vinc@6609A00 { 609 device_type = "vinc5"; 610 compatible = "allwinner,sunxi-vin-core"; 611 reg = <0x0 0x06609A00 0x0 0x200>; 612 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 613 vinc5_csi_sel = <1>; 614 vinc5_mipi_sel = <0xff>; 615 vinc5_isp_sel = <1>; 616 vinc5_isp_tx_ch = <3>; 617 vinc5_rear_sensor_sel = <1>; 618 vinc5_front_sensor_sel = <1>; 619 vinc5_sensor_list = <0>; 620 device_id = <5>; 621 iommus = <&mmu_aw 5 1>; 622 status = "okay"; 623 }; 624 }; 625 626 disp: disp@1000000 { 627 compatible = "allwinner,sunxi-disp"; 628 reg = <0x0 0x01000000 0x0 0x01400000>, /*de*/ 629 <0x0 0x06510000 0x0 0x200>, /* display_if_top */ 630 <0x0 0x06511000 0x0 0x1000>, /* tcon_lcd0 */ 631 <0x0 0x06512000 0x0 0x1000>, /* tcon_lcd1 */ 632 <0x0 0x06515000 0x0 0x1000>, /* tcon_tv0 */ 633 <0x0 0x06516000 0x0 0x1000>; /* tcon_tv1 */ 634 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, /* DE */ 635 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* tcon_lcd0 */ 636 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* tcon_lcd1 */ 637 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, /* tcon_tv0 */ 638 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* tcon_tv1 */ 639 clocks = <&ccu CLK_DE>, 640 <&ccu CLK_DE>, 641 <&ccu CLK_BUS_DE>, 642 <&ccu CLK_BUS_DE>, 643 <&ccu CLK_TCON_LCD0>, 644 <&ccu CLK_TCON_LCD1>, 645 <&ccu CLK_TCON_TV0>, 646 <&ccu CLK_TCON_TV1>, 647 <&ccu CLK_BUS_TCON_LCD0>, 648 <&ccu CLK_BUS_TCON_LCD1>, 649 <&ccu CLK_BUS_TCON_TV0>, 650 <&ccu CLK_BUS_TCON_TV1>, 651 <&ccu CLK_BUS_DISPLAY_IF_TOP>, 652 <&ccu CLK_BUS_DISPLAY_IF_TOP>, 653 <&ccu CLK_BUS_DISPLAY_IF_TOP>, 654 <&ccu CLK_BUS_DISPLAY_IF_TOP>; 655 clock-names = "clk_de0", 656 "clk_de1", 657 "clk_bus_de0", 658 "clk_bus_de1", 659 "clk_tcon0", /* tcon lcd */ 660 "clk_tcon1", 661 "clk_tcon2", /* tcon tv */ 662 "clk_tcon3", 663 "clk_bus_tcon0", 664 "clk_bus_tcon1", 665 "clk_bus_tcon2", 666 "clk_bus_tcon3", 667 "clk_bus_dpss_top0", 668 "clk_bus_dpss_top1", 669 "clk_bus_dpss_top2", 670 "clk_bus_dpss_top3"; 671 resets = <&ccu RST_BUS_DE>, 672 <&ccu RST_BUS_DE>, 673 <&ccu RST_BUS_TCON_LCD0>, 674 <&ccu RST_BUS_TCON_LCD1>, 675 <&ccu RST_BUS_TCON_TV0>, 676 <&ccu RST_BUS_TCON_TV1>, 677 <&ccu RST_BUS_LVDS>, 678 <&ccu RST_BUS_LVDS>, 679 <&ccu RST_BUS_DISPLAY_IF_TOP>, 680 <&ccu RST_BUS_DISPLAY_IF_TOP>, 681 <&ccu RST_BUS_DISPLAY_IF_TOP>, 682 <&ccu RST_BUS_DISPLAY_IF_TOP>; 683 reset-names = "rst_bus_de0", 684 "rst_bus_de1", 685 "rst_bus_tcon0", 686 "rst_bus_tcon1", 687 "rst_bus_tcon2", 688 "rst_bus_tcon3", 689 "rst_bus_lvds0", 690 "rst_bus_lvds1", 691 "rst_bus_dpss_top0", 692 "rst_bus_dpss_top1", 693 "rst_bus_dpss_top2", 694 "rst_bus_dpss_top3"; 695 assigned-clocks = <&ccu CLK_TCON_TV0>; 696 assigned-clock-parents = <&ccu CLK_PLL_VIDEO2>; 697 assigned-clock-rates = <0>; 698 iommus = <&mmu_aw 0 0>; 699 700 boot_disp = <0>; 701 fb_base = <0>; 702 }; 703 704 drm: drm@01000000 { 705 compatible = "allwinner,sunxi-drm"; 706 fb_base = <0>; 707 iommus = <&mmu_aw 0 0>; /* 1：enable iommu */ 708 status = "okay"; 709 }; 710 711 drm_de: de@01000000 { 712 compatible = "allwinner,sunxi-de"; 713 reg = <0x0 0x01000000 0x0 0x01400000>;/*de*/ 714 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; /*DE*/ 715 clocks = <&ccu CLK_DE>, 716 <&ccu CLK_BUS_DE>; 717 clock-names = "clk_de","clk_bus_de"; 718 resets = <&ccu RST_BUS_DE>; 719 reset-names = "rst_bus_de"; 720 chn_cfg_mode = <1>; 721 status = "okay"; 722 }; 723 724 drm_tcon: tcon@06511000 { 725 compatible = "allwinner,sunxi-tcon"; 726 reg = <0x0 0x06510000 0x0 0x200>,/*disp_if_top*/ 727 <0x0 0x06511000 0x0 0x1000>,/*tcon_lcd0*/ 728 <0x0 0x06512000 0x0 0x1000>,/*tcon_lcd1*/ 729 <0x0 0x06515000 0x0 0x1000>,/*tcon_tv0*/ 730 <0x0 0x06516000 0x0 0x1000>;/*tcon_tv1*/ 731 interrupts = 732 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /*tcon_lcd0*/ 733 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /*tcon_lcd1*/ 734 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, /*tcon_tv0*/ 735 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /*tcon_tv1*/ 736 clocks = <&ccu CLK_BUS_DISPLAY_IF_TOP>, 737 <&ccu CLK_TCON_LCD0>, 738 <&ccu CLK_TCON_LCD1>, 739 <&ccu CLK_TCON_TV0>, 740 <&ccu CLK_TCON_TV1>, 741 <&ccu CLK_BUS_TCON_LCD0>, 742 <&ccu CLK_BUS_TCON_LCD1>, 743 <&ccu CLK_BUS_TCON_TV0>, 744 <&ccu CLK_BUS_TCON_TV1>; 745 clock-names = "clk_bus_dpss_top0", 746 "clk_tcon0", /* tcon lcd */ 747 "clk_tcon1", 748 "clk_tcon2", /* tcon tv */ 749 "clk_tcon3", 750 "clk_bus_tcon0", 751 "clk_bus_tcon1", 752 "clk_bus_tcon2", 753 "clk_bus_tcon3"; 754 resets = <&ccu RST_BUS_DISPLAY_IF_TOP>, 755 <&ccu RST_BUS_TCON_LCD0>, 756 <&ccu RST_BUS_TCON_LCD1>, 757 <&ccu RST_BUS_TCON_TV0>, 758 <&ccu RST_BUS_TCON_TV1>; 759 reset-names = "rst_bus_dpss_top", 760 "rst_bus_tcon0", 761 "rst_bus_tcon1", 762 "rst_bus_tcon2", 763 "rst_bus_tcon3"; 764 status = "okay"; 765 }; 766 767 lcdcore: lcd-core@01c0c000 { 768 compatible = "allwinner,sunxi-lcd"; 769 resets = <&ccu RST_BUS_LVDS>; 770 reset-names = "rst_bus_lvds"; 771 status = "okay"; 772 }; 773 774 ve: ve@1c0e000 { 775 compatible = "allwinner,sunxi-cedar-ve"; 776 reg = <0x0 0x01c0e000 0x0 0x1000>, 777 <0x0 0x03000000 0x0 0x10>, 778 <0x0 0x03001000 0x0 0x1000>; 779 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 780 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, <&ccu CLK_MBUS_VE>; 781 clock-names = "bus_ve", "ve", "mbus_ve"; 782 resets = <&ccu RST_BUS_VE>; 783 iommus = <&mmu_aw 3 1>; 784 }; 785 786 ve1: ve1@1c0e000 { 787 compatible = "allwinner,sunxi-cedar-ve"; 788 iommus = <&mmu_aw 2 1>; 789 }; 790 791 792 g2d: g2d@1480000 { 793 compatible = "allwinner,sunxi-g2d"; 794 reg = <0x0 0x01480000 0x0 0x3ffff>; 795 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 796 clocks = <&ccu CLK_BUS_G2D>, <&ccu CLK_G2D>, 797 <&ccu CLK_MBUS_G2D>; 798 clock-names = "bus", "g2d", "mbus_g2d"; 799 resets = <&ccu RST_BUS_G2D>; 800 iommus = <&mmu_aw 6 1>; 801 }; 802 803 di:deinterlace@1420000{ 804 #address-cells = <1>; 805 #size-cells = <0>; 806 compatible = "allwinner,sunxi-deinterlace"; 807 reg = <0x0 0x01420000 0x0 0x040000>; 808 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 809 iommus = <&mmu_aw 1 1>; 810 status = "okay"; 811 812 clocks = <&ccu CLK_DI>, 813 <&ccu CLK_BUS_DI>, 814 <&ccu CLK_PLL_PERIPH0_2X>; 815 clock-names = "clk_di", 816 "clk_bus_di", 817 "pll_periph"; 818 resets = <&ccu RST_BUS_DI>; 819 reset-names = "rst_bus_di"; 820 821 assigned-clocks = <&ccu CLK_DI>; 822 assigned-clock-parents = <&ccu CLK_PLL_PERIPH0_2X>; 823 assigned-clock-rates = <300000000>; 824 }; 825 826 gpu: gpu@1800000 { 827 device_type = "gpu"; 828 compatible = "arm,mali-bifrost"; 829 reg = <0x0 0x01800000 0x0 0x10000>; 830 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 831 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 832 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 833 interrupt-names = "job", "mmu", "gpu"; 834 clocks = <&ccu CLK_PLL_GPU>, <&ccu CLK_GPU0>, 835 <&ccu CLK_GPU1>,<&ccu CLK_BUS_GPU>; 836 clock-names = "clk_parent", "clk_mali", 837 "clk_bak", "clk_bus"; 838 resets = <&ccu RST_BUS_GPU>; 839 reset-names = "rst_bus_gpu"; 840 #cooling-cells = <2>; 841 operating-points-v2 = <&gpu_opp_table>; 842 mali-supply = <®_dcdc4>; 843 ipa_dvfs:ipa_dvfs { 844 compatible = "arm,mali-simple-power-model"; 845 static-coefficient = <17000>; 846 dynamic-coefficient = <750>; 847 ts = <254682 9576 0xffffff98 4>; 848 thermal-zone = "gpu_thermal_zone"; 849 ss-coefficient = <36>; 850 ff-coefficient = <291>; 851 }; 852 }; 853 854 gpu_opp_table: gpu-opp-table { 855 compatible = "operating-points-v2"; 856 857 opp-420000000 { 858 opp-hz = /bits/ 64 <420000000>; 859 opp-microvolt = <820000>; 860 }; 861 opp-456000000 { 862 opp-hz = /bits/ 64 <456000000>; 863 opp-microvolt = <840000>; 864 }; 865 opp-504000000 { 866 opp-hz = /bits/ 64 <504000000>; 867 opp-microvolt = <860000>; 868 }; 869 opp-552000000 { 870 opp-hz = /bits/ 64 <552000000>; 871 opp-microvolt = <880000>; 872 }; 873 opp-600000000 { 874 opp-hz = /bits/ 64 <600000000>; 875 opp-microvolt = <900000>; 876 }; 877 opp-648000000 { 878 opp-hz = /bits/ 64 <648000000>; 879 opp-microvolt = <960000>; 880 }; 881 }; 882 883 lcd0: lcd0@1c0c000 { 884 compatible = "allwinner,sunxi-lcd0"; 885 /* Fake registers to avoid dtc compiling warnings */ 886 reg = <0x0 0x1c0c000 0x0 0x0>; 887 pinctrl-names = "active","sleep"; 888 }; 889 890 tv0: tv0@6520000 { 891 compatible = "allwinner,sunxi-tv"; 892 reg = <0x0 0x06520000 0x0 0x100>, 893 <0x0 0x06524000 0x0 0x3fc>; 894 clocks = <&ccu CLK_BUS_TVE_TOP>, 895 <&ccu CLK_TVE>, 896 <&ccu CLK_BUS_TVE>; 897 clock-names = "clk_bus_tve_top", 898 "clk_tve", 899 "clk_bus_tve"; 900 resets = <&ccu RST_BUS_TVE_TOP>, 901 <&ccu RST_BUS_TVE>; 902 reset-names = "rst_bus_tve_top", "rst_bus_tve"; 903 904 assigned-clocks = <&ccu CLK_TVE>; 905 assigned-clock-parents = <&ccu CLK_PLL_VIDEO1>; 906 nvmem-cells = <&tvout>; 907 nvmem-cell-names = "tvout"; 908 909 device_type = "tv0"; 910 pinctrl-names = "active","sleep"; 911 status = "okay"; 912 }; 913 914 ccu: ccu@3001000 { 915 compatible = "allwinner,sun50iw9-ccu"; 916 reg = <0x0 0x03001000 0x0 0x1000>; 917 clocks = <&dcxo24M>, <&osc32k>, <&iosc>; 918 clock-names = "hosc", "losc", "iosc"; 919 #clock-cells = <1>; 920 #reset-cells = <1>; 921 }; 922 923 rtc_ccu: rtc_ccu@7000000 { 924 compatible = "allwinner,sun50iw9-rtc-ccu"; 925 reg = <0x0 0x07000000 0x0 0x400>; 926 #clock-cells = <1>; 927 clocks = <&osc32k>; 928 clock-names = "losc"; 929 #reset-cells = <1>; 930 }; 931 932 rtc: rtc@7000000 { 933 compatible = "allwinner,rtc-v200"; 934 device_type = "rtc"; 935 wakeup-source; 936 reg = <0x0 0x07000000 0x0 0x200>; 937 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 938 clocks = <&r_ccu CLK_R_AHB_BUS_RTC>, <&rtc_ccu CLK_RTC_1K>; 939 clock-names = "r-ahb-rtc","rtc-1k"; 940 gpr_cur_pos = <6>; 941 }; 942 943 r_ccu: r_ccu@7010000 { 944 compatible = "allwinner,sun50iw9-r-ccu"; 945 reg = <0x0 0x07010000 0x0 0x300>; 946 /* have no irq line */ 947 clocks = <&dcxo24M>, <&osc32k>, <&iosc>, 948 <&ccu CLK_PLL_PERIPH0>; 949 clock-names = "hosc", "losc", "iosc", "pll-periph"; 950 #clock-cells = <1>; 951 #reset-cells = <1>; 952 }; 953 954 dma: dma-controller@3002000 { 955 compatible = "allwinner,sun50iw9-dma"; 956 reg = <0x0 0x03002000 0x0 0x1000>; 957 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 958 clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; 959 clock-names = "bus", "mbus"; 960 dma-channels = <16>; 961 dma-requests = <49>; 962 resets = <&ccu RST_BUS_DMA>; 963 #dma-cells = <1>; 964 }; 965 966 sram_ctrl: sram_ctrl@3000000 { 967 compatible = "allwinner,sram_ctrl"; 968 reg = <0x0 0x3000000 0 0x16C>; 969 soc_ver { 970 offset = <0x24>; 971 mask = <0x7>; 972 shift = <0>; 973 }; 974 975 soc_id { 976 offset = <0x200>; 977 mask = <0x1>; 978 shift = <22>; 979 }; 980 981 soc_bin { 982 offset = <0x0>; 983 mask = <0x3ff>; 984 shift = <0x0>; 985 }; 986 987 }; 988 989 sid@3006000 { 990 compatible = "allwinner,sun50iw9p1-sid", "allwinner,sunxi-sid"; 991 reg = <0x0 0x03006000 0 0x1000>; 992 #address-cells = <1>; 993 #size-cells = <1>; 994 995 speedbin_efuse: speed@00 { 996 reg = <0x0 2>; 997 }; 998 999 ths_calib: calib@14 { 1000 reg = <0x14 8>; 1001 }; 1002 1003 tvout: tvout@2e { 1004 reg = <0x2c 8>; 1005 }; 1006 1007 i_cpu_efuse: i-cpu@28 { 1008 reg = <0x28 2>; 1009 }; 1010 1011 /* some guys has nothing to do with nvmem */ 1012 secure_status { 1013 reg = <0x0 0>; 1014 offset = <0xa0>; 1015 size = <0x4>; 1016 }; 1017 1018 chipid { 1019 reg = <0x0 0>; 1020 offset = <0x200>; 1021 size = <0x10>; 1022 }; 1023 1024 rotpk { 1025 reg = <0x0 0>; 1026 offset = <0x270>; 1027 size = <0x20>; 1028 }; 1029 }; 1030 1031 cryptoengine: ce@1904000 { 1032 compatible = "allwinner,sunxi-ce"; 1033 device_name = "ce"; 1034 reg = <0x0 0x01904000 0x0 0xa0>, /* non-secure space */ 1035 <0x0 0x01904800 0x0 0xa0>; /* secure space */ 1036 interrupts = <GIC_SPI 91 IRQ_TYPE_EDGE_RISING>, /*non-secure*/ 1037 <GIC_SPI 92 IRQ_TYPE_EDGE_RISING>; /* secure*/ 1038 clock-frequency = <300000000>; /* 300MHz */ 1039 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>, <&ccu CLK_MBUS_CE>, 1040 <&ccu CLK_PLL_PERIPH0_2X>; 1041 clock-names = "bus_ce", "ce_clk", "mbus_ce", "pll_periph0_2x"; 1042 resets = <&ccu RST_BUS_CE>; 1043 }; 1044 1045 soc_timer0: timer@3009000 { 1046 compatible = "allwinner,sun4i-a10-timer"; 1047 device_type = "soc_timer"; 1048 /* 1049 * FIXME: After using sunxi timer driver, the number 1050 * of CPU entering idle becomes less? 1051 * "allwinner,sunxi-timer"; 1052 */ 1053 reg = <0x0 0x03009000 0x0 0x400>; 1054 interrupt-parent = <&gic>; 1055 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1056 clocks = <&dcxo24M>; 1057 }; 1058 1059 wdt: watchdog@30090a0 { 1060 compatible = "allwinner,sun6i-a31-wdt"; 1061 reg = <0x0 0x030090a0 0x0 0x20>; 1062 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1063 }; 1064 1065 pwm: pwm@300a000 { 1066 compatible = "allwinner,sunxi-pwm-v100"; 1067 reg = <0x0 0x0300a000 0x0 0x400>; 1068 clocks = <&ccu CLK_BUS_PWM>; 1069 resets = <&ccu RST_BUS_PWM>; 1070 pwm-number = <6>; 1071 pwm-base = <0>; 1072 sunxi-pwms = <&pwm0>, <&pwm1>, <&pwm2>, <&pwm3>, 1073 <&pwm4>, <&pwm5>; 1074 }; 1075 1076 pwm0: pwm0@300a010 { 1077 compatible = "allwinner,sunxi-pwm0"; 1078 reg = <0x0 0x0300a010 0x0 0x4>; 1079 reg_base = <0x0300a000>; 1080 }; 1081 1082 pwm1: pwm1@300a011 { 1083 compatible = "allwinner,sunxi-pwm1"; 1084 reg = <0x0 0x0300a011 0x0 0x4>; 1085 reg_base = <0x0300a000>; 1086 }; 1087 1088 pwm2: pwm2@300a012 { 1089 compatible = "allwinner,sunxi-pwm2"; 1090 reg = <0x0 0x0300a012 0x0 0x4>; 1091 reg_base = <0x0300a000>; 1092 }; 1093 1094 pwm3: pwm3@300a013 { 1095 compatible = "allwinner,sunxi-pwm3"; 1096 reg = <0x0 0x0300a013 0x0 0x4>; 1097 reg_base = <0x0300a000>; 1098 }; 1099 1100 pwm4: pwm4@300a014 { 1101 compatible = "allwinner,sunxi-pwm4"; 1102 reg = <0x0 0x0300a014 0x0 0x4>; 1103 reg_base = <0x0300a000>; 1104 }; 1105 1106 pwm5: pwm5@300a015 { 1107 compatible = "allwinner,sunxi-pwm5"; 1108 reg = <0x0 0x0300a015 0x0 0x4>; 1109 reg_base = <0x0300a000>; 1110 }; 1111 1112 ac200: ac200{ 1113 compatible = "allwinner,sunxi-ac200"; 1114 status = "okay"; 1115 }; 1116 1117 pio: pinctrl@300b000 { 1118 compatible = "allwinner,sun50iw9-pinctrl"; 1119 reg = <0x0 0x0300b000 0x0 0x400>; 1120 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 1121 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 1122 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 1123 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1124 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 1125 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 1126 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1127 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 1128 clocks = <&ccu CLK_APB1>, <&dcxo24M>, <&osc32k>; 1129 clock-names = "apb", "hosc", "losc"; 1130 gpio-controller; 1131 #gpio-cells = <3>; 1132 interrupt-controller; 1133 #interrupt-cells = <3>; 1134 vcc-pf-supply = <®_pio1_8>; 1135 vcc-pfo-supply = <®_pio3_3>; 1136 1137 uart0_ph_pins: uart0-ph-pins { 1138 pins = "PH0", "PH1"; 1139 function = "uart0"; 1140 }; 1141 1142 uart0_ph_sleep: uart0-ph-sleep { 1143 pins = "PH0", "PH1"; 1144 function = "gpio_in"; 1145 }; 1146 1147 sdc0_pins_a: sdc0@0 { 1148 pins = "PF0", "PF1", "PF2", 1149 "PF3", "PF4", "PF5"; 1150 function = "sdc0"; 1151 drive-strength = <30>; 1152 bias-pull-up; 1153 power-source = <3300>; 1154 }; 1155 1156 sdc0_pins_b: sdc0@1 { 1157 pins = "PF0", "PF1", "PF2", 1158 "PF3", "PF4", "PF5"; 1159 function = "sdc0"; 1160 drive-strength = <30>; 1161 bias-pull-up; 1162 power-source = <1800>; 1163 }; 1164 1165 sdc0_pins_c: sdc0@2 { 1166 pins = "PF0", "PF1", "PF2", 1167 "PF3", "PF4", "PF5"; 1168 function = "gpio_in"; 1169 }; 1170 1171 /* TODO: add jtag pin */ 1172 sdc0_pins_d: sdc0@3 { 1173 pins = "PF2", "PF4"; 1174 function = "uart0"; 1175 drive-strength = <10>; 1176 bias-pull-up; 1177 }; 1178 1179 sdc0_pins_e: sdc0@4 { 1180 pins = "PF0", "PF1", "PF3", 1181 "PF5"; 1182 function = "jtag"; 1183 drive-strength = <10>; 1184 bias-pull-up; 1185 }; 1186 1187 sdc1_pins_a: sdc1@0 { 1188 pins = "PG0", "PG1", "PG2", 1189 "PG3", "PG4", "PG5"; 1190 function = "sdc1"; 1191 drive-strength = <40>; 1192 bias-pull-up; 1193 }; 1194 1195 sdc1_pins_b: sdc1@1 { 1196 pins = "PG0", "PG1", "PG2", 1197 "PG3", "PG4", "PG5"; 1198 function = "gpio_in"; 1199 bias-pull-up; 1200 }; 1201 1202 sdc2_pins_a: sdc2@0 { 1203 pins = "PC1", "PC5", "PC6", 1204 "PC8", "PC9", "PC10", "PC11", 1205 "PC13", "PC14", "PC15", "PC16"; 1206 function = "sdc2"; 1207 drive-strength = <30>; 1208 bias-pull-up; 1209 }; 1210 1211 sdc2_pins_b: sdc2@1 { 1212 pins = "PC0", "PC1", "PC5", "PC6", 1213 "PC8", "PC9", "PC10", "PC11", 1214 "PC13", "PC14", "PC15", "PC16"; 1215 function = "gpio_in"; 1216 bias-pull-up; 1217 }; 1218 1219 sdc2_pins_c: sdc2@2 { 1220 allwinner,pins = "PC0"; 1221 allwinner,function = "sdc2"; 1222 drive-strength = <30>; 1223 bias-pull-down; 1224 }; 1225 1226 nand0_pins_a: nand0@0 { 1227 pins = "PC0", "PC1", "PC2", "PC5", 1228 "PC8", "PC9", "PC10", "PC11", 1229 "PC12", "PC13", "PC14", "PC15", 1230 "PC16"; 1231 function = "nand0"; 1232 drive-strength = <40>; 1233 }; 1234 1235 nand0_pins_b: nand0@1 { 1236 pins = "PC4", "PC6", "PC3", "PC7"; 1237 function = "nand0"; 1238 drive-strength = <40>; 1239 bias-pull-up;/* only RB&CE should be pulled up */ 1240 }; 1241 1242 nand0_pins_c: nand0@2 { 1243 pins = "PC0", "PC1", "PC2", "PC3", 1244 "PC4", "PC5", "PC6", "PC7", 1245 "PC8", "PC9", "PC10", "PC11", 1246 "PC12", "PC13", "PC14", "PC15", 1247 "PC16"; 1248 function = "gpio_in"; 1249 }; 1250 1251 csi_mclk0_pins_a: csi_mclk0@0 { 1252 pins = "PG19"; 1253 function = "csi_mclk0"; 1254 drive-strength = <20>; 1255 }; 1256 1257 csi_mclk0_pins_b: csi_mclk0@1 { 1258 pins = "PG19"; 1259 function = "gpio_in"; 1260 }; 1261 1262 csi_mclk1_pins_a: csi_mclk1@0 { 1263 pins = "PE1"; 1264 function = "csi_mclk1"; 1265 drive-strength = <20>; 1266 }; 1267 1268 csi_mclk1_pins_b: csi_mclk1@1 { 1269 pins = "PE1"; 1270 function = "gpio_in"; 1271 }; 1272 1273 csi_cci0_pins_a: csi_cci0@0 { 1274 pins = "PG17","PG18"; 1275 function = "csi_cci0"; 1276 drive-strength = <20>; 1277 }; 1278 1279 csi_cci0_pins_b: csi_cci0@1 { 1280 pins = "PG17","PG18"; 1281 function = "gpio_in"; 1282 }; 1283 1284 csi_cci1_pins_a: csi_cci1@0 { 1285 pins = "PE20","PE21"; 1286 function = "csi_cci1"; 1287 drive-strength = <20>; 1288 }; 1289 1290 csi_cci1_pins_b: csi_cci1@1 { 1291 pins = "PE20","PE21"; 1292 function = "gpio_in"; 1293 }; 1294 1295 csi1_pins_a: csi1@0 { 1296 pins = "PE0", "PE2", "PE3", "PE4", "PE5", 1297 "PE6", "PE7", "PE8", "PE9", "PE10", "PE11", 1298 "PE12", "PE13", "PE14", "PE15", "PE16", "PE17", 1299 "PE18", "PE19"; 1300 function = "csi1"; 1301 drive-strength = <10>; 1302 }; 1303 1304 csi1_pins_b: csi1@1 { 1305 pins = "PE0", "PE2", "PE3", "PE4", "PE5", 1306 "PE6", "PE7", "PE8", "PE9", "PE10", "PE11", 1307 "PE12", "PE13", "PE14", "PE15", "PE16", "PE17", 1308 "PE18", "PE19"; 1309 function = "gpio_in"; 1310 }; 1311 1312 }; 1313 1314 r_pio: pinctrl@7022000 { 1315 compatible = "allwinner,sun50iw9-r-pinctrl"; 1316 reg = <0x0 0x07022000 0x0 0x400>; 1317 clocks = <&r_ccu CLK_R_APB1>, <&dcxo24M>, <&osc32k>; 1318 clock-names = "apb", "hosc", "losc"; 1319 gpio-controller; 1320 #gpio-cells = <3>; 1321 }; 1322 1323 mmu_aw: iommu@30f0000 { 1324 compatible = "allwinner,iommu-v12-sun50iw9"; 1325 reg = <0x0 0x030f0000 0x0 0x1000>; 1326 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 1327 interrupt-names = "iommu-irq"; 1328 clocks = <&ccu CLK_BUS_IOMMU>; 1329 clock-names = "iommu"; 1330 #iommu-cells = <2>; 1331 }; 1332 1333 sdc2: sdmmc@4022000 { 1334 compatible = "allwinner,sunxi-mmc-v4p6x"; 1335 device_type = "sdc2"; 1336 reg = <0x0 0x04022000 0x0 0x1000>; 1337 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1338 clocks = <&dcxo24M>, 1339 <&ccu CLK_PLL_PERIPH1_2X>, 1340 <&ccu CLK_MMC2>, 1341 <&ccu CLK_BUS_MMC2>; 1342 clock-names = "osc24m","pll_periph","mmc","ahb"; 1343 resets = <&ccu RST_BUS_MMC2>; 1344 reset-names = "rst"; 1345 pinctrl-names = "default","sleep"; 1346 pinctrl-0 = <&sdc2_pins_a &sdc2_pins_c>; 1347 pinctrl-1 = <&sdc2_pins_b>; 1348 bus-width = <8>; 1349 req-page-count = <2>; 1350 cap-mmc-highspeed; 1351 mmc-cache-ctrl; 1352 non-removable; 1353 /*max-frequency = <200000000>;*/ 1354 max-frequency = <50000000>; 1355 cap-erase; 1356 mmc-high-capacity-erase-size; 1357 /*-- speed mode --*/ 1358 /*sm0: DS26_SDR12*/ 1359 /*sm1: HSSDR52_SDR25*/ 1360 /*sm2: HSDDR52_DDR50*/ 1361 /*sm3: HS200_SDR104*/ 1362 /*sm4: HS400*/ 1363 /*-- frequency point --*/ 1364 /*f0: CLK_400K*/ 1365 /*f1: CLK_25M*/ 1366 /*f2: CLK_50M*/ 1367 /*f3: CLK_100M*/ 1368 /*f4: CLK_150M*/ 1369 /*f5: CLK_200M*/ 1370 sdc_tm4_sm0_freq0 = <0>; 1371 sdc_tm4_sm0_freq1 = <0>; 1372 sdc_tm4_sm1_freq0 = <0x00000000>; 1373 sdc_tm4_sm1_freq1 = <0>; 1374 sdc_tm4_sm2_freq0 = <0x00000000>; 1375 sdc_tm4_sm2_freq1 = <0>; 1376 sdc_tm4_sm3_freq0 = <0x05000000>; 1377 sdc_tm4_sm3_freq1 = <0x00000005>; 1378 sdc_tm4_sm4_freq0 = <0x00050000>; 1379 sdc_tm4_sm4_freq1 = <0x00000004>; 1380 sdc_tm4_sm4_freq0_cmd = <0>; 1381 sdc_tm4_sm4_freq1_cmd = <0>; 1382 /*vmmc-supply = <®_3p3v>;*/ 1383 /*vqmc-supply = <®_3p3v>;*/ 1384 /*vdmc-supply = <®_3p3v>;*/ 1385 /*vmmc = "vcc-card";*/ 1386 /*vqmc = "";*/ 1387 /*vdmc = "";*/ 1388 sunxi-power-save-mode; 1389 sunxi-dis-signal-vol-sw; 1390 ctl-spec-caps = <0x308>; 1391 status = "disabled"; 1392 1393 }; 1394 1395 sdc0: sdmmc@4020000 { 1396 compatible = "allwinner,sunxi-mmc-v4p1x"; 1397 device_type = "sdc0"; 1398 reg = <0x0 0x04020000 0x0 0x1000>; 1399 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1400 clocks = <&dcxo24M>, 1401 <&ccu CLK_PLL_PERIPH1_2X>, 1402 <&ccu CLK_MMC0>, 1403 <&ccu CLK_BUS_MMC0>; 1404 clock-names = "osc24m","pll_periph","mmc","ahb"; 1405 resets = <&ccu RST_BUS_MMC0>; 1406 reset-names = "rst"; 1407 pinctrl-names = "default","mmc_1v8","sleep","uart_jtag"; 1408 pinctrl-0 = <&sdc0_pins_a>; 1409 pinctrl-1 = <&sdc0_pins_b>; 1410 pinctrl-2 = <&sdc0_pins_c>; 1411 pinctrl-3 = <&sdc0_pins_d &sdc0_pins_e>; 1412 max-frequency = <50000000>; 1413 bus-width = <4>; 1414 req-page-count = <2>; 1415 /*non-removable;*/ 1416 /*broken-cd;*/ 1417 /*cd-inverted*/ 1418 /* vmmc-supply = <®_3p3v>;*/ 1419 /* vqmc-supply = <®_3p3v>;*/ 1420 /* vdmc-supply = <®_3p3v>;*/ 1421 cap-sd-highspeed; 1422 cap-wait-while-busy; 1423 /*sd-uhs-sdr50;*/ 1424 /*sd-uhs-ddr50;*/ 1425 /*cap-sdio-irq;*/ 1426 /*keep-power-in-suspend;*/ 1427 /*ignore-pm-notify;*/ 1428 /*sunxi-power-save-mode;*/ 1429 /*sunxi-dly-400k = <1 0 0 0>; */ 1430 /*sunxi-dly-26M = <1 0 0 0>;*/ 1431 /*sunxi-dly-52M = <1 0 0 0>;*/ 1432 /*sunxi-dly-52M-ddr4 = <1 0 0 0>;*/ 1433 /*sunxi-dly-52M-ddr8 = <1 0 0 0>;*/ 1434 /*sunxi-dly-104M = <1 0 0 0>;*/ 1435 /*sunxi-dly-208M = <1 0 0 0>;*/ 1436 /*sunxi-dly-104M-ddr = <1 0 0 0>;*/ 1437 /*sunxi-dly-208M-ddr = <1 0 0 0>;*/ 1438 ctl-spec-caps = <0x8>; 1439 status = "okay"; 1440 }; 1441 1442 sdc1: sdmmc@4021000 { 1443 compatible = "allwinner,sunxi-mmc-v4p1x"; 1444 device_type = "sdc1"; 1445 reg = <0x0 0x04021000 0x0 0x1000>; 1446 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1447 clocks = <&dcxo24M>, 1448 <&ccu CLK_PLL_PERIPH1_2X>, 1449 <&ccu CLK_MMC1>, 1450 <&ccu CLK_BUS_MMC1>; 1451 clock-names = "osc24m","pll_periph","mmc","ahb"; 1452 resets = <&ccu RST_BUS_MMC1>; 1453 reset-names = "rst"; 1454 pinctrl-names = "default","sleep"; 1455 pinctrl-0 = <&sdc1_pins_a>; 1456 pinctrl-1 = <&sdc1_pins_b>; 1457 max-frequency = <50000000>; 1458 bus-width = <4>; 1459 /*broken-cd;*/ 1460 /*cd-inverted*/ 1461 /*cd-gpios = <&pio PG 6 6 1 2 0>;*/ 1462 /* vmmc-supply = <®_3p3v>;*/ 1463 /* vqmc-supply = <®_3p3v>;*/ 1464 /* vdmc-supply = <®_3p3v>;*/ 1465 /*vmmc = "vcc-card";*/ 1466 /*vqmc = "";*/ 1467 /*vdmc = "";*/ 1468 cap-sd-highspeed; 1469 /*sd-uhs-sdr50;*/ 1470 /*sd-uhs-ddr50;*/ 1471 /*sd-uhs-sdr104;*/ 1472 /*cap-sdio-irq;*/ 1473 keep-power-in-suspend; 1474 /*ignore-pm-notify;*/ 1475 /*sunxi-power-save-mode;*/ 1476 /*sunxi-dly-400k = <1 0 0 0 0>; */ 1477 /*sunxi-dly-26M = <1 0 0 0 0>;*/ 1478 /*sunxi-dly-52M = <1 0 0 0 0>;*/ 1479 sunxi-dly-52M-ddr4 = <1 0 0 0 2>; 1480 /*sunxi-dly-52M-ddr8 = <1 0 0 0 0>;*/ 1481 sunxi-dly-104M = <1 0 0 0 1>; 1482 /*sunxi-dly-208M = <1 1 0 0 0>;*/ 1483 sunxi-dly-208M = <1 0 0 0 1>; 1484 /*sunxi-dly-104M-ddr = <1 0 0 0 0>;*/ 1485 /*sunxi-dly-208M-ddr = <1 0 0 0 0>;*/ 1486 ctl-spec-caps = <0x8>; 1487 status = "disabled"; 1488 }; 1489 1490 nand0:nand0@4011000 { 1491 compatible = "allwinner,sun50iw9-nand"; 1492 device_type = "nand0"; 1493 reg = <0x0 0x04011000 0x0 0x1000>;/* nand0 */ 1494 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1495 clocks = <&ccu CLK_PLL_PERIPH1_2X>, 1496 <&ccu CLK_NAND0>, 1497 <&ccu CLK_NAND1>, 1498 <&ccu CLK_BUS_NAND>, 1499 <&ccu CLK_MBUS_NAND>; 1500 clock-names = "pll_periph","mclk","ecc", "bus", "mbus"; 1501 resets = <&ccu RST_BUS_NAND>; 1502 reset-names = "rst"; 1503 pinctrl-names = "default", "sleep"; 1504 pinctrl-0 = <&nand0_pins_a &nand0_pins_b>; 1505 pinctrl-1 = <&nand0_pins_c>; 1506 nand0_cache_level = <0x55aaaa55>; 1507 nand0_flush_cache_num = <0x55aaaa55>; 1508 nand0_capacity_level = <0x55aaaa55>; 1509 nand0_id_number_ctl = <0x55aaaa55>; 1510 nand0_print_level = <0x55aaaa55>; 1511 nand0_p0 = <0x55aaaa55>; 1512 nand0_p1 = <0x55aaaa55>; 1513 nand0_p2 = <0x55aaaa55>; 1514 nand0_p3 = <0x55aaaa55>; 1515 chip_code = "sun50iw9"; 1516 status = "disabled"; 1517 /*boot_crc="disabled";*/ 1518 }; 1519 1520 1521 mbus0: mbus-controller@47fa000 { 1522 compatible = "allwinner,sun50i-mbus"; 1523 reg = <0x0 0x047fa000 0x0 0x1000>; 1524 #mbus-cells = <1>; 1525 }; 1526 1527 uart0: uart@5000000 { 1528 compatible = "allwinner,sun50i-uart"; 1529 reg = <0x0 0x05000000 0x0 0x400>; 1530 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 1531 clocks = <&ccu CLK_BUS_UART0>; 1532 resets = <&ccu RST_BUS_UART0>; 1533 uart0_port = <0>; 1534 uart0_type = <2>; 1535 status = "disabled"; 1536 }; 1537 1538 uart1: uart@5000400 { 1539 compatible = "allwinner,sun50i-uart"; 1540 reg = <0x0 0x05000400 0x0 0x400>; 1541 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 1542 clocks = <&ccu CLK_BUS_UART1>; 1543 resets = <&ccu RST_BUS_UART1>; 1544 uart1_port = <1>; 1545 uart1_type = <4>; 1546 sunxi,uart-fifosize = <256>; 1547 status = "disabled"; 1548 }; 1549 1550 uart2: uart@5000800 { 1551 compatible = "allwinner,sun50i-uart"; 1552 reg = <0x0 0x05000800 0x0 0x400>; 1553 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1554 clocks = <&ccu CLK_BUS_UART2>; 1555 resets = <&ccu RST_BUS_UART2>; 1556 uart2_port = <2>; 1557 uart2_type = <4>; 1558 sunxi,uart-fifosize = <256>; 1559 status = "disabled"; 1560 }; 1561 1562 uart3: uart@5000c00 { 1563 compatible = "allwinner,sun50i-uart"; 1564 reg = <0x0 0x05000c00 0x0 0x400>; 1565 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1566 clocks = <&ccu CLK_BUS_UART3>; 1567 resets = <&ccu RST_BUS_UART3>; 1568 uart3_port = <3>; 1569 uart3_type = <4>; 1570 sunxi,uart-fifosize = <256>; 1571 status = "disabled"; 1572 }; 1573 1574 uart4: uart@5001000 { 1575 compatible = "allwinner,sun50i-uart"; 1576 reg = <0x0 0x05001000 0x0 0x400>; 1577 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1578 clocks = <&ccu CLK_BUS_UART4>; 1579 resets = <&ccu RST_BUS_UART4>; 1580 uart4_port = <4>; 1581 uart4_type = <4>; 1582 sunxi,uart-fifosize = <256>; 1583 status = "disabled"; 1584 }; 1585 1586 uart5: uart@5001400 { 1587 compatible = "allwinner,sun50i-uart"; 1588 reg = <0x0 0x05001400 0x0 0x400>; 1589 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1590 clocks = <&ccu CLK_BUS_UART5>; 1591 resets = <&ccu RST_BUS_UART5>; 1592 uart5_port = <5>; 1593 uart5_type = <2>; 1594 sunxi,uart-fifosize = <256>; 1595 status = "disabled"; 1596 }; 1597 1598 twi0: twi@5002000 { 1599 #address-cells = <1>; 1600 #size-cells = <0>; 1601 compatible = "allwinner,sun50i-twi"; 1602 device_type = "twi0"; 1603 reg = <0x0 0x05002000 0x0 0x400>; 1604 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1605 clocks = <&ccu CLK_BUS_I2C0>; 1606 clock-names = "bus"; 1607 resets = <&ccu RST_BUS_I2C0>; 1608 dmas = <&dma 43>, <&dma 43>; 1609 dma-names = "tx", "rx"; 1610 status = "disabled"; 1611 }; 1612 1613 twi1: twi@5002400 { 1614 #address-cells = <1>; 1615 #size-cells = <0>; 1616 compatible = "allwinner,sun50i-twi"; 1617 device_type = "twi1"; 1618 reg = <0x0 0x05002400 0x0 0x400>; 1619 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1620 clocks = <&ccu CLK_BUS_I2C1>; 1621 clock-names = "bus"; 1622 resets = <&ccu RST_BUS_I2C1>; 1623 dmas = <&dma 44>, <&dma 44>; 1624 dma-names = "tx", "rx"; 1625 status = "disabled"; 1626 }; 1627 1628 twi2: twi@5002800 { 1629 #address-cells = <1>; 1630 #size-cells = <0>; 1631 compatible = "allwinner,sun50i-twi"; 1632 device_type = "twi2"; 1633 reg = <0x0 0x05002800 0x0 0x400>; 1634 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1635 clocks = <&ccu CLK_BUS_I2C2>; 1636 clock-names = "bus"; 1637 resets = <&ccu RST_BUS_I2C2>; 1638 dmas = <&dma 45>, <&dma 45>; 1639 dma-names = "tx", "rx"; 1640 status = "disabled"; 1641 }; 1642 1643 twi3: twi@5002c00 { 1644 #address-cells = <1>; 1645 #size-cells = <0>; 1646 compatible = "allwinner,sun50i-twi"; 1647 device_type = "twi3"; 1648 reg = <0x0 0x05002c00 0x0 0x400>; 1649 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1650 clocks = <&ccu CLK_BUS_I2C3>; 1651 clock-names = "bus"; 1652 resets = <&ccu RST_BUS_I2C3>; 1653 dmas = <&dma 46>, <&dma 46>; 1654 dma-names = "tx", "rx"; 1655 status = "disabled"; 1656 }; 1657 1658 twi4: twi@5003000 { 1659 #address-cells = <1>; 1660 #size-cells = <0>; 1661 compatible = "allwinner,sun50i-twi"; 1662 device_type = "twi4"; 1663 reg = <0x0 0x05003000 0x0 0x400>; 1664 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1665 clocks = <&ccu CLK_BUS_I2C4>; 1666 clock-names = "bus"; 1667 resets = <&ccu RST_BUS_I2C4>; 1668 dmas = <&dma 47>, <&dma 47>; 1669 dma-names = "tx", "rx"; 1670 status = "disabled"; 1671 }; 1672 1673 twi5: twi@7081400 { 1674 #address-cells = <1>; 1675 #size-cells = <0>; 1676 compatible = "allwinner,sun50i-twi"; 1677 device_type = "twi5"; 1678 reg = <0x0 0x07081400 0x0 0x400>; 1679 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1680 clocks = <&r_ccu CLK_R_APB2_I2C>; 1681 clock-names = "bus"; 1682 resets = <&r_ccu RST_R_APB2_I2C>; 1683 dmas = <&dma 48>, <&dma 48>; 1684 dma-names = "tx", "rx"; 1685 status = "disabled"; 1686 }; 1687 1688 spi0: spi@5010000 { 1689 #address-cells = <1>; 1690 #size-cells = <0>; 1691 compatible = "allwinner,sun50i-spi"; 1692 device_type = "spi0"; 1693 reg = <0x0 0x05010000 0x0 0x1000>; 1694 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1695 clocks = <&ccu CLK_PLL_PERIPH0>, <&ccu CLK_SPI0>, <&ccu CLK_BUS_SPI0>; 1696 clock-names = "pll", "mod", "bus"; 1697 resets = <&ccu RST_BUS_SPI0>; 1698 clock-frequency = <100000000>; 1699 spi0_cs_number = <1>; 1700 spi0_cs_bitmap = <1>; 1701 dmas = <&dma 22>, <&dma 22>; 1702 dma-names = "tx", "rx"; 1703 status = "disabled"; 1704 }; 1705 1706 spi1: spi@5011000 { 1707 #address-cells = <1>; 1708 #size-cells = <0>; 1709 compatible = "allwinner,sun50i-spi"; 1710 device_type = "spi1"; 1711 reg = <0x0 0x05011000 0x0 0x1000>; 1712 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1713 clocks = <&ccu CLK_PLL_PERIPH0>, <&ccu CLK_SPI1>, <&ccu CLK_BUS_SPI1>; 1714 clock-names = "pll", "mod", "bus"; 1715 resets = <&ccu RST_BUS_SPI1>; 1716 clock-frequency = <100000000>; 1717 spi1_cs_number = <1>; 1718 spi1_cs_bitmap = <1>; 1719 dmas = <&dma 23>, <&dma 23>; 1720 dma-names = "tx", "rx"; 1721 status = "disabled"; 1722 }; 1723 1724 ths: thermal-sensor@5070400 { 1725 compatible = "allwinner,sun50iw9p1-ths"; 1726 reg = <0x0 0x05070400 0x0 0x400>; 1727 clocks = <&ccu CLK_BUS_THS>; 1728 clock-names = "bus"; 1729 resets = <&ccu RST_BUS_THS>; 1730 nvmem-cells = <&ths_calib>; 1731 nvmem-cell-names = "calibration"; 1732 #thermal-sensor-cells = <1>; 1733 }; 1734 1735 gpadc: gpadc@5070000 { 1736 compatible = "allwinner,sunxi-gpadc"; 1737 reg = <0x0 0x05070000 0x0 0x3ff>; 1738 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1739 clocks = <&ccu CLK_BUS_GPADC>; 1740 clock-names = "bus"; 1741 resets = <&ccu RST_BUS_GPADC>; 1742 status = "disabled"; 1743 }; 1744 1745 keyboard: keyboard@5070800 { 1746 compatible = "allwinner,keyboard_1350mv"; 1747 reg = <0x0 0x05070800 0x0 0x400>; 1748 interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>; 1749 clocks = <&ccu CLK_BUS_LRADC>; 1750 resets = <&ccu RST_BUS_LRADC>; 1751 status = "disabled"; 1752 }; 1753 1754 /* audio driver use harmony ADM */ 1755 /* audio dirver module -> audio codec */ 1756 codec:codec@5096000 { 1757 compatible = "allwinner,sunxi-snd-codec"; 1758 reg = <0x0 0x05096000 0x0 0x31C>; 1759 /* clocks = <&clk_pll_audio>,<&clk_pll_audiox4>,<&clk_codec_1x>; */ 1760 resets = <&ccu RST_BUS_AUDIO_CODEC>; 1761 clocks = <&ccu CLK_PLL_AUDIO>, 1762 <&ccu CLK_PLL_AUDIO_4X>, 1763 <&ccu CLK_AUDIO>, 1764 <&ccu CLK_BUS_AUDIO_CODEC>; 1765 clock-names = "clk_pll_audio", 1766 "clk_pll_audio_4x", 1767 "clk_audio", 1768 "clk_bus_audio"; 1769 dmas = <&dma 6>, <&dma 6>; 1770 dma-names = "tx", "rx"; 1771 status = "disabled"; 1772 }; 1773 1774 /* audio dirver module -> audio hub */ 1775 ahub:ahub@5097000 { 1776 compatible = "allwinner,sunxi-snd-ahub"; 1777 reg = <0x0 0x05097000 0x0 0xAEC>; 1778 /* clocks = <&clk_pll_audio>,<&clk_pll_audiox4>,<&clk_ahub>; */ 1779 resets = <&ccu RST_BUS_AUDIO_HUB>; 1780 clocks = <&ccu CLK_PLL_AUDIO>, 1781 <&ccu CLK_PLL_AUDIO_4X>, 1782 <&ccu CLK_AUDIO_HUB>, 1783 <&ccu CLK_BUS_AUDIO_HUB>; 1784 clock-names = "clk_pll_audio", 1785 "clk_pll_audio_4x", 1786 "clk_audio_hub", 1787 "clk_bus_audio_hub"; 1788 dmas = <&dma 3>, <&dma 3>; 1789 dma-names = "tx", "rx"; 1790 status = "disabled"; 1791 }; 1792 1793/*------------------------------------------------------------------------------ 1794 codec:codec@5096000 { 1795 #sound-dai-cells = <0>; 1796 compatible = "allwinner,sunxi-snd-codec"; 1797 reg = <0x0 0x05096000 0x0 0x31C>; 1798 resets = <&ccu RST_BUS_AUDIO_CODEC>; 1799 clocks = <&ccu CLK_PLL_AUDIO_4X>, 1800 <&ccu CLK_AUDIO>, 1801 <&ccu CLK_BUS_AUDIO_CODEC>; 1802 clock-names = "clk_pll_audio_4x", 1803 "clk_audio", 1804 "clk_bus_audio"; 1805 status = "disabled"; 1806 }; 1807 1808 codec_plat:codec_plat { 1809 #sound-dai-cells = <0>; 1810 compatible = "allwinner,sunxi-snd-plat-aaudio"; 1811 playback_cma = <128>; 1812 capture_cma = <128>; 1813 tx_fifo_size = <128>; 1814 rx_fifo_size = <128>; 1815 dac_txdata = <0x05096020>; 1816 adc_txdata = <0x05096040>; 1817 dmas = <&dma 6>, <&dma 6>; 1818 dma-names = "tx", "rx"; 1819 status = "disabled"; 1820 }; 1821 1822 codec_mach:codec_mach { 1823 compatible = "allwinner,sunxi-snd-mach"; 1824 soundcard-mach,name = "audiocodec"; 1825 soundcard-mach,playback-only; 1826 soundcard-mach,pin-switches = "LINEOUT"; 1827 soundcard-mach,routing = "LINEOUT", "LINEOUTL", 1828 "LINEOUT", "LINEOUTR"; 1829 status = "disabled"; 1830 soundcard-mach,cpu { 1831 sound-dai = <&codec_plat>; 1832 }; 1833 soundcard-mach,codec { 1834 sound-dai = <&codec>; 1835 soundcard-mach,pll-fs = <4>; 1836 }; 1837 }; 1838 1839 spdif_plat:spdif_plat@5093000 { 1840 #sound-dai-cells = <0>; 1841 compatible = "allwinner,sunxi-snd-plat-spdif"; 1842 reg = <0x0 0x05093000 0x0 0x40>; 1843 resets = <&ccu RST_BUS_SPDIF>; 1844 clocks = <&ccu CLK_PLL_AUDIO_4X>, 1845 <&ccu CLK_SPDIF>, 1846 <&ccu CLK_BUS_SPDIF>; 1847 clock-names = "clk_pll_audio_4x", 1848 "clk_spdif", 1849 "clk_bus_spdif"; 1850 pll-fs = <4>; 1851 dmas = <&dma 2>, <&dma 2>; 1852 dma-names = "tx", "rx"; 1853 playback_cma = <128>; 1854 capture_cma = <128>; 1855 tx_fifo_size = <128>; 1856 rx_fifo_size = <64>; 1857 status = "disabled"; 1858 }; 1859 1860 spdif_mach:spdif_mach { 1861 compatible = "allwinner,sunxi-snd-mach"; 1862 soundcard-mach,name = "sndspdif"; 1863 status = "disabled"; 1864 soundcard-mach,cpu { 1865 sound-dai = <&spdif_plat>; 1866 soundcard-mach,pll-fs = <4>; 1867 }; 1868 soundcard-mach,codec { 1869 }; 1870 }; 1871 1872 ahub_dam_plat:ahub_dam_plat@5097000 { 1873 #sound-dai-cells = <0>; 1874 compatible = "allwinner,sunxi-snd-plat-ahub_dam"; 1875 reg = <0x0 0x05097000 0x0 0xAEC>; 1876 resets = <&ccu RST_BUS_AUDIO_HUB>; 1877 clocks = <&ccu CLK_PLL_AUDIO>, 1878 <&ccu CLK_PLL_AUDIO_4X>, 1879 <&ccu CLK_AUDIO_HUB>, 1880 <&ccu CLK_BUS_AUDIO_HUB>; 1881 clock-names = "clk_pll_audio", 1882 "clk_pll_audio_4x", 1883 "clk_audio_hub", 1884 "clk_bus_audio_hub"; 1885 status = "disabled"; 1886 }; 1887 1888 ahub_dam_mach:ahub_dam_mach { 1889 compatible = "allwinner,sunxi-snd-mach"; 1890 soundcard-mach,name = "ahubdam"; 1891 status = "disabled"; 1892 soundcard-mach,cpu { 1893 sound-dai = <&ahub_dam_plat>; 1894 }; 1895 soundcard-mach,codec { 1896 }; 1897 }; 1898 1899 ahub0_plat:ahub0_plat { 1900 #sound-dai-cells = <0>; 1901 compatible = "allwinner,sunxi-snd-plat-ahub"; 1902 apb_num = <0>; 1903 dmas = <&dma 3>, <&dma 3>; 1904 dma-names = "tx", "rx"; 1905 playback_cma = <128>; 1906 capture_cma = <128>; 1907 tx_fifo_size = <128>; 1908 rx_fifo_size = <128>; 1909 status = "disabled"; 1910 }; 1911 1912 ahub1_plat:ahub1_plat { 1913 #sound-dai-cells = <0>; 1914 compatible = "allwinner,sunxi-snd-plat-ahub"; 1915 apb_num = <1>; 1916 dmas = <&dma 4>, <&dma 4>; 1917 dma-names = "tx", "rx"; 1918 playback_cma = <128>; 1919 capture_cma = <128>; 1920 tx_fifo_size = <128>; 1921 rx_fifo_size = <128>; 1922 status = "disabled"; 1923 }; 1924 1925 ahub2_plat:ahub2_plat { 1926 #sound-dai-cells = <0>; 1927 compatible = "allwinner,sunxi-snd-plat-ahub"; 1928 apb_num = <2>; 1929 dmas = <&dma 5>, <&dma 5>; 1930 dma-names = "tx", "rx"; 1931 playback_cma = <128>; 1932 capture_cma = <128>; 1933 tx_fifo_size = <128>; 1934 rx_fifo_size = <128>; 1935 status = "disabled"; 1936 }; 1937 1938 ahub3_plat:ahub3_plat { 1939 #sound-dai-cells = <0>; 1940 compatible = "allwinner,sunxi-snd-plat-ahub"; 1941 apb_num = <2>; 1942 dmas = <&dma 5>, <&dma 5>; 1943 dma-names = "tx", "rx"; 1944 playback_cma = <128>; 1945 capture_cma = <128>; 1946 tx_fifo_size = <128>; 1947 rx_fifo_size = <128>; 1948 status = "disabled"; 1949 }; 1950 1951 ahub0_mach:ahub0_mach { 1952 compatible = "allwinner,sunxi-snd-mach"; 1953 soundcard-mach,name = "ahubi2s0"; 1954 status = "disabled"; 1955 soundcard-mach,cpu { 1956 sound-dai = <&ahub0_plat>; 1957 }; 1958 soundcard-mach,codec { 1959 }; 1960 }; 1961 1962 ahub1_mach:ahub1_mach { 1963 compatible = "allwinner,sunxi-snd-mach"; 1964 soundcard-mach,name = "ahubhdmi"; 1965 status = "disabled"; 1966 soundcard-mach,cpu { 1967 sound-dai = <&ahub1_plat>; 1968 }; 1969 soundcard-mach,codec { 1970 }; 1971 }; 1972 1973 ahub2_mach:ahub2_mach { 1974 compatible = "allwinner,sunxi-snd-mach"; 1975 soundcard-mach,name = "ahubi2s2"; 1976 status = "disabled"; 1977 soundcard-mach,cpu { 1978 sound-dai = <&ahub2_plat>; 1979 }; 1980 soundcard-mach,codec { 1981 }; 1982 }; 1983 1984 ahub3_mach:ahub3_mach { 1985 compatible = "allwinner,sunxi-snd-mach"; 1986 soundcard-mach,name = "ahubi2s3"; 1987 status = "disabled"; 1988 soundcard-mach,cpu { 1989 sound-dai = <&ahub3_plat>; 1990 }; 1991 soundcard-mach,codec { 1992 }; 1993 }; 1994------------------------------------------------------------------------------*/ 1995 1996 gpio_para:gpio_para { 1997 device_type = "gpio_para"; 1998 compatible = "allwinner,sunxi-init-gpio"; 1999 status = "disabled"; 2000 }; 2001 2002 mdio0: mdio0@5020048 { 2003 compatible = "allwinner,sunxi-mdio"; 2004 #address-cells = <1>; 2005 #size-cells = <0>; 2006 reg = <0x0 0x05020048 0x0 0x8>; 2007 status = "okay"; 2008 gmac0_phy0: ethernet-phy@1 { 2009 /* RTL8211F (0x001cc916) */ 2010 reg = <1>; 2011 max-speed = <1000>; /* Max speed capability */ 2012 reset-gpios = <&pio PI 6 GPIO_ACTIVE_LOW>; 2013 /* PHY datasheet rst time */ 2014 reset-assert-us = <10000>; 2015 reset-deassert-us = <150000>; 2016 }; 2017 }; 2018 2019 gmac0: gmac0@5020000 { 2020 compatible = "allwinner,sunxi-gmac"; 2021 reg = <0x0 0x05020000 0x0 0x10000>, 2022 <0x0 0x03000030 0x0 0x4>; 2023 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2024 interrupt-names = "gmacirq"; 2025 clocks = <&ccu CLK_BUS_EMAC0>, <&ccu CLK_EMAC_25M>; 2026 clock-names = "gmac", "phy25m"; 2027 resets = <&ccu RST_BUS_EMAC0>; 2028 phy-handle = <&gmac0_phy0>; 2029 status = "disabled"; 2030 }; 2031 2032 usbc0: usbc0@0 { 2033 device_type = "usbc0"; 2034 compatible = "allwinner,sunxi-otg-manager"; 2035 usb_port_type = <2>; 2036 usb_detect_type = <1>; 2037 usb_detect_mode = <0>; 2038 usb_id_gpio; 2039 usb_det_vbus_gpio; 2040 usb_drv_vbus_gpio; 2041 usb_host_init_state = <0>; 2042 usb_regulator_io = "nocare"; 2043 usb_wakeup_suspend = <0>; 2044 usb_luns = <3>; 2045 usb_serial_unique = <0>; 2046 usb_serial_number = "20080411"; 2047 rndis_wceis = <1>; 2048 wakeup-source; 2049 }; 2050 2051 udc: udc-controller@5100000 { 2052 compatible = "allwinner,sunxi-udc"; 2053 reg = <0x0 0x05100000 0x0 0x1000>, 2054 <0x0 0x00000000 0x0 0x100>; 2055 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 2056 interrupt-parent = <&gic>; 2057 clocks = <&ccu CLK_BUS_OTG>, <&ccu CLK_USB_PHY0>; 2058 clock-names = "bus_otg", "phy"; 2059 resets = <&ccu RST_BUS_OTG>, <&ccu RST_USB_PHY0>; 2060 reset-names = "otg", "phy"; 2061 }; 2062 2063 ehci0: ehci0-controller@5101000 { 2064 compatible = "allwinner,sunxi-ehci0"; 2065 reg = <0x0 0x05101000 0x0 0xFFF>, 2066 <0x0 0x00000000 0x0 0x100>, 2067 <0x0 0x05100000 0x0 0x1000>; 2068 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 2069 clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_USB_PHY0>; 2070 clock-names = "bus_hci", "phy"; 2071 resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_USB_PHY0>; 2072 reset-names = "hci", "phy"; 2073 hci_ctrl_no = <0>; 2074 }; 2075 2076 ohci0: ohci0-controller@5101400 { 2077 compatible = "allwinner,sunxi-ohci0"; 2078 reg = <0x0 0x05101400 0x0 0xFFF>, 2079 <0x0 0x00000000 0x0 0x100>, 2080 <0x0 0x05100000 0x0 0x1000>; 2081 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 2082 clocks = <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>, <&ccu CLK_USB_PHY0>; 2083 clock-names = "bus_hci", "ohci", "phy"; 2084 resets = <&ccu RST_BUS_OHCI0>, <&ccu RST_USB_PHY0>; 2085 reset-names = "hci", "phy"; 2086 hci_ctrl_no = <0>; 2087 }; 2088 2089 usbc1: usbc1@0 { 2090 device_type = "usbc1"; 2091 usb_drv_vbus_gpio; 2092 usb_host_init_state = <1>; 2093 usb_regulatior_io = "nocare"; 2094 usb_wakeup_suspend = <0>; 2095 wakeup-source; 2096 }; 2097 2098 ehci1: ehci1-controller@5200000 { 2099 compatible = "allwinner,sunxi-ehci1"; 2100 reg = <0x0 0x05200000 0x0 0xFFF>, 2101 <0x0 0x00000000 0x0 0x100>, 2102 <0x0 0x05100000 0x0 0x1000>; 2103 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 2104 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_USB_PHY1>; 2105 clock-names = "bus_hci", "phy"; 2106 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_USB_PHY1>; 2107 reset-names = "hci", "phy"; 2108 hci_ctrl_no = <1>; 2109 }; 2110 2111 ohci1: ohci1-controller@5200400 { 2112 compatible = "allwinner,sunxi-ohci1"; 2113 reg = <0x0 0x05200400 0x0 0xFFF>, 2114 <0x0 0x00000000 0x0 0x100>, 2115 <0x0 0x05100000 0x0 0x1000>; 2116 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 2117 clocks = <&ccu CLK_BUS_OHCI1>, <&ccu CLK_USB_OHCI1>, <&ccu CLK_USB_PHY1>; 2118 clock-names = "bus_hci", "ohci", "phy"; 2119 resets = <&ccu RST_BUS_OHCI1>, <&ccu RST_USB_PHY1>; 2120 reset-names = "hci", "phy"; 2121 hci_ctrl_no = <1>; 2122 }; 2123 2124 usbc2: usbc2@0 { 2125 device_type = "usbc2"; 2126 usb_drv_vbus_gpio; 2127 usb_host_init_state = <1>; 2128 usb_regulatior_io = "nocare"; 2129 usb_wakeup_suspend = <0>; 2130 wakeup-source; 2131 }; 2132 2133 ehci2: ehci2-controller@5310000 { 2134 compatible = "allwinner,sunxi-ehci2"; 2135 reg = <0x0 0x05310000 0x0 0xFFF>, 2136 <0x0 0x00000000 0x0 0x100>, 2137 <0x0 0x05100000 0x0 0x1000>; 2138 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 2139 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_USB_PHY2>; 2140 clock-names = "bus_hci", "phy"; 2141 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_USB_PHY2>; 2142 reset-names = "hci", "phy"; 2143 hci_ctrl_no = <2>; 2144 }; 2145 2146 ohci2: ohci2-controller@5310400 { 2147 compatible = "allwinner,sunxi-ohci2"; 2148 reg = <0x0 0x05310400 0x0 0xFFF>, 2149 <0x0 0x00000000 0x0 0x100>, 2150 <0x0 0x05100000 0x0 0x1000>; 2151 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 2152 clocks = <&ccu CLK_BUS_OHCI2>, <&ccu CLK_USB_OHCI2>, <&ccu CLK_USB_PHY2>; 2153 clock-names = "bus_hci", "ohci", "phy"; 2154 resets = <&ccu RST_BUS_OHCI2>, <&ccu RST_USB_PHY2>; 2155 reset-names = "hci", "phy"; 2156 hci_ctrl_no = <2>; 2157 }; 2158 2159 usbc3: usbc3@0 { 2160 device_type = "usbc3"; 2161 usb_drv_vbus_gpio; 2162 usb_host_init_state = <1>; 2163 usb_regulatior_io = "nocare"; 2164 usb_wakeup_suspend = <0>; 2165 wakeup-source; 2166 }; 2167 2168 ehci3: ehci3-controller@5311000 { 2169 compatible = "allwinner,sunxi-ehci3"; 2170 reg = <0x0 0x05311000 0x0 0xFFF>, 2171 <0x0 0x00000000 0x0 0x100>, 2172 <0x0 0x05100000 0x0 0x1000>; 2173 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 2174 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_USB_PHY3>; 2175 clock-names = "bus_hci", "phy"; 2176 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_USB_PHY3>; 2177 reset-names = "hci", "phy"; 2178 hci_ctrl_no = <3>; 2179 }; 2180 2181 ohci3: ohci3-controller@5311400 { 2182 compatible = "allwinner,sunxi-ohci3"; 2183 reg = <0x0 0x05311400 0x0 0xFFF>, 2184 <0x0 0x00000000 0x0 0x100>, 2185 <0x0 0x05100000 0x0 0x1000>; 2186 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 2187 clocks = <&ccu CLK_BUS_OHCI3>, <&ccu CLK_USB_OHCI3>, <&ccu CLK_USB_PHY3>; 2188 clock-names = "bus_hci", "ohci", "phy"; 2189 resets = <&ccu RST_BUS_OHCI3>, <&ccu RST_USB_PHY3>; 2190 reset-names = "hci", "phy"; 2191 hci_ctrl_no = <3>; 2192 }; 2193 2194 hdmi: hdmi@6000000 { 2195 compatible = "allwinner,sunxi-hdmi"; 2196 reg = <0x0 0x06000000 0x0 0x100000>; 2197 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 2198 clocks = <&ccu CLK_BUS_HDMI>, 2199 <&ccu CLK_HDMI>, 2200 <&ccu CLK_HDMI_SLOW>, 2201 <&ccu CLK_HDMI_CEC>, 2202 <&ccu CLK_BUS_HDMI_HDCP>, 2203 <&ccu CLK_HDMI_HDCP>, 2204 <&ccu CLK_TCON_TV0>; 2205 clock-names = "clk_bus_hdmi", 2206 "clk_hdmi", 2207 "clk_ddc", 2208 "clk_cec", 2209 "clk_bus_hdcp", 2210 "clk_hdcp", 2211 "clk_tcon_tv"; 2212 resets = <&ccu RST_BUS_HDMI_SUB>, 2213 <&ccu RST_BUS_HDMI_MAIN>, 2214 <&ccu RST_BUS_HDMI_HDCP>; 2215 reset-names = "rst_bus_sub", 2216 "rst_bus_main", 2217 "rst_bus_hdcp"; 2218 assigned-clocks = <&ccu CLK_HDMI>, 2219 <&ccu CLK_HDMI_HDCP>; 2220 assigned-clock-parents = <&ccu CLK_PLL_VIDEO2>, 2221 <&ccu CLK_PLL_PERIPH1>; 2222 assigned-clock-rates = <0>, <0>; 2223 2224 status = "okay"; 2225 }; 2226 2227 nmi_intc: interrupt-controller@7010320 { 2228 compatible = "allwinner,sun8i-nmi"; 2229 interrupt-controller; 2230 #interrupt-cells = <2>; 2231 reg = <0x0 0x07010320 0 0xc>; 2232 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 2233 pad-control-v1 = <0x07000208>; 2234 }; 2235 2236 s_cir0: s_cir@7040000 { 2237 compatible = "allwinner,s_cir"; 2238 reg = <0x0 0x07040000 0x0 0x400>; 2239 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 2240 clocks = <&r_ccu CLK_R_APB1_BUS_IR>, <&dcxo24M>, <&r_ccu CLK_R_APB1_IR>; 2241 clock-names = "bus", "pclk", "mclk"; 2242 resets = <&r_ccu RST_R_APB1_BUS_IR>; 2243 status = "disabled"; 2244 }; 2245 2246 rfkill: rfkill { 2247 compatible = "allwinner,sunxi-rfkill"; 2248 status = "disabled"; 2249 }; 2250 2251 addr_mgt: addr_mgt { 2252 compatible = "allwinner,sunxi-addr_mgt"; 2253 status = "disabled"; 2254 }; 2255 2256 btlpm: btlpm { 2257 compatible = "allwinner,sunxi-btlpm"; 2258 status = "disabled"; 2259 }; 2260 }; 2261 2262 uboot_disp: uboot_disp@1000000 { 2263 compatible = "allwinner,sunxi-disp"; 2264 reg = <0x0 0x01000000 0x0 0x01400000>, /* de */ 2265 <0x0 0x06510000 0x0 0x200>, /* display_if_top */ 2266 <0x0 0x06511000 0x0 0x1000>, /* tcon_lcd0 */ 2267 <0x0 0x06512000 0x0 0x1000>, /* tcon_lcd1 */ 2268 <0x0 0x06515000 0x0 0x1000>, /* tcon_tv0 */ 2269 <0x0 0x06516000 0x0 0x1000>; /* tcon_tv1 */ 2270 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, /* DE */ 2271 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* tcon_lcd0 */ 2272 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* tcon_lcd1 */ 2273 <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, /* tcon_tv0 */ 2274 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* tcon_tv1 */ 2275 clocks = <&clk_de>, 2276 <&clk_display_top>, 2277 <&clk_tcon_lcd>, 2278 <&clk_tcon_lcd1>, 2279 <&clk_tcon_tv>, 2280 <&clk_tcon_tv1>, 2281 <&clk_lvds>; 2282 boot_disp = <0>; 2283 fb_base = <0>; 2284 }; 2285 2286 uboot_hdmi: uboot_hdmi@6000000 { 2287 compatible = "allwinner,sunxi-hdmi"; 2288 reg = <0x0 0x06000000 0x0 0x100000>; 2289 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 2290 clocks = <&clk_hdmi>, <&clk_hdmi_slow>, 2291 <&clk_hdmi_hdcp>, <&clk_hdmi_cec>; 2292 }; 2293 2294 thermal-zones{ 2295 cpu_thermal_zone{ 2296 polling-delay-passive = <500>; 2297 polling-delay = <1000>; 2298 thermal-sensors = <&ths 2>; 2299 sustainable-power = <927>; 2300 2301 cpu_trips: trips{ 2302 cpu_threshold: trip-point@0 { 2303 temperature = <70000>; 2304 type = "passive"; 2305 hysteresis = <0>; 2306 }; 2307 cpu_target: trip-point@1 { 2308 temperature = <90000>; 2309 type = "passive"; 2310 hysteresis = <0>; 2311 }; 2312 }; 2313 2314 cooling-maps { 2315 map0 { 2316 trip = <&cpu_target>; 2317 cooling-device = <&cpu0 2318 THERMAL_NO_LIMIT 2319 THERMAL_NO_LIMIT>; 2320 contribution = <1024>; 2321 }; 2322 map1{ 2323 trip = <&cpu_target>; 2324 cooling-device = <&gpu 2325 THERMAL_NO_LIMIT 2326 THERMAL_NO_LIMIT>; 2327 contribution = <1024>; 2328 }; 2329 }; 2330 }; 2331 2332 ddr_thermal_zone { 2333 polling-delay-passive = <0>; 2334 polling-delay = <0>; 2335 thermal-sensors = <&ths 3>; 2336 }; 2337 2338 gpu_thermal_zone { 2339 polling-delay-passive = <500>; 2340 polling-delay = <1000>; 2341 thermal-sensors = <&ths 0>; 2342 sustainable-power = <1100>; 2343 }; 2344 2345 ve_thermal_zone { 2346 polling-delay-passive = <0>; 2347 polling-delay = <0>; 2348 thermal-sensors = <&ths 1>; 2349 }; 2350 }; 2351}; 2352