1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2020 frank@allwinnertech.com
4 */
5
6 #include <linux/clk-provider.h>
7 #include <linux/module.h>
8 #include <linux/of_address.h>
9 #include <linux/platform_device.h>
10
11 #include "ccu_common.h"
12 #include "ccu_reset.h"
13
14 #include "ccu_div.h"
15 #include "ccu_gate.h"
16 #include "ccu_mp.h"
17 #include "ccu_nm.h"
18
19 #include "ccu-sun50iw10-r.h"
20
21 static const char * const cpus_r_apb2_parents[] = { "dcxo24M", "osc32k",
22 "iosc", "pll-periph0" };
23 static const struct ccu_mux_var_prediv cpus_r_apb2_predivs[] = {
24 { .index = 3, .shift = 0, .width = 5 },
25 };
26
27 static struct ccu_div cpus_clk = {
28 .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
29
30 .mux = {
31 .shift = 24,
32 .width = 2,
33
34 .var_predivs = cpus_r_apb2_predivs,
35 .n_var_predivs = ARRAY_SIZE(cpus_r_apb2_predivs),
36 },
37
38 .common = {
39 .reg = 0x000,
40 .features = CCU_FEATURE_VARIABLE_PREDIV,
41 .hw.init = CLK_HW_INIT_PARENTS("cpus",
42 cpus_r_apb2_parents,
43 &ccu_div_ops,
44 0),
45 },
46 };
47
48 static CLK_FIXED_FACTOR_HW(r_ahb_clk, "r-ahb", &cpus_clk.common.hw, 1, 1, 0);
49
50 static struct ccu_div r_apb1_clk = {
51 .div = _SUNXI_CCU_DIV(0, 2),
52
53 .common = {
54 .reg = 0x00c,
55 .hw.init = CLK_HW_INIT("r-apb1",
56 "r-ahb",
57 &ccu_div_ops,
58 0),
59 },
60 };
61
62 static struct ccu_div r_apb2_clk = {
63 .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
64
65 .mux = {
66 .shift = 24,
67 .width = 2,
68
69 .var_predivs = cpus_r_apb2_predivs,
70 .n_var_predivs = ARRAY_SIZE(cpus_r_apb2_predivs),
71 },
72
73 .common = {
74 .reg = 0x010,
75 .features = CCU_FEATURE_VARIABLE_PREDIV,
76 .hw.init = CLK_HW_INIT_PARENTS("r-apb2",
77 cpus_r_apb2_parents,
78 &ccu_div_ops,
79 0),
80 },
81 };
82
83 static SUNXI_CCU_GATE(r_apb1_timer_clk, "r-apb1-timer", "r-apb1",
84 0x11c, BIT(0), 0);
85
86 static SUNXI_CCU_GATE(r_apb1_twd_clk, "r-apb1-twd", "r-apb1",
87 0x12c, BIT(0), 0);
88
89 static const char * const r_apb1_pwm_clk_parents[] = { "dcxo24M", "osc32k",
90 "iosc" };
91 static SUNXI_CCU_MUX(r_apb1_pwm_clk, "r-apb1-pwm", r_apb1_pwm_clk_parents,
92 0x130, 24, 2, 0);
93
94 static SUNXI_CCU_GATE(r_apb1_bus_pwm_clk, "r-apb1-bus-pwm", "r-apb1",
95 0x13c, BIT(0), 0);
96
97 static SUNXI_CCU_GATE(r_apb1_ppu_clk, "r-apb1-ppu", "r-apb1",
98 0x17c, BIT(0), 0);
99
100 static SUNXI_CCU_GATE(r_apb2_uart_clk, "r-apb2-uart", "r-apb2",
101 0x18c, BIT(0), 0);
102
103 static SUNXI_CCU_GATE(r_apb2_i2c0_clk, "r-apb2-i2c0", "r-apb2",
104 0x19c, BIT(0), 0);
105
106 static SUNXI_CCU_GATE(r_apb2_i2c1_clk, "r-apb2-i2c1", "r-apb2",
107 0x19c, BIT(1), 0);
108
109 static const char * const r_apb1_ir_rx_parents[] = { "osc32k", "dcxo24M" };
110 static SUNXI_CCU_MP_WITH_MUX_GATE(r_apb1_ir_rx_clk, "r-apb1-ir-rx",
111 r_apb1_ir_rx_parents, 0x1c0,
112 0, 5, /* M */
113 8, 2, /* P */
114 24, 1, /* mux */
115 BIT(31), /* gate */
116 0);
117
118 static SUNXI_CCU_GATE(r_apb1_bus_ir_rx_clk, "r-apb1-bus-ir-rx", "r-apb1",
119 0x1cc, BIT(0), 0);
120
121 static SUNXI_CCU_GATE(r_ahb_bus_rtc_clk, "r-ahb-rtc", "r-ahb",
122 0x20c, BIT(0), 0);
123
124 static struct ccu_common *sun50iw10_r_ccu_clks[] = {
125 &cpus_clk.common,
126 &r_apb1_clk.common,
127 &r_apb2_clk.common,
128 &r_apb1_timer_clk.common,
129 &r_apb1_twd_clk.common,
130 &r_apb1_pwm_clk.common,
131 &r_apb1_bus_pwm_clk.common,
132 &r_apb1_ppu_clk.common,
133 &r_apb2_uart_clk.common,
134 &r_apb2_i2c0_clk.common,
135 &r_apb2_i2c1_clk.common,
136 &r_apb1_ir_rx_clk.common,
137 &r_apb1_bus_ir_rx_clk.common,
138 &r_ahb_bus_rtc_clk.common,
139 };
140
141 static struct clk_hw_onecell_data sun50iw10_r_hw_clks = {
142 .hws = {
143 [CLK_CPUS] = &cpus_clk.common.hw,
144 [CLK_R_AHB] = &r_ahb_clk.hw,
145 [CLK_R_APB1] = &r_apb1_clk.common.hw,
146 [CLK_R_APB2] = &r_apb2_clk.common.hw,
147 [CLK_R_APB1_TIMER] = &r_apb1_timer_clk.common.hw,
148 [CLK_R_APB1_TWD] = &r_apb1_twd_clk.common.hw,
149 [CLK_R_APB1_PWM] = &r_apb1_pwm_clk.common.hw,
150 [CLK_R_APB1_BUS_PWM] = &r_apb1_bus_pwm_clk.common.hw,
151 [CLK_R_APB1_PPU] = &r_apb1_ppu_clk.common.hw,
152 [CLK_R_APB2_UART] = &r_apb2_uart_clk.common.hw,
153 [CLK_R_APB2_I2C0] = &r_apb2_i2c0_clk.common.hw,
154 [CLK_R_APB2_I2C1] = &r_apb2_i2c1_clk.common.hw,
155 [CLK_R_APB1_IR] = &r_apb1_ir_rx_clk.common.hw,
156 [CLK_R_APB1_BUS_IR] = &r_apb1_bus_ir_rx_clk.common.hw,
157 [CLK_R_AHB_BUS_RTC] = &r_ahb_bus_rtc_clk.common.hw,
158 },
159 .num = CLK_NUMBER,
160 };
161
162 static struct ccu_reset_map sun50iw10_r_ccu_resets[] = {
163 [RST_R_APB1_TIMER] = { 0x11c, BIT(16) },
164 [RST_R_APB1_BUS_PWM] = { 0x13c, BIT(16) },
165 [RST_R_APB1_PPU] = { 0x17c, BIT(16) },
166 [RST_R_APB2_UART] = { 0x18c, BIT(16) },
167 [RST_R_APB2_I2C0] = { 0x19c, BIT(16) },
168 [RST_R_APB2_I2C1] = { 0x19c, BIT(17) },
169 [RST_R_APB1_BUS_IR] = { 0x1cc, BIT(16) },
170 [RST_R_AHB_BUS_RTC] = { 0x20c, BIT(16) },
171 };
172
173 static const struct sunxi_ccu_desc sun50iw10_r_ccu_desc = {
174 .ccu_clks = sun50iw10_r_ccu_clks,
175 .num_ccu_clks = ARRAY_SIZE(sun50iw10_r_ccu_clks),
176
177 .hw_clks = &sun50iw10_r_hw_clks,
178
179 .resets = sun50iw10_r_ccu_resets,
180 .num_resets = ARRAY_SIZE(sun50iw10_r_ccu_resets),
181 };
182
sun50iw10_r_ccu_probe(struct platform_device * pdev)183 static int sun50iw10_r_ccu_probe(struct platform_device *pdev)
184 {
185 void __iomem *reg;
186 int ret;
187
188 reg = devm_platform_ioremap_resource(pdev, 0);
189 if (IS_ERR(reg))
190 return PTR_ERR(reg);
191
192 ret = sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50iw10_r_ccu_desc);
193 if (ret)
194 return ret;
195
196 sunxi_ccu_sleep_init(reg, sun50iw10_r_ccu_clks,
197 ARRAY_SIZE(sun50iw10_r_ccu_clks),
198 NULL, 0);
199
200 printk("Sunxi ccu sun50iw10-r init OK\n");
201
202 return 0;
203 }
204
205 static const struct of_device_id sun50iw10_r_ccu_ids[] = {
206 { .compatible = "allwinner,sun50iw10-r-ccu" },
207 { }
208 };
209
210 static struct platform_driver sun50iw10_r_ccu_driver = {
211 .probe = sun50iw10_r_ccu_probe,
212 .driver = {
213 .name = "sun50iw10-r-ccu",
214 .of_match_table = sun50iw10_r_ccu_ids,
215 },
216 };
217
sunxi_ccu_sun50iw10_r_init(void)218 static int __init sunxi_ccu_sun50iw10_r_init(void)
219 {
220 int ret;
221
222 ret = platform_driver_register(&sun50iw10_r_ccu_driver);
223 if (ret)
224 pr_err("register ccu sun50iw10-r failed\n");
225
226 return ret;
227 }
228 core_initcall(sunxi_ccu_sun50iw10_r_init);
229
sunxi_ccu_sun50iw10_r_exit(void)230 static void __exit sunxi_ccu_sun50iw10_r_exit(void)
231 {
232 return platform_driver_unregister(&sun50iw10_r_ccu_driver);
233 }
234 module_exit(sunxi_ccu_sun50iw10_r_exit);
235
236 MODULE_DESCRIPTION("Allwinner sun50iw10-r clk driver");
237 MODULE_LICENSE("GPL v2");
238 MODULE_VERSION("1.0.5");
239