1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2020 frank@allwinnertech.com
4 */
5
6 #include <linux/clk-provider.h>
7 #include <linux/module.h>
8 #include <linux/of_address.h>
9 #include <linux/platform_device.h>
10
11 #include "ccu_common.h"
12 #include "ccu_reset.h"
13
14 #include "ccu_div.h"
15 #include "ccu_gate.h"
16 #include "ccu_mp.h"
17 #include "ccu_nm.h"
18
19 #include "ccu-sun50iw9-r.h"
20
21 static const char * const cpus_r_apb2_parents[] = { "dcxo24M", "osc32k",
22 "iosc", "pll-periph0" };
23 static const struct ccu_mux_var_prediv cpus_r_apb2_predivs[] = {
24 { .index = 3, .shift = 0, .width = 5 },
25 };
26
27 static struct ccu_div r_cpus_clk = {
28 .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
29
30 .mux = {
31 .shift = 24,
32 .width = 2,
33
34 .var_predivs = cpus_r_apb2_predivs,
35 .n_var_predivs = ARRAY_SIZE(cpus_r_apb2_predivs),
36 },
37
38 .common = {
39 .reg = 0x000,
40 .features = CCU_FEATURE_VARIABLE_PREDIV,
41 .hw.init = CLK_HW_INIT_PARENTS("cpus",
42 cpus_r_apb2_parents,
43 &ccu_div_ops,
44 0),
45 },
46 };
47
48 static CLK_FIXED_FACTOR_HW(r_ahb_clk, "r-ahb", &r_cpus_clk.common.hw, 1, 1, 0);
49
50 static struct ccu_div r_apb1_clk = {
51 .div = _SUNXI_CCU_DIV(0, 2),
52
53 .common = {
54 .reg = 0x00c,
55 .hw.init = CLK_HW_INIT("r-apb1",
56 "r-ahb",
57 &ccu_div_ops,
58 0),
59 },
60 };
61
62 static struct ccu_div r_apb2_clk = {
63 .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
64
65 .mux = {
66 .shift = 24,
67 .width = 2,
68
69 .var_predivs = cpus_r_apb2_predivs,
70 .n_var_predivs = ARRAY_SIZE(cpus_r_apb2_predivs),
71 },
72
73 .common = {
74 .reg = 0x010,
75 .features = CCU_FEATURE_VARIABLE_PREDIV,
76 .hw.init = CLK_HW_INIT_PARENTS("r-apb2",
77 cpus_r_apb2_parents,
78 &ccu_div_ops,
79 0),
80 },
81 };
82
83 static SUNXI_CCU_GATE(r_apb1_twd_clk, "r-apb1-twd", "r-apb1",
84 0x12c, BIT(0), 0);
85
86 static SUNXI_CCU_GATE(r_apb2_i2c_clk, "r-apb2-i2c", "r-apb2",
87 0x19c, BIT(0), 0);
88
89 /* APB2? */
90 static const char * const r_apb1_ir_rx_parents[] = { "osc32k", "dcxo24M" };
91 static SUNXI_CCU_MP_WITH_MUX_GATE(r_apb1_ir_rx_clk, "r-apb1-ir-rx",
92 r_apb1_ir_rx_parents, 0x1c0,
93 0, 5, /* M */
94 8, 2, /* P */
95 24, 1, /* mux */
96 BIT(31), /* gate */
97 0);
98
99 static SUNXI_CCU_GATE(r_apb1_bus_ir_rx_clk, "r-apb1-bus-ir-rx", "r-apb1",
100 0x1cc, BIT(0), 0);
101
102 static SUNXI_CCU_GATE(r_ahb_bus_rtc_clk, "r-ahb-rtc", "r-ahb",
103 0x20c, BIT(0), 0);
104
105 static struct ccu_common *sun50iw9_r_ccu_clks[] = {
106 &r_cpus_clk.common,
107 &r_apb1_clk.common,
108 &r_apb2_clk.common,
109 &r_apb1_twd_clk.common,
110 &r_apb2_i2c_clk.common,
111 &r_apb1_ir_rx_clk.common,
112 &r_apb1_bus_ir_rx_clk.common,
113 &r_ahb_bus_rtc_clk.common,
114 };
115
116 static struct clk_hw_onecell_data sun50iw9_r_hw_clks = {
117 .hws = {
118 [CLK_R_CPUS] = &r_cpus_clk.common.hw,
119 [CLK_R_AHB] = &r_ahb_clk.hw,
120 [CLK_R_APB1] = &r_apb1_clk.common.hw,
121 [CLK_R_APB2] = &r_apb2_clk.common.hw,
122 [CLK_R_APB1_TWD] = &r_apb1_twd_clk.common.hw,
123 [CLK_R_APB2_I2C] = &r_apb2_i2c_clk.common.hw,
124 [CLK_R_APB1_IR] = &r_apb1_ir_rx_clk.common.hw,
125 [CLK_R_APB1_BUS_IR] = &r_apb1_bus_ir_rx_clk.common.hw,
126 [CLK_R_AHB_BUS_RTC] = &r_ahb_bus_rtc_clk.common.hw,
127 },
128 .num = CLK_NUMBER,
129 };
130
131 static struct ccu_reset_map sun50iw9_r_ccu_resets[] = {
132 [RST_R_APB1_TWD] = { 0x12c, BIT(16) },
133 [RST_R_APB2_I2C] = { 0x19c, BIT(16) },
134 [RST_R_APB1_BUS_IR] = { 0x1cc, BIT(16) },
135 };
136
137 static const struct sunxi_ccu_desc sun50iw9_r_ccu_desc = {
138 .ccu_clks = sun50iw9_r_ccu_clks,
139 .num_ccu_clks = ARRAY_SIZE(sun50iw9_r_ccu_clks),
140
141 .hw_clks = &sun50iw9_r_hw_clks,
142
143 .resets = sun50iw9_r_ccu_resets,
144 .num_resets = ARRAY_SIZE(sun50iw9_r_ccu_resets),
145 };
146
sun50iw9_r_ccu_probe(struct platform_device * pdev)147 static int sun50iw9_r_ccu_probe(struct platform_device *pdev)
148 {
149 void __iomem *reg;
150 int ret;
151
152 reg = devm_platform_ioremap_resource(pdev, 0);
153 if (IS_ERR(reg))
154 return PTR_ERR(reg);
155
156 ret = sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50iw9_r_ccu_desc);
157 if (ret)
158 return ret;
159
160 sunxi_ccu_sleep_init(reg, sun50iw9_r_ccu_clks,
161 ARRAY_SIZE(sun50iw9_r_ccu_clks),
162 NULL, 0);
163
164 printk("Sunxi ccu sun50iw9-r init OK\n");
165
166 return 0;
167 }
168
169 static const struct of_device_id sun50iw9_r_ccu_ids[] = {
170 { .compatible = "allwinner,sun50iw9-r-ccu" },
171 { }
172 };
173
174 static struct platform_driver sun50iw9_r_ccu_driver = {
175 .probe = sun50iw9_r_ccu_probe,
176 .driver = {
177 .name = "sun50iw9-r-ccu",
178 .of_match_table = sun50iw9_r_ccu_ids,
179 },
180 };
181
sunxi_ccu_sun50iw9_r_init(void)182 static int __init sunxi_ccu_sun50iw9_r_init(void)
183 {
184 return platform_driver_register(&sun50iw9_r_ccu_driver);
185 }
186 core_initcall(sunxi_ccu_sun50iw9_r_init);
187
188 MODULE_DESCRIPTION("Allwinner sun50iw9-r clk driver");
189 MODULE_LICENSE("GPL v2");
190 MODULE_VERSION("1.0.5");
191