1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2016 Linaro.
4 * Viresh Kumar <viresh.kumar@linaro.org>
5 */
6
7 #include <linux/err.h>
8 #include <linux/of.h>
9 #include <linux/of_device.h>
10 #include <linux/platform_device.h>
11 #include <linux/module.h>
12
13 #include "cpufreq-dt.h"
14
15 /*
16 * Machines for which the cpufreq device is *always* created, mostly used for
17 * platforms using "operating-points" (V1) property.
18 */
19 static const struct of_device_id whitelist[] __initconst = {
20 { .compatible = "allwinner,sun4i-a10", },
21 { .compatible = "allwinner,sun5i-a10s", },
22 { .compatible = "allwinner,sun5i-a13", },
23 { .compatible = "allwinner,sun5i-r8", },
24 { .compatible = "allwinner,sun6i-a31", },
25 { .compatible = "allwinner,sun6i-a31s", },
26 { .compatible = "allwinner,sun7i-a20", },
27 { .compatible = "allwinner,sun8i-a23", },
28 { .compatible = "allwinner,sun8i-a83t", },
29 { .compatible = "allwinner,sun8i-h3", },
30
31 { .compatible = "apm,xgene-shadowcat", },
32
33 { .compatible = "arm,integrator-ap", },
34 { .compatible = "arm,integrator-cp", },
35
36 { .compatible = "hisilicon,hi3660", },
37
38 { .compatible = "fsl,imx27", },
39 { .compatible = "fsl,imx51", },
40 { .compatible = "fsl,imx53", },
41
42 { .compatible = "marvell,berlin", },
43 { .compatible = "marvell,pxa250", },
44 { .compatible = "marvell,pxa270", },
45
46 { .compatible = "samsung,exynos3250", },
47 { .compatible = "samsung,exynos4210", },
48 { .compatible = "samsung,exynos5250", },
49 #ifndef CONFIG_BL_SWITCHER
50 { .compatible = "samsung,exynos5800", },
51 #endif
52
53 { .compatible = "renesas,emev2", },
54 { .compatible = "renesas,r7s72100", },
55 { .compatible = "renesas,r8a73a4", },
56 { .compatible = "renesas,r8a7740", },
57 { .compatible = "renesas,r8a7742", },
58 { .compatible = "renesas,r8a7743", },
59 { .compatible = "renesas,r8a7744", },
60 { .compatible = "renesas,r8a7745", },
61 { .compatible = "renesas,r8a7778", },
62 { .compatible = "renesas,r8a7779", },
63 { .compatible = "renesas,r8a7790", },
64 { .compatible = "renesas,r8a7791", },
65 { .compatible = "renesas,r8a7792", },
66 { .compatible = "renesas,r8a7793", },
67 { .compatible = "renesas,r8a7794", },
68 { .compatible = "renesas,sh73a0", },
69
70 { .compatible = "rockchip,rk2928", },
71 { .compatible = "rockchip,rk3036", },
72 { .compatible = "rockchip,rk3066a", },
73 { .compatible = "rockchip,rk3066b", },
74 { .compatible = "rockchip,rk3188", },
75 { .compatible = "rockchip,rk3228", },
76 { .compatible = "rockchip,rk3288", },
77 { .compatible = "rockchip,rk3328", },
78 { .compatible = "rockchip,rk3366", },
79 { .compatible = "rockchip,rk3368", },
80 { .compatible = "rockchip,rk3399",
81 .data = &(struct cpufreq_dt_platform_data)
82 { .have_governor_per_policy = true, },
83 },
84
85 { .compatible = "st-ericsson,u8500", },
86 { .compatible = "st-ericsson,u8540", },
87 { .compatible = "st-ericsson,u9500", },
88 { .compatible = "st-ericsson,u9540", },
89
90 { .compatible = "ti,omap2", },
91 { .compatible = "ti,omap4", },
92 { .compatible = "ti,omap5", },
93
94 { .compatible = "xlnx,zynq-7000", },
95 { .compatible = "xlnx,zynqmp", },
96
97 { }
98 };
99
100 /*
101 * Machines for which the cpufreq device is *not* created, mostly used for
102 * platforms using "operating-points-v2" property.
103 */
104 static const struct of_device_id blacklist[] __initconst = {
105 { .compatible = "allwinner,sun50i-h6", },
106
107 { .compatible = "arm,sun50iw9p1", },
108 { .compatible = "arm,sun50iw10p1", },
109 { .compatible = "arm,sun8iw20p1", },
110 { .compatible = "arm,sun20iw1p1", },
111
112 { .compatible = "arm,vexpress", },
113
114 { .compatible = "calxeda,highbank", },
115 { .compatible = "calxeda,ecx-2000", },
116
117 { .compatible = "fsl,imx7ulp", },
118 { .compatible = "fsl,imx7d", },
119 { .compatible = "fsl,imx8mq", },
120 { .compatible = "fsl,imx8mm", },
121 { .compatible = "fsl,imx8mn", },
122 { .compatible = "fsl,imx8mp", },
123
124 { .compatible = "marvell,armadaxp", },
125
126 { .compatible = "mediatek,mt2701", },
127 { .compatible = "mediatek,mt2712", },
128 { .compatible = "mediatek,mt7622", },
129 { .compatible = "mediatek,mt7623", },
130 { .compatible = "mediatek,mt817x", },
131 { .compatible = "mediatek,mt8173", },
132 { .compatible = "mediatek,mt8176", },
133 { .compatible = "mediatek,mt8183", },
134
135 { .compatible = "nvidia,tegra20", },
136 { .compatible = "nvidia,tegra30", },
137 { .compatible = "nvidia,tegra124", },
138 { .compatible = "nvidia,tegra210", },
139
140 { .compatible = "qcom,apq8096", },
141 { .compatible = "qcom,msm8996", },
142 { .compatible = "qcom,qcs404", },
143 { .compatible = "qcom,sc7180", },
144 { .compatible = "qcom,sdm845", },
145
146 { .compatible = "st,stih407", },
147 { .compatible = "st,stih410", },
148 { .compatible = "st,stih418", },
149
150 { .compatible = "sigma,tango4", },
151
152 { .compatible = "ti,am33xx", },
153 { .compatible = "ti,am43", },
154 { .compatible = "ti,dra7", },
155 { .compatible = "ti,omap3", },
156
157 { .compatible = "qcom,ipq8064", },
158 { .compatible = "qcom,apq8064", },
159 { .compatible = "qcom,msm8974", },
160 { .compatible = "qcom,msm8960", },
161
162 { }
163 };
164
cpu0_node_has_opp_v2_prop(void)165 static bool __init cpu0_node_has_opp_v2_prop(void)
166 {
167 struct device_node *np = of_cpu_device_node_get(0);
168 bool ret = false;
169
170 if (of_get_property(np, "operating-points-v2", NULL))
171 ret = true;
172
173 of_node_put(np);
174 return ret;
175 }
176
cpufreq_dt_platdev_init(void)177 static int __init cpufreq_dt_platdev_init(void)
178 {
179 struct device_node *np = of_find_node_by_path("/");
180 const struct of_device_id *match;
181 const void *data = NULL;
182
183 if (!np)
184 return -ENODEV;
185
186 match = of_match_node(whitelist, np);
187 if (match) {
188 data = match->data;
189 goto create_pdev;
190 }
191
192 if (cpu0_node_has_opp_v2_prop() && !of_match_node(blacklist, np))
193 goto create_pdev;
194
195 of_node_put(np);
196 return -ENODEV;
197
198 create_pdev:
199 of_node_put(np);
200 return PTR_ERR_OR_ZERO(platform_device_register_data(NULL, "cpufreq-dt",
201 -1, data,
202 sizeof(struct cpufreq_dt_platform_data)));
203 }
204 core_initcall(cpufreq_dt_platdev_init);
205 MODULE_LICENSE("GPL");
206
207