1 /* g2d_regs.h 2 * 3 * Copyright (c) 2011 Allwinnertech Co., Ltd. 4 * 2011 Yupu Tang 5 * 6 * G2D driver 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the 16 * GNU General Public License for more details. 17 */ 18 19 #ifndef __G2D_MIXER_REGS_H 20 #define __G2D_MIXER_REGS_H 21 22 /* 23 *Graphics 2D General Registers 24 */ 25 #define G2D_BASE_ADDR (0x01e80000)/* Base Address */ 26 #define G2D_CONTROL_REG (0x00) /* Control register */ 27 #define G2D_STATUS_REG (0x04) /* Status register */ 28 /* DMA scan order control register */ 29 #define G2D_SCAN_ORDER_REG (0x08) 30 31 /* 32 * Graphics 2D Input Address Parameter Setting Registers 33 */ 34 /* Input DMA high 4 bits start addr register */ 35 #define G2D_DMA_HADDR_REG (0x0c) 36 /* Input DMA0 low 32 bits start addr register */ 37 #define G2D_DMA0_LADDR_REG (0x10) 38 /* Input DMA1 low 32 bits start addr register */ 39 #define G2D_DMA1_LADDR_REG (0x14) 40 /* Input DMA2 low 32 bits start addr register */ 41 #define G2D_DMA2_LADDR_REG (0x18) 42 /* Input DMA3 low 32 bits start addr register */ 43 #define G2D_DMA3_LADDR_REG (0x1c) 44 45 /* 46 * Graphics 2D Input Linewidth Buffer Parameter Setting Registers 47 */ 48 /* Input DMA0 line stride register */ 49 #define G2D_DMA0_STRIDE_REG (0x20) 50 /* Input DMA1 line stride register */ 51 52 #define G2D_DMA1_STRIDE_REG (0x24) 53 /* Input DMA2 line stride register */ 54 55 #define G2D_DMA2_STRIDE_REG (0x28) 56 /* Input DMA3 line stride register */ 57 58 #define G2D_DMA3_STRIDE_REG (0x2c) 59 60 /* Input DMA0 memory block size register */ 61 #define G2D_DMA0_SIZE_REG (0x30) 62 /* Input DMA1 memory block size register */ 63 #define G2D_DMA1_SIZE_REG (0x34) 64 /* Input DMA2 memory block size register */ 65 #define G2D_DMA2_SIZE_REG (0x38) 66 /* Input DMA3 memory block size register */ 67 #define G2D_DMA3_SIZE_REG (0x3c) 68 69 /* Input DMA0 memory block coordinate register */ 70 #define G2D_DMA0_COOR_REG (0x40) 71 /* Input DMA1 memory block coordinate register */ 72 #define G2D_DMA1_COOR_REG (0x44) 73 /* Input DMA2 memory block coordinate register */ 74 #define G2D_DMA2_COOR_REG (0x48) 75 /* Input DMA3 memory block coordinate register */ 76 #define G2D_DMA3_COOR_REG (0x4c) 77 78 /* Input DMA0 control register */ 79 #define G2D_DMA0_CONTROL_REG (0x50) 80 /* Input DMA1 control register */ 81 #define G2D_DMA1_CONTROL_REG (0x54) 82 /* Input DMA2 control register */ 83 #define G2D_DMA2_CONTROL_REG (0x58) 84 /* Input DMA3 control register */ 85 #define G2D_DMA3_CONTROL_REG (0x5c) 86 /* Input DMA0 fillcolor register */ 87 88 #define G2D_DMA0_FILLCOLOR_REG (0x60) 89 /* Input DMA1 fillcolor register */ 90 #define G2D_DMA1_FILLCOLOR_REG (0x64) 91 /* Input DMA2 fillcolor register */ 92 #define G2D_DMA2_FILLCOLOR_REG (0x68) 93 /* Input DMA3 fillcolor register */ 94 #define G2D_DMA3_FILLCOLOR_REG (0x6c) 95 96 /* Color space converter0 control register */ 97 #define G2D_CSC0_CONTROL_REG (0x74) 98 /* Color space converter1 control register */ 99 #define G2D_CSC1_CONTROL_REG (0x78) 100 101 /* Scaler control register */ 102 #define G2D_SCALER_CONTROL_REG (0x80) 103 /* Scaler output size control register */ 104 #define G2D_SCALER_SIZE_REG (0x84) 105 /* Scaler horizontal scaling factor register */ 106 #define G2D_SCALER_HFACTOR_REG (0x88) 107 /* Scaler vertical scaling factor register */ 108 #define G2D_SCALER_VFACTOR_REG (0x8c) 109 /* Scaler horizontal start phase register */ 110 #define G2D_SCALER_HPHASE_REG (0x90) 111 /* Scaler vertical start phase register */ 112 #define G2D_SCALER_VPHASE_REG (0x94) 113 114 /* Rop control register */ 115 #define G2D_ROP_CONTROL_REG (0xb0) 116 /* Rop index0 control table setting register */ 117 #define G2D_ROP_INDEX0_REG (0xb8) 118 /* Rop index1 control table setting register */ 119 #define G2D_ROP_INDEX1_REG (0xbc) 120 121 /* Colorkey/alpha control register */ 122 #define G2D_CK_CONTROL_REG (0xc0) 123 /* Colorkey min color control register */ 124 #define G2D_CK_MINCOLOR_REG (0xc4) 125 /* Colorkey max color control register */ 126 #define G2D_CK_MAXCOLOR_REG (0xc8) 127 /* Rop output fillcolor setting register */ 128 #define G2D_ROP_FILLCOLOR_REG (0xcc) 129 /* Color space converter2 control register */ 130 #define G2D_CSC2_CONTROL_REG (0xd0) 131 132 /* Output control register */ 133 #define G2D_OUTPUT_CONTROL_REG (0xe0) 134 /* Output size register */ 135 #define G2D_OUTPUT_SIZE_REG (0xe8) 136 /* Output high 4 bits address control register */ 137 #define G2D_OUTPUT_HADDR_REG (0xec) 138 /* Output low 32 bits address control register */ 139 #define G2D_OUTPUT0_LADDR_REG (0xf0) 140 /* Output low 32 bits address control register */ 141 #define G2D_OUTPUT1_LADDR_REG (0xf4) 142 /* Output low 32 bits address control register */ 143 #define G2D_OUTPUT2_LADDR_REG (0xf8) 144 145 /* Output channel0 line stride control register */ 146 #define G2D_OUTPUT0_STRIDE_REG (0x100) 147 /* Output channel1 line stride control register */ 148 #define G2D_OUTPUT1_STRIDE_REG (0x104) 149 /* Output channel2 line stride control register */ 150 #define G2D_OUTPUT2_STRIDE_REG (0x108) 151 /* Output alpha control register */ 152 #define G2D_OALPHA_CONTROL_REG (0x120) 153 154 /* Input DMA0 micro block control register */ 155 #define G2D_DMA0_MBCTL_REG (0x130) 156 /* Input DMA1 micro block control register */ 157 #define G2D_DMA1_MBCTL_REG (0x134) 158 /* Input DMA2 micro block control register */ 159 #define G2D_DMA2_MBCTL_REG (0x138) 160 /* Input DMA3 micro block control register */ 161 #define G2D_DMA3_MBCTL_REG (0x13c) 162 163 /* command queue control register */ 164 #define G2D_CMDQ_CTL_REG (0x140) 165 /* command queue status register */ 166 #define G2D_CMDQ_STS_REG (0x144) 167 /* command queue storage start address register */ 168 #define G2D_CMDQ_ADDR_REG (0x148) 169 170 /* CSC0/1 coefficient/constant start addr register(0x180-0x1ac) */ 171 #define G2D_CSC01_ADDR_REG (0x180) 172 /* CSC2 coefficient/constant start addr register(0x1c0-0x1ec) */ 173 #define G2D_CSC2_ADDR_REG (0x1c0) 174 /* Scaling horizontal filtering coefficient ram block register(0x200-0x27c) */ 175 #define G2D_SCALER_HFILTER_REG (0x200) 176 /* Scaling vertical filtering coefficient ram block register(0x280-0x2fc) */ 177 #define G2D_SCALER_VFILTER_REG (0x280) 178 /* Scaling horizontal filtering coefficient ram block register(0x400-0x7fc) */ 179 #define G2D_PALETTE_TAB_REG (0x400) 180 181 /* Input DMA setting */ 182 #define G2D_FILL_ENABLE (1<<16) 183 #define G2D_FILL_DISABLE (0<<16) 184 185 /* Work Mode Select */ 186 #define G2D_IDMA_ENABLE (1<<0) 187 #define G2D_IDMA_DISABLE (0<<0) 188 189 /* Scaler Control Select */ 190 #define G2D_SCALER_DISABLE (0<<0) 191 #define G2D_SCALER_ENABLE (1<<0) 192 #define G2D_SCALER_4TAP4 (0<<4) 193 194 /* byte input */ 195 #define get_bvalue(n) (*((volatile __u8 *)(n))) 196 /* byte output */ 197 #define put_bvalue(n, c) (*((volatile __u8 *)(n)) = (c)) 198 /* half word input */ 199 #define get_hvalue(n) (*((volatile __u16 *)(n))) 200 /* half word output */ 201 #define put_hvalue(n, c) (*((volatile __u16 *)(n)) = (c)) 202 /* word input */ 203 #define get_wvalue(n) (*((volatile __u32 *)(n))) 204 /* word output */ 205 #define put_wvalue(n, c) (*((volatile __u32 *)(n)) = (c)) 206 207 #endif /* __G2D_MIXER_REGS_H */ 208 209