1 /* SPDX-License-Identifier: GPL-2.0-only 2 * drivers/input/sensor/sunxi_gpadc.h 3 * 4 * Copyright (C) 2016 Allwinner. 5 * fuzhaoke <fuzhaoke@allwinnertech.com> 6 * 7 * SUNXI GPADC Controller Driver Header 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 */ 14 15 #ifndef SUNXI_GPADC_H 16 #define SUNXI_GPADC_H 17 18 #define GPADC_DEV_NAME ("sunxi-gpadc") 19 20 #define OSC_24MHZ (24000000UL) 21 #define MAX_SR (100000UL) 22 #define MIN_SR (400UL) 23 #define DEFAULT_SR (1000UL) 24 /* voltage range 0~2.3v, unit is uv */ 25 #define VOL_RANGE (1800000UL) 26 #define VOL_VALUE_MASK (0Xfff) 27 28 29 /* GPADC register offset */ 30 #define GP_SR_REG (0x00) /* Sample Rate config register */ 31 #define GP_CTRL_REG (0x04) /* control register */ 32 #define GP_CS_EN_REG (0x08) /* compare and select enable register */ 33 #define GP_FIFO_INTC_REG (0x0c) /* FIFO interrupt config register */ 34 #define GP_FIFO_INTS_REG (0x10) /* FIFO interrupt status register */ 35 #define GP_FIFO_DATA_REG (0X14) /* FIFO data register */ 36 #define GP_CB_DATA_REG (0X18) /* calibration data register */ 37 #define GP_DATAL_INTC_REG (0x20) 38 #define GP_DATAH_INTC_REG (0x24) 39 #define GP_DATA_INTC_REG (0x28) 40 #define GP_DATAL_INTS_REG (0x30) 41 #define GP_DATAH_INTS_REG (0x34) 42 #define GP_DATA_INTS_REG (0x38) 43 #define GP_CH0_CMP_DATA_REG (0x40) /* channal 0 compare data register */ 44 #define GP_CH1_CMP_DATA_REG (0x44) /* channal 1 compare data register */ 45 #define GP_CH2_CMP_DATA_REG (0x48) /* channal 2 compare data register */ 46 #define GP_CH3_CMP_DATA_REG (0x4c) /* channal 3 compare data register */ 47 #define GP_CH4_CMP_DATA_REG (0x50) /* channal 4 compare data register */ 48 #define GP_CH5_CMP_DATA_REG (0x54) /* channal 5 compare data register */ 49 #define GP_CH6_CMP_DATA_REG (0x58) /* channal 6 compare data register */ 50 #define GP_CH7_CMP_DATA_REG (0x5c) /* channal 7 compare data register */ 51 #define GP_CH0_DATA_REG (0x80) /* channal 0 data register */ 52 #define GP_CH1_DATA_REG (0x84) /* channal 1 data register */ 53 #define GP_CH2_DATA_REG (0x88) /* channal 2 data register */ 54 #define GP_CH3_DATA_REG (0x8c) /* channal 3 data register */ 55 #define GP_CH4_DATA_REG (0x90) /* channal 4 data register */ 56 #define GP_CH5_DATA_REG (0x94) /* channal 5 data register */ 57 #define GP_CH6_DATA_REG (0x98) /* channal 6 data register */ 58 #define GP_CH7_DATA_REG (0x9c) /* channal 7 data register */ 59 60 #define LDOA_EFUSE_REG 0x03006224 61 62 /* 63 * GP_SR_REG default value: 0x01df_002f 50KHZ 64 * sample_rate = clk_in/(n+1) = 24MHZ/(0x1df + 1) = 50KHZ 65 */ 66 #define GP_SR_CON (0xffff << 16) 67 68 /* GP_CTRL_REG default value:0x0000_0000 */ 69 #define GP_FIRST_CONCERT_DLY (0xff<<24) /* delay time of the first time */ 70 #define GP_CALI_EN (1 << 17) /* enable calibration */ 71 #define GP_ADC_EN (1 << 16) /* GPADC function enable */ 72 73 /* 74 * 00:single conversion mode 75 * 01:single-cycle conversion mode 76 * 10:continuous mode, 11:burst mode 77 */ 78 #define GP_MODE_SELECT (3 << 18) 79 80 /* 0:disable, 1:enable */ 81 #define GP_CH7_CMP_EN (1 << 23) 82 #define GP_CH6_CMP_EN (1 << 22) 83 #define GP_CH5_CMP_EN (1 << 21) 84 #define GP_CH4_CMP_EN (1 << 20) 85 #define GP_CH3_CMP_EN (1 << 19) 86 #define GP_CH2_CMP_EN (1 << 18) 87 #define GP_CH1_CMP_EN (1 << 17) 88 #define GP_CH0_CMP_EN (1 << 16) 89 #define GP_CH7_SELECT (1 << 7) 90 #define GP_CH6_SELECT (1 << 6) 91 #define GP_CH5_SELECT (1 << 5) 92 #define GP_CH4_SELECT (1 << 4) 93 #define GP_CH3_SELECT (1 << 3) 94 #define GP_CH2_SELECT (1 << 2) 95 #define GP_CH1_SELECT (1 << 1) 96 #define GP_CH0_SELECT (1 << 0) 97 98 /* 99 * GP_FIFO_INTC_REG default value: 0x0000_0f00 100 * 0:disable, 1:enable 101 */ 102 #define FIFO_OVER_IRQ_EN (1 << 17) /* fifo over run irq enable */ 103 #define FIFO_DATA_IRQ_EN (1 << 16) /* fifo data irq enable */ 104 105 /* write 1 to flush TX FIFO, self clear to 0 */ 106 #define FIFO_FLUSH (1 << 4) 107 108 /* 109 * GP_FIFO_INTS_REG default value: 0x0000_0000 110 * 0:no pending irq, 1: over pending, need write 1 to clear flag 111 */ 112 #define FIFO_OVER_PEND (1 << 17) /* fifo over pending flag */ 113 #define FIFO_DATA_PEND (1 << 16) /* fifo data pending flag */ 114 #define FIFO_CNT (0x3f << 8) /* the data count in fifo */ 115 116 /* GP_FIFO_DATA_REG default value: 0x0000_0000 */ 117 #define GP_FIFO_DATA (0xfff << 0) /* GPADC data in fifo */ 118 119 /* GP_CB_DATA_REG default value: 0x0000_0000 */ 120 #define GP_CB_DATA (0xfff << 0) /* GPADC calibration data */ 121 122 /* GP_INTC_REG default value: 0x0000_0000 */ 123 #define GP_CH7_LOW_IRQ_EN (1 << 7) /* 0:disable, 1:enable */ 124 #define GP_CH6_LOW_IRQ_EN (1 << 6) 125 #define GP_CH5_LOW_IRQ_EN (1 << 5) 126 #define GP_CH4_LOW_IRQ_EN (1 << 4) 127 #define GP_CH3_LOW_IRQ_EN (1 << 3) 128 #define GP_CH2_LOW_IRQ_EN (1 << 2) 129 #define GP_CH1_LOW_IRQ_EN (1 << 1) 130 #define GP_CH0_LOW_IRQ_EN (1 << 0) 131 #define GP_CH7_HIG_IRQ_EN (1 << 7) 132 #define GP_CH6_HIG_IRQ_EN (1 << 6) 133 #define GP_CH5_HIG_IRQ_EN (1 << 5) 134 #define GP_CH4_HIG_IRQ_EN (1 << 4) 135 #define GP_CH3_HIG_IRQ_EN (1 << 3) 136 #define GP_CH2_HIG_IRQ_EN (1 << 2) 137 #define GP_CH1_HIG_IRQ_EN (1 << 1) 138 #define GP_CH0_HIG_IRQ_EN (1 << 0) 139 #define GP_CH7_DATA_IRQ_EN (1 << 7) 140 #define GP_CH6_DATA_IRQ_EN (1 << 6) 141 #define GP_CH5_DATA_IRQ_EN (1 << 5) 142 #define GP_CH4_DATA_IRQ_EN (1 << 4) 143 #define GP_CH3_DATA_IRQ_EN (1 << 3) 144 #define GP_CH2_DATA_IRQ_EN (1 << 2) 145 #define GP_CH1_DATA_IRQ_EN (1 << 1) 146 #define GP_CH0_DATA_IRQ_EN (1 << 0) 147 148 /* GP_INTS_REG default value: 0x0000_0000 */ 149 #define GP_CH7_LOW (1 << 7) /* 0:no pending, 1:pending */ 150 #define GP_CH6_LOW (1 << 6) 151 #define GP_CH5_LOW (1 << 5) 152 #define GP_CH4_LOW (1 << 4) 153 #define GP_CH3_LOW (1 << 3) 154 #define GP_CH2_LOW (1 << 2) 155 #define GP_CH1_LOW (1 << 1) 156 #define GP_CH0_LOW (1 << 0) 157 #define GP_CH7_HIG (1 << 7) 158 #define GP_CH6_HIG (1 << 6) 159 #define GP_CH5_HIG (1 << 5) 160 #define GP_CH4_HIG (1 << 4) 161 #define GP_CH3_HIG (1 << 3) 162 #define GP_CH2_HIG (1 << 2) 163 #define GP_CH1_HIG (1 << 1) 164 #define GP_CH0_HIG (1 << 0) 165 #define GP_CH7_DATA (1 << 7) 166 #define GP_CH6_DATA (1 << 6) 167 #define GP_CH5_DATA (1 << 5) 168 #define GP_CH4_DATA (1 << 4) 169 #define GP_CH3_DATA (1 << 3) 170 #define GP_CH2_DATA (1 << 2) 171 #define GP_CH1_DATA (1 << 1) 172 #define GP_CH0_DATA (1 << 0) 173 174 /* GP_CH0_CMP_DATA_REG default value 0x0bff_0400 */ 175 #define GP_CH0_CMP_HIG_DATA (0xfff << 16) 176 #define GP_CH0_CMP_LOW_DATA (0xfff << 0) 177 /* GP_CH1_CMP_DATA_REG default value 0x0bff_0400 */ 178 #define GP_CH1_CMP_HIG_DATA (0xfff << 16) 179 #define GP_CH1_CMP_LOW_DATA (0xfff << 0) 180 /* GP_CH2_CMP_DATA_REG default value 0x0bff_0400 */ 181 #define GP_CH2_CMP_HIG_DATA (0xfff << 16) 182 #define GP_CH2_CMP_LOW_DATA (0xfff << 0) 183 /* GP_CH3_CMP_DATA_REG default value 0x0bff_0400 */ 184 #define GP_CH3_CMP_HIG_DATA (0xfff << 16) 185 #define GP_CH3_CMP_LOW_DATA (0xfff << 0) 186 /* GP_CH4_CMP_DATA_REG default value 0x0bff_0400 */ 187 #define GP_CH4_CMP_HIG_DATA (0xfff << 16) 188 #define GP_CH4_CMP_LOW_DATA (0xfff << 0) 189 /* GP_CH5_CMP_DATA_REG default value 0x0bff_0400 */ 190 #define GP_CH5_CMP_HIG_DATA (0xfff << 16) 191 #define GP_CH5_CMP_LOW_DATA (0xfff << 0) 192 /* GP_CH6_CMP_DATA_REG default value 0x0bff_0400 */ 193 #define GP_CH6_CMP_HIG_DATA (0xfff << 16) 194 #define GP_CH6_CMP_LOW_DATA (0xfff << 0) 195 /* GP_CH7_CMP_DATA_REG default value 0x0bff_0400 */ 196 #define GP_CH7_CMP_HIG_DATA (0xfff << 16) 197 #define GP_CH7_CMP_LOW_DATA (0xfff << 0) 198 199 /* GP_CH0_DATA_REG default value:0x0000_0000 */ 200 #define GP_CH0_DATA_MASK (0xfff << 0) /* channel 0 data mask */ 201 /* GP_CH1_DATA_REG default value:0x0000_0000 */ 202 #define GP_CH1_DATA_MASK (0xfff << 0) /* channel 1 data mask */ 203 /* GP_CH2_DATA_REG default value:0x0000_0000 */ 204 #define GP_CH2_DATA_MASK (0xfff << 0) /* channel 2 data mask */ 205 /* GP_CH3_DATA_REG default value:0x0000_0000 */ 206 #define GP_CH3_DATA_MASK (0xfff << 0) /* channel 3 data mask */ 207 /* GP_CH4_DATA_REG default value:0x0000_0000 */ 208 #define GP_CH4_DATA_MASK (0xfff << 0) /* channel 4 data mask */ 209 /* GP_CH5_DATA_REG default value:0x0000_0000 */ 210 #define GP_CH5_DATA_MASK (0xfff << 0) /* channel 5 data mask */ 211 /* GP_CH6_DATA_REG default value:0x0000_0000 */ 212 #define GP_CH6_DATA_MASK (0xfff << 0) /* channel 6 data mask */ 213 /* GP_CH7_DATA_REG default value:0x0000_0000 */ 214 #define GP_CH7_DATA_MASK (0xfff << 0) /* channel 7 data mask */ 215 #define GP_CALIBRATION_ENABLE (0x1 << 17) 216 #define CHANNEL_0_SELECT 0x01 217 #define CHANNEL_1_SELECT 0x02 218 #define CHANNEL_2_SELECT 0x04 219 #define CHANNEL_3_SELECT 0x08 220 #define CHANNEL_4_SELECT 0x10 221 #define CHANNEL_5_SELECT 0x20 222 #define CHANNEL_6_SELECT 0x40 223 #define CHANNEL_7_SELECT 0x80 224 225 #define CHANNEL_MAX_NUM 8 226 #define KEY_MAX_CNT (13) 227 #define VOL_NUM KEY_MAX_CNT 228 #define MAXIMUM_INPUT_VOLTAGE 1800 229 #define DEVIATION 100 230 #define SUNXIKEY_DOWN (MAXIMUM_INPUT_VOLTAGE-DEVIATION) 231 #define SUNXIKEY_UP SUNXIKEY_DOWN 232 #define MAXIMUM_SCALE 128 233 #define SCALE_UNIT (MAXIMUM_INPUT_VOLTAGE/MAXIMUM_SCALE) 234 #define SAMPLING_FREQUENCY 10 235 236 #ifdef CONFIG_ARCH_SUN8IW19 237 #define USE_DATA_SCAN 238 #endif 239 240 enum { 241 DEBUG_INFO = 1U << 0, 242 DEBUG_RUN = 1U << 1, 243 }; 244 245 enum gp_select_mode { 246 GP_SINGLE_MODE = 0, 247 GP_SINGLE_CYCLE_MODE, 248 GP_CONTINUOUS_MODE, 249 GP_BURST_MODE, 250 }; 251 252 enum gp_channel_id { 253 GP_CH_0 = 0, 254 GP_CH_1, 255 GP_CH_2, 256 GP_CH_3, 257 GP_CH_4, 258 GP_CH_5, 259 GP_CH_6, 260 GP_CH_7, 261 }; 262 263 struct sunxi_config { 264 u32 channel_select; 265 u32 channel_data_select; 266 u32 channel_compare_select; 267 u32 channel_cld_select; 268 u32 channel_chd_select; 269 u32 channel_compare_lowdata[CHANNEL_MAX_NUM]; 270 u32 channel_compare_higdata[CHANNEL_MAX_NUM]; 271 u32 channel_scan_data; 272 }; 273 274 /* Registers which needs to be saved and restored before and after sleeping */ 275 static u32 sunxi_gpadc_regs_offset[] = { 276 GP_SR_REG, 277 GP_CS_EN_REG, 278 GP_DATAL_INTC_REG, 279 GP_DATAH_INTC_REG, 280 GP_CH0_CMP_DATA_REG, 281 GP_CH1_CMP_DATA_REG, 282 GP_CH2_CMP_DATA_REG, 283 GP_CH3_CMP_DATA_REG, 284 GP_CH4_CMP_DATA_REG, 285 GP_CH5_CMP_DATA_REG, 286 GP_CH6_CMP_DATA_REG, 287 GP_CH7_CMP_DATA_REG, 288 GP_CTRL_REG, 289 GP_FIFO_INTC_REG, 290 }; 291 292 struct sunxi_gpadc { 293 struct platform_device *pdev; 294 struct input_dev *input_gpadc[CHANNEL_MAX_NUM]; 295 struct sunxi_config gpadc_config; 296 struct clk *mclk; 297 struct clk *pclk; 298 void __iomem *reg_base; 299 int irq_num; 300 u32 wakeup_en; 301 u32 channel_num; 302 u32 scankeycodes[KEY_MAX_CNT]; 303 u32 gpadc_sample_rate; 304 char key_name[16]; 305 u32 key_num; 306 u8 key_cnt; 307 u8 compare_before; 308 u8 compare_later; 309 u8 key_code; 310 u32 key_val; 311 struct delayed_work gpadc_work; 312 unsigned int interval; 313 int bus_num; 314 struct device *dev; 315 struct clk *bus_clk; 316 struct reset_control *reset; 317 u32 regs_backup[ARRAY_SIZE(sunxi_gpadc_regs_offset)]; 318 }; 319 320 struct status_reg { 321 char *pst; 322 char *ped; 323 unsigned char channel; 324 unsigned char val; 325 }; 326 327 struct vol_reg { 328 char *pst; 329 char *ped; 330 unsigned char index; 331 unsigned long vol; 332 }; 333 334 struct sr_reg { 335 char *pst; 336 unsigned long val; 337 }; 338 339 struct filter_reg { 340 char *pst; 341 unsigned long val; 342 }; 343 344 struct channel_reg { 345 char *pst; 346 unsigned long val; 347 }; 348 349 #if defined(CONFIG_SUNXI_IR_CUT) 350 extern int ir_cut_condition, ir_cut_data, ir_cut_volt_data; 351 extern wait_queue_head_t ir_cut_queue; 352 #endif 353 354 #endif 355