1 /*
2 * Allwinner A20/A31 SoCs NMI IRQ chip driver.
3 *
4 * Carlo Caione <carlo.caione@gmail.com>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11 #define DRV_NAME "sunxi-8i-nmi"
12 #define pr_fmt(fmt) DRV_NAME ": " fmt
13
14 #include <linux/bitops.h>
15 #include <linux/device.h>
16 #include <linux/io.h>
17 #include <linux/irq.h>
18 #include <linux/interrupt.h>
19 #include <linux/irqdomain.h>
20 #include <linux/of_irq.h>
21 #include <linux/of_address.h>
22 #include <linux/of_platform.h>
23 #include <linux/irqchip.h>
24 #include <linux/irqchip/chained_irq.h>
25 #include <linux/syscore_ops.h>
26 #include <linux/pinctrl/consumer.h>
27 #include <linux/init.h>
28 #include <linux/module.h>
29 #include <linux/platform_device.h>
30
31 #define SUNXI_NMI_SRC_TYPE_MASK 0x00000003
32
33 enum {
34 SUNXI_SRC_TYPE_LEVEL_LOW = 0,
35 SUNXI_SRC_TYPE_EDGE_FALLING,
36 SUNXI_SRC_TYPE_LEVEL_HIGH,
37 SUNXI_SRC_TYPE_EDGE_RISING,
38 };
39
40 struct sunxi_sc_nmi_reg_offs {
41 u32 ctrl;
42 u32 pend;
43 u32 enable;
44 };
45
46 static struct sunxi_sc_nmi_reg_offs sun8i_reg_offs = {
47 .ctrl = 0x00,
48 .pend = 0x08,
49 .enable = 0x04,
50 };
51
sunxi_sc_nmi_write(struct irq_chip_generic * gc,u32 off,u32 val)52 static inline void sunxi_sc_nmi_write(struct irq_chip_generic *gc, u32 off,
53 u32 val)
54 {
55 irq_reg_writel(gc, val, off);
56 }
57
sunxi_sc_nmi_read(struct irq_chip_generic * gc,u32 off)58 static inline u32 sunxi_sc_nmi_read(struct irq_chip_generic *gc, u32 off)
59 {
60 return irq_reg_readl(gc, off);
61 }
62
sunxi_sc_nmi_handle_irq(struct irq_desc * desc)63 static void sunxi_sc_nmi_handle_irq(struct irq_desc *desc)
64 {
65 struct irq_domain *domain = irq_desc_get_handler_data(desc);
66 struct irq_chip *chip = irq_desc_get_chip(desc);
67 unsigned int virq = irq_find_mapping(domain, 0);
68
69 chained_irq_enter(chip, desc);
70 generic_handle_irq(virq);
71 chained_irq_exit(chip, desc);
72 }
73
sunxi_sc_nmi_set_type(struct irq_data * data,unsigned int flow_type)74 static int sunxi_sc_nmi_set_type(struct irq_data *data, unsigned int flow_type)
75 {
76 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
77 struct irq_chip_type *ct = gc->chip_types;
78 u32 src_type_reg;
79 u32 ctrl_off = ct->regs.type;
80 unsigned int src_type;
81 unsigned int i;
82
83 irq_gc_lock(gc);
84
85 switch (flow_type & IRQF_TRIGGER_MASK) {
86 case IRQ_TYPE_EDGE_FALLING:
87 src_type = SUNXI_SRC_TYPE_EDGE_FALLING;
88 break;
89 case IRQ_TYPE_EDGE_RISING:
90 src_type = SUNXI_SRC_TYPE_EDGE_RISING;
91 break;
92 case IRQ_TYPE_LEVEL_HIGH:
93 src_type = SUNXI_SRC_TYPE_LEVEL_HIGH;
94 break;
95 case IRQ_TYPE_NONE:
96 case IRQ_TYPE_LEVEL_LOW:
97 src_type = SUNXI_SRC_TYPE_LEVEL_LOW;
98 break;
99 default:
100 irq_gc_unlock(gc);
101 pr_err("Cannot assign multiple trigger modes to IRQ %d.\n",
102 data->irq);
103 return -EBADR;
104 }
105
106 irqd_set_trigger_type(data, flow_type);
107 irq_setup_alt_chip(data, flow_type);
108
109 for (i = 0; i < gc->num_ct; i++, ct++)
110 if (ct->type & flow_type)
111 ctrl_off = ct->regs.type;
112
113 src_type_reg = sunxi_sc_nmi_read(gc, ctrl_off);
114 src_type_reg &= ~SUNXI_NMI_SRC_TYPE_MASK;
115 src_type_reg |= src_type;
116 sunxi_sc_nmi_write(gc, ctrl_off, src_type_reg);
117
118 irq_gc_unlock(gc);
119
120 return IRQ_SET_MASK_OK;
121 }
122
sunxi_nmi_pad_control(struct device_node * node)123 static void sunxi_nmi_pad_control(struct device_node *node)
124 {
125 u32 v;
126 u32 __iomem *pad;
127
128 /* if we read pad-control-v1, the we use the addr to contorl nmi */
129 if (of_property_read_u32(node, "pad-control-v1", &v))
130 return;
131
132 pad = ioremap(v, 4);
133 *pad = *pad & ~BIT(0);
134 iounmap(pad);
135 }
136
137 /*
138 * on some standby, the prcm control register can lowpower down
139 * so it must resume the register value first
140 */
141 static struct irq_chip_generic *sys_gc;
142 static struct sunxi_sc_nmi_reg_offs *sys_reg_offs;
143 static uint32_t sys_vaule;
sunxi_nmi_suspend(void)144 static int sunxi_nmi_suspend(void)
145 {
146 sys_vaule = sunxi_sc_nmi_read(sys_gc, sys_reg_offs->enable);
147 return 0;
148 }
149
sunxi_nmi_resume(void)150 static void sunxi_nmi_resume(void)
151 {
152 sunxi_sc_nmi_write(sys_gc, sys_reg_offs->enable, sys_vaule);
153 }
154
155 static struct syscore_ops sunxi_nmi_syscore_ops = {
156 .suspend = sunxi_nmi_suspend,
157 .resume = sunxi_nmi_resume,
158 };
159
sunxi_sc_nmi_irq_init(struct device_node * node,struct sunxi_sc_nmi_reg_offs * reg_offs)160 static int sunxi_sc_nmi_irq_init(struct device_node *node,
161 struct sunxi_sc_nmi_reg_offs *reg_offs)
162 {
163 struct irq_domain *domain;
164 struct irq_chip_generic *gc;
165 unsigned int irq;
166 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
167 int ret;
168
169
170 domain = irq_domain_add_linear(node, 1, &irq_generic_chip_ops, NULL);
171 if (!domain) {
172 pr_err("Could not register interrupt domain.\n");
173 return -ENOMEM;
174 }
175
176 ret = irq_alloc_domain_generic_chips(domain, 1, 2, DRV_NAME,
177 handle_fasteoi_irq, clr, 0,
178 IRQ_GC_INIT_MASK_CACHE);
179 if (ret) {
180 pr_err("Could not allocate generic interrupt chip.\n");
181 goto fail_irqd_remove;
182 }
183
184 irq = irq_of_parse_and_map(node, 0);
185 if (irq <= 0) {
186 pr_err("unable to parse irq\n");
187 ret = -EINVAL;
188 goto fail_irqd_remove;
189 }
190
191 gc = irq_get_domain_generic_chip(domain, 0);
192 gc->reg_base = of_io_request_and_map(node, 0, of_node_full_name(node));
193 if (IS_ERR(gc->reg_base)) {
194 pr_err("unable to map resource\n");
195 ret = PTR_ERR(gc->reg_base);
196 goto fail_irqd_remove;
197 }
198
199 gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK;
200 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
201 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
202 gc->chip_types[0].chip.irq_eoi = irq_gc_ack_set_bit;
203 gc->chip_types[0].chip.irq_set_type = sunxi_sc_nmi_set_type;
204 gc->chip_types[0].chip.flags = IRQCHIP_EOI_THREADED |
205 IRQCHIP_EOI_IF_HANDLED |
206 IRQCHIP_SKIP_SET_WAKE;
207 gc->chip_types[0].regs.ack = reg_offs->pend;
208 gc->chip_types[0].regs.mask = reg_offs->enable;
209 gc->chip_types[0].regs.type = reg_offs->ctrl;
210
211 gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH;
212 gc->chip_types[1].chip.name = gc->chip_types[0].chip.name;
213 gc->chip_types[1].chip.irq_ack = irq_gc_ack_set_bit;
214 gc->chip_types[1].chip.irq_mask = irq_gc_mask_clr_bit;
215 gc->chip_types[1].chip.irq_unmask = irq_gc_mask_set_bit;
216 gc->chip_types[1].chip.irq_set_type = sunxi_sc_nmi_set_type;
217 gc->chip_types[1].regs.ack = reg_offs->pend;
218 gc->chip_types[1].regs.mask = reg_offs->enable;
219 gc->chip_types[1].regs.type = reg_offs->ctrl;
220 gc->chip_types[1].handler = handle_edge_irq;
221
222 sunxi_sc_nmi_write(gc, reg_offs->enable, 0);
223 sunxi_sc_nmi_write(gc, reg_offs->pend, 0x1);
224
225 sunxi_nmi_pad_control(node);
226 sys_gc = gc;
227 sys_reg_offs = reg_offs;
228 register_syscore_ops(&sunxi_nmi_syscore_ops);
229
230 irq_set_chained_handler_and_data(irq, sunxi_sc_nmi_handle_irq, domain);
231
232 return 0;
233
234 fail_irqd_remove:
235 irq_domain_remove(domain);
236
237 return ret;
238 }
239
sunxi_irq_nmi_probe(struct platform_device * pdev)240 static int sunxi_irq_nmi_probe(struct platform_device *pdev)
241 {
242 struct pinctrl *pctrl;
243 struct pinctrl_state *pctrl_state = NULL;
244
245 pctrl = devm_pinctrl_get(&pdev->dev);
246 if (!IS_ERR_OR_NULL(pctrl)) {
247 pctrl_state = pinctrl_lookup_state(pctrl, "default");
248
249 pinctrl_select_state(pctrl, pctrl_state);
250 }
251
252 return sunxi_sc_nmi_irq_init(pdev->dev.of_node, &sun8i_reg_offs);
253 }
254
sunxi_irq_nmi_remove(struct platform_device * pdev)255 static int sunxi_irq_nmi_remove(struct platform_device *pdev)
256 {
257 struct device_node *node = pdev->dev.of_node;
258 struct resource res;
259
260 unregister_syscore_ops(&sunxi_nmi_syscore_ops);
261 iounmap(sys_gc->reg_base);
262 of_address_to_resource(node, 0, &res);
263 release_mem_region(res.start, resource_size(&res));
264 irq_domain_remove(sys_gc->domain);
265
266 return 0;
267 }
268
269 static struct of_device_id sunxi_irq_nmi_match[] = {
270 { .compatible = "allwinner,sun8i-nmi" },
271 {}
272 };
273
274 static struct platform_driver sunxi_irq_nmi_driver = {
275 .probe = sunxi_irq_nmi_probe,
276 .remove = sunxi_irq_nmi_remove,
277 .driver = {
278 .name = "sunxi_irq_nmi",
279 .owner = THIS_MODULE,
280 .of_match_table = sunxi_irq_nmi_match,
281 },
282 };
283
sun8i_nmi_irq_init(void)284 static int __init sun8i_nmi_irq_init(void)
285 {
286 return platform_driver_register(&sunxi_irq_nmi_driver);
287 }
288 postcore_initcall_sync(sun8i_nmi_irq_init);
289
sun8i_nmi_irq_exit(void)290 static void __exit sun8i_nmi_irq_exit(void)
291 {
292 platform_driver_unregister(&sunxi_irq_nmi_driver);
293 }
294 module_exit(sun8i_nmi_irq_exit);
295
296 MODULE_AUTHOR("lihuaxing");
297 MODULE_DESCRIPTION("Allwinner nmi irq");
298 MODULE_LICENSE("GPL");
299 MODULE_VERSION("1.0.0");
300