1 /*
2 * Broadcom BCMSDH to gSPI Protocol Conversion Layer
3 *
4 * Copyright (C) 1999-2017, Broadcom Corporation
5 *
6 * Unless you and Broadcom execute a separate written software license
7 * agreement governing use of this software, this software is licensed to you
8 * under the terms of the GNU General Public License version 2 (the "GPL"),
9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the
10 * following added to such license:
11 *
12 * As a special exception, the copyright holders of this software give you
13 * permission to link this software with independent modules, and to copy and
14 * distribute the resulting executable under terms of your choice, provided that
15 * you also meet, for each linked independent module, the terms and conditions of
16 * the license of that module. An independent module is a module which is not
17 * derived from this software. The special exception does not apply to any
18 * modifications of the software.
19 *
20 * Notwithstanding the above, under no circumstances may you combine this
21 * software in any way with any other Broadcom software provided under a license
22 * other than the GPL, without Broadcom's express prior written consent.
23 *
24 *
25 * <<Broadcom-WL-IPTag/Open:>>
26 *
27 * $Id: bcmspibrcm.c 611787 2016-01-12 06:07:27Z $
28 */
29
30 #define HSMODE
31
32 #include <typedefs.h>
33
34 #include <bcmdevs.h>
35 #include <bcmendian.h>
36 #include <bcmutils.h>
37 #include <osl.h>
38 #include <hndsoc.h>
39 #include <siutils.h>
40 #include <sbchipc.h>
41 #include <sbsdio.h> /* SDIO device core hardware definitions. */
42 #include <spid.h>
43
44 #include <bcmsdbus.h> /* bcmsdh to/from specific controller APIs */
45 #include <sdiovar.h> /* ioctl/iovars */
46 #include <sdio.h> /* SDIO Device and Protocol Specs */
47
48 #include <pcicfg.h>
49
50
51 #include <bcmspibrcm.h>
52 #include <bcmspi.h>
53
54 /* these are for the older cores... for newer cores we have control for each of them */
55 #define F0_RESPONSE_DELAY 16
56 #define F1_RESPONSE_DELAY 16
57 #define F2_RESPONSE_DELAY F0_RESPONSE_DELAY
58
59
60 #define GSPI_F0_RESP_DELAY 0
61 #define GSPI_F1_RESP_DELAY F1_RESPONSE_DELAY
62 #define GSPI_F2_RESP_DELAY 0
63 #define GSPI_F3_RESP_DELAY 0
64
65 #define CMDLEN 4
66
67 /* Globals */
68 #if defined(DHD_DEBUG)
69 uint sd_msglevel = SDH_ERROR_VAL;
70 #else
71 uint sd_msglevel = 0;
72 #endif
73
74 uint sd_hiok = FALSE; /* Use hi-speed mode if available? */
75 uint sd_sdmode = SDIOH_MODE_SPI; /* Use SD4 mode by default */
76 uint sd_f2_blocksize = 64; /* Default blocksize */
77
78
79 uint sd_divisor = 2;
80 uint sd_power = 1; /* Default to SD Slot powered ON */
81 uint sd_clock = 1; /* Default to SD Clock turned ON */
82 uint sd_crc = 0; /* Default to SPI CRC Check turned OFF */
83 uint sd_pci_slot = 0xFFFFffff; /* Used to force selection of a particular PCI slot */
84
85 uint8 spi_outbuf[SPI_MAX_PKT_LEN];
86 uint8 spi_inbuf[SPI_MAX_PKT_LEN];
87
88 /* 128bytes buffer is enough to clear data-not-available and program response-delay F0 bits
89 * assuming we will not exceed F0 response delay > 100 bytes at 48MHz.
90 */
91 #define BUF2_PKT_LEN 128
92 uint8 spi_outbuf2[BUF2_PKT_LEN];
93 uint8 spi_inbuf2[BUF2_PKT_LEN];
94
95 #define SPISWAP_WD4(x) bcmswap32(x);
96 #define SPISWAP_WD2(x) (bcmswap16(x & 0xffff)) | \
97 (bcmswap16((x & 0xffff0000) >> 16) << 16);
98
99 /* Prototypes */
100 static bool bcmspi_test_card(sdioh_info_t *sd);
101 static bool bcmspi_host_device_init_adapt(sdioh_info_t *sd);
102 static int bcmspi_set_highspeed_mode(sdioh_info_t *sd, bool hsmode);
103 static int bcmspi_cmd_issue(sdioh_info_t *sd, bool use_dma, uint32 cmd_arg,
104 uint32 *data, uint32 datalen);
105 static int bcmspi_card_regread(sdioh_info_t *sd, int func, uint32 regaddr,
106 int regsize, uint32 *data);
107 static int bcmspi_card_regwrite(sdioh_info_t *sd, int func, uint32 regaddr,
108 int regsize, uint32 data);
109 static int bcmspi_card_bytewrite(sdioh_info_t *sd, int func, uint32 regaddr,
110 uint8 *data);
111 static int bcmspi_driver_init(sdioh_info_t *sd);
112 static int bcmspi_card_buf(sdioh_info_t *sd, int rw, int func, bool fifo,
113 uint32 addr, int nbytes, uint32 *data);
114 static int bcmspi_card_regread_fixedaddr(sdioh_info_t *sd, int func, uint32 regaddr, int regsize,
115 uint32 *data);
116 static void bcmspi_cmd_getdstatus(sdioh_info_t *sd, uint32 *dstatus_buffer);
117 static int bcmspi_update_stats(sdioh_info_t *sd, uint32 cmd_arg);
118
119 /*
120 * Public entry points & extern's
121 */
122 extern sdioh_info_t *
sdioh_attach(osl_t * osh,void * bar0,uint irq)123 sdioh_attach(osl_t *osh, void *bar0, uint irq)
124 {
125 sdioh_info_t *sd;
126
127 sd_trace(("%s\n", __FUNCTION__));
128 if ((sd = (sdioh_info_t *)MALLOC(osh, sizeof(sdioh_info_t))) == NULL) {
129 sd_err(("%s: out of memory, malloced %d bytes\n", __FUNCTION__, MALLOCED(osh)));
130 return NULL;
131 }
132 bzero((char *)sd, sizeof(sdioh_info_t));
133 sd->osh = osh;
134 if (spi_osinit(sd) != 0) {
135 sd_err(("%s: spi_osinit() failed\n", __FUNCTION__));
136 MFREE(sd->osh, sd, sizeof(sdioh_info_t));
137 return NULL;
138 }
139
140 sd->bar0 = bar0;
141 sd->irq = irq;
142 sd->intr_handler = NULL;
143 sd->intr_handler_arg = NULL;
144 sd->intr_handler_valid = FALSE;
145
146 /* Set defaults */
147 sd->use_client_ints = TRUE;
148 sd->sd_use_dma = FALSE; /* DMA Not supported */
149
150 /* Spi device default is 16bit mode, change to 4 when device is changed to 32bit
151 * mode
152 */
153 sd->wordlen = 2;
154
155
156 if (!spi_hw_attach(sd)) {
157 sd_err(("%s: spi_hw_attach() failed\n", __FUNCTION__));
158 spi_osfree(sd);
159 MFREE(sd->osh, sd, sizeof(sdioh_info_t));
160 return (NULL);
161 }
162
163 if (bcmspi_driver_init(sd) != SUCCESS) {
164 sd_err(("%s: bcmspi_driver_init() failed()\n", __FUNCTION__));
165 spi_hw_detach(sd);
166 spi_osfree(sd);
167 MFREE(sd->osh, sd, sizeof(sdioh_info_t));
168 return (NULL);
169 }
170
171 if (spi_register_irq(sd, irq) != SUCCESS) {
172 sd_err(("%s: spi_register_irq() failed for irq = %d\n", __FUNCTION__, irq));
173 spi_hw_detach(sd);
174 spi_osfree(sd);
175 MFREE(sd->osh, sd, sizeof(sdioh_info_t));
176 return (NULL);
177 }
178
179 sd_trace(("%s: Done\n", __FUNCTION__));
180
181 return sd;
182 }
183
184 extern SDIOH_API_RC
sdioh_detach(osl_t * osh,sdioh_info_t * sd)185 sdioh_detach(osl_t *osh, sdioh_info_t *sd)
186 {
187 sd_trace(("%s\n", __FUNCTION__));
188 if (sd) {
189 sd_err(("%s: detaching from hardware\n", __FUNCTION__));
190 spi_free_irq(sd->irq, sd);
191 spi_hw_detach(sd);
192 spi_osfree(sd);
193 MFREE(sd->osh, sd, sizeof(sdioh_info_t));
194 }
195 return SDIOH_API_RC_SUCCESS;
196 }
197
198 /* Configure callback to client when we recieve client interrupt */
199 extern SDIOH_API_RC
sdioh_interrupt_register(sdioh_info_t * sd,sdioh_cb_fn_t fn,void * argh)200 sdioh_interrupt_register(sdioh_info_t *sd, sdioh_cb_fn_t fn, void *argh)
201 {
202 sd_trace(("%s: Entering\n", __FUNCTION__));
203 #if !defined(OOB_INTR_ONLY)
204 sd->intr_handler = fn;
205 sd->intr_handler_arg = argh;
206 sd->intr_handler_valid = TRUE;
207 #endif /* !defined(OOB_INTR_ONLY) */
208 return SDIOH_API_RC_SUCCESS;
209 }
210
211 extern SDIOH_API_RC
sdioh_interrupt_deregister(sdioh_info_t * sd)212 sdioh_interrupt_deregister(sdioh_info_t *sd)
213 {
214 sd_trace(("%s: Entering\n", __FUNCTION__));
215 #if !defined(OOB_INTR_ONLY)
216 sd->intr_handler_valid = FALSE;
217 sd->intr_handler = NULL;
218 sd->intr_handler_arg = NULL;
219 #endif /* !defined(OOB_INTR_ONLY) */
220 return SDIOH_API_RC_SUCCESS;
221 }
222
223 extern SDIOH_API_RC
sdioh_interrupt_query(sdioh_info_t * sd,bool * onoff)224 sdioh_interrupt_query(sdioh_info_t *sd, bool *onoff)
225 {
226 sd_trace(("%s: Entering\n", __FUNCTION__));
227 *onoff = sd->client_intr_enabled;
228 return SDIOH_API_RC_SUCCESS;
229 }
230
231 #if defined(DHD_DEBUG)
232 extern bool
sdioh_interrupt_pending(sdioh_info_t * sd)233 sdioh_interrupt_pending(sdioh_info_t *sd)
234 {
235 return 0;
236 }
237 #endif
238
239 /* Provide dstatus bits of spi-transaction for dhd layers. */
240 extern uint32
sdioh_get_dstatus(sdioh_info_t * sd)241 sdioh_get_dstatus(sdioh_info_t *sd)
242 {
243 return sd->card_dstatus;
244 }
245
246 extern void
sdioh_chipinfo(sdioh_info_t * sd,uint32 chip,uint32 chiprev)247 sdioh_chipinfo(sdioh_info_t *sd, uint32 chip, uint32 chiprev)
248 {
249 sd->chip = chip;
250 sd->chiprev = chiprev;
251 }
252
253 extern void
sdioh_dwordmode(sdioh_info_t * sd,bool set)254 sdioh_dwordmode(sdioh_info_t *sd, bool set)
255 {
256 uint8 reg = 0;
257 int status;
258
259 if ((status = sdioh_request_byte(sd, SDIOH_READ, SPI_FUNC_0, SPID_STATUS_ENABLE, ®)) !=
260 SUCCESS) {
261 sd_err(("%s: Failed to set dwordmode in gSPI\n", __FUNCTION__));
262 return;
263 }
264
265 if (set) {
266 reg |= DWORD_PKT_LEN_EN;
267 sd->dwordmode = TRUE;
268 sd->client_block_size[SPI_FUNC_2] = 4096; /* h2spi's limit is 4KB, we support 8KB */
269 } else {
270 reg &= ~DWORD_PKT_LEN_EN;
271 sd->dwordmode = FALSE;
272 sd->client_block_size[SPI_FUNC_2] = 2048;
273 }
274
275 if ((status = sdioh_request_byte(sd, SDIOH_WRITE, SPI_FUNC_0, SPID_STATUS_ENABLE, ®)) !=
276 SUCCESS) {
277 sd_err(("%s: Failed to set dwordmode in gSPI\n", __FUNCTION__));
278 return;
279 }
280 }
281
282
283 uint
sdioh_query_iofnum(sdioh_info_t * sd)284 sdioh_query_iofnum(sdioh_info_t *sd)
285 {
286 return sd->num_funcs;
287 }
288
289 /* IOVar table */
290 enum {
291 IOV_MSGLEVEL = 1,
292 IOV_BLOCKMODE,
293 IOV_BLOCKSIZE,
294 IOV_DMA,
295 IOV_USEINTS,
296 IOV_NUMINTS,
297 IOV_NUMLOCALINTS,
298 IOV_HOSTREG,
299 IOV_DEVREG,
300 IOV_DIVISOR,
301 IOV_SDMODE,
302 IOV_HISPEED,
303 IOV_HCIREGS,
304 IOV_POWER,
305 IOV_CLOCK,
306 IOV_SPIERRSTATS,
307 IOV_RESP_DELAY_ALL
308 };
309
310 const bcm_iovar_t sdioh_iovars[] = {
311 {"sd_msglevel", IOV_MSGLEVEL, 0, IOVT_UINT32, 0 },
312 {"sd_blocksize", IOV_BLOCKSIZE, 0, IOVT_UINT32, 0 }, /* ((fn << 16) | size) */
313 {"sd_dma", IOV_DMA, 0, IOVT_BOOL, 0 },
314 {"sd_ints", IOV_USEINTS, 0, IOVT_BOOL, 0 },
315 {"sd_numints", IOV_NUMINTS, 0, IOVT_UINT32, 0 },
316 {"sd_numlocalints", IOV_NUMLOCALINTS, 0, IOVT_UINT32, 0 },
317 {"sd_hostreg", IOV_HOSTREG, 0, IOVT_BUFFER, sizeof(sdreg_t) },
318 {"sd_devreg", IOV_DEVREG, 0, IOVT_BUFFER, sizeof(sdreg_t) },
319 {"sd_divisor", IOV_DIVISOR, 0, IOVT_UINT32, 0 },
320 {"sd_power", IOV_POWER, 0, IOVT_UINT32, 0 },
321 {"sd_clock", IOV_CLOCK, 0, IOVT_UINT32, 0 },
322 {"sd_mode", IOV_SDMODE, 0, IOVT_UINT32, 100},
323 {"sd_highspeed", IOV_HISPEED, 0, IOVT_UINT32, 0},
324 {"spi_errstats", IOV_SPIERRSTATS, 0, IOVT_BUFFER, sizeof(struct spierrstats_t) },
325 {"spi_respdelay", IOV_RESP_DELAY_ALL, 0, IOVT_BOOL, 0 },
326 {NULL, 0, 0, 0, 0 }
327 };
328
329 int
sdioh_iovar_op(sdioh_info_t * si,const char * name,void * params,int plen,void * arg,int len,bool set)330 sdioh_iovar_op(sdioh_info_t *si, const char *name,
331 void *params, int plen, void *arg, int len, bool set)
332 {
333 const bcm_iovar_t *vi = NULL;
334 int bcmerror = 0;
335 int val_size;
336 int32 int_val = 0;
337 bool bool_val;
338 uint32 actionid;
339
340 ASSERT(name);
341 ASSERT(len >= 0);
342
343 /* Get must have return space; Set does not take qualifiers */
344 ASSERT(set || (arg && len));
345 ASSERT(!set || (!params && !plen));
346
347 sd_trace(("%s: Enter (%s %s)\n", __FUNCTION__, (set ? "set" : "get"), name));
348
349 if ((vi = bcm_iovar_lookup(sdioh_iovars, name)) == NULL) {
350 bcmerror = BCME_UNSUPPORTED;
351 goto exit;
352 }
353
354 if ((bcmerror = bcm_iovar_lencheck(vi, arg, len, set)) != 0)
355 goto exit;
356
357 /* Set up params so get and set can share the convenience variables */
358 if (params == NULL) {
359 params = arg;
360 plen = len;
361 }
362
363 if (vi->type == IOVT_VOID)
364 val_size = 0;
365 else if (vi->type == IOVT_BUFFER)
366 val_size = len;
367 else
368 val_size = sizeof(int);
369
370 if (plen >= (int)sizeof(int_val))
371 bcopy(params, &int_val, sizeof(int_val));
372
373 bool_val = (int_val != 0) ? TRUE : FALSE;
374
375 actionid = set ? IOV_SVAL(vi->varid) : IOV_GVAL(vi->varid);
376 switch (actionid) {
377 case IOV_GVAL(IOV_MSGLEVEL):
378 int_val = (int32)sd_msglevel;
379 bcopy(&int_val, arg, val_size);
380 break;
381
382 case IOV_SVAL(IOV_MSGLEVEL):
383 sd_msglevel = int_val;
384 break;
385
386 case IOV_GVAL(IOV_BLOCKSIZE):
387 if ((uint32)int_val > si->num_funcs) {
388 bcmerror = BCME_BADARG;
389 break;
390 }
391 int_val = (int32)si->client_block_size[int_val];
392 bcopy(&int_val, arg, val_size);
393 break;
394
395 case IOV_GVAL(IOV_DMA):
396 int_val = (int32)si->sd_use_dma;
397 bcopy(&int_val, arg, val_size);
398 break;
399
400 case IOV_SVAL(IOV_DMA):
401 si->sd_use_dma = (bool)int_val;
402 break;
403
404 case IOV_GVAL(IOV_USEINTS):
405 int_val = (int32)si->use_client_ints;
406 bcopy(&int_val, arg, val_size);
407 break;
408
409 case IOV_SVAL(IOV_USEINTS):
410 break;
411
412 case IOV_GVAL(IOV_DIVISOR):
413 int_val = (uint32)sd_divisor;
414 bcopy(&int_val, arg, val_size);
415 break;
416
417 case IOV_SVAL(IOV_DIVISOR):
418 sd_divisor = int_val;
419 if (!spi_start_clock(si, (uint16)sd_divisor)) {
420 sd_err(("%s: set clock failed\n", __FUNCTION__));
421 bcmerror = BCME_ERROR;
422 }
423 break;
424
425 case IOV_GVAL(IOV_POWER):
426 int_val = (uint32)sd_power;
427 bcopy(&int_val, arg, val_size);
428 break;
429
430 case IOV_SVAL(IOV_POWER):
431 sd_power = int_val;
432 break;
433
434 case IOV_GVAL(IOV_CLOCK):
435 int_val = (uint32)sd_clock;
436 bcopy(&int_val, arg, val_size);
437 break;
438
439 case IOV_SVAL(IOV_CLOCK):
440 sd_clock = int_val;
441 break;
442
443 case IOV_GVAL(IOV_SDMODE):
444 int_val = (uint32)sd_sdmode;
445 bcopy(&int_val, arg, val_size);
446 break;
447
448 case IOV_SVAL(IOV_SDMODE):
449 sd_sdmode = int_val;
450 break;
451
452 case IOV_GVAL(IOV_HISPEED):
453 int_val = (uint32)sd_hiok;
454 bcopy(&int_val, arg, val_size);
455 break;
456
457 case IOV_SVAL(IOV_HISPEED):
458 sd_hiok = int_val;
459
460 if (!bcmspi_set_highspeed_mode(si, (bool)sd_hiok)) {
461 sd_err(("%s: Failed changing highspeed mode to %d.\n",
462 __FUNCTION__, sd_hiok));
463 bcmerror = BCME_ERROR;
464 return ERROR;
465 }
466 break;
467
468 case IOV_GVAL(IOV_NUMINTS):
469 int_val = (int32)si->intrcount;
470 bcopy(&int_val, arg, val_size);
471 break;
472
473 case IOV_GVAL(IOV_NUMLOCALINTS):
474 int_val = (int32)si->local_intrcount;
475 bcopy(&int_val, arg, val_size);
476 break;
477 case IOV_GVAL(IOV_DEVREG):
478 {
479 sdreg_t *sd_ptr = (sdreg_t *)params;
480 uint8 data;
481
482 if (sdioh_cfg_read(si, sd_ptr->func, sd_ptr->offset, &data)) {
483 bcmerror = BCME_SDIO_ERROR;
484 break;
485 }
486
487 int_val = (int)data;
488 bcopy(&int_val, arg, sizeof(int_val));
489 break;
490 }
491
492 case IOV_SVAL(IOV_DEVREG):
493 {
494 sdreg_t *sd_ptr = (sdreg_t *)params;
495 uint8 data = (uint8)sd_ptr->value;
496
497 if (sdioh_cfg_write(si, sd_ptr->func, sd_ptr->offset, &data)) {
498 bcmerror = BCME_SDIO_ERROR;
499 break;
500 }
501 break;
502 }
503
504
505 case IOV_GVAL(IOV_SPIERRSTATS):
506 {
507 bcopy(&si->spierrstats, arg, sizeof(struct spierrstats_t));
508 break;
509 }
510
511 case IOV_SVAL(IOV_SPIERRSTATS):
512 {
513 bzero(&si->spierrstats, sizeof(struct spierrstats_t));
514 break;
515 }
516
517 case IOV_GVAL(IOV_RESP_DELAY_ALL):
518 int_val = (int32)si->resp_delay_all;
519 bcopy(&int_val, arg, val_size);
520 break;
521
522 case IOV_SVAL(IOV_RESP_DELAY_ALL):
523 si->resp_delay_all = (bool)int_val;
524 int_val = STATUS_ENABLE|INTR_WITH_STATUS;
525 if (si->resp_delay_all)
526 int_val |= RESP_DELAY_ALL;
527 else {
528 if (bcmspi_card_regwrite(si, SPI_FUNC_0, SPID_RESPONSE_DELAY, 1,
529 F1_RESPONSE_DELAY) != SUCCESS) {
530 sd_err(("%s: Unable to set response delay.\n", __FUNCTION__));
531 bcmerror = BCME_SDIO_ERROR;
532 break;
533 }
534 }
535
536 if (bcmspi_card_regwrite(si, SPI_FUNC_0, SPID_STATUS_ENABLE, 1, int_val)
537 != SUCCESS) {
538 sd_err(("%s: Unable to set response delay.\n", __FUNCTION__));
539 bcmerror = BCME_SDIO_ERROR;
540 break;
541 }
542 break;
543
544 default:
545 bcmerror = BCME_UNSUPPORTED;
546 break;
547 }
548 exit:
549
550 return bcmerror;
551 }
552
553 extern SDIOH_API_RC
sdioh_cfg_read(sdioh_info_t * sd,uint fnc_num,uint32 addr,uint8 * data)554 sdioh_cfg_read(sdioh_info_t *sd, uint fnc_num, uint32 addr, uint8 *data)
555 {
556 SDIOH_API_RC status;
557 /* No lock needed since sdioh_request_byte does locking */
558 status = sdioh_request_byte(sd, SDIOH_READ, fnc_num, addr, data);
559 return status;
560 }
561
562 extern SDIOH_API_RC
sdioh_cfg_write(sdioh_info_t * sd,uint fnc_num,uint32 addr,uint8 * data)563 sdioh_cfg_write(sdioh_info_t *sd, uint fnc_num, uint32 addr, uint8 *data)
564 {
565 /* No lock needed since sdioh_request_byte does locking */
566 SDIOH_API_RC status;
567
568 if ((fnc_num == SPI_FUNC_1) && (addr == SBSDIO_FUNC1_FRAMECTRL)) {
569 uint8 dummy_data;
570 status = sdioh_cfg_read(sd, fnc_num, addr, &dummy_data);
571 if (status) {
572 sd_err(("sdioh_cfg_read() failed.\n"));
573 return status;
574 }
575 }
576
577 status = sdioh_request_byte(sd, SDIOH_WRITE, fnc_num, addr, data);
578 return status;
579 }
580
581 extern SDIOH_API_RC
sdioh_cis_read(sdioh_info_t * sd,uint func,uint8 * cisd,uint32 length)582 sdioh_cis_read(sdioh_info_t *sd, uint func, uint8 *cisd, uint32 length)
583 {
584 uint32 count;
585 int offset;
586 uint32 cis_byte;
587 uint16 *cis = (uint16 *)cisd;
588 uint bar0 = SI_ENUM_BASE;
589 int status;
590 uint8 data;
591
592 sd_trace(("%s: Func %d\n", __FUNCTION__, func));
593
594 spi_lock(sd);
595
596 /* Set sb window address to 0x18000000 */
597 data = (bar0 >> 8) & SBSDIO_SBADDRLOW_MASK;
598 status = bcmspi_card_bytewrite(sd, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRLOW, &data);
599 if (status == SUCCESS) {
600 data = (bar0 >> 16) & SBSDIO_SBADDRMID_MASK;
601 status = bcmspi_card_bytewrite(sd, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRMID, &data);
602 } else {
603 sd_err(("%s: Unable to set sb-addr-windows\n", __FUNCTION__));
604 spi_unlock(sd);
605 return (BCME_ERROR);
606 }
607 if (status == SUCCESS) {
608 data = (bar0 >> 24) & SBSDIO_SBADDRHIGH_MASK;
609 status = bcmspi_card_bytewrite(sd, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRHIGH, &data);
610 } else {
611 sd_err(("%s: Unable to set sb-addr-windows\n", __FUNCTION__));
612 spi_unlock(sd);
613 return (BCME_ERROR);
614 }
615
616 offset = CC_SROM_OTP; /* OTP offset in chipcommon. */
617 for (count = 0; count < length/2; count++) {
618 if (bcmspi_card_regread (sd, SDIO_FUNC_1, offset, 2, &cis_byte) < 0) {
619 sd_err(("%s: regread failed: Can't read CIS\n", __FUNCTION__));
620 spi_unlock(sd);
621 return (BCME_ERROR);
622 }
623
624 *cis = (uint16)cis_byte;
625 cis++;
626 offset += 2;
627 }
628
629 spi_unlock(sd);
630
631 return (BCME_OK);
632 }
633
634 extern SDIOH_API_RC
sdioh_request_byte(sdioh_info_t * sd,uint rw,uint func,uint regaddr,uint8 * byte)635 sdioh_request_byte(sdioh_info_t *sd, uint rw, uint func, uint regaddr, uint8 *byte)
636 {
637 int status;
638 uint32 cmd_arg;
639 uint32 dstatus;
640 uint32 data = (uint32)(*byte);
641
642 spi_lock(sd);
643
644 cmd_arg = 0;
645 cmd_arg = SFIELD(cmd_arg, SPI_FUNCTION, func);
646 cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 1); /* Incremental access */
647 cmd_arg = SFIELD(cmd_arg, SPI_REG_ADDR, regaddr);
648 cmd_arg = SFIELD(cmd_arg, SPI_RW_FLAG, rw == SDIOH_READ ? 0 : 1);
649 cmd_arg = SFIELD(cmd_arg, SPI_LEN, 1);
650
651 if (rw == SDIOH_READ) {
652 sd_trace(("%s: RD cmd_arg=0x%x func=%d regaddr=0x%x\n",
653 __FUNCTION__, cmd_arg, func, regaddr));
654 } else {
655 sd_trace(("%s: WR cmd_arg=0x%x func=%d regaddr=0x%x data=0x%x\n",
656 __FUNCTION__, cmd_arg, func, regaddr, data));
657 }
658
659 if ((status = bcmspi_cmd_issue(sd, sd->sd_use_dma, cmd_arg, &data, 1)) != SUCCESS) {
660 spi_unlock(sd);
661 return status;
662 }
663
664 if (rw == SDIOH_READ) {
665 *byte = (uint8)data;
666 sd_trace(("%s: RD result=0x%x\n", __FUNCTION__, *byte));
667 }
668
669 bcmspi_cmd_getdstatus(sd, &dstatus);
670 if (dstatus)
671 sd_trace(("dstatus=0x%x\n", dstatus));
672
673 spi_unlock(sd);
674 return SDIOH_API_RC_SUCCESS;
675 }
676
677 extern SDIOH_API_RC
sdioh_request_word(sdioh_info_t * sd,uint cmd_type,uint rw,uint func,uint addr,uint32 * word,uint nbytes)678 sdioh_request_word(sdioh_info_t *sd, uint cmd_type, uint rw, uint func, uint addr,
679 uint32 *word, uint nbytes)
680 {
681 int status;
682
683 spi_lock(sd);
684
685 if (rw == SDIOH_READ)
686 status = bcmspi_card_regread(sd, func, addr, nbytes, word);
687 else
688 status = bcmspi_card_regwrite(sd, func, addr, nbytes, *word);
689
690 spi_unlock(sd);
691 return (status == SUCCESS ? SDIOH_API_RC_SUCCESS : SDIOH_API_RC_FAIL);
692 }
693
694 extern SDIOH_API_RC
sdioh_request_buffer(sdioh_info_t * sd,uint pio_dma,uint fix_inc,uint rw,uint func,uint addr,uint reg_width,uint buflen_u,uint8 * buffer,void * pkt)695 sdioh_request_buffer(sdioh_info_t *sd, uint pio_dma, uint fix_inc, uint rw, uint func,
696 uint addr, uint reg_width, uint buflen_u, uint8 *buffer, void *pkt)
697 {
698 int len;
699 int buflen = (int)buflen_u;
700 bool fifo = (fix_inc == SDIOH_DATA_FIX);
701
702 spi_lock(sd);
703
704 ASSERT(reg_width == 4);
705 ASSERT(buflen_u < (1 << 30));
706 ASSERT(sd->client_block_size[func]);
707
708 sd_data(("%s: %c len %d r_cnt %d t_cnt %d, pkt @0x%p\n",
709 __FUNCTION__, rw == SDIOH_READ ? 'R' : 'W',
710 buflen_u, sd->r_cnt, sd->t_cnt, pkt));
711
712 /* Break buffer down into blocksize chunks. */
713 while (buflen > 0) {
714 len = MIN(sd->client_block_size[func], buflen);
715 if (bcmspi_card_buf(sd, rw, func, fifo, addr, len, (uint32 *)buffer) != SUCCESS) {
716 sd_err(("%s: bcmspi_card_buf %s failed\n",
717 __FUNCTION__, rw == SDIOH_READ ? "Read" : "Write"));
718 spi_unlock(sd);
719 return SDIOH_API_RC_FAIL;
720 }
721 buffer += len;
722 buflen -= len;
723 if (!fifo)
724 addr += len;
725 }
726 spi_unlock(sd);
727 return SDIOH_API_RC_SUCCESS;
728 }
729
730 /* This function allows write to gspi bus when another rd/wr function is deep down the call stack.
731 * Its main aim is to have simpler spi writes rather than recursive writes.
732 * e.g. When there is a need to program response delay on the fly after detecting the SPI-func
733 * this call will allow to program the response delay.
734 */
735 static int
bcmspi_card_byterewrite(sdioh_info_t * sd,int func,uint32 regaddr,uint8 byte)736 bcmspi_card_byterewrite(sdioh_info_t *sd, int func, uint32 regaddr, uint8 byte)
737 {
738 uint32 cmd_arg;
739 uint32 datalen = 1;
740 uint32 hostlen;
741
742 cmd_arg = 0;
743
744 cmd_arg = SFIELD(cmd_arg, SPI_RW_FLAG, 1);
745 cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 1); /* Incremental access */
746 cmd_arg = SFIELD(cmd_arg, SPI_FUNCTION, func);
747 cmd_arg = SFIELD(cmd_arg, SPI_REG_ADDR, regaddr);
748 cmd_arg = SFIELD(cmd_arg, SPI_LEN, datalen);
749
750 sd_trace(("%s cmd_arg = 0x%x\n", __FUNCTION__, cmd_arg));
751
752
753 /* Set up and issue the SPI command. MSByte goes out on bus first. Increase datalen
754 * according to the wordlen mode(16/32bit) the device is in.
755 */
756 ASSERT(sd->wordlen == 4 || sd->wordlen == 2);
757 datalen = ROUNDUP(datalen, sd->wordlen);
758
759 /* Start by copying command in the spi-outbuffer */
760 if (sd->wordlen == 4) { /* 32bit spid */
761 *(uint32 *)spi_outbuf2 = SPISWAP_WD4(cmd_arg);
762 if (datalen & 0x3)
763 datalen += (4 - (datalen & 0x3));
764 } else if (sd->wordlen == 2) { /* 16bit spid */
765 *(uint32 *)spi_outbuf2 = SPISWAP_WD2(cmd_arg);
766 if (datalen & 0x1)
767 datalen++;
768 } else {
769 sd_err(("%s: Host is %d bit spid, could not create SPI command.\n",
770 __FUNCTION__, 8 * sd->wordlen));
771 return ERROR;
772 }
773
774 /* for Write, put the data into the output buffer */
775 if (datalen != 0) {
776 if (sd->wordlen == 4) { /* 32bit spid */
777 *(uint32 *)&spi_outbuf2[CMDLEN] = SPISWAP_WD4(byte);
778 } else if (sd->wordlen == 2) { /* 16bit spid */
779 *(uint32 *)&spi_outbuf2[CMDLEN] = SPISWAP_WD2(byte);
780 }
781 }
782
783 /* +4 for cmd, +4 for dstatus */
784 hostlen = datalen + 8;
785 hostlen += (4 - (hostlen & 0x3));
786 spi_sendrecv(sd, spi_outbuf2, spi_inbuf2, hostlen);
787
788 /* Last 4bytes are dstatus. Device is configured to return status bits. */
789 if (sd->wordlen == 4) { /* 32bit spid */
790 sd->card_dstatus = SPISWAP_WD4(*(uint32 *)&spi_inbuf2[datalen + CMDLEN ]);
791 } else if (sd->wordlen == 2) { /* 16bit spid */
792 sd->card_dstatus = SPISWAP_WD2(*(uint32 *)&spi_inbuf2[datalen + CMDLEN ]);
793 } else {
794 sd_err(("%s: Host is %d bit machine, could not read SPI dstatus.\n",
795 __FUNCTION__, 8 * sd->wordlen));
796 return ERROR;
797 }
798
799 if (sd->card_dstatus)
800 sd_trace(("dstatus after byte rewrite = 0x%x\n", sd->card_dstatus));
801
802 return (BCME_OK);
803 }
804
805 /* Program the response delay corresponding to the spi function */
806 static int
bcmspi_prog_resp_delay(sdioh_info_t * sd,int func,uint8 resp_delay)807 bcmspi_prog_resp_delay(sdioh_info_t *sd, int func, uint8 resp_delay)
808 {
809 if (sd->resp_delay_all == FALSE)
810 return (BCME_OK);
811
812 if (sd->prev_fun == func)
813 return (BCME_OK);
814
815 if (F0_RESPONSE_DELAY == F1_RESPONSE_DELAY)
816 return (BCME_OK);
817
818 bcmspi_card_byterewrite(sd, SPI_FUNC_0, SPID_RESPONSE_DELAY, resp_delay);
819
820 /* Remember function for which to avoid reprogramming resp-delay in next iteration */
821 sd->prev_fun = func;
822
823 return (BCME_OK);
824 }
825
826 #define GSPI_RESYNC_PATTERN 0x0
827
828 /* A resync pattern is a 32bit MOSI line with all zeros. Its a special command in gSPI.
829 * It resets the spi-bkplane logic so that all F1 related ping-pong buffer logic is
830 * synchronised and all queued resuests are cancelled.
831 */
832 static int
bcmspi_resync_f1(sdioh_info_t * sd)833 bcmspi_resync_f1(sdioh_info_t *sd)
834 {
835 uint32 cmd_arg = GSPI_RESYNC_PATTERN, data = 0, datalen = 0;
836
837
838 /* Set up and issue the SPI command. MSByte goes out on bus first. Increase datalen
839 * according to the wordlen mode(16/32bit) the device is in.
840 */
841 ASSERT(sd->wordlen == 4 || sd->wordlen == 2);
842 datalen = ROUNDUP(datalen, sd->wordlen);
843
844 /* Start by copying command in the spi-outbuffer */
845 *(uint32 *)spi_outbuf2 = cmd_arg;
846
847 /* for Write, put the data into the output buffer */
848 *(uint32 *)&spi_outbuf2[CMDLEN] = data;
849
850 /* +4 for cmd, +4 for dstatus */
851 spi_sendrecv(sd, spi_outbuf2, spi_inbuf2, datalen + 8);
852
853 /* Last 4bytes are dstatus. Device is configured to return status bits. */
854 if (sd->wordlen == 4) { /* 32bit spid */
855 sd->card_dstatus = SPISWAP_WD4(*(uint32 *)&spi_inbuf2[datalen + CMDLEN ]);
856 } else if (sd->wordlen == 2) { /* 16bit spid */
857 sd->card_dstatus = SPISWAP_WD2(*(uint32 *)&spi_inbuf2[datalen + CMDLEN ]);
858 } else {
859 sd_err(("%s: Host is %d bit machine, could not read SPI dstatus.\n",
860 __FUNCTION__, 8 * sd->wordlen));
861 return ERROR;
862 }
863
864 if (sd->card_dstatus)
865 sd_trace(("dstatus after resync pattern write = 0x%x\n", sd->card_dstatus));
866
867 return (BCME_OK);
868 }
869
870 uint32 dstatus_count = 0;
871
872 static int
bcmspi_update_stats(sdioh_info_t * sd,uint32 cmd_arg)873 bcmspi_update_stats(sdioh_info_t *sd, uint32 cmd_arg)
874 {
875 uint32 dstatus = sd->card_dstatus;
876 struct spierrstats_t *spierrstats = &sd->spierrstats;
877 int err = SUCCESS;
878
879 sd_trace(("cmd = 0x%x, dstatus = 0x%x\n", cmd_arg, dstatus));
880
881 /* Store dstatus of last few gSPI transactions */
882 spierrstats->dstatus[dstatus_count % NUM_PREV_TRANSACTIONS] = dstatus;
883 spierrstats->spicmd[dstatus_count % NUM_PREV_TRANSACTIONS] = cmd_arg;
884 dstatus_count++;
885
886 if (sd->card_init_done == FALSE)
887 return err;
888
889 if (dstatus & STATUS_DATA_NOT_AVAILABLE) {
890 spierrstats->dna++;
891 sd_trace(("Read data not available on F1 addr = 0x%x\n",
892 GFIELD(cmd_arg, SPI_REG_ADDR)));
893 /* Clear dna bit */
894 bcmspi_card_byterewrite(sd, SPI_FUNC_0, SPID_INTR_REG, DATA_UNAVAILABLE);
895 }
896
897 if (dstatus & STATUS_UNDERFLOW) {
898 spierrstats->rdunderflow++;
899 sd_err(("FIFO underflow happened due to current F2 read command.\n"));
900 }
901
902 if (dstatus & STATUS_OVERFLOW) {
903 spierrstats->wroverflow++;
904 sd_err(("FIFO overflow happened due to current (F1/F2) write command.\n"));
905 bcmspi_card_byterewrite(sd, SPI_FUNC_0, SPID_INTR_REG, F1_OVERFLOW);
906 bcmspi_resync_f1(sd);
907 sd_err(("Recovering from F1 FIFO overflow.\n"));
908 }
909
910 if (dstatus & STATUS_F2_INTR) {
911 spierrstats->f2interrupt++;
912 sd_trace(("Interrupt from F2. SW should clear corresponding IntStatus bits\n"));
913 }
914
915 if (dstatus & STATUS_F3_INTR) {
916 spierrstats->f3interrupt++;
917 sd_err(("Interrupt from F3. SW should clear corresponding IntStatus bits\n"));
918 }
919
920 if (dstatus & STATUS_HOST_CMD_DATA_ERR) {
921 spierrstats->hostcmddataerr++;
922 sd_err(("Error in CMD or Host data, detected by CRC/Checksum (optional)\n"));
923 }
924
925 if (dstatus & STATUS_F2_PKT_AVAILABLE) {
926 spierrstats->f2pktavailable++;
927 sd_trace(("Packet is available/ready in F2 TX FIFO\n"));
928 sd_trace(("Packet length = %d\n", sd->dwordmode ?
929 ((dstatus & STATUS_F2_PKT_LEN_MASK) >> (STATUS_F2_PKT_LEN_SHIFT - 2)) :
930 ((dstatus & STATUS_F2_PKT_LEN_MASK) >> STATUS_F2_PKT_LEN_SHIFT)));
931 }
932
933 if (dstatus & STATUS_F3_PKT_AVAILABLE) {
934 spierrstats->f3pktavailable++;
935 sd_err(("Packet is available/ready in F3 TX FIFO\n"));
936 sd_err(("Packet length = %d\n",
937 (dstatus & STATUS_F3_PKT_LEN_MASK) >> STATUS_F3_PKT_LEN_SHIFT));
938 }
939
940 return err;
941 }
942
943 extern int
sdioh_abort(sdioh_info_t * sd,uint func)944 sdioh_abort(sdioh_info_t *sd, uint func)
945 {
946 return 0;
947 }
948
949 int
sdioh_start(sdioh_info_t * sd,int stage)950 sdioh_start(sdioh_info_t *sd, int stage)
951 {
952 return SUCCESS;
953 }
954
955 int
sdioh_stop(sdioh_info_t * sd)956 sdioh_stop(sdioh_info_t *sd)
957 {
958 return SUCCESS;
959 }
960
961 int
sdioh_waitlockfree(sdioh_info_t * sd)962 sdioh_waitlockfree(sdioh_info_t *sd)
963 {
964 return SUCCESS;
965 }
966
967
968 /*
969 * Private/Static work routines
970 */
971 static int
bcmspi_host_init(sdioh_info_t * sd)972 bcmspi_host_init(sdioh_info_t *sd)
973 {
974 /* Default power on mode */
975 sd->sd_mode = SDIOH_MODE_SPI;
976 sd->polled_mode = TRUE;
977 sd->host_init_done = TRUE;
978 sd->card_init_done = FALSE;
979 sd->adapter_slot = 1;
980
981 return (SUCCESS);
982 }
983
984 static int
get_client_blocksize(sdioh_info_t * sd)985 get_client_blocksize(sdioh_info_t *sd)
986 {
987 uint32 regdata[2];
988 int status;
989
990 /* Find F1/F2/F3 max packet size */
991 if ((status = bcmspi_card_regread(sd, 0, SPID_F1_INFO_REG,
992 8, regdata)) != SUCCESS) {
993 return status;
994 }
995
996 sd_trace(("pkt_size regdata[0] = 0x%x, regdata[1] = 0x%x\n",
997 regdata[0], regdata[1]));
998
999 sd->client_block_size[1] = (regdata[0] & F1_MAX_PKT_SIZE) >> 2;
1000 sd_trace(("Func1 blocksize = %d\n", sd->client_block_size[1]));
1001 ASSERT(sd->client_block_size[1] == BLOCK_SIZE_F1);
1002
1003 sd->client_block_size[2] = ((regdata[0] >> 16) & F2_MAX_PKT_SIZE) >> 2;
1004 sd_trace(("Func2 blocksize = %d\n", sd->client_block_size[2]));
1005 ASSERT(sd->client_block_size[2] == BLOCK_SIZE_F2);
1006
1007 sd->client_block_size[3] = (regdata[1] & F3_MAX_PKT_SIZE) >> 2;
1008 sd_trace(("Func3 blocksize = %d\n", sd->client_block_size[3]));
1009 ASSERT(sd->client_block_size[3] == BLOCK_SIZE_F3);
1010
1011 return 0;
1012 }
1013
1014 static int
bcmspi_client_init(sdioh_info_t * sd)1015 bcmspi_client_init(sdioh_info_t *sd)
1016 {
1017 uint32 status_en_reg = 0;
1018 sd_trace(("%s: Powering up slot %d\n", __FUNCTION__, sd->adapter_slot));
1019
1020 #ifdef HSMODE
1021 if (!spi_start_clock(sd, (uint16)sd_divisor)) {
1022 sd_err(("spi_start_clock failed\n"));
1023 return ERROR;
1024 }
1025 #else
1026 /* Start at ~400KHz clock rate for initialization */
1027 if (!spi_start_clock(sd, 128)) {
1028 sd_err(("spi_start_clock failed\n"));
1029 return ERROR;
1030 }
1031 #endif /* HSMODE */
1032
1033 if (!bcmspi_host_device_init_adapt(sd)) {
1034 sd_err(("bcmspi_host_device_init_adapt failed\n"));
1035 return ERROR;
1036 }
1037
1038 if (!bcmspi_test_card(sd)) {
1039 sd_err(("bcmspi_test_card failed\n"));
1040 return ERROR;
1041 }
1042
1043 sd->num_funcs = SPI_MAX_IOFUNCS;
1044
1045 get_client_blocksize(sd);
1046
1047 /* Apply resync pattern cmd with all zeros to reset spi-bkplane F1 logic */
1048 bcmspi_resync_f1(sd);
1049
1050 sd->dwordmode = FALSE;
1051
1052 bcmspi_card_regread(sd, 0, SPID_STATUS_ENABLE, 1, &status_en_reg);
1053
1054 sd_trace(("%s: Enabling interrupt with dstatus \n", __FUNCTION__));
1055 status_en_reg |= INTR_WITH_STATUS;
1056
1057 if (bcmspi_card_regwrite(sd, SPI_FUNC_0, SPID_STATUS_ENABLE, 1,
1058 status_en_reg & 0xff) != SUCCESS) {
1059 sd_err(("%s: Unable to set response delay for all fun's.\n", __FUNCTION__));
1060 return ERROR;
1061 }
1062
1063 #ifndef HSMODE
1064 /* After configuring for High-Speed mode, set the desired clock rate. */
1065 if (!spi_start_clock(sd, 4)) {
1066 sd_err(("spi_start_clock failed\n"));
1067 return ERROR;
1068 }
1069 #endif /* HSMODE */
1070
1071 /* check to see if the response delay needs to be programmed properly */
1072 {
1073 uint32 f1_respdelay = 0;
1074 bcmspi_card_regread(sd, 0, SPID_RESP_DELAY_F1, 1, &f1_respdelay);
1075 if ((f1_respdelay == 0) || (f1_respdelay == 0xFF)) {
1076 /* older sdiodevice core and has no separte resp delay for each of */
1077 sd_err(("older corerev < 4 so use the same resp delay for all funcs\n"));
1078 sd->resp_delay_new = FALSE;
1079 }
1080 else {
1081 /* older sdiodevice core and has no separte resp delay for each of */
1082 int ret_val;
1083 sd->resp_delay_new = TRUE;
1084 sd_err(("new corerev >= 4 so set the resp delay for each of the funcs\n"));
1085 sd_trace(("resp delay for funcs f0(%d), f1(%d), f2(%d), f3(%d)\n",
1086 GSPI_F0_RESP_DELAY, GSPI_F1_RESP_DELAY,
1087 GSPI_F2_RESP_DELAY, GSPI_F3_RESP_DELAY));
1088 ret_val = bcmspi_card_regwrite(sd, SPI_FUNC_0, SPID_RESP_DELAY_F0, 1,
1089 GSPI_F0_RESP_DELAY);
1090 if (ret_val != SUCCESS) {
1091 sd_err(("%s: Unable to set response delay for F0\n", __FUNCTION__));
1092 return ERROR;
1093 }
1094 ret_val = bcmspi_card_regwrite(sd, SPI_FUNC_0, SPID_RESP_DELAY_F1, 1,
1095 GSPI_F1_RESP_DELAY);
1096 if (ret_val != SUCCESS) {
1097 sd_err(("%s: Unable to set response delay for F1\n", __FUNCTION__));
1098 return ERROR;
1099 }
1100 ret_val = bcmspi_card_regwrite(sd, SPI_FUNC_0, SPID_RESP_DELAY_F2, 1,
1101 GSPI_F2_RESP_DELAY);
1102 if (ret_val != SUCCESS) {
1103 sd_err(("%s: Unable to set response delay for F2\n", __FUNCTION__));
1104 return ERROR;
1105 }
1106 ret_val = bcmspi_card_regwrite(sd, SPI_FUNC_0, SPID_RESP_DELAY_F3, 1,
1107 GSPI_F3_RESP_DELAY);
1108 if (ret_val != SUCCESS) {
1109 sd_err(("%s: Unable to set response delay for F2\n", __FUNCTION__));
1110 return ERROR;
1111 }
1112 }
1113 }
1114
1115
1116 sd->card_init_done = TRUE;
1117
1118 /* get the device rev to program the prop respdelays */
1119
1120 return SUCCESS;
1121 }
1122
1123 static int
bcmspi_set_highspeed_mode(sdioh_info_t * sd,bool hsmode)1124 bcmspi_set_highspeed_mode(sdioh_info_t *sd, bool hsmode)
1125 {
1126 uint32 regdata;
1127 int status;
1128
1129 if ((status = bcmspi_card_regread(sd, 0, SPID_CONFIG,
1130 4, ®data)) != SUCCESS)
1131 return status;
1132
1133 sd_trace(("In %s spih-ctrl = 0x%x \n", __FUNCTION__, regdata));
1134
1135
1136 if (hsmode == TRUE) {
1137 sd_trace(("Attempting to enable High-Speed mode.\n"));
1138
1139 if (regdata & HIGH_SPEED_MODE) {
1140 sd_trace(("Device is already in High-Speed mode.\n"));
1141 return status;
1142 } else {
1143 regdata |= HIGH_SPEED_MODE;
1144 sd_trace(("Writing %08x to device at %08x\n", regdata, SPID_CONFIG));
1145 if ((status = bcmspi_card_regwrite(sd, 0, SPID_CONFIG,
1146 4, regdata)) != SUCCESS) {
1147 return status;
1148 }
1149 }
1150 } else {
1151 sd_trace(("Attempting to disable High-Speed mode.\n"));
1152
1153 if (regdata & HIGH_SPEED_MODE) {
1154 regdata &= ~HIGH_SPEED_MODE;
1155 sd_trace(("Writing %08x to device at %08x\n", regdata, SPID_CONFIG));
1156 if ((status = bcmspi_card_regwrite(sd, 0, SPID_CONFIG,
1157 4, regdata)) != SUCCESS)
1158 return status;
1159 } else {
1160 sd_trace(("Device is already in Low-Speed mode.\n"));
1161 return status;
1162 }
1163 }
1164 spi_controller_highspeed_mode(sd, hsmode);
1165
1166 return TRUE;
1167 }
1168
1169 #define bcmspi_find_curr_mode(sd) { \
1170 sd->wordlen = 2; \
1171 status = bcmspi_card_regread_fixedaddr(sd, 0, SPID_TEST_READ, 4, ®data); \
1172 regdata &= 0xff; \
1173 if ((regdata == 0xad) || (regdata == 0x5b) || \
1174 (regdata == 0x5d) || (regdata == 0x5a)) \
1175 break; \
1176 sd->wordlen = 4; \
1177 status = bcmspi_card_regread_fixedaddr(sd, 0, SPID_TEST_READ, 4, ®data); \
1178 regdata &= 0xff; \
1179 if ((regdata == 0xad) || (regdata == 0x5b) || \
1180 (regdata == 0x5d) || (regdata == 0x5a)) \
1181 break; \
1182 sd_trace(("Silicon testability issue: regdata = 0x%x." \
1183 " Expected 0xad, 0x5a, 0x5b or 0x5d.\n", regdata)); \
1184 OSL_DELAY(100000); \
1185 }
1186
1187 #define INIT_ADAPT_LOOP 100
1188
1189 /* Adapt clock-phase-speed-bitwidth between host and device */
1190 static bool
bcmspi_host_device_init_adapt(sdioh_info_t * sd)1191 bcmspi_host_device_init_adapt(sdioh_info_t *sd)
1192 {
1193 uint32 wrregdata, regdata = 0;
1194 int status;
1195 int i;
1196
1197 /* Due to a silicon testability issue, the first command from the Host
1198 * to the device will get corrupted (first bit will be lost). So the
1199 * Host should poll the device with a safe read request. ie: The Host
1200 * should try to read F0 addr 0x14 using the Fixed address mode
1201 * (This will prevent a unintended write command to be detected by device)
1202 */
1203 for (i = 0; i < INIT_ADAPT_LOOP; i++) {
1204 /* If device was not power-cycled it will stay in 32bit mode with
1205 * response-delay-all bit set. Alternate the iteration so that
1206 * read either with or without response-delay for F0 to succeed.
1207 */
1208 bcmspi_find_curr_mode(sd);
1209 sd->resp_delay_all = (i & 0x1) ? TRUE : FALSE;
1210
1211 bcmspi_find_curr_mode(sd);
1212 sd->dwordmode = TRUE;
1213
1214 bcmspi_find_curr_mode(sd);
1215 sd->dwordmode = FALSE;
1216 }
1217
1218 /* Bail out, device not detected */
1219 if (i == INIT_ADAPT_LOOP)
1220 return FALSE;
1221
1222 /* Softreset the spid logic */
1223 if ((sd->dwordmode) || (sd->wordlen == 4)) {
1224 bcmspi_card_regwrite(sd, 0, SPID_RESET_BP, 1, RESET_ON_WLAN_BP_RESET|RESET_SPI);
1225 bcmspi_card_regread(sd, 0, SPID_RESET_BP, 1, ®data);
1226 sd_trace(("reset reg read = 0x%x\n", regdata));
1227 sd_trace(("dwordmode = %d, wordlen = %d, resp_delay_all = %d\n", sd->dwordmode,
1228 sd->wordlen, sd->resp_delay_all));
1229 /* Restore default state after softreset */
1230 sd->wordlen = 2;
1231 sd->dwordmode = FALSE;
1232 }
1233
1234 if (sd->wordlen == 4) {
1235 if ((status = bcmspi_card_regread(sd, 0, SPID_TEST_READ, 4, ®data)) !=
1236 SUCCESS)
1237 return FALSE;
1238 if (regdata == TEST_RO_DATA_32BIT_LE) {
1239 sd_trace(("Spid is already in 32bit LE mode. Value read = 0x%x\n",
1240 regdata));
1241 sd_trace(("Spid power was left on.\n"));
1242 } else {
1243 sd_err(("Spid power was left on but signature read failed."
1244 " Value read = 0x%x\n", regdata));
1245 return FALSE;
1246 }
1247 } else {
1248 sd->wordlen = 2;
1249
1250 #define CTRL_REG_DEFAULT 0x00010430 /* according to the host m/c */
1251
1252 wrregdata = (CTRL_REG_DEFAULT);
1253
1254 if ((status = bcmspi_card_regread(sd, 0, SPID_TEST_READ, 4, ®data)) != SUCCESS)
1255 return FALSE;
1256 sd_trace(("(we are still in 16bit mode) 32bit READ LE regdata = 0x%x\n", regdata));
1257
1258 #ifndef HSMODE
1259 wrregdata |= (CLOCK_PHASE | CLOCK_POLARITY);
1260 wrregdata &= ~HIGH_SPEED_MODE;
1261 bcmspi_card_regwrite(sd, 0, SPID_CONFIG, 4, wrregdata);
1262 #endif /* HSMODE */
1263
1264 for (i = 0; i < INIT_ADAPT_LOOP; i++) {
1265 if ((regdata == 0xfdda7d5b) || (regdata == 0xfdda7d5a)) {
1266 sd_trace(("0xfeedbead was leftshifted by 1-bit.\n"));
1267 if ((status = bcmspi_card_regread(sd, 0, SPID_TEST_READ, 4,
1268 ®data)) != SUCCESS)
1269 return FALSE;
1270 }
1271 OSL_DELAY(1000);
1272 }
1273
1274 #if defined(CHANGE_SPI_INTR_POLARITY_ACTIVE_HIGH)
1275 /* Change to host controller intr-polarity of active-high */
1276 wrregdata |= INTR_POLARITY;
1277 #else
1278 /* Change to host controller intr-polarity of active-low */
1279 wrregdata &= ~INTR_POLARITY;
1280 #endif /* CHANGE_SPI_INTR_POLARITY_ACTIVE_HIGH */
1281
1282 sd_trace(("(we are still in 16bit mode) 32bit Write LE reg-ctrl-data = 0x%x\n",
1283 wrregdata));
1284 /* Change to 32bit mode */
1285 wrregdata |= WORD_LENGTH_32;
1286 bcmspi_card_regwrite(sd, 0, SPID_CONFIG, 4, wrregdata);
1287
1288 /* Change command/data packaging in 32bit LE mode */
1289 sd->wordlen = 4;
1290
1291 if ((status = bcmspi_card_regread(sd, 0, SPID_TEST_READ, 4, ®data)) != SUCCESS)
1292 return FALSE;
1293
1294 if (regdata == TEST_RO_DATA_32BIT_LE) {
1295 sd_trace(("Read spid passed. Value read = 0x%x\n", regdata));
1296 sd_trace(("Spid had power-on cycle OR spi was soft-resetted \n"));
1297 } else {
1298 sd_err(("Stale spid reg values read as it was kept powered. Value read ="
1299 "0x%x\n", regdata));
1300 return FALSE;
1301 }
1302 }
1303
1304
1305 return TRUE;
1306 }
1307
1308 static bool
bcmspi_test_card(sdioh_info_t * sd)1309 bcmspi_test_card(sdioh_info_t *sd)
1310 {
1311 uint32 regdata;
1312 int status;
1313
1314 if ((status = bcmspi_card_regread(sd, 0, SPID_TEST_READ, 4, ®data)) != SUCCESS)
1315 return FALSE;
1316
1317 if (regdata == (TEST_RO_DATA_32BIT_LE))
1318 sd_trace(("32bit LE regdata = 0x%x\n", regdata));
1319 else {
1320 sd_trace(("Incorrect 32bit LE regdata = 0x%x\n", regdata));
1321 return FALSE;
1322 }
1323
1324
1325 #define RW_PATTERN1 0xA0A1A2A3
1326 #define RW_PATTERN2 0x4B5B6B7B
1327
1328 regdata = RW_PATTERN1;
1329 if ((status = bcmspi_card_regwrite(sd, 0, SPID_TEST_RW, 4, regdata)) != SUCCESS)
1330 return FALSE;
1331 regdata = 0;
1332 if ((status = bcmspi_card_regread(sd, 0, SPID_TEST_RW, 4, ®data)) != SUCCESS)
1333 return FALSE;
1334 if (regdata != RW_PATTERN1) {
1335 sd_err(("Write-Read spid failed. Value wrote = 0x%x, Value read = 0x%x\n",
1336 RW_PATTERN1, regdata));
1337 return FALSE;
1338 } else
1339 sd_trace(("R/W spid passed. Value read = 0x%x\n", regdata));
1340
1341 regdata = RW_PATTERN2;
1342 if ((status = bcmspi_card_regwrite(sd, 0, SPID_TEST_RW, 4, regdata)) != SUCCESS)
1343 return FALSE;
1344 regdata = 0;
1345 if ((status = bcmspi_card_regread(sd, 0, SPID_TEST_RW, 4, ®data)) != SUCCESS)
1346 return FALSE;
1347 if (regdata != RW_PATTERN2) {
1348 sd_err(("Write-Read spid failed. Value wrote = 0x%x, Value read = 0x%x\n",
1349 RW_PATTERN2, regdata));
1350 return FALSE;
1351 } else
1352 sd_trace(("R/W spid passed. Value read = 0x%x\n", regdata));
1353
1354 return TRUE;
1355 }
1356
1357 static int
bcmspi_driver_init(sdioh_info_t * sd)1358 bcmspi_driver_init(sdioh_info_t *sd)
1359 {
1360 sd_trace(("%s\n", __FUNCTION__));
1361 if ((bcmspi_host_init(sd)) != SUCCESS) {
1362 return ERROR;
1363 }
1364
1365 if (bcmspi_client_init(sd) != SUCCESS) {
1366 return ERROR;
1367 }
1368
1369 return SUCCESS;
1370 }
1371
1372 /* Read device reg */
1373 static int
bcmspi_card_regread(sdioh_info_t * sd,int func,uint32 regaddr,int regsize,uint32 * data)1374 bcmspi_card_regread(sdioh_info_t *sd, int func, uint32 regaddr, int regsize, uint32 *data)
1375 {
1376 int status;
1377 uint32 cmd_arg, dstatus;
1378
1379 ASSERT(regsize);
1380
1381 if (func == 2)
1382 sd_trace(("Reg access on F2 will generate error indication in dstatus bits.\n"));
1383
1384 cmd_arg = 0;
1385 cmd_arg = SFIELD(cmd_arg, SPI_RW_FLAG, 0);
1386 cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 1); /* Incremental access */
1387 cmd_arg = SFIELD(cmd_arg, SPI_FUNCTION, func);
1388 cmd_arg = SFIELD(cmd_arg, SPI_REG_ADDR, regaddr);
1389 cmd_arg = SFIELD(cmd_arg, SPI_LEN, regsize == BLOCK_SIZE_F2 ? 0 : regsize);
1390
1391 sd_trace(("%s: RD cmd_arg=0x%x func=%d regaddr=0x%x regsize=%d\n",
1392 __FUNCTION__, cmd_arg, func, regaddr, regsize));
1393
1394 if ((status = bcmspi_cmd_issue(sd, sd->sd_use_dma, cmd_arg, data, regsize)) != SUCCESS)
1395 return status;
1396
1397 bcmspi_cmd_getdstatus(sd, &dstatus);
1398 if (dstatus)
1399 sd_trace(("dstatus =0x%x\n", dstatus));
1400
1401 return SUCCESS;
1402 }
1403
1404 static int
bcmspi_card_regread_fixedaddr(sdioh_info_t * sd,int func,uint32 regaddr,int regsize,uint32 * data)1405 bcmspi_card_regread_fixedaddr(sdioh_info_t *sd, int func, uint32 regaddr, int regsize, uint32 *data)
1406 {
1407 int status;
1408 uint32 cmd_arg;
1409 uint32 dstatus;
1410
1411 ASSERT(regsize);
1412
1413 if (func == 2)
1414 sd_trace(("Reg access on F2 will generate error indication in dstatus bits.\n"));
1415
1416 cmd_arg = 0;
1417 cmd_arg = SFIELD(cmd_arg, SPI_RW_FLAG, 0);
1418 cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 0); /* Fixed access */
1419 cmd_arg = SFIELD(cmd_arg, SPI_FUNCTION, func);
1420 cmd_arg = SFIELD(cmd_arg, SPI_REG_ADDR, regaddr);
1421 cmd_arg = SFIELD(cmd_arg, SPI_LEN, regsize);
1422
1423 sd_trace(("%s: RD cmd_arg=0x%x func=%d regaddr=0x%x regsize=%d\n",
1424 __FUNCTION__, cmd_arg, func, regaddr, regsize));
1425
1426 if ((status = bcmspi_cmd_issue(sd, sd->sd_use_dma, cmd_arg, data, regsize)) != SUCCESS)
1427 return status;
1428
1429 sd_trace(("%s: RD result=0x%x\n", __FUNCTION__, *data));
1430
1431 bcmspi_cmd_getdstatus(sd, &dstatus);
1432 sd_trace(("dstatus =0x%x\n", dstatus));
1433 return SUCCESS;
1434 }
1435
1436 /* write a device register */
1437 static int
bcmspi_card_regwrite(sdioh_info_t * sd,int func,uint32 regaddr,int regsize,uint32 data)1438 bcmspi_card_regwrite(sdioh_info_t *sd, int func, uint32 regaddr, int regsize, uint32 data)
1439 {
1440 int status;
1441 uint32 cmd_arg, dstatus;
1442
1443 ASSERT(regsize);
1444
1445 cmd_arg = 0;
1446
1447 cmd_arg = SFIELD(cmd_arg, SPI_RW_FLAG, 1);
1448 cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 1); /* Incremental access */
1449 cmd_arg = SFIELD(cmd_arg, SPI_FUNCTION, func);
1450 cmd_arg = SFIELD(cmd_arg, SPI_REG_ADDR, regaddr);
1451 cmd_arg = SFIELD(cmd_arg, SPI_LEN, regsize == BLOCK_SIZE_F2 ? 0 : regsize);
1452
1453 sd_trace(("%s: WR cmd_arg=0x%x func=%d regaddr=0x%x regsize=%d data=0x%x\n",
1454 __FUNCTION__, cmd_arg, func, regaddr, regsize, data));
1455
1456 if ((status = bcmspi_cmd_issue(sd, sd->sd_use_dma, cmd_arg, &data, regsize)) != SUCCESS)
1457 return status;
1458
1459 bcmspi_cmd_getdstatus(sd, &dstatus);
1460 if (dstatus)
1461 sd_trace(("dstatus=0x%x\n", dstatus));
1462
1463 return SUCCESS;
1464 }
1465
1466 /* write a device register - 1 byte */
1467 static int
bcmspi_card_bytewrite(sdioh_info_t * sd,int func,uint32 regaddr,uint8 * byte)1468 bcmspi_card_bytewrite(sdioh_info_t *sd, int func, uint32 regaddr, uint8 *byte)
1469 {
1470 int status;
1471 uint32 cmd_arg;
1472 uint32 dstatus;
1473 uint32 data = (uint32)(*byte);
1474
1475 cmd_arg = 0;
1476 cmd_arg = SFIELD(cmd_arg, SPI_FUNCTION, func);
1477 cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 1); /* Incremental access */
1478 cmd_arg = SFIELD(cmd_arg, SPI_REG_ADDR, regaddr);
1479 cmd_arg = SFIELD(cmd_arg, SPI_RW_FLAG, 1);
1480 cmd_arg = SFIELD(cmd_arg, SPI_LEN, 1);
1481
1482 sd_trace(("%s: WR cmd_arg=0x%x func=%d regaddr=0x%x data=0x%x\n",
1483 __FUNCTION__, cmd_arg, func, regaddr, data));
1484
1485 if ((status = bcmspi_cmd_issue(sd, sd->sd_use_dma, cmd_arg, &data, 1)) != SUCCESS)
1486 return status;
1487
1488 bcmspi_cmd_getdstatus(sd, &dstatus);
1489 if (dstatus)
1490 sd_trace(("dstatus =0x%x\n", dstatus));
1491
1492 return SUCCESS;
1493 }
1494
1495 void
bcmspi_cmd_getdstatus(sdioh_info_t * sd,uint32 * dstatus_buffer)1496 bcmspi_cmd_getdstatus(sdioh_info_t *sd, uint32 *dstatus_buffer)
1497 {
1498 *dstatus_buffer = sd->card_dstatus;
1499 }
1500
1501 /* 'data' is of type uint32 whereas other buffers are of type uint8 */
1502 static int
bcmspi_cmd_issue(sdioh_info_t * sd,bool use_dma,uint32 cmd_arg,uint32 * data,uint32 datalen)1503 bcmspi_cmd_issue(sdioh_info_t *sd, bool use_dma, uint32 cmd_arg,
1504 uint32 *data, uint32 datalen)
1505 {
1506 uint32 i, j;
1507 uint8 resp_delay = 0;
1508 int err = SUCCESS;
1509 uint32 hostlen;
1510 uint32 spilen = 0;
1511 uint32 dstatus_idx = 0;
1512 uint16 templen, buslen, len, *ptr = NULL;
1513
1514 sd_trace(("spi cmd = 0x%x\n", cmd_arg));
1515
1516 /* Set up and issue the SPI command. MSByte goes out on bus first. Increase datalen
1517 * according to the wordlen mode(16/32bit) the device is in.
1518 */
1519 if (sd->wordlen == 4) { /* 32bit spid */
1520 *(uint32 *)spi_outbuf = SPISWAP_WD4(cmd_arg);
1521 if (datalen & 0x3)
1522 datalen += (4 - (datalen & 0x3));
1523 } else if (sd->wordlen == 2) { /* 16bit spid */
1524 *(uint32 *)spi_outbuf = SPISWAP_WD2(cmd_arg);
1525 if (datalen & 0x1)
1526 datalen++;
1527 if (datalen < 4)
1528 datalen = ROUNDUP(datalen, 4);
1529 } else {
1530 sd_err(("Host is %d bit spid, could not create SPI command.\n",
1531 8 * sd->wordlen));
1532 return ERROR;
1533 }
1534
1535 /* for Write, put the data into the output buffer */
1536 if (GFIELD(cmd_arg, SPI_RW_FLAG) == 1) {
1537 /* We send len field of hw-header always a mod16 size, both from host and dongle */
1538 if (datalen != 0) {
1539 for (i = 0; i < datalen/4; i++) {
1540 if (sd->wordlen == 4) { /* 32bit spid */
1541 *(uint32 *)&spi_outbuf[i * 4 + CMDLEN] =
1542 SPISWAP_WD4(data[i]);
1543 } else if (sd->wordlen == 2) { /* 16bit spid */
1544 *(uint32 *)&spi_outbuf[i * 4 + CMDLEN] =
1545 SPISWAP_WD2(data[i]);
1546 }
1547 }
1548 }
1549 }
1550
1551 /* Append resp-delay number of bytes and clock them out for F0/1/2 reads. */
1552 if ((GFIELD(cmd_arg, SPI_RW_FLAG) == 0)) {
1553 int func = GFIELD(cmd_arg, SPI_FUNCTION);
1554 switch (func) {
1555 case 0:
1556 if (sd->resp_delay_new)
1557 resp_delay = GSPI_F0_RESP_DELAY;
1558 else
1559 resp_delay = sd->resp_delay_all ? F0_RESPONSE_DELAY : 0;
1560 break;
1561 case 1:
1562 if (sd->resp_delay_new)
1563 resp_delay = GSPI_F1_RESP_DELAY;
1564 else
1565 resp_delay = F1_RESPONSE_DELAY;
1566 break;
1567 case 2:
1568 if (sd->resp_delay_new)
1569 resp_delay = GSPI_F2_RESP_DELAY;
1570 else
1571 resp_delay = sd->resp_delay_all ? F2_RESPONSE_DELAY : 0;
1572 break;
1573 default:
1574 ASSERT(0);
1575 break;
1576 }
1577 /* Program response delay */
1578 if (sd->resp_delay_new == FALSE)
1579 bcmspi_prog_resp_delay(sd, func, resp_delay);
1580 }
1581
1582 /* +4 for cmd and +4 for dstatus */
1583 hostlen = datalen + 8 + resp_delay;
1584 hostlen += dstatus_idx;
1585 hostlen += (4 - (hostlen & 0x3));
1586 spi_sendrecv(sd, spi_outbuf, spi_inbuf, hostlen);
1587
1588 /* for Read, get the data into the input buffer */
1589 if (datalen != 0) {
1590 if (GFIELD(cmd_arg, SPI_RW_FLAG) == 0) { /* if read cmd */
1591 for (j = 0; j < datalen/4; j++) {
1592 if (sd->wordlen == 4) { /* 32bit spid */
1593 data[j] = SPISWAP_WD4(*(uint32 *)&spi_inbuf[j * 4 +
1594 CMDLEN + resp_delay]);
1595 } else if (sd->wordlen == 2) { /* 16bit spid */
1596 data[j] = SPISWAP_WD2(*(uint32 *)&spi_inbuf[j * 4 +
1597 CMDLEN + resp_delay]);
1598 }
1599 }
1600 }
1601 }
1602
1603 dstatus_idx += (datalen + CMDLEN + resp_delay);
1604 /* Last 4bytes are dstatus. Device is configured to return status bits. */
1605 if (sd->wordlen == 4) { /* 32bit spid */
1606 sd->card_dstatus = SPISWAP_WD4(*(uint32 *)&spi_inbuf[dstatus_idx]);
1607 } else if (sd->wordlen == 2) { /* 16bit spid */
1608 sd->card_dstatus = SPISWAP_WD2(*(uint32 *)&spi_inbuf[dstatus_idx]);
1609 } else {
1610 sd_err(("Host is %d bit machine, could not read SPI dstatus.\n",
1611 8 * sd->wordlen));
1612 return ERROR;
1613 }
1614 if (sd->card_dstatus == 0xffffffff) {
1615 sd_err(("looks like not a GSPI device or device is not powered.\n"));
1616 }
1617
1618 err = bcmspi_update_stats(sd, cmd_arg);
1619
1620 return err;
1621 }
1622
1623 static int
bcmspi_card_buf(sdioh_info_t * sd,int rw,int func,bool fifo,uint32 addr,int nbytes,uint32 * data)1624 bcmspi_card_buf(sdioh_info_t *sd, int rw, int func, bool fifo,
1625 uint32 addr, int nbytes, uint32 *data)
1626 {
1627 int status;
1628 uint32 cmd_arg;
1629 bool write = rw == SDIOH_READ ? 0 : 1;
1630 uint retries = 0;
1631
1632 bool enable;
1633 uint32 spilen;
1634
1635 cmd_arg = 0;
1636
1637 ASSERT(nbytes);
1638 ASSERT(nbytes <= sd->client_block_size[func]);
1639
1640 if (write) {
1641 sd->t_cnt++;
1642 } else {
1643 sd->r_cnt++;
1644 }
1645
1646 if (func == 2) {
1647 /* Frame len check limited by gSPI. */
1648 if ((nbytes > 2000) && write) {
1649 sd_trace((">2KB write: F2 wr of %d bytes\n", nbytes));
1650 }
1651 /* ASSERT(nbytes <= 2048); Fix bigger len gspi issue and uncomment. */
1652 /* If F2 fifo on device is not ready to receive data, don't do F2 transfer */
1653 if (write) {
1654 uint32 dstatus;
1655 /* check F2 ready with cached one */
1656 bcmspi_cmd_getdstatus(sd, &dstatus);
1657 if ((dstatus & STATUS_F2_RX_READY) == 0) {
1658 retries = WAIT_F2RXFIFORDY;
1659 enable = 0;
1660 while (retries-- && !enable) {
1661 OSL_DELAY(WAIT_F2RXFIFORDY_DELAY * 1000);
1662 bcmspi_card_regread(sd, SPI_FUNC_0, SPID_STATUS_REG, 4,
1663 &dstatus);
1664 if (dstatus & STATUS_F2_RX_READY)
1665 enable = TRUE;
1666 }
1667 if (!enable) {
1668 struct spierrstats_t *spierrstats = &sd->spierrstats;
1669 spierrstats->f2rxnotready++;
1670 sd_err(("F2 FIFO is not ready to receive data.\n"));
1671 return ERROR;
1672 }
1673 sd_trace(("No of retries on F2 ready %d\n",
1674 (WAIT_F2RXFIFORDY - retries)));
1675 }
1676 }
1677 }
1678
1679 /* F2 transfers happen on 0 addr */
1680 addr = (func == 2) ? 0 : addr;
1681
1682 /* In pio mode buffer is read using fixed address fifo in func 1 */
1683 if ((func == 1) && (fifo))
1684 cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 0);
1685 else
1686 cmd_arg = SFIELD(cmd_arg, SPI_ACCESS, 1);
1687
1688 cmd_arg = SFIELD(cmd_arg, SPI_FUNCTION, func);
1689 cmd_arg = SFIELD(cmd_arg, SPI_REG_ADDR, addr);
1690 cmd_arg = SFIELD(cmd_arg, SPI_RW_FLAG, write);
1691 spilen = sd->data_xfer_count = MIN(sd->client_block_size[func], nbytes);
1692 if ((sd->dwordmode == TRUE) && (GFIELD(cmd_arg, SPI_FUNCTION) == SPI_FUNC_2)) {
1693 /* convert len to mod4 size */
1694 spilen = spilen + ((spilen & 0x3) ? (4 - (spilen & 0x3)): 0);
1695 cmd_arg = SFIELD(cmd_arg, SPI_LEN, (spilen >> 2));
1696 } else
1697 cmd_arg = SFIELD(cmd_arg, SPI_LEN, spilen);
1698
1699 if ((func == 2) && (fifo == 1)) {
1700 sd_data(("%s: %s func %d, %s, addr 0x%x, len %d bytes, r_cnt %d t_cnt %d\n",
1701 __FUNCTION__, write ? "Wr" : "Rd", func, "INCR",
1702 addr, nbytes, sd->r_cnt, sd->t_cnt));
1703 }
1704
1705 sd_trace(("%s cmd_arg = 0x%x\n", __FUNCTION__, cmd_arg));
1706 sd_data(("%s: %s func %d, %s, addr 0x%x, len %d bytes, r_cnt %d t_cnt %d\n",
1707 __FUNCTION__, write ? "Wd" : "Rd", func, "INCR",
1708 addr, nbytes, sd->r_cnt, sd->t_cnt));
1709
1710
1711 if ((status = bcmspi_cmd_issue(sd, sd->sd_use_dma, cmd_arg, data, nbytes)) != SUCCESS) {
1712 sd_err(("%s: cmd_issue failed for %s\n", __FUNCTION__,
1713 (write ? "write" : "read")));
1714 return status;
1715 }
1716
1717 /* gSPI expects that hw-header-len is equal to spi-command-len */
1718 if ((func == 2) && (rw == SDIOH_WRITE) && (sd->dwordmode == FALSE)) {
1719 ASSERT((uint16)sd->data_xfer_count == (uint16)(*data & 0xffff));
1720 ASSERT((uint16)sd->data_xfer_count == (uint16)(~((*data & 0xffff0000) >> 16)));
1721 }
1722
1723 if ((nbytes > 2000) && !write) {
1724 sd_trace((">2KB read: F2 rd of %d bytes\n", nbytes));
1725 }
1726
1727 return SUCCESS;
1728 }
1729
1730 /* Reset and re-initialize the device */
1731 int
sdioh_sdio_reset(sdioh_info_t * si)1732 sdioh_sdio_reset(sdioh_info_t *si)
1733 {
1734 si->card_init_done = FALSE;
1735 return bcmspi_client_init(si);
1736 }
1737
1738 SDIOH_API_RC
sdioh_gpioouten(sdioh_info_t * sd,uint32 gpio)1739 sdioh_gpioouten(sdioh_info_t *sd, uint32 gpio)
1740 {
1741 return SDIOH_API_RC_FAIL;
1742 }
1743
1744 SDIOH_API_RC
sdioh_gpioout(sdioh_info_t * sd,uint32 gpio,bool enab)1745 sdioh_gpioout(sdioh_info_t *sd, uint32 gpio, bool enab)
1746 {
1747 return SDIOH_API_RC_FAIL;
1748 }
1749
1750 bool
sdioh_gpioin(sdioh_info_t * sd,uint32 gpio)1751 sdioh_gpioin(sdioh_info_t *sd, uint32 gpio)
1752 {
1753 return FALSE;
1754 }
1755
1756 SDIOH_API_RC
sdioh_gpio_init(sdioh_info_t * sd)1757 sdioh_gpio_init(sdioh_info_t *sd)
1758 {
1759 return SDIOH_API_RC_FAIL;
1760 }
1761