1 /* 2 * Broadcom HND chip & on-chip-interconnect-related definitions. 3 * 4 * Copyright (C) 1999-2017, Broadcom Corporation 5 * 6 * Unless you and Broadcom execute a separate written software license 7 * agreement governing use of this software, this software is licensed to you 8 * under the terms of the GNU General Public License version 2 (the "GPL"), 9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 10 * following added to such license: 11 * 12 * As a special exception, the copyright holders of this software give you 13 * permission to link this software with independent modules, and to copy and 14 * distribute the resulting executable under terms of your choice, provided that 15 * you also meet, for each linked independent module, the terms and conditions of 16 * the license of that module. An independent module is a module which is not 17 * derived from this software. The special exception does not apply to any 18 * modifications of the software. 19 * 20 * Notwithstanding the above, under no circumstances may you combine this 21 * software in any way with any other Broadcom software provided under a license 22 * other than the GPL, without Broadcom's express prior written consent. 23 * 24 * 25 * <<Broadcom-WL-IPTag/Open:>> 26 * 27 * $Id: hndsoc.h 613129 2016-01-17 09:25:52Z $ 28 */ 29 30 #ifndef _HNDSOC_H 31 #define _HNDSOC_H 32 33 /* Include the soci specific files */ 34 #include <sbconfig.h> 35 #include <aidmp.h> 36 37 /* 38 * SOC Interconnect Address Map. 39 * All regions may not exist on all chips. 40 */ 41 #define SI_SDRAM_BASE 0x00000000 /* Physical SDRAM */ 42 #define SI_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */ 43 #define SI_PCI_MEM_SZ (64 * 1024 * 1024) 44 #define SI_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */ 45 #define SI_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */ 46 #define SI_SDRAM_R2 0x80000000 /* Region 2 for sdram (512 MB) */ 47 48 #define SI_ENUM_BASE 0x18000000 /* Enumeration space base */ 49 #define SI_WRAP_BASE 0x18100000 /* Wrapper space base */ 50 #define SI_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */ 51 52 #ifndef SI_MAXCORES 53 #define SI_MAXCORES 32 /* NorthStar has more cores */ 54 #endif /* SI_MAXCORES */ 55 56 #define SI_MAXBR 4 /* Max bridges (this is arbitrary, for software 57 * convenience and could be changed if we 58 * make any larger chips 59 */ 60 61 #define SI_FASTRAM 0x19000000 /* On-chip RAM on chips that also have DDR */ 62 #define SI_FASTRAM_SWAPPED 0x19800000 63 64 #define SI_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */ 65 #define SI_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */ 66 #define SI_ARMCM3_ROM 0x1e000000 /* ARM Cortex-M3 ROM */ 67 #define SI_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */ 68 #define SI_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */ 69 #define SI_FLASH_WINDOW 0x01000000 /* Flash XIP Window */ 70 71 #define SI_NS_NANDFLASH 0x1c000000 /* NorthStar NAND flash base */ 72 #define SI_NS_NORFLASH 0x1e000000 /* NorthStar NOR flash base */ 73 #define SI_NS_ROM 0xfffd0000 /* NorthStar ROM */ 74 #define SI_NS_FLASH_WINDOW 0x02000000 /* Flash XIP Window */ 75 76 #define SI_ARM7S_ROM 0x20000000 /* ARM7TDMI-S ROM */ 77 #define SI_ARMCR4_ROM 0x000f0000 /* ARM Cortex-R4 ROM */ 78 #define SI_ARMCM3_SRAM2 0x60000000 /* ARM Cortex-M3 SRAM Region 2 */ 79 #define SI_ARM7S_SRAM2 0x80000000 /* ARM7TDMI-S SRAM Region 2 */ 80 #define SI_ARMCA7_ROM 0x00000000 /* ARM Cortex-A7 ROM */ 81 #define SI_ARMCA7_RAM 0x00200000 /* ARM Cortex-A7 RAM */ 82 #define SI_ARM_FLASH1 0xffff0000 /* ARM Flash Region 1 */ 83 #define SI_ARM_FLASH1_SZ 0x00010000 /* ARM Size of Flash Region 1 */ 84 85 #define SI_SFLASH 0x14000000 86 #define SI_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */ 87 #define SI_PCI_DMA2 0x80000000 /* Client Mode sb2pcitranslation2 (1 GB) */ 88 #define SI_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */ 89 #define SI_PCIE_DMA_L32 0x00000000 /* PCIE Client Mode sb2pcitranslation2 90 * (2 ZettaBytes), low 32 bits 91 */ 92 #define SI_PCIE_DMA_H32 0x80000000 /* PCIE Client Mode sb2pcitranslation2 93 * (2 ZettaBytes), high 32 bits 94 */ 95 96 #define SI_BCM53573_NANDFLASH 0x30000000 /* 53573 NAND flash base */ 97 #define SI_BCM53573_NORFLASH 0x1c000000 /* 53573 NOR flash base */ 98 #define SI_BCM53573_FLASH2_SZ 0x04000000 /* 53573 NOR flash2 size */ 99 100 #define SI_BCM53573_NORFLASH_WINDOW 0x01000000 /* only support 16M direct access for 101 * 3-byte address modes in spi flash 102 */ 103 #define SI_BCM53573_BOOTDEV_MASK 0x3 104 #define SI_BCM53573_BOOTDEV_NOR 0x0 105 106 #define SI_BCM53573_NAND_PRE_MASK 0x100 /* 53573 NAND present mask */ 107 108 #define SI_BCM53573_DDRTYPE_MASK 0x10 109 #define SI_BCM53573_DDRTYPE_DDR3 0x10 110 111 #define SI_BCM47189_RGMII_VDD_MASK 0x3 112 #define SI_BCM47189_RGMII_VDD_SHIFT 21 113 #define SI_BCM47189_RGMII_VDD_3_3V 0 114 #define SI_BCM47189_RGMII_VDD_2_5V 1 115 #define SI_BCM47189_RGMII_VDD_1_5V 1 116 117 #define SI_BCM53573_LOCKED_CPUPLL 0x1 118 119 /* APB bridge code */ 120 #define APB_BRIDGE_ID 0x135 /* APB Bridge 0, 1, etc. */ 121 122 /* core codes */ 123 #define NODEV_CORE_ID 0x700 /* Invalid coreid */ 124 #define CC_CORE_ID 0x800 /* chipcommon core */ 125 #define ILINE20_CORE_ID 0x801 /* iline20 core */ 126 #define SRAM_CORE_ID 0x802 /* sram core */ 127 #define SDRAM_CORE_ID 0x803 /* sdram core */ 128 #define PCI_CORE_ID 0x804 /* pci core */ 129 #define MIPS_CORE_ID 0x805 /* mips core */ 130 #define ENET_CORE_ID 0x806 /* enet mac core */ 131 #define CODEC_CORE_ID 0x807 /* v90 codec core */ 132 #define USB_CORE_ID 0x808 /* usb 1.1 host/device core */ 133 #define ADSL_CORE_ID 0x809 /* ADSL core */ 134 #define ILINE100_CORE_ID 0x80a /* iline100 core */ 135 #define IPSEC_CORE_ID 0x80b /* ipsec core */ 136 #define UTOPIA_CORE_ID 0x80c /* utopia core */ 137 #define PCMCIA_CORE_ID 0x80d /* pcmcia core */ 138 #define SOCRAM_CORE_ID 0x80e /* internal memory core */ 139 #define MEMC_CORE_ID 0x80f /* memc sdram core */ 140 #define OFDM_CORE_ID 0x810 /* OFDM phy core */ 141 #define EXTIF_CORE_ID 0x811 /* external interface core */ 142 #define D11_CORE_ID 0x812 /* 802.11 MAC core */ 143 #define APHY_CORE_ID 0x813 /* 802.11a phy core */ 144 #define BPHY_CORE_ID 0x814 /* 802.11b phy core */ 145 #define GPHY_CORE_ID 0x815 /* 802.11g phy core */ 146 #define MIPS33_CORE_ID 0x816 /* mips3302 core */ 147 #define USB11H_CORE_ID 0x817 /* usb 1.1 host core */ 148 #define USB11D_CORE_ID 0x818 /* usb 1.1 device core */ 149 #define USB20H_CORE_ID 0x819 /* usb 2.0 host core */ 150 #define USB20D_CORE_ID 0x81a /* usb 2.0 device core */ 151 #define SDIOH_CORE_ID 0x81b /* sdio host core */ 152 #define ROBO_CORE_ID 0x81c /* roboswitch core */ 153 #define ATA100_CORE_ID 0x81d /* parallel ATA core */ 154 #define SATAXOR_CORE_ID 0x81e /* serial ATA & XOR DMA core */ 155 #define GIGETH_CORE_ID 0x81f /* gigabit ethernet core */ 156 #define PCIE_CORE_ID 0x820 /* pci express core */ 157 #define NPHY_CORE_ID 0x821 /* 802.11n 2x2 phy core */ 158 #define SRAMC_CORE_ID 0x822 /* SRAM controller core */ 159 #define MINIMAC_CORE_ID 0x823 /* MINI MAC/phy core */ 160 #define ARM11_CORE_ID 0x824 /* ARM 1176 core */ 161 #define ARM7S_CORE_ID 0x825 /* ARM7tdmi-s core */ 162 #define LPPHY_CORE_ID 0x826 /* 802.11a/b/g phy core */ 163 #define PMU_CORE_ID 0x827 /* PMU core */ 164 #define SSNPHY_CORE_ID 0x828 /* 802.11n single-stream phy core */ 165 #define SDIOD_CORE_ID 0x829 /* SDIO device core */ 166 #define ARMCM3_CORE_ID 0x82a /* ARM Cortex M3 core */ 167 #define HTPHY_CORE_ID 0x82b /* 802.11n 4x4 phy core */ 168 #define MIPS74K_CORE_ID 0x82c /* mips 74k core */ 169 #define GMAC_CORE_ID 0x82d /* Gigabit MAC core */ 170 #define DMEMC_CORE_ID 0x82e /* DDR1/2 memory controller core */ 171 #define PCIERC_CORE_ID 0x82f /* PCIE Root Complex core */ 172 #define OCP_CORE_ID 0x830 /* OCP2OCP bridge core */ 173 #define SC_CORE_ID 0x831 /* shared common core */ 174 #define AHB_CORE_ID 0x832 /* OCP2AHB bridge core */ 175 #define SPIH_CORE_ID 0x833 /* SPI host core */ 176 #define I2S_CORE_ID 0x834 /* I2S core */ 177 #define DMEMS_CORE_ID 0x835 /* SDR/DDR1 memory controller core */ 178 #define DEF_SHIM_COMP 0x837 /* SHIM component in ubus/6362 */ 179 180 #define ACPHY_CORE_ID 0x83b /* Dot11 ACPHY */ 181 #define PCIE2_CORE_ID 0x83c /* pci express Gen2 core */ 182 #define USB30D_CORE_ID 0x83d /* usb 3.0 device core */ 183 #define ARMCR4_CORE_ID 0x83e /* ARM CR4 CPU */ 184 #define GCI_CORE_ID 0x840 /* GCI Core */ 185 #define M2MDMA_CORE_ID 0x844 /* memory to memory dma */ 186 #define CMEM_CORE_ID 0x846 /* CNDS DDR2/3 memory controller */ 187 #define ARMCA7_CORE_ID 0x847 /* ARM CA7 CPU */ 188 #define SYSMEM_CORE_ID 0x849 /* System memory core */ 189 #define APB_BRIDGE_CORE_ID 0x135 /* APB bridge core ID */ 190 #define AXI_CORE_ID 0x301 /* AXI/GPV core ID */ 191 #define EROM_CORE_ID 0x366 /* EROM core ID */ 192 #define OOB_ROUTER_CORE_ID 0x367 /* OOB router core ID */ 193 #define DEF_AI_COMP 0xfff /* Default component, in ai chips it maps all 194 * unused address ranges 195 */ 196 197 #define CC_4706_CORE_ID 0x500 /* chipcommon core */ 198 #define NS_PCIEG2_CORE_ID 0x501 /* PCIE Gen 2 core */ 199 #define NS_DMA_CORE_ID 0x502 /* DMA core */ 200 #define NS_SDIO3_CORE_ID 0x503 /* SDIO3 core */ 201 #define NS_USB20_CORE_ID 0x504 /* USB2.0 core */ 202 #define NS_USB30_CORE_ID 0x505 /* USB3.0 core */ 203 #define NS_A9JTAG_CORE_ID 0x506 /* ARM Cortex A9 JTAG core */ 204 #define NS_DDR23_CORE_ID 0x507 /* Denali DDR2/DDR3 memory controller */ 205 #define NS_ROM_CORE_ID 0x508 /* ROM core */ 206 #define NS_NAND_CORE_ID 0x509 /* NAND flash controller core */ 207 #define NS_QSPI_CORE_ID 0x50a /* SPI flash controller core */ 208 #define NS_CCB_CORE_ID 0x50b /* ChipcommonB core */ 209 #define SOCRAM_4706_CORE_ID 0x50e /* internal memory core */ 210 #define NS_SOCRAM_CORE_ID SOCRAM_4706_CORE_ID 211 #define ARMCA9_CORE_ID 0x510 /* ARM Cortex A9 core (ihost) */ 212 #define NS_IHOST_CORE_ID ARMCA9_CORE_ID /* ARM Cortex A9 core (ihost) */ 213 #define GMAC_COMMON_4706_CORE_ID 0x5dc /* Gigabit MAC core */ 214 #define GMAC_4706_CORE_ID 0x52d /* Gigabit MAC core */ 215 #define AMEMC_CORE_ID 0x52e /* DDR1/2 memory controller core */ 216 #define ALTA_CORE_ID 0x534 /* I2S core */ 217 #define DDR23_PHY_CORE_ID 0x5dd 218 219 #define SI_PCI1_MEM 0x40000000 /* Host Mode sb2pcitranslation0 (64 MB) */ 220 #define SI_PCI1_CFG 0x44000000 /* Host Mode sb2pcitranslation1 (64 MB) */ 221 #define SI_PCIE1_DMA_H32 0xc0000000 /* PCIE Client Mode sb2pcitranslation2 222 * (2 ZettaBytes), high 32 bits 223 */ 224 #define CC_4706B0_CORE_REV 0x8000001f /* chipcommon core */ 225 #define SOCRAM_4706B0_CORE_REV 0x80000005 /* internal memory core */ 226 #define GMAC_4706B0_CORE_REV 0x80000000 /* Gigabit MAC core */ 227 #define NS_PCIEG2_CORE_REV_B0 0x7 /* NS-B0 PCIE Gen 2 core rev */ 228 229 /* There are TWO constants on all HND chips: SI_ENUM_BASE above, 230 * and chipcommon being the first core: 231 */ 232 #define SI_CC_IDX 0 233 /* SOC Interconnect types (aka chip types) */ 234 #define SOCI_SB 0 235 #define SOCI_AI 1 236 #define SOCI_UBUS 2 237 #define SOCI_NAI 3 238 239 /* Common core control flags */ 240 #define SICF_BIST_EN 0x8000 241 #define SICF_PME_EN 0x4000 242 #define SICF_CORE_BITS 0x3ffc 243 #define SICF_FGC 0x0002 244 #define SICF_CLOCK_EN 0x0001 245 246 /* Common core status flags */ 247 #define SISF_BIST_DONE 0x8000 248 #define SISF_BIST_ERROR 0x4000 249 #define SISF_GATED_CLK 0x2000 250 #define SISF_DMA64 0x1000 251 #define SISF_CORE_BITS 0x0fff 252 253 /* Norstar core status flags */ 254 #define SISF_NS_BOOTDEV_MASK 0x0003 /* ROM core */ 255 #define SISF_NS_BOOTDEV_NOR 0x0000 /* ROM core */ 256 #define SISF_NS_BOOTDEV_NAND 0x0001 /* ROM core */ 257 #define SISF_NS_BOOTDEV_ROM 0x0002 /* ROM core */ 258 #define SISF_NS_BOOTDEV_OFFLOAD 0x0003 /* ROM core */ 259 #define SISF_NS_SKUVEC_MASK 0x000c /* ROM core */ 260 261 /* A register that is common to all cores to 262 * communicate w/PMU regarding clock control. 263 */ 264 #define SI_CLK_CTL_ST 0x1e0 /* clock control and status */ 265 #define SI_PWR_CTL_ST 0x1e8 /* For memory clock gating */ 266 267 /* clk_ctl_st register */ 268 #define CCS_FORCEALP 0x00000001 /* force ALP request */ 269 #define CCS_FORCEHT 0x00000002 /* force HT request */ 270 #define CCS_FORCEILP 0x00000004 /* force ILP request */ 271 #define CCS_ALPAREQ 0x00000008 /* ALP Avail Request */ 272 #define CCS_HTAREQ 0x00000010 /* HT Avail Request */ 273 #define CCS_FORCEHWREQOFF 0x00000020 /* Force HW Clock Request Off */ 274 #define CCS_HQCLKREQ 0x00000040 /* HQ Clock Required */ 275 #define CCS_USBCLKREQ 0x00000100 /* USB Clock Req */ 276 #define CCS_SECICLKREQ 0x00000100 /* SECI Clock Req */ 277 #define CCS_ARMFASTCLOCKREQ 0x00000100 /* ARM CR4/CA7 fast clock request */ 278 #define CCS_AVBCLKREQ 0x00000400 /* AVB Clock enable request */ 279 #define CCS_ERSRC_REQ_MASK 0x00000700 /* external resource requests */ 280 #define CCS_ERSRC_REQ_SHIFT 8 281 #define CCS_ALPAVAIL 0x00010000 /* ALP is available */ 282 #define CCS_HTAVAIL 0x00020000 /* HT is available */ 283 #define CCS_BP_ON_APL 0x00040000 /* RO: Backplane is running on ALP clock */ 284 #define CCS_BP_ON_HT 0x00080000 /* RO: Backplane is running on HT clock */ 285 #define CCS_ARMFASTCLOCKSTATUS 0x01000000 /* Fast CPU clock is running */ 286 #define CCS_ERSRC_STS_MASK 0x07000000 /* external resource status */ 287 #define CCS_ERSRC_STS_SHIFT 24 288 #define CCS_SECI_AVAIL 0x01000000 /* RO: SECI is available */ 289 290 #define CCS0_HTAVAIL 0x00010000 /* HT avail in chipc and pcmcia on 4328a0 */ 291 #define CCS0_ALPAVAIL 0x00020000 /* ALP avail in chipc and pcmcia on 4328a0 */ 292 293 /* Not really related to SOC Interconnect, but a couple of software 294 * conventions for the use the flash space: 295 */ 296 297 /* Minumum amount of flash we support */ 298 #define FLASH_MIN 0x00020000 /* Minimum flash size */ 299 300 /* A boot/binary may have an embedded block that describes its size */ 301 #define BISZ_OFFSET 0x3e0 /* At this offset into the binary */ 302 #define BISZ_MAGIC 0x4249535a /* Marked with this value: 'BISZ' */ 303 #define BISZ_MAGIC_IDX 0 /* Word 0: magic */ 304 #define BISZ_TXTST_IDX 1 /* 1: text start */ 305 #define BISZ_TXTEND_IDX 2 /* 2: text end */ 306 #define BISZ_DATAST_IDX 3 /* 3: data start */ 307 #define BISZ_DATAEND_IDX 4 /* 4: data end */ 308 #define BISZ_BSSST_IDX 5 /* 5: bss start */ 309 #define BISZ_BSSEND_IDX 6 /* 6: bss end */ 310 #define BISZ_SIZE 7 /* descriptor size in 32-bit integers */ 311 312 /* Boot/Kernel related defintion and functions */ 313 #define SOC_BOOTDEV_ROM 0x00000001 314 #define SOC_BOOTDEV_PFLASH 0x00000002 315 #define SOC_BOOTDEV_SFLASH 0x00000004 316 #define SOC_BOOTDEV_NANDFLASH 0x00000008 317 318 #define SOC_KNLDEV_NORFLASH 0x00000002 319 #define SOC_KNLDEV_NANDFLASH 0x00000004 320 321 #if !defined(_LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLY__) 322 int soc_boot_dev(void *sih); 323 int soc_knl_dev(void *sih); 324 #endif /* !defined(_LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLY__) */ 325 326 #define PMU_BASE_OFFSET 0x00012000 /* PMU offset is changed for ccrev >= 56 */ 327 #endif /* _HNDSOC_H */ 328