1 /* 2 * pcicfg.h: PCI configuration constants and structures. 3 * 4 * Copyright (C) 1999-2017, Broadcom Corporation 5 * 6 * Unless you and Broadcom execute a separate written software license 7 * agreement governing use of this software, this software is licensed to you 8 * under the terms of the GNU General Public License version 2 (the "GPL"), 9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 10 * following added to such license: 11 * 12 * As a special exception, the copyright holders of this software give you 13 * permission to link this software with independent modules, and to copy and 14 * distribute the resulting executable under terms of your choice, provided that 15 * you also meet, for each linked independent module, the terms and conditions of 16 * the license of that module. An independent module is a module which is not 17 * derived from this software. The special exception does not apply to any 18 * modifications of the software. 19 * 20 * Notwithstanding the above, under no circumstances may you combine this 21 * software in any way with any other Broadcom software provided under a license 22 * other than the GPL, without Broadcom's express prior written consent. 23 * 24 * 25 * <<Broadcom-WL-IPTag/Open:>> 26 * 27 * $Id: pcicfg.h 621340 2016-02-25 12:26:40Z $ 28 */ 29 30 #ifndef _h_pcicfg_ 31 #define _h_pcicfg_ 32 33 34 /* pci config status reg has a bit to indicate that capability ptr is present */ 35 36 #define PCI_CAPPTR_PRESENT 0x0010 37 38 /* A structure for the config registers is nice, but in most 39 * systems the config space is not memory mapped, so we need 40 * field offsetts. :-( 41 */ 42 #define PCI_CFG_VID 0 43 #define PCI_CFG_DID 2 44 #define PCI_CFG_CMD 4 45 #define PCI_CFG_STAT 6 46 #define PCI_CFG_REV 8 47 #define PCI_CFG_PROGIF 9 48 #define PCI_CFG_SUBCL 0xa 49 #define PCI_CFG_BASECL 0xb 50 #define PCI_CFG_CLSZ 0xc 51 #define PCI_CFG_LATTIM 0xd 52 #define PCI_CFG_HDR 0xe 53 #define PCI_CFG_BIST 0xf 54 #define PCI_CFG_BAR0 0x10 55 /* 56 * TODO: PCI_CFG_BAR1 is wrongly defined to be 0x14 whereas it should be 57 * 0x18 as per the PCIe full dongle spec. Need to modify the values below 58 * correctly at a later point of time 59 */ 60 #ifdef DHD_EFI 61 #define PCI_CFG_BAR1 0x18 62 #else 63 #define PCI_CFG_BAR1 0x14 64 #endif /* DHD_EFI */ 65 #define PCI_CFG_BAR2 0x18 66 #define PCI_CFG_BAR3 0x1c 67 #define PCI_CFG_BAR4 0x20 68 #define PCI_CFG_BAR5 0x24 69 #define PCI_CFG_CIS 0x28 70 #define PCI_CFG_SVID 0x2c 71 #define PCI_CFG_SSID 0x2e 72 #define PCI_CFG_ROMBAR 0x30 73 #define PCI_CFG_CAPPTR 0x34 74 #define PCI_CFG_INT 0x3c 75 #define PCI_CFG_PIN 0x3d 76 #define PCI_CFG_MINGNT 0x3e 77 #define PCI_CFG_MAXLAT 0x3f 78 #define PCI_CFG_DEVCTRL 0xd8 79 #define PCI_CFG_TLCNTRL_5 0x814 80 81 82 /* PCI CAPABILITY DEFINES */ 83 #define PCI_CAP_POWERMGMTCAP_ID 0x01 84 #define PCI_CAP_MSICAP_ID 0x05 85 #define PCI_CAP_VENDSPEC_ID 0x09 86 #define PCI_CAP_PCIECAP_ID 0x10 87 88 /* Data structure to define the Message Signalled Interrupt facility 89 * Valid for PCI and PCIE configurations 90 */ 91 typedef struct _pciconfig_cap_msi { 92 uint8 capID; 93 uint8 nextptr; 94 uint16 msgctrl; 95 uint32 msgaddr; 96 } pciconfig_cap_msi; 97 #define MSI_ENABLE 0x1 /* bit 0 of msgctrl */ 98 99 /* Data structure to define the Power managment facility 100 * Valid for PCI and PCIE configurations 101 */ 102 typedef struct _pciconfig_cap_pwrmgmt { 103 uint8 capID; 104 uint8 nextptr; 105 uint16 pme_cap; 106 uint16 pme_sts_ctrl; 107 uint8 pme_bridge_ext; 108 uint8 data; 109 } pciconfig_cap_pwrmgmt; 110 111 #define PME_CAP_PM_STATES (0x1f << 27) /* Bits 31:27 states that can generate PME */ 112 #define PME_CSR_OFFSET 0x4 /* 4-bytes offset */ 113 #define PME_CSR_PME_EN (1 << 8) /* Bit 8 Enable generating of PME */ 114 #define PME_CSR_PME_STAT (1 << 15) /* Bit 15 PME got asserted */ 115 116 /* Data structure to define the PCIE capability */ 117 typedef struct _pciconfig_cap_pcie { 118 uint8 capID; 119 uint8 nextptr; 120 uint16 pcie_cap; 121 uint32 dev_cap; 122 uint16 dev_ctrl; 123 uint16 dev_status; 124 uint32 link_cap; 125 uint16 link_ctrl; 126 uint16 link_status; 127 uint32 slot_cap; 128 uint16 slot_ctrl; 129 uint16 slot_status; 130 uint16 root_ctrl; 131 uint16 root_cap; 132 uint32 root_status; 133 } pciconfig_cap_pcie; 134 135 /* PCIE Enhanced CAPABILITY DEFINES */ 136 #define PCIE_EXTCFG_OFFSET 0x100 137 #define PCIE_ADVERRREP_CAPID 0x0001 138 #define PCIE_VC_CAPID 0x0002 139 #define PCIE_DEVSNUM_CAPID 0x0003 140 #define PCIE_PWRBUDGET_CAPID 0x0004 141 142 /* PCIE Extended configuration */ 143 #define PCIE_ADV_CORR_ERR_MASK 0x114 144 #define CORR_ERR_RE (1 << 0) /* Receiver */ 145 #define CORR_ERR_BT (1 << 6) /* Bad TLP */ 146 #define CORR_ERR_BD (1 << 7) /* Bad DLLP */ 147 #define CORR_ERR_RR (1 << 8) /* REPLAY_NUM rollover */ 148 #define CORR_ERR_RT (1 << 12) /* Reply timer timeout */ 149 #define ALL_CORR_ERRORS (CORR_ERR_RE | CORR_ERR_BT | CORR_ERR_BD | \ 150 CORR_ERR_RR | CORR_ERR_RT) 151 152 /* PCIE Root Control Register bits (Host mode only) */ 153 #define PCIE_RC_CORR_SERR_EN 0x0001 154 #define PCIE_RC_NONFATAL_SERR_EN 0x0002 155 #define PCIE_RC_FATAL_SERR_EN 0x0004 156 #define PCIE_RC_PME_INT_EN 0x0008 157 #define PCIE_RC_CRS_EN 0x0010 158 159 /* PCIE Root Capability Register bits (Host mode only) */ 160 #define PCIE_RC_CRS_VISIBILITY 0x0001 161 162 /* Header to define the PCIE specific capabilities in the extended config space */ 163 typedef struct _pcie_enhanced_caphdr { 164 uint16 capID; 165 uint16 cap_ver : 4; 166 uint16 next_ptr : 12; 167 } pcie_enhanced_caphdr; 168 169 170 #define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */ 171 #define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */ 172 #define PCI_SPROM_CONTROL 0x88 /* sprom property control */ 173 #define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */ 174 #define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */ 175 #define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */ 176 #define PCI_TO_SB_MB 0x98 /* signal backplane interrupts */ 177 #define PCI_BACKPLANE_ADDR 0xa0 /* address an arbitrary location on the system backplane */ 178 #define PCI_BACKPLANE_DATA 0xa4 /* data at the location specified by above address */ 179 #define PCI_CLK_CTL_ST 0xa8 /* pci config space clock control/status (>=rev14) */ 180 #define PCI_BAR0_WIN2 0xac /* backplane addres space accessed by second 4KB of BAR0 */ 181 #define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */ 182 #define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */ 183 #define PCIE_CFG_DEVICE_CONTROL 0xb4 /* 0xb4 is used as device control in PCIE devices */ 184 #define PCIE_DC_AER_CORR_EN (1u << 0u) 185 #define PCIE_DC_AER_NON_FATAL_EN (1u << 1u) 186 #define PCIE_DC_AER_FATAL_EN (1u << 2u) 187 #define PCIE_DC_AER_UNSUP_EN (1u << 3u) 188 189 #define PCI_BAR0_WIN2_OFFSET 0x1000u 190 #define PCIE2_BAR0_CORE2_WIN2_OFFSET 0x5000u 191 192 #define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */ 193 #define PCI_L1SS_CTRL2 0x24c /* The L1 PM Substates Control register */ 194 195 /* Private Registers */ 196 #define PCI_STAT_CTRL 0xa80 197 #define PCI_L0_EVENTCNT 0xa84 198 #define PCI_L0_STATETMR 0xa88 199 #define PCI_L1_EVENTCNT 0xa8c 200 #define PCI_L1_STATETMR 0xa90 201 #define PCI_L1_1_EVENTCNT 0xa94 202 #define PCI_L1_1_STATETMR 0xa98 203 #define PCI_L1_2_EVENTCNT 0xa9c 204 #define PCI_L1_2_STATETMR 0xaa0 205 #define PCI_L2_EVENTCNT 0xaa4 206 #define PCI_L2_STATETMR 0xaa8 207 208 #define PCI_LINK_STATUS 0x4dc 209 #define PCI_LINK_SPEED_MASK (15u << 0u) 210 #define PCI_LINK_SPEED_SHIFT (0) 211 #define PCIE_LNK_SPEED_GEN1 0x1 212 #define PCIE_LNK_SPEED_GEN2 0x2 213 #define PCIE_LNK_SPEED_GEN3 0x3 214 215 #define PCI_PL_SPARE 0x1808 /* Config to Increase external clkreq deasserted minimum time */ 216 #define PCI_CONFIG_EXT_CLK_MIN_TIME_MASK (1u << 31u) 217 #define PCI_CONFIG_EXT_CLK_MIN_TIME_SHIFT (31) 218 219 #define PCI_PMCR_REFUP 0x1814 /* Trefup time */ 220 #define PCI_PMCR_REFUP_EXT 0x1818 /* Trefup extend Max */ 221 #define PCI_TPOWER_SCALE_MASK 0x3 222 #define PCI_TPOWER_SCALE_SHIFT 3 /* 0:1 is scale and 2 is rsvd */ 223 224 225 #define PCI_BAR0_SHADOW_OFFSET (2 * 1024) /* bar0 + 2K accesses sprom shadow (in pci core) */ 226 #define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */ 227 #define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) /* bar0 + 6K accesses pci core registers */ 228 #define PCI_BAR0_PCISBR_OFFSET (4 * 1024) /* pci core SB registers are at the end of the 229 * 8KB window, so their address is the "regular" 230 * address plus 4K 231 */ 232 /* 233 * PCIE GEN2 changed some of the above locations for 234 * Bar0WrapperBase, SecondaryBAR0Window and SecondaryBAR0WrapperBase 235 * BAR0 maps 32K of register space 236 */ 237 #define PCIE2_BAR0_WIN2 0x70 /* backplane addres space accessed by second 4KB of BAR0 */ 238 #define PCIE2_BAR0_CORE2_WIN 0x74 /* backplane addres space accessed by second 4KB of BAR0 */ 239 #define PCIE2_BAR0_CORE2_WIN2 0x78 /* backplane addres space accessed by second 4KB of BAR0 */ 240 241 #define PCI_BAR0_WIN2_OFFSET 0x1000u 242 #define PCI_CORE_ENUM_OFFSET 0x2000u 243 #define PCI_CC_CORE_ENUM_OFFSET 0x3000u 244 #define PCI_SEC_BAR0_WIN_OFFSET 0x4000u 245 #define PCI_SEC_BAR0_WRAP_OFFSET 0x5000u 246 #define PCI_CORE_ENUM2_OFFSET 0x6000u 247 #define PCI_CC_CORE_ENUM2_OFFSET 0x7000u 248 #define PCI_LAST_OFFSET 0x8000u 249 250 #define PCI_BAR0_WINSZ (16 * 1024) /* bar0 window size Match with corerev 13 */ 251 /* On pci corerev >= 13 and all pcie, the bar0 is now 16KB and it maps: */ 252 #define PCI_16KB0_PCIREGS_OFFSET (8 * 1024) /* bar0 + 8K accesses pci/pcie core registers */ 253 #define PCI_16KB0_CCREGS_OFFSET (12 * 1024) /* bar0 + 12K accesses chipc core registers */ 254 #define PCI_16KBB0_WINSZ (16 * 1024) /* bar0 window size */ 255 #define PCI_SECOND_BAR0_OFFSET (16 * 1024) /* secondary bar 0 window */ 256 257 /* On AI chips we have a second window to map DMP regs are mapped: */ 258 #define PCI_16KB0_WIN2_OFFSET (4 * 1024) /* bar0 + 4K is "Window 2" */ 259 260 /* PCI_INT_STATUS */ 261 #define PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */ 262 263 /* PCI_INT_MASK */ 264 #define PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */ 265 #define PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */ 266 #define PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */ 267 #define PCI_CTO_INT_SHIFT 16 /* backplane SBErr interrupt mask */ 268 #define PCI_CTO_INT_MASK (1 << PCI_CTO_INT_SHIFT) /* backplane SBErr interrupt mask */ 269 270 /* PCI_SPROM_CONTROL */ 271 #define SPROM_SZ_MSK 0x02 /* SPROM Size Mask */ 272 #define SPROM_LOCKED 0x08 /* SPROM Locked */ 273 #define SPROM_BLANK 0x04 /* indicating a blank SPROM */ 274 #define SPROM_WRITEEN 0x10 /* SPROM write enable */ 275 #define SPROM_BOOTROM_WE 0x20 /* external bootrom write enable */ 276 #define SPROM_BACKPLANE_EN 0x40 /* Enable indirect backplane access */ 277 #define SPROM_OTPIN_USE 0x80 /* device OTP In use */ 278 #define SPROM_CFG_TO_SB_RST 0x400 /* backplane reset */ 279 280 /* Bits in PCI command and status regs */ 281 #define PCI_CMD_IO 0x00000001 /* I/O enable */ 282 #define PCI_CMD_MEMORY 0x00000002 /* Memory enable */ 283 #define PCI_CMD_MASTER 0x00000004 /* Master enable */ 284 #define PCI_CMD_SPECIAL 0x00000008 /* Special cycles enable */ 285 #define PCI_CMD_INVALIDATE 0x00000010 /* Invalidate? */ 286 #define PCI_CMD_VGA_PAL 0x00000040 /* VGA Palate */ 287 #define PCI_STAT_TA 0x08000000 /* target abort status */ 288 289 /* Header types */ 290 #define PCI_HEADER_MULTI 0x80 291 #define PCI_HEADER_MASK 0x7f 292 typedef enum { 293 PCI_HEADER_NORMAL, 294 PCI_HEADER_BRIDGE, 295 PCI_HEADER_CARDBUS 296 } pci_header_types; 297 298 #define PCI_CONFIG_SPACE_SIZE 256 299 300 #define DWORD_ALIGN(x) (x & ~(0x03)) 301 #define BYTE_POS(x) (x & 0x3) 302 #define WORD_POS(x) (x & 0x1) 303 304 #define BYTE_SHIFT(x) (8 * BYTE_POS(x)) 305 #define WORD_SHIFT(x) (16 * WORD_POS(x)) 306 307 #define BYTE_VAL(a, x) ((a >> BYTE_SHIFT(x)) & 0xFF) 308 #define WORD_VAL(a, x) ((a >> WORD_SHIFT(x)) & 0xFFFF) 309 310 #define read_pci_cfg_byte(a) \ 311 (BYTE_VAL(OSL_PCI_READ_CONFIG(osh, DWORD_ALIGN(a), 4), a) & 0xff) 312 313 #define read_pci_cfg_word(a) \ 314 (WORD_VAL(OSL_PCI_READ_CONFIG(osh, DWORD_ALIGN(a), 4), a) & 0xffff) 315 316 #define write_pci_cfg_byte(a, val) do { \ 317 uint32 tmpval; \ 318 tmpval = (OSL_PCI_READ_CONFIG(osh, DWORD_ALIGN(a), 4) & ~0xFF << BYTE_POS(a)) | \ 319 val << BYTE_POS(a); \ 320 OSL_PCI_WRITE_CONFIG(osh, DWORD_ALIGN(a), 4, tmpval); \ 321 } while (0) 322 323 #define write_pci_cfg_word(a, val) do { \ 324 uint32 tmpval; \ 325 tmpval = (OSL_PCI_READ_CONFIG(osh, DWORD_ALIGN(a), 4) & ~0xFFFF << WORD_POS(a)) | \ 326 val << WORD_POS(a); \ 327 OSL_PCI_WRITE_CONFIG(osh, DWORD_ALIGN(a), 4, tmpval); \ 328 } while (0) 329 330 #endif /* _h_pcicfg_ */ 331