1 /* 2 * Generic Broadcom Home Networking Division (HND) DMA engine HW interface 3 * This supports the following chips: BCM42xx, 44xx, 47xx . 4 * 5 * Copyright (C) 1999-2017, Broadcom Corporation 6 * 7 * Unless you and Broadcom execute a separate written software license 8 * agreement governing use of this software, this software is licensed to you 9 * under the terms of the GNU General Public License version 2 (the "GPL"), 10 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 11 * following added to such license: 12 * 13 * As a special exception, the copyright holders of this software give you 14 * permission to link this software with independent modules, and to copy and 15 * distribute the resulting executable under terms of your choice, provided that 16 * you also meet, for each linked independent module, the terms and conditions of 17 * the license of that module. An independent module is a module which is not 18 * derived from this software. The special exception does not apply to any 19 * modifications of the software. 20 * 21 * Notwithstanding the above, under no circumstances may you combine this 22 * software in any way with any other Broadcom software provided under a license 23 * other than the GPL, without Broadcom's express prior written consent. 24 * 25 * 26 * <<Broadcom-WL-IPTag/Open:>> 27 * 28 * $Id: sbhnddma.h 615537 2016-01-28 00:46:34Z $ 29 */ 30 31 #ifndef _sbhnddma_h_ 32 #define _sbhnddma_h_ 33 34 /* DMA structure: 35 * support two DMA engines: 32 bits address or 64 bit addressing 36 * basic DMA register set is per channel(transmit or receive) 37 * a pair of channels is defined for convenience 38 */ 39 40 41 /* 32 bits addressing */ 42 43 /** dma registers per channel(xmt or rcv) */ 44 typedef volatile struct { 45 uint32 control; /**< enable, et al */ 46 uint32 addr; /**< descriptor ring base address (4K aligned) */ 47 uint32 ptr; /**< last descriptor posted to chip */ 48 uint32 status; /**< current active descriptor, et al */ 49 } dma32regs_t; 50 51 typedef volatile struct { 52 dma32regs_t xmt; /**< dma tx channel */ 53 dma32regs_t rcv; /**< dma rx channel */ 54 } dma32regp_t; 55 56 typedef volatile struct { /* diag access */ 57 uint32 fifoaddr; /**< diag address */ 58 uint32 fifodatalow; /**< low 32bits of data */ 59 uint32 fifodatahigh; /**< high 32bits of data */ 60 uint32 pad; /**< reserved */ 61 } dma32diag_t; 62 63 /** 64 * DMA Descriptor 65 * Descriptors are only read by the hardware, never written back. 66 */ 67 typedef volatile struct { 68 uint32 ctrl; /**< misc control bits & bufcount */ 69 uint32 addr; /**< data buffer address */ 70 } dma32dd_t; 71 72 /** Each descriptor ring must be 4096byte aligned, and fit within a single 4096byte page. */ 73 #define D32RINGALIGN_BITS 12 74 #define D32MAXRINGSZ (1 << D32RINGALIGN_BITS) 75 #define D32RINGALIGN (1 << D32RINGALIGN_BITS) 76 77 #define D32MAXDD (D32MAXRINGSZ / sizeof (dma32dd_t)) 78 79 /* transmit channel control */ 80 #define XC_XE ((uint32)1 << 0) /**< transmit enable */ 81 #define XC_SE ((uint32)1 << 1) /**< transmit suspend request */ 82 #define XC_LE ((uint32)1 << 2) /**< loopback enable */ 83 #define XC_FL ((uint32)1 << 4) /**< flush request */ 84 #define XC_MR_MASK 0x000001C0 /**< Multiple outstanding reads */ 85 #define XC_MR_SHIFT 6 86 #define XC_PD ((uint32)1 << 11) /**< parity check disable */ 87 #define XC_AE ((uint32)3 << 16) /**< address extension bits */ 88 #define XC_AE_SHIFT 16 89 #define XC_BL_MASK 0x001C0000 /**< BurstLen bits */ 90 #define XC_BL_SHIFT 18 91 #define XC_PC_MASK 0x00E00000 /**< Prefetch control */ 92 #define XC_PC_SHIFT 21 93 #define XC_PT_MASK 0x03000000 /**< Prefetch threshold */ 94 #define XC_PT_SHIFT 24 95 96 /** Multiple outstanding reads */ 97 #define DMA_MR_1 0 98 #define DMA_MR_2 1 99 #define DMA_MR_4 2 100 #define DMA_MR_8 3 101 #define DMA_MR_12 4 102 #define DMA_MR_16 5 103 #define DMA_MR_20 6 104 #define DMA_MR_32 7 105 106 /** DMA Burst Length in bytes */ 107 #define DMA_BL_16 0 108 #define DMA_BL_32 1 109 #define DMA_BL_64 2 110 #define DMA_BL_128 3 111 #define DMA_BL_256 4 112 #define DMA_BL_512 5 113 #define DMA_BL_1024 6 114 115 /** Prefetch control */ 116 #define DMA_PC_0 0 117 #define DMA_PC_4 1 118 #define DMA_PC_8 2 119 #define DMA_PC_16 3 120 /* others: reserved */ 121 122 /** Prefetch threshold */ 123 #define DMA_PT_1 0 124 #define DMA_PT_2 1 125 #define DMA_PT_4 2 126 #define DMA_PT_8 3 127 128 /** Channel Switch */ 129 #define DMA_CS_OFF 0 130 #define DMA_CS_ON 1 131 132 /* transmit descriptor table pointer */ 133 #define XP_LD_MASK 0xfff /**< last valid descriptor */ 134 135 /* transmit channel status */ 136 #define XS_CD_MASK 0x0fff /**< current descriptor pointer */ 137 #define XS_XS_MASK 0xf000 /**< transmit state */ 138 #define XS_XS_SHIFT 12 139 #define XS_XS_DISABLED 0x0000 /**< disabled */ 140 #define XS_XS_ACTIVE 0x1000 /**< active */ 141 #define XS_XS_IDLE 0x2000 /**< idle wait */ 142 #define XS_XS_STOPPED 0x3000 /**< stopped */ 143 #define XS_XS_SUSP 0x4000 /**< suspend pending */ 144 #define XS_XE_MASK 0xf0000 /**< transmit errors */ 145 #define XS_XE_SHIFT 16 146 #define XS_XE_NOERR 0x00000 /**< no error */ 147 #define XS_XE_DPE 0x10000 /**< descriptor protocol error */ 148 #define XS_XE_DFU 0x20000 /**< data fifo underrun */ 149 #define XS_XE_BEBR 0x30000 /**< bus error on buffer read */ 150 #define XS_XE_BEDA 0x40000 /**< bus error on descriptor access */ 151 #define XS_AD_MASK 0xfff00000 /**< active descriptor */ 152 #define XS_AD_SHIFT 20 153 154 /* receive channel control */ 155 #define RC_RE ((uint32)1 << 0) /**< receive enable */ 156 #define RC_RO_MASK 0xfe /**< receive frame offset */ 157 #define RC_RO_SHIFT 1 158 #define RC_FM ((uint32)1 << 8) /**< direct fifo receive (pio) mode */ 159 #define RC_SH ((uint32)1 << 9) /**< separate rx header descriptor enable */ 160 #define RC_OC ((uint32)1 << 10) /**< overflow continue */ 161 #define RC_PD ((uint32)1 << 11) /**< parity check disable */ 162 #define RC_AE ((uint32)3 << 16) /**< address extension bits */ 163 #define RC_AE_SHIFT 16 164 #define RC_BL_MASK 0x001C0000 /**< BurstLen bits */ 165 #define RC_BL_SHIFT 18 166 #define RC_PC_MASK 0x00E00000 /**< Prefetch control */ 167 #define RC_PC_SHIFT 21 168 #define RC_PT_MASK 0x03000000 /**< Prefetch threshold */ 169 #define RC_PT_SHIFT 24 170 #define RC_WAITCMP_MASK 0x00001000 171 #define RC_WAITCMP_SHIFT 12 172 /* receive descriptor table pointer */ 173 #define RP_LD_MASK 0xfff /**< last valid descriptor */ 174 175 /* receive channel status */ 176 #define RS_CD_MASK 0x0fff /**< current descriptor pointer */ 177 #define RS_RS_MASK 0xf000 /**< receive state */ 178 #define RS_RS_SHIFT 12 179 #define RS_RS_DISABLED 0x0000 /**< disabled */ 180 #define RS_RS_ACTIVE 0x1000 /**< active */ 181 #define RS_RS_IDLE 0x2000 /**< idle wait */ 182 #define RS_RS_STOPPED 0x3000 /**< reserved */ 183 #define RS_RE_MASK 0xf0000 /**< receive errors */ 184 #define RS_RE_SHIFT 16 185 #define RS_RE_NOERR 0x00000 /**< no error */ 186 #define RS_RE_DPE 0x10000 /**< descriptor protocol error */ 187 #define RS_RE_DFO 0x20000 /**< data fifo overflow */ 188 #define RS_RE_BEBW 0x30000 /**< bus error on buffer write */ 189 #define RS_RE_BEDA 0x40000 /**< bus error on descriptor access */ 190 #define RS_AD_MASK 0xfff00000 /**< active descriptor */ 191 #define RS_AD_SHIFT 20 192 193 /* fifoaddr */ 194 #define FA_OFF_MASK 0xffff /**< offset */ 195 #define FA_SEL_MASK 0xf0000 /**< select */ 196 #define FA_SEL_SHIFT 16 197 #define FA_SEL_XDD 0x00000 /**< transmit dma data */ 198 #define FA_SEL_XDP 0x10000 /**< transmit dma pointers */ 199 #define FA_SEL_RDD 0x40000 /**< receive dma data */ 200 #define FA_SEL_RDP 0x50000 /**< receive dma pointers */ 201 #define FA_SEL_XFD 0x80000 /**< transmit fifo data */ 202 #define FA_SEL_XFP 0x90000 /**< transmit fifo pointers */ 203 #define FA_SEL_RFD 0xc0000 /**< receive fifo data */ 204 #define FA_SEL_RFP 0xd0000 /**< receive fifo pointers */ 205 #define FA_SEL_RSD 0xe0000 /**< receive frame status data */ 206 #define FA_SEL_RSP 0xf0000 /**< receive frame status pointers */ 207 208 /* descriptor control flags */ 209 #define CTRL_BC_MASK 0x00001fff /**< buffer byte count, real data len must <= 4KB */ 210 #define CTRL_AE ((uint32)3 << 16) /**< address extension bits */ 211 #define CTRL_AE_SHIFT 16 212 #define CTRL_PARITY ((uint32)3 << 18) /**< parity bit */ 213 #define CTRL_EOT ((uint32)1 << 28) /**< end of descriptor table */ 214 #define CTRL_IOC ((uint32)1 << 29) /**< interrupt on completion */ 215 #define CTRL_EOF ((uint32)1 << 30) /**< end of frame */ 216 #define CTRL_SOF ((uint32)1 << 31) /**< start of frame */ 217 218 /** control flags in the range [27:20] are core-specific and not defined here */ 219 #define CTRL_CORE_MASK 0x0ff00000 220 221 /* 64 bits addressing */ 222 223 /** dma registers per channel(xmt or rcv) */ 224 typedef volatile struct { 225 uint32 control; /**< enable, et al */ 226 uint32 ptr; /**< last descriptor posted to chip */ 227 uint32 addrlow; /**< descriptor ring base address low 32-bits (8K aligned) */ 228 uint32 addrhigh; /**< descriptor ring base address bits 63:32 (8K aligned) */ 229 uint32 status0; /**< current descriptor, xmt state */ 230 uint32 status1; /**< active descriptor, xmt error */ 231 } dma64regs_t; 232 233 typedef volatile struct { 234 dma64regs_t tx; /**< dma64 tx channel */ 235 dma64regs_t rx; /**< dma64 rx channel */ 236 } dma64regp_t; 237 238 typedef volatile struct { /**< diag access */ 239 uint32 fifoaddr; /**< diag address */ 240 uint32 fifodatalow; /**< low 32bits of data */ 241 uint32 fifodatahigh; /**< high 32bits of data */ 242 uint32 pad; /**< reserved */ 243 } dma64diag_t; 244 245 /** 246 * DMA Descriptor 247 * Descriptors are only read by the hardware, never written back. 248 */ 249 typedef volatile struct { 250 uint32 ctrl1; /**< misc control bits */ 251 uint32 ctrl2; /**< buffer count and address extension */ 252 uint32 addrlow; /**< memory address of the date buffer, bits 31:0 */ 253 uint32 addrhigh; /**< memory address of the date buffer, bits 63:32 */ 254 } dma64dd_t; 255 256 /** 257 * Each descriptor ring must be 8kB aligned, and fit within a contiguous 8kB physical addresss. 258 */ 259 #define D64RINGALIGN_BITS 13 260 #define D64MAXRINGSZ (1 << D64RINGALIGN_BITS) 261 #define D64RINGBOUNDARY (1 << D64RINGALIGN_BITS) 262 263 #define D64MAXDD (D64MAXRINGSZ / sizeof (dma64dd_t)) 264 265 /** for cores with large descriptor ring support, descriptor ring size can be up to 4096 */ 266 #define D64MAXDD_LARGE ((1 << 16) / sizeof (dma64dd_t)) 267 268 /** 269 * for cores with large descriptor ring support (4k descriptors), descriptor ring cannot cross 270 * 64K boundary 271 */ 272 #define D64RINGBOUNDARY_LARGE (1 << 16) 273 274 /* 275 * Default DMA Burstlen values for USBRev >= 12 and SDIORev >= 11. 276 * When this field contains the value N, the burst length is 2**(N + 4) bytes. 277 */ 278 #define D64_DEF_USBBURSTLEN 2 279 #define D64_DEF_SDIOBURSTLEN 1 280 281 282 #ifndef D64_USBBURSTLEN 283 #define D64_USBBURSTLEN DMA_BL_64 284 #endif 285 #ifndef D64_SDIOBURSTLEN 286 #define D64_SDIOBURSTLEN DMA_BL_32 287 #endif 288 289 /* transmit channel control */ 290 #define D64_XC_XE 0x00000001 /**< transmit enable */ 291 #define D64_XC_SE 0x00000002 /**< transmit suspend request */ 292 #define D64_XC_LE 0x00000004 /**< loopback enable */ 293 #define D64_XC_FL 0x00000010 /**< flush request */ 294 #define D64_XC_MR_MASK 0x000001C0 /**< Multiple outstanding reads */ 295 #define D64_XC_MR_SHIFT 6 296 #define D64_XC_CS_SHIFT 9 /**< channel switch enable */ 297 #define D64_XC_CS_MASK 0x00000200 /**< channel switch enable */ 298 #define D64_XC_PD 0x00000800 /**< parity check disable */ 299 #define D64_XC_AE 0x00030000 /**< address extension bits */ 300 #define D64_XC_AE_SHIFT 16 301 #define D64_XC_BL_MASK 0x001C0000 /**< BurstLen bits */ 302 #define D64_XC_BL_SHIFT 18 303 #define D64_XC_PC_MASK 0x00E00000 /**< Prefetch control */ 304 #define D64_XC_PC_SHIFT 21 305 #define D64_XC_PT_MASK 0x03000000 /**< Prefetch threshold */ 306 #define D64_XC_PT_SHIFT 24 307 308 /* transmit descriptor table pointer */ 309 #define D64_XP_LD_MASK 0x00001fff /**< last valid descriptor */ 310 311 /* transmit channel status */ 312 #define D64_XS0_CD_MASK (di->d64_xs0_cd_mask) /**< current descriptor pointer */ 313 #define D64_XS0_XS_MASK 0xf0000000 /**< transmit state */ 314 #define D64_XS0_XS_SHIFT 28 315 #define D64_XS0_XS_DISABLED 0x00000000 /**< disabled */ 316 #define D64_XS0_XS_ACTIVE 0x10000000 /**< active */ 317 #define D64_XS0_XS_IDLE 0x20000000 /**< idle wait */ 318 #define D64_XS0_XS_STOPPED 0x30000000 /**< stopped */ 319 #define D64_XS0_XS_SUSP 0x40000000 /**< suspend pending */ 320 321 #define D64_XS1_AD_MASK (di->d64_xs1_ad_mask) /**< active descriptor */ 322 #define D64_XS1_XE_MASK 0xf0000000 /**< transmit errors */ 323 #define D64_XS1_XE_SHIFT 28 324 #define D64_XS1_XE_NOERR 0x00000000 /**< no error */ 325 #define D64_XS1_XE_DPE 0x10000000 /**< descriptor protocol error */ 326 #define D64_XS1_XE_DFU 0x20000000 /**< data fifo underrun */ 327 #define D64_XS1_XE_DTE 0x30000000 /**< data transfer error */ 328 #define D64_XS1_XE_DESRE 0x40000000 /**< descriptor read error */ 329 #define D64_XS1_XE_COREE 0x50000000 /**< core error */ 330 331 /* receive channel control */ 332 #define D64_RC_RE 0x00000001 /**< receive enable */ 333 #define D64_RC_RO_MASK 0x000000fe /**< receive frame offset */ 334 #define D64_RC_RO_SHIFT 1 335 #define D64_RC_FM 0x00000100 /**< direct fifo receive (pio) mode */ 336 #define D64_RC_SH 0x00000200 /**< separate rx header descriptor enable */ 337 #define D64_RC_SHIFT 9 /**< separate rx header descriptor enable */ 338 #define D64_RC_OC 0x00000400 /**< overflow continue */ 339 #define D64_RC_PD 0x00000800 /**< parity check disable */ 340 #define D64_RC_SA 0x00002000 /**< select active */ 341 #define D64_RC_GE 0x00004000 /**< Glom enable */ 342 #define D64_RC_AE 0x00030000 /**< address extension bits */ 343 #define D64_RC_AE_SHIFT 16 344 #define D64_RC_BL_MASK 0x001C0000 /**< BurstLen bits */ 345 #define D64_RC_BL_SHIFT 18 346 #define D64_RC_PC_MASK 0x00E00000 /**< Prefetch control */ 347 #define D64_RC_PC_SHIFT 21 348 #define D64_RC_PT_MASK 0x03000000 /**< Prefetch threshold */ 349 #define D64_RC_PT_SHIFT 24 350 #define D64_RC_WAITCMP_MASK 0x00001000 351 #define D64_RC_WAITCMP_SHIFT 12 352 353 /* flags for dma controller */ 354 #define DMA_CTRL_PEN (1 << 0) /**< partity enable */ 355 #define DMA_CTRL_ROC (1 << 1) /**< rx overflow continue */ 356 #define DMA_CTRL_RXMULTI (1 << 2) /**< allow rx scatter to multiple descriptors */ 357 #define DMA_CTRL_UNFRAMED (1 << 3) /**< Unframed Rx/Tx data */ 358 #define DMA_CTRL_USB_BOUNDRY4KB_WAR (1 << 4) 359 #define DMA_CTRL_DMA_AVOIDANCE_WAR (1 << 5) /**< DMA avoidance WAR for 4331 */ 360 #define DMA_CTRL_RXSINGLE (1 << 6) /**< always single buffer */ 361 #define DMA_CTRL_SDIO_RXGLOM (1 << 7) /**< DMA Rx glome is enabled */ 362 363 /* receive descriptor table pointer */ 364 #define D64_RP_LD_MASK 0x00001fff /**< last valid descriptor */ 365 366 /* receive channel status */ 367 #define D64_RS0_CD_MASK (di->d64_rs0_cd_mask) /**< current descriptor pointer */ 368 #define D64_RS0_RS_MASK 0xf0000000 /**< receive state */ 369 #define D64_RS0_RS_SHIFT 28 370 #define D64_RS0_RS_DISABLED 0x00000000 /**< disabled */ 371 #define D64_RS0_RS_ACTIVE 0x10000000 /**< active */ 372 #define D64_RS0_RS_IDLE 0x20000000 /**< idle wait */ 373 #define D64_RS0_RS_STOPPED 0x30000000 /**< stopped */ 374 #define D64_RS0_RS_SUSP 0x40000000 /**< suspend pending */ 375 376 #define D64_RS1_AD_MASK (di->d64_rs1_ad_mask) /* active descriptor pointer */ 377 #define D64_RS1_RE_MASK 0xf0000000 /* receive errors */ 378 #define D64_RS1_RE_SHIFT 28 379 #define D64_RS1_RE_NOERR 0x00000000 /**< no error */ 380 #define D64_RS1_RE_DPO 0x10000000 /**< descriptor protocol error */ 381 #define D64_RS1_RE_DFU 0x20000000 /**< data fifo overflow */ 382 #define D64_RS1_RE_DTE 0x30000000 /**< data transfer error */ 383 #define D64_RS1_RE_DESRE 0x40000000 /**< descriptor read error */ 384 #define D64_RS1_RE_COREE 0x50000000 /**< core error */ 385 386 /* fifoaddr */ 387 #define D64_FA_OFF_MASK 0xffff /**< offset */ 388 #define D64_FA_SEL_MASK 0xf0000 /**< select */ 389 #define D64_FA_SEL_SHIFT 16 390 #define D64_FA_SEL_XDD 0x00000 /**< transmit dma data */ 391 #define D64_FA_SEL_XDP 0x10000 /**< transmit dma pointers */ 392 #define D64_FA_SEL_RDD 0x40000 /**< receive dma data */ 393 #define D64_FA_SEL_RDP 0x50000 /**< receive dma pointers */ 394 #define D64_FA_SEL_XFD 0x80000 /**< transmit fifo data */ 395 #define D64_FA_SEL_XFP 0x90000 /**< transmit fifo pointers */ 396 #define D64_FA_SEL_RFD 0xc0000 /**< receive fifo data */ 397 #define D64_FA_SEL_RFP 0xd0000 /**< receive fifo pointers */ 398 #define D64_FA_SEL_RSD 0xe0000 /**< receive frame status data */ 399 #define D64_FA_SEL_RSP 0xf0000 /**< receive frame status pointers */ 400 401 /* descriptor control flags 1 */ 402 #define D64_CTRL_COREFLAGS 0x0ff00000 /**< core specific flags */ 403 #define D64_CTRL1_NOTPCIE ((uint32)1 << 18) /**< buirst size control */ 404 #define D64_CTRL1_EOT ((uint32)1 << 28) /**< end of descriptor table */ 405 #define D64_CTRL1_IOC ((uint32)1 << 29) /**< interrupt on completion */ 406 #define D64_CTRL1_EOF ((uint32)1 << 30) /**< end of frame */ 407 #define D64_CTRL1_SOF ((uint32)1 << 31) /**< start of frame */ 408 409 /* descriptor control flags 2 */ 410 #define D64_CTRL2_BC_MASK 0x00007fff /**< buffer byte count. real data len must <= 16KB */ 411 #define D64_CTRL2_AE 0x00030000 /**< address extension bits */ 412 #define D64_CTRL2_AE_SHIFT 16 413 #define D64_CTRL2_PARITY 0x00040000 /* parity bit */ 414 415 /** control flags in the range [27:20] are core-specific and not defined here */ 416 #define D64_CTRL_CORE_MASK 0x0ff00000 417 418 #define D64_RX_FRM_STS_LEN 0x0000ffff /**< frame length mask */ 419 #define D64_RX_FRM_STS_OVFL 0x00800000 /**< RxOverFlow */ 420 #define D64_RX_FRM_STS_DSCRCNT 0x0f000000 /**< no. of descriptors used - 1, d11corerev >= 22 */ 421 #define D64_RX_FRM_STS_DATATYPE 0xf0000000 /**< core-dependent data type */ 422 423 /** receive frame status */ 424 typedef volatile struct { 425 uint16 len; 426 uint16 flags; 427 } dma_rxh_t; 428 429 #endif /* _sbhnddma_h_ */ 430