1 /* 2 * BCM47XX Sonics SiliconBackplane embedded ram core 3 * 4 * Copyright (C) 1999-2017, Broadcom Corporation 5 * 6 * Unless you and Broadcom execute a separate written software license 7 * agreement governing use of this software, this software is licensed to you 8 * under the terms of the GNU General Public License version 2 (the "GPL"), 9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 10 * following added to such license: 11 * 12 * As a special exception, the copyright holders of this software give you 13 * permission to link this software with independent modules, and to copy and 14 * distribute the resulting executable under terms of your choice, provided that 15 * you also meet, for each linked independent module, the terms and conditions of 16 * the license of that module. An independent module is a module which is not 17 * derived from this software. The special exception does not apply to any 18 * modifications of the software. 19 * 20 * Notwithstanding the above, under no circumstances may you combine this 21 * software in any way with any other Broadcom software provided under a license 22 * other than the GPL, without Broadcom's express prior written consent. 23 * 24 * 25 * <<Broadcom-WL-IPTag/Open:>> 26 * 27 * $Id: sbsocram.h 604712 2015-12-08 08:05:42Z $ 28 */ 29 30 #ifndef _SBSOCRAM_H 31 #define _SBSOCRAM_H 32 33 #ifndef _LANGUAGE_ASSEMBLY 34 35 /* cpp contortions to concatenate w/arg prescan */ 36 #ifndef PAD 37 #define _PADLINE(line) pad ## line 38 #define _XSTR(line) _PADLINE(line) 39 #define PAD _XSTR(__LINE__) 40 #endif /* PAD */ 41 42 /* Memcsocram core registers */ 43 typedef volatile struct sbsocramregs { 44 uint32 coreinfo; 45 uint32 bwalloc; 46 uint32 extracoreinfo; 47 uint32 biststat; 48 uint32 bankidx; 49 uint32 standbyctrl; 50 51 uint32 errlogstatus; /* rev 6 */ 52 uint32 errlogaddr; /* rev 6 */ 53 /* used for patching rev 3 & 5 */ 54 uint32 cambankidx; 55 uint32 cambankstandbyctrl; 56 uint32 cambankpatchctrl; 57 uint32 cambankpatchtblbaseaddr; 58 uint32 cambankcmdreg; 59 uint32 cambankdatareg; 60 uint32 cambankmaskreg; 61 uint32 PAD[1]; 62 uint32 bankinfo; /* corev 8 */ 63 uint32 bankpda; 64 uint32 PAD[14]; 65 uint32 extmemconfig; 66 uint32 extmemparitycsr; 67 uint32 extmemparityerrdata; 68 uint32 extmemparityerrcnt; 69 uint32 extmemwrctrlandsize; 70 uint32 PAD[84]; 71 uint32 workaround; 72 uint32 pwrctl; /* corerev >= 2 */ 73 uint32 PAD[133]; 74 uint32 sr_control; /* corerev >= 15 */ 75 uint32 sr_status; /* corerev >= 15 */ 76 uint32 sr_address; /* corerev >= 15 */ 77 uint32 sr_data; /* corerev >= 15 */ 78 } sbsocramregs_t; 79 80 #endif /* _LANGUAGE_ASSEMBLY */ 81 82 /* Register offsets */ 83 #define SR_COREINFO 0x00 84 #define SR_BWALLOC 0x04 85 #define SR_BISTSTAT 0x0c 86 #define SR_BANKINDEX 0x10 87 #define SR_BANKSTBYCTL 0x14 88 #define SR_PWRCTL 0x1e8 89 90 /* Coreinfo register */ 91 #define SRCI_PT_MASK 0x00070000 /* corerev >= 6; port type[18:16] */ 92 #define SRCI_PT_SHIFT 16 93 /* port types : SRCI_PT_<processorPT>_<backplanePT> */ 94 #define SRCI_PT_OCP_OCP 0 95 #define SRCI_PT_AXI_OCP 1 96 #define SRCI_PT_ARM7AHB_OCP 2 97 #define SRCI_PT_CM3AHB_OCP 3 98 #define SRCI_PT_AXI_AXI 4 99 #define SRCI_PT_AHB_AXI 5 100 /* corerev >= 3 */ 101 #define SRCI_LSS_MASK 0x00f00000 102 #define SRCI_LSS_SHIFT 20 103 #define SRCI_LRS_MASK 0x0f000000 104 #define SRCI_LRS_SHIFT 24 105 106 /* In corerev 0, the memory size is 2 to the power of the 107 * base plus 16 plus to the contents of the memsize field plus 1. 108 */ 109 #define SRCI_MS0_MASK 0xf 110 #define SR_MS0_BASE 16 111 112 /* 113 * In corerev 1 the bank size is 2 ^ the bank size field plus 14, 114 * the memory size is number of banks times bank size. 115 * The same applies to rom size. 116 */ 117 #define SRCI_ROMNB_MASK 0xf000 118 #define SRCI_ROMNB_SHIFT 12 119 #define SRCI_ROMBSZ_MASK 0xf00 120 #define SRCI_ROMBSZ_SHIFT 8 121 #define SRCI_SRNB_MASK 0xf0 122 #define SRCI_SRNB_SHIFT 4 123 #define SRCI_SRBSZ_MASK 0xf 124 #define SRCI_SRBSZ_SHIFT 0 125 126 #define SRCI_SRNB_MASK_EXT 0x100 127 128 #define SR_BSZ_BASE 14 129 130 /* Standby control register */ 131 #define SRSC_SBYOVR_MASK 0x80000000 132 #define SRSC_SBYOVR_SHIFT 31 133 #define SRSC_SBYOVRVAL_MASK 0x60000000 134 #define SRSC_SBYOVRVAL_SHIFT 29 135 #define SRSC_SBYEN_MASK 0x01000000 /* rev >= 3 */ 136 #define SRSC_SBYEN_SHIFT 24 137 138 /* Power control register */ 139 #define SRPC_PMU_STBYDIS_MASK 0x00000010 /* rev >= 3 */ 140 #define SRPC_PMU_STBYDIS_SHIFT 4 141 #define SRPC_STBYOVRVAL_MASK 0x00000008 142 #define SRPC_STBYOVRVAL_SHIFT 3 143 #define SRPC_STBYOVR_MASK 0x00000007 144 #define SRPC_STBYOVR_SHIFT 0 145 146 /* Extra core capability register */ 147 #define SRECC_NUM_BANKS_MASK 0x000000F0 148 #define SRECC_NUM_BANKS_SHIFT 4 149 #define SRECC_BANKSIZE_MASK 0x0000000F 150 #define SRECC_BANKSIZE_SHIFT 0 151 152 #define SRECC_BANKSIZE(value) (1 << (value)) 153 154 /* CAM bank patch control */ 155 #define SRCBPC_PATCHENABLE 0x80000000 156 157 #define SRP_ADDRESS 0x0001FFFC 158 #define SRP_VALID 0x8000 159 160 /* CAM bank command reg */ 161 #define SRCMD_WRITE 0x00020000 162 #define SRCMD_READ 0x00010000 163 #define SRCMD_DONE 0x80000000 164 165 #define SRCMD_DONE_DLY 1000 166 167 /* bankidx and bankinfo reg defines corerev >= 8 */ 168 #define SOCRAM_BANKINFO_SZMASK 0x7f 169 #define SOCRAM_BANKIDX_ROM_MASK 0x100 170 171 #define SOCRAM_BANKIDX_MEMTYPE_SHIFT 8 172 /* socram bankinfo memtype */ 173 #define SOCRAM_MEMTYPE_RAM 0 174 #define SOCRAM_MEMTYPE_R0M 1 175 #define SOCRAM_MEMTYPE_DEVRAM 2 176 177 #define SOCRAM_BANKINFO_REG 0x40 178 #define SOCRAM_BANKIDX_REG 0x10 179 #define SOCRAM_BANKINFO_STDBY_MASK 0x400 180 #define SOCRAM_BANKINFO_STDBY_TIMER 0x800 181 182 /* bankinfo rev >= 10 */ 183 #define SOCRAM_BANKINFO_DEVRAMSEL_SHIFT 13 184 #define SOCRAM_BANKINFO_DEVRAMSEL_MASK 0x2000 185 #define SOCRAM_BANKINFO_DEVRAMPRO_SHIFT 14 186 #define SOCRAM_BANKINFO_DEVRAMPRO_MASK 0x4000 187 #define SOCRAM_BANKINFO_SLPSUPP_SHIFT 15 188 #define SOCRAM_BANKINFO_SLPSUPP_MASK 0x8000 189 #define SOCRAM_BANKINFO_RETNTRAM_SHIFT 16 190 #define SOCRAM_BANKINFO_RETNTRAM_MASK 0x00010000 191 #define SOCRAM_BANKINFO_PDASZ_SHIFT 17 192 #define SOCRAM_BANKINFO_PDASZ_MASK 0x003E0000 193 #define SOCRAM_BANKINFO_DEVRAMREMAP_SHIFT 24 194 #define SOCRAM_BANKINFO_DEVRAMREMAP_MASK 0x01000000 195 196 /* extracoreinfo register */ 197 #define SOCRAM_DEVRAMBANK_MASK 0xF000 198 #define SOCRAM_DEVRAMBANK_SHIFT 12 199 200 /* bank info to calculate bank size */ 201 #define SOCRAM_BANKINFO_SZBASE 8192 202 #define SOCRAM_BANKSIZE_SHIFT 13 /* SOCRAM_BANKINFO_SZBASE */ 203 204 205 #endif /* _SBSOCRAM_H */ 206