1 /* 2 * SDIO spec header file 3 * Protocol and standard (common) device definitions 4 * 5 * Copyright (C) 1999-2017, Broadcom Corporation 6 * 7 * Unless you and Broadcom execute a separate written software license 8 * agreement governing use of this software, this software is licensed to you 9 * under the terms of the GNU General Public License version 2 (the "GPL"), 10 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 11 * following added to such license: 12 * 13 * As a special exception, the copyright holders of this software give you 14 * permission to link this software with independent modules, and to copy and 15 * distribute the resulting executable under terms of your choice, provided that 16 * you also meet, for each linked independent module, the terms and conditions of 17 * the license of that module. An independent module is a module which is not 18 * derived from this software. The special exception does not apply to any 19 * modifications of the software. 20 * 21 * Notwithstanding the above, under no circumstances may you combine this 22 * software in any way with any other Broadcom software provided under a license 23 * other than the GPL, without Broadcom's express prior written consent. 24 * 25 * 26 * <<Broadcom-WL-IPTag/Open:>> 27 * 28 * $Id: sdio.h 644725 2016-06-21 12:26:04Z $ 29 */ 30 31 #ifndef _SDIO_H 32 #define _SDIO_H 33 34 #ifdef BCMSDIO 35 36 /* CCCR structure for function 0 */ 37 typedef volatile struct { 38 uint8 cccr_sdio_rev; /* RO, cccr and sdio revision */ 39 uint8 sd_rev; /* RO, sd spec revision */ 40 uint8 io_en; /* I/O enable */ 41 uint8 io_rdy; /* I/O ready reg */ 42 uint8 intr_ctl; /* Master and per function interrupt enable control */ 43 uint8 intr_status; /* RO, interrupt pending status */ 44 uint8 io_abort; /* read/write abort or reset all functions */ 45 uint8 bus_inter; /* bus interface control */ 46 uint8 capability; /* RO, card capability */ 47 48 uint8 cis_base_low; /* 0x9 RO, common CIS base address, LSB */ 49 uint8 cis_base_mid; 50 uint8 cis_base_high; /* 0xB RO, common CIS base address, MSB */ 51 52 /* suspend/resume registers */ 53 uint8 bus_suspend; /* 0xC */ 54 uint8 func_select; /* 0xD */ 55 uint8 exec_flag; /* 0xE */ 56 uint8 ready_flag; /* 0xF */ 57 58 uint8 fn0_blk_size[2]; /* 0x10(LSB), 0x11(MSB) */ 59 60 uint8 power_control; /* 0x12 (SDIO version 1.10) */ 61 62 uint8 speed_control; /* 0x13 */ 63 } sdio_regs_t; 64 65 /* SDIO Device CCCR offsets */ 66 #define SDIOD_CCCR_REV 0x00 67 #define SDIOD_CCCR_SDREV 0x01 68 #define SDIOD_CCCR_IOEN 0x02 69 #define SDIOD_CCCR_IORDY 0x03 70 #define SDIOD_CCCR_INTEN 0x04 71 #define SDIOD_CCCR_INTPEND 0x05 72 #define SDIOD_CCCR_IOABORT 0x06 73 #define SDIOD_CCCR_BICTRL 0x07 74 #define SDIOD_CCCR_CAPABLITIES 0x08 75 #define SDIOD_CCCR_CISPTR_0 0x09 76 #define SDIOD_CCCR_CISPTR_1 0x0A 77 #define SDIOD_CCCR_CISPTR_2 0x0B 78 #define SDIOD_CCCR_BUSSUSP 0x0C 79 #define SDIOD_CCCR_FUNCSEL 0x0D 80 #define SDIOD_CCCR_EXECFLAGS 0x0E 81 #define SDIOD_CCCR_RDYFLAGS 0x0F 82 #define SDIOD_CCCR_BLKSIZE_0 0x10 83 #define SDIOD_CCCR_BLKSIZE_1 0x11 84 #define SDIOD_CCCR_POWER_CONTROL 0x12 85 #define SDIOD_CCCR_SPEED_CONTROL 0x13 86 #define SDIOD_CCCR_UHSI_SUPPORT 0x14 87 #define SDIOD_CCCR_DRIVER_STRENGTH 0x15 88 #define SDIOD_CCCR_INTR_EXTN 0x16 89 90 /* Broadcom extensions (corerev >= 1) */ 91 #define SDIOD_CCCR_BRCM_CARDCAP 0xf0 92 #define SDIOD_CCCR_BRCM_CARDCAP_CMD14_SUPPORT 0x02 93 #define SDIOD_CCCR_BRCM_CARDCAP_CMD14_EXT 0x04 94 #define SDIOD_CCCR_BRCM_CARDCAP_CMD_NODEC 0x08 95 #define SDIOD_CCCR_BRCM_CARDCTL 0xf1 96 #define SDIOD_CCCR_BRCM_SEPINT 0xf2 97 98 /* cccr_sdio_rev */ 99 #define SDIO_REV_SDIOID_MASK 0xf0 /* SDIO spec revision number */ 100 #define SDIO_REV_CCCRID_MASK 0x0f /* CCCR format version number */ 101 #define SDIO_SPEC_VERSION_3_0 0x40 /* SDIO spec version 3.0 */ 102 103 /* sd_rev */ 104 #define SD_REV_PHY_MASK 0x0f /* SD format version number */ 105 106 /* io_en */ 107 #define SDIO_FUNC_ENABLE_1 0x02 /* function 1 I/O enable */ 108 #define SDIO_FUNC_ENABLE_2 0x04 /* function 2 I/O enable */ 109 #if defined(BT_OVER_SDIO) 110 #define SDIO_FUNC_ENABLE_3 0x08 /* function 2 I/O enable */ 111 #define SDIO_FUNC_DISABLE_3 0xF0 /* function 2 I/O enable */ 112 #endif /* defined (BT_OVER_SDIO) */ 113 114 /* io_rdys */ 115 #define SDIO_FUNC_READY_1 0x02 /* function 1 I/O ready */ 116 #define SDIO_FUNC_READY_2 0x04 /* function 2 I/O ready */ 117 118 /* intr_ctl */ 119 #define INTR_CTL_MASTER_EN 0x1 /* interrupt enable master */ 120 #define INTR_CTL_FUNC1_EN 0x2 /* interrupt enable for function 1 */ 121 #define INTR_CTL_FUNC2_EN 0x4 /* interrupt enable for function 2 */ 122 #if defined(BT_OVER_SDIO) 123 #define INTR_CTL_FUNC3_EN 0x8 /* interrupt enable for function 3 */ 124 #endif /* defined (BT_OVER_SDIO) */ 125 /* intr_status */ 126 #define INTR_STATUS_FUNC1 0x2 /* interrupt pending for function 1 */ 127 #define INTR_STATUS_FUNC2 0x4 /* interrupt pending for function 2 */ 128 129 /* io_abort */ 130 #define IO_ABORT_RESET_ALL 0x08 /* I/O card reset */ 131 #define IO_ABORT_FUNC_MASK 0x07 /* abort selction: function x */ 132 133 /* bus_inter */ 134 #define BUS_CARD_DETECT_DIS 0x80 /* Card Detect disable */ 135 #define BUS_SPI_CONT_INTR_CAP 0x40 /* support continuous SPI interrupt */ 136 #define BUS_SPI_CONT_INTR_EN 0x20 /* continuous SPI interrupt enable */ 137 #define BUS_SD_DATA_WIDTH_MASK 0x03 /* bus width mask */ 138 #define BUS_SD_DATA_WIDTH_4BIT 0x02 /* bus width 4-bit mode */ 139 #define BUS_SD_DATA_WIDTH_1BIT 0x00 /* bus width 1-bit mode */ 140 141 /* capability */ 142 #define SDIO_CAP_4BLS 0x80 /* 4-bit support for low speed card */ 143 #define SDIO_CAP_LSC 0x40 /* low speed card */ 144 #define SDIO_CAP_E4MI 0x20 /* enable interrupt between block of data in 4-bit mode */ 145 #define SDIO_CAP_S4MI 0x10 /* support interrupt between block of data in 4-bit mode */ 146 #define SDIO_CAP_SBS 0x08 /* support suspend/resume */ 147 #define SDIO_CAP_SRW 0x04 /* support read wait */ 148 #define SDIO_CAP_SMB 0x02 /* support multi-block transfer */ 149 #define SDIO_CAP_SDC 0x01 /* Support Direct commands during multi-byte transfer */ 150 151 /* power_control */ 152 #define SDIO_POWER_SMPC 0x01 /* supports master power control (RO) */ 153 #define SDIO_POWER_EMPC 0x02 /* enable master power control (allow > 200mA) (RW) */ 154 155 /* speed_control (control device entry into high-speed clocking mode) */ 156 #define SDIO_SPEED_SHS 0x01 /* supports high-speed [clocking] mode (RO) */ 157 #define SDIO_SPEED_EHS 0x02 /* enable high-speed [clocking] mode (RW) */ 158 #define SDIO_SPEED_UHSI_DDR50 0x08 159 160 /* for setting bus speed in card: 0x13h */ 161 #define SDIO_BUS_SPEED_UHSISEL_M BITFIELD_MASK(3) 162 #define SDIO_BUS_SPEED_UHSISEL_S 1 163 164 /* for getting bus speed cap in card: 0x14h */ 165 #define SDIO_BUS_SPEED_UHSICAP_M BITFIELD_MASK(3) 166 #define SDIO_BUS_SPEED_UHSICAP_S 0 167 168 /* for getting driver type CAP in card: 0x15h */ 169 #define SDIO_BUS_DRVR_TYPE_CAP_M BITFIELD_MASK(3) 170 #define SDIO_BUS_DRVR_TYPE_CAP_S 0 171 172 /* for setting driver type selection in card: 0x15h */ 173 #define SDIO_BUS_DRVR_TYPE_SEL_M BITFIELD_MASK(2) 174 #define SDIO_BUS_DRVR_TYPE_SEL_S 4 175 176 /* for getting async int support in card: 0x16h */ 177 #define SDIO_BUS_ASYNCINT_CAP_M BITFIELD_MASK(1) 178 #define SDIO_BUS_ASYNCINT_CAP_S 0 179 180 /* for setting async int selection in card: 0x16h */ 181 #define SDIO_BUS_ASYNCINT_SEL_M BITFIELD_MASK(1) 182 #define SDIO_BUS_ASYNCINT_SEL_S 1 183 184 /* brcm sepint */ 185 #define SDIO_SEPINT_MASK 0x01 /* route sdpcmdev intr onto separate pad (chip-specific) */ 186 #define SDIO_SEPINT_OE 0x02 /* 1 asserts output enable for above pad */ 187 #define SDIO_SEPINT_ACT_HI 0x04 /* use active high interrupt level instead of active low */ 188 189 /* FBR structure for function 1-7, FBR addresses and register offsets */ 190 typedef volatile struct { 191 uint8 devctr; /* device interface, CSA control */ 192 uint8 ext_dev; /* extended standard I/O device type code */ 193 uint8 pwr_sel; /* power selection support */ 194 uint8 PAD[6]; /* reserved */ 195 196 uint8 cis_low; /* CIS LSB */ 197 uint8 cis_mid; 198 uint8 cis_high; /* CIS MSB */ 199 uint8 csa_low; /* code storage area, LSB */ 200 uint8 csa_mid; 201 uint8 csa_high; /* code storage area, MSB */ 202 uint8 csa_dat_win; /* data access window to function */ 203 204 uint8 fnx_blk_size[2]; /* block size, little endian */ 205 } sdio_fbr_t; 206 207 /* Maximum number of I/O funcs */ 208 #define SDIOD_MAX_FUNCS 8 209 #define SDIOD_MAX_IOFUNCS 7 210 211 /* SDIO Device FBR Start Address */ 212 #define SDIOD_FBR_STARTADDR 0x100 213 214 /* SDIO Device FBR Size */ 215 #define SDIOD_FBR_SIZE 0x100 216 217 /* Macro to calculate FBR register base */ 218 #define SDIOD_FBR_BASE(n) ((n) * 0x100) 219 220 /* Function register offsets */ 221 #define SDIOD_FBR_DEVCTR 0x00 /* basic info for function */ 222 #define SDIOD_FBR_EXT_DEV 0x01 /* extended I/O device code */ 223 #define SDIOD_FBR_PWR_SEL 0x02 /* power selection bits */ 224 225 /* SDIO Function CIS ptr offset */ 226 #define SDIOD_FBR_CISPTR_0 0x09 227 #define SDIOD_FBR_CISPTR_1 0x0A 228 #define SDIOD_FBR_CISPTR_2 0x0B 229 230 /* Code Storage Area pointer */ 231 #define SDIOD_FBR_CSA_ADDR_0 0x0C 232 #define SDIOD_FBR_CSA_ADDR_1 0x0D 233 #define SDIOD_FBR_CSA_ADDR_2 0x0E 234 #define SDIOD_FBR_CSA_DATA 0x0F 235 236 /* SDIO Function I/O Block Size */ 237 #define SDIOD_FBR_BLKSIZE_0 0x10 238 #define SDIOD_FBR_BLKSIZE_1 0x11 239 240 /* devctr */ 241 #define SDIOD_FBR_DEVCTR_DIC 0x0f /* device interface code */ 242 #define SDIOD_FBR_DECVTR_CSA 0x40 /* CSA support flag */ 243 #define SDIOD_FBR_DEVCTR_CSA_EN 0x80 /* CSA enabled */ 244 /* interface codes */ 245 #define SDIOD_DIC_NONE 0 /* SDIO standard interface is not supported */ 246 #define SDIOD_DIC_UART 1 247 #define SDIOD_DIC_BLUETOOTH_A 2 248 #define SDIOD_DIC_BLUETOOTH_B 3 249 #define SDIOD_DIC_GPS 4 250 #define SDIOD_DIC_CAMERA 5 251 #define SDIOD_DIC_PHS 6 252 #define SDIOD_DIC_WLAN 7 253 #define SDIOD_DIC_EXT 0xf /* extended device interface, read ext_dev register */ 254 255 /* pwr_sel */ 256 #define SDIOD_PWR_SEL_SPS 0x01 /* supports power selection */ 257 #define SDIOD_PWR_SEL_EPS 0x02 /* enable power selection (low-current mode) */ 258 259 /* misc defines */ 260 #define SDIO_FUNC_0 0 261 #define SDIO_FUNC_1 1 262 #define SDIO_FUNC_2 2 263 #define SDIO_FUNC_4 4 264 #define SDIO_FUNC_5 5 265 #define SDIO_FUNC_6 6 266 #define SDIO_FUNC_7 7 267 268 #define SD_CARD_TYPE_UNKNOWN 0 /* bad type or unrecognized */ 269 #define SD_CARD_TYPE_IO 1 /* IO only card */ 270 #define SD_CARD_TYPE_MEMORY 2 /* memory only card */ 271 #define SD_CARD_TYPE_COMBO 3 /* IO and memory combo card */ 272 273 #define SDIO_MAX_BLOCK_SIZE 2048 /* maximum block size for block mode operation */ 274 #define SDIO_MIN_BLOCK_SIZE 1 /* minimum block size for block mode operation */ 275 276 /* Card registers: status bit position */ 277 #define CARDREG_STATUS_BIT_OUTOFRANGE 31 278 #define CARDREG_STATUS_BIT_COMCRCERROR 23 279 #define CARDREG_STATUS_BIT_ILLEGALCOMMAND 22 280 #define CARDREG_STATUS_BIT_ERROR 19 281 #define CARDREG_STATUS_BIT_IOCURRENTSTATE3 12 282 #define CARDREG_STATUS_BIT_IOCURRENTSTATE2 11 283 #define CARDREG_STATUS_BIT_IOCURRENTSTATE1 10 284 #define CARDREG_STATUS_BIT_IOCURRENTSTATE0 9 285 #define CARDREG_STATUS_BIT_FUN_NUM_ERROR 4 286 287 288 289 #define SD_CMD_GO_IDLE_STATE 0 /* mandatory for SDIO */ 290 #define SD_CMD_SEND_OPCOND 1 291 #define SD_CMD_MMC_SET_RCA 3 292 #define SD_CMD_IO_SEND_OP_COND 5 /* mandatory for SDIO */ 293 #define SD_CMD_SELECT_DESELECT_CARD 7 294 #define SD_CMD_SEND_CSD 9 295 #define SD_CMD_SEND_CID 10 296 #define SD_CMD_STOP_TRANSMISSION 12 297 #define SD_CMD_SEND_STATUS 13 298 #define SD_CMD_GO_INACTIVE_STATE 15 299 #define SD_CMD_SET_BLOCKLEN 16 300 #define SD_CMD_READ_SINGLE_BLOCK 17 301 #define SD_CMD_READ_MULTIPLE_BLOCK 18 302 #define SD_CMD_WRITE_BLOCK 24 303 #define SD_CMD_WRITE_MULTIPLE_BLOCK 25 304 #define SD_CMD_PROGRAM_CSD 27 305 #define SD_CMD_SET_WRITE_PROT 28 306 #define SD_CMD_CLR_WRITE_PROT 29 307 #define SD_CMD_SEND_WRITE_PROT 30 308 #define SD_CMD_ERASE_WR_BLK_START 32 309 #define SD_CMD_ERASE_WR_BLK_END 33 310 #define SD_CMD_ERASE 38 311 #define SD_CMD_LOCK_UNLOCK 42 312 #define SD_CMD_IO_RW_DIRECT 52 /* mandatory for SDIO */ 313 #define SD_CMD_IO_RW_EXTENDED 53 /* mandatory for SDIO */ 314 #define SD_CMD_APP_CMD 55 315 #define SD_CMD_GEN_CMD 56 316 #define SD_CMD_READ_OCR 58 317 #define SD_CMD_CRC_ON_OFF 59 /* mandatory for SDIO */ 318 #define SD_ACMD_SD_STATUS 13 319 #define SD_ACMD_SEND_NUM_WR_BLOCKS 22 320 #define SD_ACMD_SET_WR_BLOCK_ERASE_CNT 23 321 #define SD_ACMD_SD_SEND_OP_COND 41 322 #define SD_ACMD_SET_CLR_CARD_DETECT 42 323 #define SD_ACMD_SEND_SCR 51 324 325 /* argument for SD_CMD_IO_RW_DIRECT and SD_CMD_IO_RW_EXTENDED */ 326 #define SD_IO_OP_READ 0 /* Read_Write: Read */ 327 #define SD_IO_OP_WRITE 1 /* Read_Write: Write */ 328 #define SD_IO_RW_NORMAL 0 /* no RAW */ 329 #define SD_IO_RW_RAW 1 /* RAW */ 330 #define SD_IO_BYTE_MODE 0 /* Byte Mode */ 331 #define SD_IO_BLOCK_MODE 1 /* BlockMode */ 332 #define SD_IO_FIXED_ADDRESS 0 /* fix Address */ 333 #define SD_IO_INCREMENT_ADDRESS 1 /* IncrementAddress */ 334 335 /* build SD_CMD_IO_RW_DIRECT Argument */ 336 #define SDIO_IO_RW_DIRECT_ARG(rw, raw, func, addr, data) \ 337 ((((rw) & 1) << 31) | (((func) & 0x7) << 28) | (((raw) & 1) << 27) | \ 338 (((addr) & 0x1FFFF) << 9) | ((data) & 0xFF)) 339 340 /* build SD_CMD_IO_RW_EXTENDED Argument */ 341 #define SDIO_IO_RW_EXTENDED_ARG(rw, blk, func, addr, inc_addr, count) \ 342 ((((rw) & 1) << 31) | (((func) & 0x7) << 28) | (((blk) & 1) << 27) | \ 343 (((inc_addr) & 1) << 26) | (((addr) & 0x1FFFF) << 9) | ((count) & 0x1FF)) 344 345 /* SDIO response parameters */ 346 #define SD_RSP_NO_NONE 0 347 #define SD_RSP_NO_1 1 348 #define SD_RSP_NO_2 2 349 #define SD_RSP_NO_3 3 350 #define SD_RSP_NO_4 4 351 #define SD_RSP_NO_5 5 352 #define SD_RSP_NO_6 6 353 354 /* Modified R6 response (to CMD3) */ 355 #define SD_RSP_MR6_COM_CRC_ERROR 0x8000 356 #define SD_RSP_MR6_ILLEGAL_COMMAND 0x4000 357 #define SD_RSP_MR6_ERROR 0x2000 358 359 /* Modified R1 in R4 Response (to CMD5) */ 360 #define SD_RSP_MR1_SBIT 0x80 361 #define SD_RSP_MR1_PARAMETER_ERROR 0x40 362 #define SD_RSP_MR1_RFU5 0x20 363 #define SD_RSP_MR1_FUNC_NUM_ERROR 0x10 364 #define SD_RSP_MR1_COM_CRC_ERROR 0x08 365 #define SD_RSP_MR1_ILLEGAL_COMMAND 0x04 366 #define SD_RSP_MR1_RFU1 0x02 367 #define SD_RSP_MR1_IDLE_STATE 0x01 368 369 /* R5 response (to CMD52 and CMD53) */ 370 #define SD_RSP_R5_COM_CRC_ERROR 0x80 371 #define SD_RSP_R5_ILLEGAL_COMMAND 0x40 372 #define SD_RSP_R5_IO_CURRENTSTATE1 0x20 373 #define SD_RSP_R5_IO_CURRENTSTATE0 0x10 374 #define SD_RSP_R5_ERROR 0x08 375 #define SD_RSP_R5_RFU 0x04 376 #define SD_RSP_R5_FUNC_NUM_ERROR 0x02 377 #define SD_RSP_R5_OUT_OF_RANGE 0x01 378 379 #define SD_RSP_R5_ERRBITS 0xCB 380 381 382 /* ------------------------------------------------ 383 * SDIO Commands and responses 384 * 385 * I/O only commands are: 386 * CMD0, CMD3, CMD5, CMD7, CMD14, CMD15, CMD52, CMD53 387 * ------------------------------------------------ 388 */ 389 390 /* SDIO Commands */ 391 #define SDIOH_CMD_0 0 392 #define SDIOH_CMD_3 3 393 #define SDIOH_CMD_5 5 394 #define SDIOH_CMD_7 7 395 #define SDIOH_CMD_11 11 396 #define SDIOH_CMD_14 14 397 #define SDIOH_CMD_15 15 398 #define SDIOH_CMD_19 19 399 #define SDIOH_CMD_52 52 400 #define SDIOH_CMD_53 53 401 #define SDIOH_CMD_59 59 402 403 /* SDIO Command Responses */ 404 #define SDIOH_RSP_NONE 0 405 #define SDIOH_RSP_R1 1 406 #define SDIOH_RSP_R2 2 407 #define SDIOH_RSP_R3 3 408 #define SDIOH_RSP_R4 4 409 #define SDIOH_RSP_R5 5 410 #define SDIOH_RSP_R6 6 411 412 /* 413 * SDIO Response Error flags 414 */ 415 #define SDIOH_RSP5_ERROR_FLAGS 0xCB 416 417 /* ------------------------------------------------ 418 * SDIO Command structures. I/O only commands are: 419 * 420 * CMD0, CMD3, CMD5, CMD7, CMD15, CMD52, CMD53 421 * ------------------------------------------------ 422 */ 423 424 #define CMD5_OCR_M BITFIELD_MASK(24) 425 #define CMD5_OCR_S 0 426 427 #define CMD5_S18R_M BITFIELD_MASK(1) 428 #define CMD5_S18R_S 24 429 430 #define CMD7_RCA_M BITFIELD_MASK(16) 431 #define CMD7_RCA_S 16 432 433 #define CMD14_RCA_M BITFIELD_MASK(16) 434 #define CMD14_RCA_S 16 435 #define CMD14_SLEEP_M BITFIELD_MASK(1) 436 #define CMD14_SLEEP_S 15 437 438 #define CMD_15_RCA_M BITFIELD_MASK(16) 439 #define CMD_15_RCA_S 16 440 441 #define CMD52_DATA_M BITFIELD_MASK(8) /* Bits [7:0] - Write Data/Stuff bits of CMD52 442 */ 443 #define CMD52_DATA_S 0 444 #define CMD52_REG_ADDR_M BITFIELD_MASK(17) /* Bits [25:9] - register address */ 445 #define CMD52_REG_ADDR_S 9 446 #define CMD52_RAW_M BITFIELD_MASK(1) /* Bit 27 - Read after Write flag */ 447 #define CMD52_RAW_S 27 448 #define CMD52_FUNCTION_M BITFIELD_MASK(3) /* Bits [30:28] - Function number */ 449 #define CMD52_FUNCTION_S 28 450 #define CMD52_RW_FLAG_M BITFIELD_MASK(1) /* Bit 31 - R/W flag */ 451 #define CMD52_RW_FLAG_S 31 452 453 454 #define CMD53_BYTE_BLK_CNT_M BITFIELD_MASK(9) /* Bits [8:0] - Byte/Block Count of CMD53 */ 455 #define CMD53_BYTE_BLK_CNT_S 0 456 #define CMD53_REG_ADDR_M BITFIELD_MASK(17) /* Bits [25:9] - register address */ 457 #define CMD53_REG_ADDR_S 9 458 #define CMD53_OP_CODE_M BITFIELD_MASK(1) /* Bit 26 - R/W Operation Code */ 459 #define CMD53_OP_CODE_S 26 460 #define CMD53_BLK_MODE_M BITFIELD_MASK(1) /* Bit 27 - Block Mode */ 461 #define CMD53_BLK_MODE_S 27 462 #define CMD53_FUNCTION_M BITFIELD_MASK(3) /* Bits [30:28] - Function number */ 463 #define CMD53_FUNCTION_S 28 464 #define CMD53_RW_FLAG_M BITFIELD_MASK(1) /* Bit 31 - R/W flag */ 465 #define CMD53_RW_FLAG_S 31 466 467 /* ------------------------------------------------------ 468 * SDIO Command Response structures for SD1 and SD4 modes 469 * ----------------------------------------------------- 470 */ 471 #define RSP4_IO_OCR_M BITFIELD_MASK(24) /* Bits [23:0] - Card's OCR Bits [23:0] */ 472 #define RSP4_IO_OCR_S 0 473 474 #define RSP4_S18A_M BITFIELD_MASK(1) /* Bits [23:0] - Card's OCR Bits [23:0] */ 475 #define RSP4_S18A_S 24 476 477 #define RSP4_STUFF_M BITFIELD_MASK(3) /* Bits [26:24] - Stuff bits */ 478 #define RSP4_STUFF_S 24 479 #define RSP4_MEM_PRESENT_M BITFIELD_MASK(1) /* Bit 27 - Memory present */ 480 #define RSP4_MEM_PRESENT_S 27 481 #define RSP4_NUM_FUNCS_M BITFIELD_MASK(3) /* Bits [30:28] - Number of I/O funcs */ 482 #define RSP4_NUM_FUNCS_S 28 483 #define RSP4_CARD_READY_M BITFIELD_MASK(1) /* Bit 31 - SDIO card ready */ 484 #define RSP4_CARD_READY_S 31 485 486 #define RSP6_STATUS_M BITFIELD_MASK(16) /* Bits [15:0] - Card status bits [19,22,23,12:0] 487 */ 488 #define RSP6_STATUS_S 0 489 #define RSP6_IO_RCA_M BITFIELD_MASK(16) /* Bits [31:16] - RCA bits[31-16] */ 490 #define RSP6_IO_RCA_S 16 491 492 #define RSP1_AKE_SEQ_ERROR_M BITFIELD_MASK(1) /* Bit 3 - Authentication seq error */ 493 #define RSP1_AKE_SEQ_ERROR_S 3 494 #define RSP1_APP_CMD_M BITFIELD_MASK(1) /* Bit 5 - Card expects ACMD */ 495 #define RSP1_APP_CMD_S 5 496 #define RSP1_READY_FOR_DATA_M BITFIELD_MASK(1) /* Bit 8 - Ready for data (buff empty) */ 497 #define RSP1_READY_FOR_DATA_S 8 498 #define RSP1_CURR_STATE_M BITFIELD_MASK(4) /* Bits [12:9] - State of card 499 * when Cmd was received 500 */ 501 #define RSP1_CURR_STATE_S 9 502 #define RSP1_EARSE_RESET_M BITFIELD_MASK(1) /* Bit 13 - Erase seq cleared */ 503 #define RSP1_EARSE_RESET_S 13 504 #define RSP1_CARD_ECC_DISABLE_M BITFIELD_MASK(1) /* Bit 14 - Card ECC disabled */ 505 #define RSP1_CARD_ECC_DISABLE_S 14 506 #define RSP1_WP_ERASE_SKIP_M BITFIELD_MASK(1) /* Bit 15 - Partial blocks erased due to W/P */ 507 #define RSP1_WP_ERASE_SKIP_S 15 508 #define RSP1_CID_CSD_OVERW_M BITFIELD_MASK(1) /* Bit 16 - Illegal write to CID or R/O bits 509 * of CSD 510 */ 511 #define RSP1_CID_CSD_OVERW_S 16 512 #define RSP1_ERROR_M BITFIELD_MASK(1) /* Bit 19 - General/Unknown error */ 513 #define RSP1_ERROR_S 19 514 #define RSP1_CC_ERROR_M BITFIELD_MASK(1) /* Bit 20 - Internal Card Control error */ 515 #define RSP1_CC_ERROR_S 20 516 #define RSP1_CARD_ECC_FAILED_M BITFIELD_MASK(1) /* Bit 21 - Card internal ECC failed 517 * to correct data 518 */ 519 #define RSP1_CARD_ECC_FAILED_S 21 520 #define RSP1_ILLEGAL_CMD_M BITFIELD_MASK(1) /* Bit 22 - Cmd not legal for the card state */ 521 #define RSP1_ILLEGAL_CMD_S 22 522 #define RSP1_COM_CRC_ERROR_M BITFIELD_MASK(1) /* Bit 23 - CRC check of previous command failed 523 */ 524 #define RSP1_COM_CRC_ERROR_S 23 525 #define RSP1_LOCK_UNLOCK_FAIL_M BITFIELD_MASK(1) /* Bit 24 - Card lock-unlock Cmd Seq error */ 526 #define RSP1_LOCK_UNLOCK_FAIL_S 24 527 #define RSP1_CARD_LOCKED_M BITFIELD_MASK(1) /* Bit 25 - Card locked by the host */ 528 #define RSP1_CARD_LOCKED_S 25 529 #define RSP1_WP_VIOLATION_M BITFIELD_MASK(1) /* Bit 26 - Attempt to program 530 * write-protected blocks 531 */ 532 #define RSP1_WP_VIOLATION_S 26 533 #define RSP1_ERASE_PARAM_M BITFIELD_MASK(1) /* Bit 27 - Invalid erase blocks */ 534 #define RSP1_ERASE_PARAM_S 27 535 #define RSP1_ERASE_SEQ_ERR_M BITFIELD_MASK(1) /* Bit 28 - Erase Cmd seq error */ 536 #define RSP1_ERASE_SEQ_ERR_S 28 537 #define RSP1_BLK_LEN_ERR_M BITFIELD_MASK(1) /* Bit 29 - Block length error */ 538 #define RSP1_BLK_LEN_ERR_S 29 539 #define RSP1_ADDR_ERR_M BITFIELD_MASK(1) /* Bit 30 - Misaligned address */ 540 #define RSP1_ADDR_ERR_S 30 541 #define RSP1_OUT_OF_RANGE_M BITFIELD_MASK(1) /* Bit 31 - Cmd arg was out of range */ 542 #define RSP1_OUT_OF_RANGE_S 31 543 544 545 #define RSP5_DATA_M BITFIELD_MASK(8) /* Bits [0:7] - data */ 546 #define RSP5_DATA_S 0 547 #define RSP5_FLAGS_M BITFIELD_MASK(8) /* Bit [15:8] - Rsp flags */ 548 #define RSP5_FLAGS_S 8 549 #define RSP5_STUFF_M BITFIELD_MASK(16) /* Bits [31:16] - Stuff bits */ 550 #define RSP5_STUFF_S 16 551 552 /* ---------------------------------------------- 553 * SDIO Command Response structures for SPI mode 554 * ---------------------------------------------- 555 */ 556 #define SPIRSP4_IO_OCR_M BITFIELD_MASK(16) /* Bits [15:0] - Card's OCR Bits [23:8] */ 557 #define SPIRSP4_IO_OCR_S 0 558 #define SPIRSP4_STUFF_M BITFIELD_MASK(3) /* Bits [18:16] - Stuff bits */ 559 #define SPIRSP4_STUFF_S 16 560 #define SPIRSP4_MEM_PRESENT_M BITFIELD_MASK(1) /* Bit 19 - Memory present */ 561 #define SPIRSP4_MEM_PRESENT_S 19 562 #define SPIRSP4_NUM_FUNCS_M BITFIELD_MASK(3) /* Bits [22:20] - Number of I/O funcs */ 563 #define SPIRSP4_NUM_FUNCS_S 20 564 #define SPIRSP4_CARD_READY_M BITFIELD_MASK(1) /* Bit 23 - SDIO card ready */ 565 #define SPIRSP4_CARD_READY_S 23 566 #define SPIRSP4_IDLE_STATE_M BITFIELD_MASK(1) /* Bit 24 - idle state */ 567 #define SPIRSP4_IDLE_STATE_S 24 568 #define SPIRSP4_ILLEGAL_CMD_M BITFIELD_MASK(1) /* Bit 26 - Illegal Cmd error */ 569 #define SPIRSP4_ILLEGAL_CMD_S 26 570 #define SPIRSP4_COM_CRC_ERROR_M BITFIELD_MASK(1) /* Bit 27 - COM CRC error */ 571 #define SPIRSP4_COM_CRC_ERROR_S 27 572 #define SPIRSP4_FUNC_NUM_ERROR_M BITFIELD_MASK(1) /* Bit 28 - Function number error 573 */ 574 #define SPIRSP4_FUNC_NUM_ERROR_S 28 575 #define SPIRSP4_PARAM_ERROR_M BITFIELD_MASK(1) /* Bit 30 - Parameter Error Bit */ 576 #define SPIRSP4_PARAM_ERROR_S 30 577 #define SPIRSP4_START_BIT_M BITFIELD_MASK(1) /* Bit 31 - Start Bit */ 578 #define SPIRSP4_START_BIT_S 31 579 580 #define SPIRSP5_DATA_M BITFIELD_MASK(8) /* Bits [23:16] - R/W Data */ 581 #define SPIRSP5_DATA_S 16 582 #define SPIRSP5_IDLE_STATE_M BITFIELD_MASK(1) /* Bit 24 - Idle state */ 583 #define SPIRSP5_IDLE_STATE_S 24 584 #define SPIRSP5_ILLEGAL_CMD_M BITFIELD_MASK(1) /* Bit 26 - Illegal Cmd error */ 585 #define SPIRSP5_ILLEGAL_CMD_S 26 586 #define SPIRSP5_COM_CRC_ERROR_M BITFIELD_MASK(1) /* Bit 27 - COM CRC error */ 587 #define SPIRSP5_COM_CRC_ERROR_S 27 588 #define SPIRSP5_FUNC_NUM_ERROR_M BITFIELD_MASK(1) /* Bit 28 - Function number error 589 */ 590 #define SPIRSP5_FUNC_NUM_ERROR_S 28 591 #define SPIRSP5_PARAM_ERROR_M BITFIELD_MASK(1) /* Bit 30 - Parameter Error Bit */ 592 #define SPIRSP5_PARAM_ERROR_S 30 593 #define SPIRSP5_START_BIT_M BITFIELD_MASK(1) /* Bit 31 - Start Bit */ 594 #define SPIRSP5_START_BIT_S 31 595 596 /* RSP6 card status format; Pg 68 Physical Layer spec v 1.10 */ 597 #define RSP6STAT_AKE_SEQ_ERROR_M BITFIELD_MASK(1) /* Bit 3 - Authentication seq error 598 */ 599 #define RSP6STAT_AKE_SEQ_ERROR_S 3 600 #define RSP6STAT_APP_CMD_M BITFIELD_MASK(1) /* Bit 5 - Card expects ACMD */ 601 #define RSP6STAT_APP_CMD_S 5 602 #define RSP6STAT_READY_FOR_DATA_M BITFIELD_MASK(1) /* Bit 8 - Ready for data 603 * (buff empty) 604 */ 605 #define RSP6STAT_READY_FOR_DATA_S 8 606 #define RSP6STAT_CURR_STATE_M BITFIELD_MASK(4) /* Bits [12:9] - Card state at 607 * Cmd reception 608 */ 609 #define RSP6STAT_CURR_STATE_S 9 610 #define RSP6STAT_ERROR_M BITFIELD_MASK(1) /* Bit 13 - General/Unknown error Bit 19 611 */ 612 #define RSP6STAT_ERROR_S 13 613 #define RSP6STAT_ILLEGAL_CMD_M BITFIELD_MASK(1) /* Bit 14 - Illegal cmd for 614 * card state Bit 22 615 */ 616 #define RSP6STAT_ILLEGAL_CMD_S 14 617 #define RSP6STAT_COM_CRC_ERROR_M BITFIELD_MASK(1) /* Bit 15 - CRC previous command 618 * failed Bit 23 619 */ 620 #define RSP6STAT_COM_CRC_ERROR_S 15 621 622 #define SDIOH_XFER_TYPE_READ SD_IO_OP_READ 623 #define SDIOH_XFER_TYPE_WRITE SD_IO_OP_WRITE 624 625 /* command issue options */ 626 #define CMD_OPTION_DEFAULT 0 627 #define CMD_OPTION_TUNING 1 628 629 #endif /* def BCMSDIO */ 630 #endif /* _SDIO_H */ 631