1 /*
2 * Misc utility routines for accessing the SOC Interconnects
3 * of Broadcom HNBU chips.
4 *
5 * Copyright (C) 1999-2017, Broadcom Corporation
6 *
7 * Unless you and Broadcom execute a separate written software license
8 * agreement governing use of this software, this software is licensed to you
9 * under the terms of the GNU General Public License version 2 (the "GPL"),
10 * available at http://www.broadcom.com/licenses/GPLv2.php, with the
11 * following added to such license:
12 *
13 * As a special exception, the copyright holders of this software give you
14 * permission to link this software with independent modules, and to copy and
15 * distribute the resulting executable under terms of your choice, provided that
16 * you also meet, for each linked independent module, the terms and conditions of
17 * the license of that module. An independent module is a module which is not
18 * derived from this software. The special exception does not apply to any
19 * modifications of the software.
20 *
21 * Notwithstanding the above, under no circumstances may you combine this
22 * software in any way with any other Broadcom software provided under a license
23 * other than the GPL, without Broadcom's express prior written consent.
24 *
25 *
26 * <<Broadcom-WL-IPTag/Open:>>
27 *
28 * $Id: siutils.h 668442 2016-11-03 08:42:43Z $
29 */
30
31 #ifndef _siutils_h_
32 #define _siutils_h_
33
34 #ifdef SR_DEBUG
35 #include "wlioctl.h"
36 #endif /* SR_DEBUG */
37
38
39 #define WARM_BOOT 0xA0B0C0D0
40
41 #ifdef BCM_BACKPLANE_TIMEOUT
42
43 #define SI_MAX_ERRLOG_SIZE 4
44 typedef struct si_axi_error
45 {
46 uint32 error;
47 uint32 coreid;
48 uint32 errlog_lo;
49 uint32 errlog_hi;
50 uint32 errlog_id;
51 uint32 errlog_flags;
52 uint32 errlog_status;
53 } si_axi_error_t;
54
55 typedef struct si_axi_error_info
56 {
57 uint32 count;
58 si_axi_error_t axi_error[SI_MAX_ERRLOG_SIZE];
59 } si_axi_error_info_t;
60 #endif /* BCM_BACKPLANE_TIMEOUT */
61
62 /**
63 * Data structure to export all chip specific common variables
64 * public (read-only) portion of siutils handle returned by si_attach()/si_kattach()
65 */
66 struct si_pub {
67 uint socitype; /**< SOCI_SB, SOCI_AI */
68
69 uint bustype; /**< SI_BUS, PCI_BUS */
70 uint buscoretype; /**< PCI_CORE_ID, PCIE_CORE_ID, PCMCIA_CORE_ID */
71 uint buscorerev; /**< buscore rev */
72 uint buscoreidx; /**< buscore index */
73 int ccrev; /**< chip common core rev */
74 uint32 cccaps; /**< chip common capabilities */
75 uint32 cccaps_ext; /**< chip common capabilities extension */
76 int pmurev; /**< pmu core rev */
77 uint32 pmucaps; /**< pmu capabilities */
78 uint boardtype; /**< board type */
79 uint boardrev; /* board rev */
80 uint boardvendor; /**< board vendor */
81 uint boardflags; /**< board flags */
82 uint boardflags2; /**< board flags2 */
83 uint chip; /**< chip number */
84 uint chiprev; /**< chip revision */
85 uint chippkg; /**< chip package option */
86 uint32 chipst; /**< chip status */
87 bool issim; /**< chip is in simulation or emulation */
88 uint socirev; /**< SOC interconnect rev */
89 bool pci_pr32414;
90 int gcirev; /**< gci core rev */
91 #ifdef BCM_BACKPLANE_TIMEOUT
92 si_axi_error_info_t * err_info;
93 #endif /* BCM_BACKPLANE_TIMEOUT */
94 };
95
96 /* for HIGH_ONLY driver, the si_t must be writable to allow states sync from BMAC to HIGH driver
97 * for monolithic driver, it is readonly to prevent accident change
98 */
99 typedef const struct si_pub si_t;
100
101 /*
102 * Many of the routines below take an 'sih' handle as their first arg.
103 * Allocate this by calling si_attach(). Free it by calling si_detach().
104 * At any one time, the sih is logically focused on one particular si core
105 * (the "current core").
106 * Use si_setcore() or si_setcoreidx() to change the association to another core.
107 */
108 #define SI_OSH NULL /**< Use for si_kattach when no osh is available */
109
110 #define BADIDX (SI_MAXCORES + 1)
111
112 /* clkctl xtal what flags */
113 #define XTAL 0x1 /**< primary crystal oscillator (2050) */
114 #define PLL 0x2 /**< main chip pll */
115
116 /* clkctl clk mode */
117 #define CLK_FAST 0 /**< force fast (pll) clock */
118 #define CLK_DYNAMIC 2 /**< enable dynamic clock control */
119
120 /* GPIO usage priorities */
121 #define GPIO_DRV_PRIORITY 0 /**< Driver */
122 #define GPIO_APP_PRIORITY 1 /**< Application */
123 #define GPIO_HI_PRIORITY 2 /**< Highest priority. Ignore GPIO reservation */
124
125 /* GPIO pull up/down */
126 #define GPIO_PULLUP 0
127 #define GPIO_PULLDN 1
128
129 /* GPIO event regtype */
130 #define GPIO_REGEVT 0 /**< GPIO register event */
131 #define GPIO_REGEVT_INTMSK 1 /**< GPIO register event int mask */
132 #define GPIO_REGEVT_INTPOL 2 /**< GPIO register event int polarity */
133
134 /* device path */
135 #define SI_DEVPATH_BUFSZ 16 /**< min buffer size in bytes */
136
137 /* SI routine enumeration: to be used by update function with multiple hooks */
138 #define SI_DOATTACH 1
139 #define SI_PCIDOWN 2 /**< wireless interface is down */
140 #define SI_PCIUP 3 /**< wireless interface is up */
141
142 #ifdef SR_DEBUG
143 #define PMU_RES 31
144 #endif /* SR_DEBUG */
145
146 /* "access" param defines for si_seci_access() below */
147 #define SECI_ACCESS_STATUSMASK_SET 0
148 #define SECI_ACCESS_INTRS 1
149 #define SECI_ACCESS_UART_CTS 2
150 #define SECI_ACCESS_UART_RTS 3
151 #define SECI_ACCESS_UART_RXEMPTY 4
152 #define SECI_ACCESS_UART_GETC 5
153 #define SECI_ACCESS_UART_TXFULL 6
154 #define SECI_ACCESS_UART_PUTC 7
155 #define SECI_ACCESS_STATUSMASK_GET 8
156
157 #define ISSIM_ENAB(sih) FALSE
158
159 #define INVALID_ADDR (~0)
160
161 /* PMU clock/power control */
162 #if defined(BCMPMUCTL)
163 #define PMUCTL_ENAB(sih) (BCMPMUCTL)
164 #else
165 #define PMUCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PMU)
166 #endif
167
168 #if defined(BCMAOBENAB)
169 #define AOB_ENAB(sih) (BCMAOBENAB)
170 #else
171 #define AOB_ENAB(sih) ((sih)->ccrev >= 35 ? \
172 ((sih)->cccaps_ext & CC_CAP_EXT_AOB_PRESENT) : 0)
173 #endif /* BCMAOBENAB */
174
175 /* chipcommon clock/power control (exclusive with PMU's) */
176 #if defined(BCMPMUCTL) && BCMPMUCTL
177 #define CCCTL_ENAB(sih) (0)
178 #define CCPLL_ENAB(sih) (0)
179 #else
180 #define CCCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PWR_CTL)
181 #define CCPLL_ENAB(sih) ((sih)->cccaps & CC_CAP_PLL_MASK)
182 #endif
183
184 typedef void (*gci_gpio_handler_t)(uint32 stat, void *arg);
185
186 /* External BT Coex enable mask */
187 #define CC_BTCOEX_EN_MASK 0x01
188 /* External PA enable mask */
189 #define GPIO_CTRL_EPA_EN_MASK 0x40
190 /* WL/BT control enable mask */
191 #define GPIO_CTRL_5_6_EN_MASK 0x60
192 #define GPIO_CTRL_7_6_EN_MASK 0xC0
193 #define GPIO_OUT_7_EN_MASK 0x80
194
195
196
197 /* CR4 specific defines used by the host driver */
198 #define SI_CR4_CAP (0x04)
199 #define SI_CR4_BANKIDX (0x40)
200 #define SI_CR4_BANKINFO (0x44)
201 #define SI_CR4_BANKPDA (0x4C)
202
203 #define ARMCR4_TCBBNB_MASK 0xf0
204 #define ARMCR4_TCBBNB_SHIFT 4
205 #define ARMCR4_TCBANB_MASK 0xf
206 #define ARMCR4_TCBANB_SHIFT 0
207
208 #define SICF_CPUHALT (0x0020)
209 #define ARMCR4_BSZ_MASK 0x3f
210 #define ARMCR4_BSZ_MULT 8192
211 #define SI_BPIND_1BYTE 0x1
212 #define SI_BPIND_2BYTE 0x3
213 #define SI_BPIND_4BYTE 0xF
214 #include <osl_decl.h>
215 /* === exported functions === */
216 extern si_t *si_attach(uint pcidev, osl_t *osh, volatile void *regs, uint bustype,
217 void *sdh, char **vars, uint *varsz);
218 extern si_t *si_kattach(osl_t *osh);
219 extern void si_detach(si_t *sih);
220 extern bool si_pci_war16165(si_t *sih);
221 extern volatile void *
222 si_d11_switch_addrbase(si_t *sih, uint coreunit);
223 extern uint si_corelist(si_t *sih, uint coreid[]);
224 extern uint si_coreid(si_t *sih);
225 extern uint si_flag(si_t *sih);
226 extern uint si_flag_alt(si_t *sih);
227 extern uint si_intflag(si_t *sih);
228 extern uint si_coreidx(si_t *sih);
229 extern uint si_coreunit(si_t *sih);
230 extern uint si_corevendor(si_t *sih);
231 extern uint si_corerev(si_t *sih);
232 extern void *si_osh(si_t *sih);
233 extern void si_setosh(si_t *sih, osl_t *osh);
234 extern uint si_backplane_access(si_t *sih, uint addr, uint size,
235 uint *val, bool read);
236 extern uint si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
237 extern uint si_pmu_corereg(si_t *sih, uint32 idx, uint regoff, uint mask, uint val);
238 extern volatile uint32 *si_corereg_addr(si_t *sih, uint coreidx, uint regoff);
239 extern volatile void *si_coreregs(si_t *sih);
240 extern uint si_wrapperreg(si_t *sih, uint32 offset, uint32 mask, uint32 val);
241 extern uint si_core_wrapperreg(si_t *sih, uint32 coreidx, uint32 offset, uint32 mask, uint32 val);
242 extern void *si_wrapperregs(si_t *sih);
243 extern uint32 si_core_cflags(si_t *sih, uint32 mask, uint32 val);
244 extern void si_core_cflags_wo(si_t *sih, uint32 mask, uint32 val);
245 extern uint32 si_core_sflags(si_t *sih, uint32 mask, uint32 val);
246 extern void si_commit(si_t *sih);
247 extern bool si_iscoreup(si_t *sih);
248 extern uint si_numcoreunits(si_t *sih, uint coreid);
249 extern uint si_numd11coreunits(si_t *sih);
250 extern uint si_findcoreidx(si_t *sih, uint coreid, uint coreunit);
251 extern volatile void *si_setcoreidx(si_t *sih, uint coreidx);
252 extern volatile void *si_setcore(si_t *sih, uint coreid, uint coreunit);
253 extern volatile void *si_switch_core(si_t *sih, uint coreid, uint *origidx, uint *intr_val);
254 extern void si_restore_core(si_t *sih, uint coreid, uint intr_val);
255 extern int si_numaddrspaces(si_t *sih);
256 extern uint32 si_addrspace(si_t *sih, uint asidx);
257 extern uint32 si_addrspacesize(si_t *sih, uint asidx);
258 extern void si_coreaddrspaceX(si_t *sih, uint asidx, uint32 *addr, uint32 *size);
259 extern int si_corebist(si_t *sih);
260 extern void si_core_reset(si_t *sih, uint32 bits, uint32 resetbits);
261 extern void si_core_disable(si_t *sih, uint32 bits);
262 extern uint32 si_clock_rate(uint32 pll_type, uint32 n, uint32 m);
263 extern uint si_chip_hostif(si_t *sih);
264 extern bool si_read_pmu_autopll(si_t *sih);
265 extern uint32 si_clock(si_t *sih);
266 extern uint32 si_alp_clock(si_t *sih); /* returns [Hz] units */
267 extern uint32 si_ilp_clock(si_t *sih); /* returns [Hz] units */
268 extern void si_pci_setup(si_t *sih, uint coremask);
269 extern void si_pcmcia_init(si_t *sih);
270 extern void si_setint(si_t *sih, int siflag);
271 extern bool si_backplane64(si_t *sih);
272 extern void si_register_intr_callback(si_t *sih, void *intrsoff_fn, void *intrsrestore_fn,
273 void *intrsenabled_fn, void *intr_arg);
274 extern void si_deregister_intr_callback(si_t *sih);
275 extern void si_clkctl_init(si_t *sih);
276 extern uint16 si_clkctl_fast_pwrup_delay(si_t *sih);
277 extern bool si_clkctl_cc(si_t *sih, uint mode);
278 extern int si_clkctl_xtal(si_t *sih, uint what, bool on);
279 extern uint32 si_gpiotimerval(si_t *sih, uint32 mask, uint32 val);
280 extern void si_btcgpiowar(si_t *sih);
281 extern bool si_deviceremoved(si_t *sih);
282 extern void si_set_device_removed(si_t *sih, bool status);
283 extern uint32 si_sysmem_size(si_t *sih);
284 extern uint32 si_socram_size(si_t *sih);
285 extern uint32 si_socdevram_size(si_t *sih);
286 extern uint32 si_socram_srmem_size(si_t *sih);
287 extern void si_socram_set_bankpda(si_t *sih, uint32 bankidx, uint32 bankpda);
288 extern void si_socdevram(si_t *sih, bool set, uint8 *ennable, uint8 *protect, uint8 *remap);
289 extern bool si_socdevram_pkg(si_t *sih);
290 extern bool si_socdevram_remap_isenb(si_t *sih);
291 extern uint32 si_socdevram_remap_size(si_t *sih);
292
293 extern void si_watchdog(si_t *sih, uint ticks);
294 extern void si_watchdog_ms(si_t *sih, uint32 ms);
295 extern uint32 si_watchdog_msticks(void);
296 extern volatile void *si_gpiosetcore(si_t *sih);
297 extern uint32 si_gpiocontrol(si_t *sih, uint32 mask, uint32 val, uint8 priority);
298 extern uint32 si_gpioouten(si_t *sih, uint32 mask, uint32 val, uint8 priority);
299 extern uint32 si_gpioout(si_t *sih, uint32 mask, uint32 val, uint8 priority);
300 extern uint32 si_gpioin(si_t *sih);
301 extern uint32 si_gpiointpolarity(si_t *sih, uint32 mask, uint32 val, uint8 priority);
302 extern uint32 si_gpiointmask(si_t *sih, uint32 mask, uint32 val, uint8 priority);
303 extern uint32 si_gpioeventintmask(si_t *sih, uint32 mask, uint32 val, uint8 priority);
304 extern uint32 si_gpioled(si_t *sih, uint32 mask, uint32 val);
305 extern uint32 si_gpioreserve(si_t *sih, uint32 gpio_num, uint8 priority);
306 extern uint32 si_gpiorelease(si_t *sih, uint32 gpio_num, uint8 priority);
307 extern uint32 si_gpiopull(si_t *sih, bool updown, uint32 mask, uint32 val);
308 extern uint32 si_gpioevent(si_t *sih, uint regtype, uint32 mask, uint32 val);
309 extern uint32 si_gpio_int_enable(si_t *sih, bool enable);
310 extern void si_gci_uart_init(si_t *sih, osl_t *osh, uint8 seci_mode);
311 extern void si_gci_enable_gpio(si_t *sih, uint8 gpio, uint32 mask, uint32 value);
312 extern uint8 si_gci_host_wake_gpio_init(si_t *sih);
313 extern void si_gci_host_wake_gpio_enable(si_t *sih, uint8 gpio, bool state);
314
315 extern void si_invalidate_second_bar0win(si_t *sih);
316
317 /* GCI interrupt handlers */
318 extern void si_gci_handler_process(si_t *sih);
319
320 /* GCI GPIO event handlers */
321 extern void *si_gci_gpioint_handler_register(si_t *sih, uint8 gpio, uint8 sts,
322 gci_gpio_handler_t cb, void *arg);
323 extern void si_gci_gpioint_handler_unregister(si_t *sih, void* gci_i);
324 extern uint8 si_gci_gpio_status(si_t *sih, uint8 gci_gpio, uint8 mask, uint8 value);
325
326 /* Wake-on-wireless-LAN (WOWL) */
327 extern bool si_pci_pmecap(si_t *sih);
328 extern bool si_pci_fastpmecap(struct osl_info *osh);
329 extern bool si_pci_pmestat(si_t *sih);
330 extern void si_pci_pmeclr(si_t *sih);
331 extern void si_pci_pmeen(si_t *sih);
332 extern void si_pci_pmestatclr(si_t *sih);
333 extern uint si_pcie_readreg(void *sih, uint addrtype, uint offset);
334 extern uint si_pcie_writereg(void *sih, uint addrtype, uint offset, uint val);
335 extern void si_deepsleep_count(si_t *sih, bool arm_wakeup);
336
337
338 #ifdef BCMSDIO
339 extern void si_sdio_init(si_t *sih);
340 #endif
341
342 extern uint16 si_d11_devid(si_t *sih);
343 extern int si_corepciid(si_t *sih, uint func, uint16 *pcivendor, uint16 *pcidevice,
344 uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif, uint8 *pciheader);
345
346 extern uint32 si_seci_access(si_t *sih, uint32 val, int access);
347 extern volatile void* si_seci_init(si_t *sih, uint8 seci_mode);
348 extern void si_seci_clk_force(si_t *sih, bool val);
349 extern bool si_seci_clk_force_status(si_t *sih);
350
351 #define si_eci(sih) 0
si_eci_init(si_t * sih)352 static INLINE void * si_eci_init(si_t *sih) {return NULL;}
353 #define si_eci_notify_bt(sih, type, val) (0)
354 #define si_seci(sih) 0
355 #define si_seci_upd(sih, a) do {} while (0)
si_gci_init(si_t * sih)356 static INLINE void * si_gci_init(si_t *sih) {return NULL;}
357 #define si_seci_down(sih) do {} while (0)
358 #define si_gci(sih) 0
359
360 /* OTP status */
361 extern bool si_is_otp_disabled(si_t *sih);
362 extern bool si_is_otp_powered(si_t *sih);
363 extern void si_otp_power(si_t *sih, bool on, uint32* min_res_mask);
364
365 /* SPROM availability */
366 extern bool si_is_sprom_available(si_t *sih);
367
368 /* OTP/SROM CIS stuff */
369 extern int si_cis_source(si_t *sih);
370 #define CIS_DEFAULT 0
371 #define CIS_SROM 1
372 #define CIS_OTP 2
373
374 /* Fab-id information */
375 #define DEFAULT_FAB 0x0 /**< Original/first fab used for this chip */
376 #define CSM_FAB7 0x1 /**< CSM Fab7 chip */
377 #define TSMC_FAB12 0x2 /**< TSMC Fab12/Fab14 chip */
378 #define SMIC_FAB4 0x3 /**< SMIC Fab4 chip */
379
380 extern int si_otp_fabid(si_t *sih, uint16 *fabid, bool rw);
381 extern uint16 si_fabid(si_t *sih);
382 extern uint16 si_chipid(si_t *sih);
383
384 /*
385 * Build device path. Path size must be >= SI_DEVPATH_BUFSZ.
386 * The returned path is NULL terminated and has trailing '/'.
387 * Return 0 on success, nonzero otherwise.
388 */
389 extern int si_devpath(si_t *sih, char *path, int size);
390 extern int si_devpath_pcie(si_t *sih, char *path, int size);
391 /* Read variable with prepending the devpath to the name */
392 extern char *si_getdevpathvar(si_t *sih, const char *name);
393 extern int si_getdevpathintvar(si_t *sih, const char *name);
394 extern char *si_coded_devpathvar(si_t *sih, char *varname, int var_len, const char *name);
395
396
397 extern uint8 si_pcieclkreq(si_t *sih, uint32 mask, uint32 val);
398 extern uint32 si_pcielcreg(si_t *sih, uint32 mask, uint32 val);
399 extern uint8 si_pcieltrenable(si_t *sih, uint32 mask, uint32 val);
400 extern uint8 si_pcieobffenable(si_t *sih, uint32 mask, uint32 val);
401 extern uint32 si_pcieltr_reg(si_t *sih, uint32 reg, uint32 mask, uint32 val);
402 extern uint32 si_pcieltrspacing_reg(si_t *sih, uint32 mask, uint32 val);
403 extern uint32 si_pcieltrhysteresiscnt_reg(si_t *sih, uint32 mask, uint32 val);
404 extern void si_pcie_set_error_injection(si_t *sih, uint32 mode);
405 extern void si_pcie_set_L1substate(si_t *sih, uint32 substate);
406 extern uint32 si_pcie_get_L1substate(si_t *sih);
407 extern void si_war42780_clkreq(si_t *sih, bool clkreq);
408 extern void si_pci_down(si_t *sih);
409 extern void si_pci_up(si_t *sih);
410 extern void si_pci_sleep(si_t *sih);
411 extern void si_pcie_war_ovr_update(si_t *sih, uint8 aspm);
412 extern void si_pcie_power_save_enable(si_t *sih, bool enable);
413 extern void si_pcie_extendL1timer(si_t *sih, bool extend);
414 extern int si_pci_fixcfg(si_t *sih);
415 extern void si_chippkg_set(si_t *sih, uint);
416 extern bool si_is_warmboot(void);
417
418 extern void si_chipcontrl_btshd0_4331(si_t *sih, bool on);
419 extern void si_chipcontrl_restore(si_t *sih, uint32 val);
420 extern uint32 si_chipcontrl_read(si_t *sih);
421 extern void si_chipcontrl_epa4331(si_t *sih, bool on);
422 extern void si_chipcontrl_epa4331_wowl(si_t *sih, bool enter_wowl);
423 extern void si_chipcontrl_srom4360(si_t *sih, bool on);
424 extern void si_clk_srom4365(si_t *sih);
425 /* Enable BT-COEX & Ex-PA for 4313 */
426 extern void si_epa_4313war(si_t *sih);
427 extern void si_btc_enable_chipcontrol(si_t *sih);
428 /* BT/WL selection for 4313 bt combo >= P250 boards */
429 extern void si_btcombo_p250_4313_war(si_t *sih);
430 extern void si_btcombo_43228_war(si_t *sih);
431 extern void si_clk_pmu_htavail_set(si_t *sih, bool set_clear);
432 extern void si_pmu_avb_clk_set(si_t *sih, osl_t *osh, bool set_flag);
433 extern void si_pmu_synth_pwrsw_4313_war(si_t *sih);
434 extern uint si_pll_reset(si_t *sih);
435 /* === debug routines === */
436
437 extern bool si_taclear(si_t *sih, bool details);
438
439 #if defined(BCMDBG_PHYDUMP)
440 struct bcmstrbuf;
441 extern int si_dump_pcieinfo(si_t *sih, struct bcmstrbuf *b);
442 extern void si_dump_pmuregs(si_t *sih, struct bcmstrbuf *b);
443 extern int si_dump_pcieregs(si_t *sih, struct bcmstrbuf *b);
444 #endif
445
446 #if defined(BCMDBG_PHYDUMP)
447 extern void si_dumpregs(si_t *sih, struct bcmstrbuf *b);
448 #endif
449
450 extern uint32 si_ccreg(si_t *sih, uint32 offset, uint32 mask, uint32 val);
451 extern uint32 si_pciereg(si_t *sih, uint32 offset, uint32 mask, uint32 val, uint type);
452 extern int si_bpind_access(si_t *sih, uint32 addr_high, uint32 addr_low,
453 int32* data, bool read);
454 #ifdef SR_DEBUG
455 extern void si_dump_pmu(si_t *sih, void *pmu_var);
456 extern void si_pmu_keep_on(si_t *sih, int32 int_val);
457 extern uint32 si_pmu_keep_on_get(si_t *sih);
458 extern uint32 si_power_island_set(si_t *sih, uint32 int_val);
459 extern uint32 si_power_island_get(si_t *sih);
460 #endif /* SR_DEBUG */
461 extern uint32 si_pcieserdesreg(si_t *sih, uint32 mdioslave, uint32 offset, uint32 mask, uint32 val);
462 extern void si_pcie_set_request_size(si_t *sih, uint16 size);
463 extern uint16 si_pcie_get_request_size(si_t *sih);
464 extern void si_pcie_set_maxpayload_size(si_t *sih, uint16 size);
465 extern uint16 si_pcie_get_maxpayload_size(si_t *sih);
466 extern uint16 si_pcie_get_ssid(si_t *sih);
467 extern uint32 si_pcie_get_bar0(si_t *sih);
468 extern int si_pcie_configspace_cache(si_t *sih);
469 extern int si_pcie_configspace_restore(si_t *sih);
470 extern int si_pcie_configspace_get(si_t *sih, uint8 *buf, uint size);
471
472
473 #ifdef BCM_BACKPLANE_TIMEOUT
474 extern const si_axi_error_info_t * si_get_axi_errlog_info(si_t *sih);
475 extern void si_reset_axi_errlog_info(si_t * sih);
476 #endif /* BCM_BACKPLANE_TIMEOUT */
477
478 extern uint32 si_tcm_size(si_t *sih);
479 extern bool si_has_flops(si_t *sih);
480
481 extern int si_set_sromctl(si_t *sih, uint32 value);
482 extern uint32 si_get_sromctl(si_t *sih);
483
484 extern uint32 si_gci_direct(si_t *sih, uint offset, uint32 mask, uint32 val);
485 extern uint32 si_gci_indirect(si_t *sih, uint regidx, uint offset, uint32 mask, uint32 val);
486 extern uint32 si_gci_output(si_t *sih, uint reg, uint32 mask, uint32 val);
487 extern uint32 si_gci_input(si_t *sih, uint reg);
488 extern uint32 si_gci_int_enable(si_t *sih, bool enable);
489 extern void si_gci_reset(si_t *sih);
490 #ifdef BCMLTECOEX
491 extern void si_gci_seci_init(si_t *sih);
492 extern void si_ercx_init(si_t *sih, uint32 ltecx_mux, uint32 ltecx_padnum,
493 uint32 ltecx_fnsel, uint32 ltecx_gcigpio);
494 #endif /* BCMLTECOEX */
495 extern void si_wci2_init(si_t *sih, uint8 baudrate, uint32 ltecx_mux, uint32 ltecx_padnum,
496 uint32 ltecx_fnsel, uint32 ltecx_gcigpio);
497
498 extern bool si_btcx_wci2_init(si_t *sih);
499
500 extern void si_gci_set_functionsel(si_t *sih, uint32 pin, uint8 fnsel);
501 extern uint32 si_gci_get_functionsel(si_t *sih, uint32 pin);
502 extern void si_gci_clear_functionsel(si_t *sih, uint8 fnsel);
503 extern uint8 si_gci_get_chipctrlreg_idx(uint32 pin, uint32 *regidx, uint32 *pos);
504 extern uint32 si_gci_chipcontrol(si_t *sih, uint reg, uint32 mask, uint32 val);
505 extern uint32 si_gci_chipstatus(si_t *sih, uint reg);
506 extern uint8 si_enable_device_wake(si_t *sih, uint8 *wake_status, uint8 *cur_status);
507 extern void si_swdenable(si_t *sih, uint32 swdflag);
508 extern uint8 si_enable_perst_wake(si_t *sih, uint8 *perst_wake_mask, uint8 *perst_cur_status);
509
510 extern uint32 si_get_pmu_reg_addr(si_t *sih, uint32 offset);
511 #define CHIPCTRLREG1 0x1
512 #define CHIPCTRLREG2 0x2
513 #define CHIPCTRLREG3 0x3
514 #define CHIPCTRLREG4 0x4
515 #define CHIPCTRLREG5 0x5
516 #define MINRESMASKREG 0x618
517 #define MAXRESMASKREG 0x61c
518 #define CHIPCTRLADDR 0x650
519 #define CHIPCTRLDATA 0x654
520 #define RSRCTABLEADDR 0x620
521 #define RSRCUPDWNTIME 0x628
522 #define PMUREG_RESREQ_MASK 0x68c
523
524 void si_update_masks(si_t *sih);
525 void si_force_islanding(si_t *sih, bool enable);
526 extern uint32 si_pmu_res_req_timer_clr(si_t *sih);
527 extern void si_pmu_rfldo(si_t *sih, bool on);
528 extern void si_survive_perst_war(si_t *sih, bool reset, uint32 sperst_mask, uint32 spert_val);
529 extern uint32 si_pcie_set_ctrlreg(si_t *sih, uint32 sperst_mask, uint32 spert_val);
530 extern void si_pcie_ltr_war(si_t *sih);
531 extern void si_pcie_hw_LTR_war(si_t *sih);
532 extern void si_pcie_hw_L1SS_war(si_t *sih);
533 extern void si_pciedev_crwlpciegen2(si_t *sih);
534 extern void si_pcie_prep_D3(si_t *sih, bool enter_D3);
535 extern void si_pciedev_reg_pm_clk_period(si_t *sih);
536 extern void si_d11rsdb_core1_alt_reg_clk_dis(si_t *sih);
537 extern void si_d11rsdb_core1_alt_reg_clk_en(si_t *sih);
538 extern void si_pcie_disable_oobselltr(si_t *sih);
539 extern uint32 si_raw_reg(si_t *sih, uint32 reg, uint32 val, uint32 wrire_req);
540
541 #ifdef WLRSDB
542 extern void si_d11rsdb_core_disable(si_t *sih, uint32 bits);
543 extern void si_d11rsdb_core_reset(si_t *sih, uint32 bits, uint32 resetbits);
544 extern void set_secondary_d11_core(si_t *sih, void **secmap, void **secwrap);
545 #endif
546
547
548 /* Macro to enable clock gating changes in different cores */
549 #define MEM_CLK_GATE_BIT 5
550 #define GCI_CLK_GATE_BIT 18
551
552 #define USBAPP_CLK_BIT 0
553 #define PCIE_CLK_BIT 3
554 #define ARMCR4_DBG_CLK_BIT 4
555 #define SAMPLE_SYNC_CLK_BIT 17
556 #define PCIE_TL_CLK_BIT 18
557 #define HQ_REQ_BIT 24
558 #define PLL_DIV2_BIT_START 9
559 #define PLL_DIV2_MASK (0x37 << PLL_DIV2_BIT_START)
560 #define PLL_DIV2_DIS_OP (0x37 << PLL_DIV2_BIT_START)
561
562 #define pmu_corereg(si, cc_idx, member, mask, val) \
563 (AOB_ENAB(si) ? \
564 si_pmu_corereg(si, si_findcoreidx(si, PMU_CORE_ID, 0), \
565 OFFSETOF(pmuregs_t, member), mask, val): \
566 si_pmu_corereg(si, cc_idx, OFFSETOF(chipcregs_t, member), mask, val))
567
568 /* Used only for the regs present in the pmu core and not present in the old cc core */
569 #define PMU_REG_NEW(si, member, mask, val) \
570 si_corereg(si, si_findcoreidx(si, PMU_CORE_ID, 0), \
571 OFFSETOF(pmuregs_t, member), mask, val)
572
573 #define PMU_REG(si, member, mask, val) \
574 (AOB_ENAB(si) ? \
575 si_corereg(si, si_findcoreidx(si, PMU_CORE_ID, 0), \
576 OFFSETOF(pmuregs_t, member), mask, val): \
577 si_corereg(si, SI_CC_IDX, OFFSETOF(chipcregs_t, member), mask, val))
578
579 #define LHL_REG(si, member, mask, val) \
580 si_corereg(si, si_findcoreidx(si, GCI_CORE_ID, 0), \
581 OFFSETOF(gciregs_t, member), mask, val)
582
583 #define CHIPC_REG(si, member, mask, val) \
584 si_corereg(si, SI_CC_IDX, OFFSETOF(chipcregs_t, member), mask, val)
585
586 /* GCI Macros */
587 #define ALLONES_32 0xFFFFFFFF
588 #define GCI_CCTL_SECIRST_OFFSET 0 /**< SeciReset */
589 #define GCI_CCTL_RSTSL_OFFSET 1 /**< ResetSeciLogic */
590 #define GCI_CCTL_SECIEN_OFFSET 2 /**< EnableSeci */
591 #define GCI_CCTL_FSL_OFFSET 3 /**< ForceSeciOutLow */
592 #define GCI_CCTL_SMODE_OFFSET 4 /**< SeciOpMode, 6:4 */
593 #define GCI_CCTL_US_OFFSET 7 /**< UpdateSeci */
594 #define GCI_CCTL_BRKONSLP_OFFSET 8 /**< BreakOnSleep */
595 #define GCI_CCTL_SILOWTOUT_OFFSET 9 /**< SeciInLowTimeout, 10:9 */
596 #define GCI_CCTL_RSTOCC_OFFSET 11 /**< ResetOffChipCoex */
597 #define GCI_CCTL_ARESEND_OFFSET 12 /**< AutoBTSigResend */
598 #define GCI_CCTL_FGCR_OFFSET 16 /**< ForceGciClkReq */
599 #define GCI_CCTL_FHCRO_OFFSET 17 /**< ForceHWClockReqOff */
600 #define GCI_CCTL_FREGCLK_OFFSET 18 /**< ForceRegClk */
601 #define GCI_CCTL_FSECICLK_OFFSET 19 /**< ForceSeciClk */
602 #define GCI_CCTL_FGCA_OFFSET 20 /**< ForceGciClkAvail */
603 #define GCI_CCTL_FGCAV_OFFSET 21 /**< ForceGciClkAvailValue */
604 #define GCI_CCTL_SCS_OFFSET 24 /**< SeciClkStretch, 31:24 */
605
606 #define GCI_MODE_UART 0x0
607 #define GCI_MODE_SECI 0x1
608 #define GCI_MODE_BTSIG 0x2
609 #define GCI_MODE_GPIO 0x3
610 #define GCI_MODE_MASK 0x7
611
612 #define GCI_CCTL_LOWTOUT_DIS 0x0
613 #define GCI_CCTL_LOWTOUT_10BIT 0x1
614 #define GCI_CCTL_LOWTOUT_20BIT 0x2
615 #define GCI_CCTL_LOWTOUT_30BIT 0x3
616 #define GCI_CCTL_LOWTOUT_MASK 0x3
617
618 #define GCI_CCTL_SCS_DEF 0x19
619 #define GCI_CCTL_SCS_MASK 0xFF
620
621 #define GCI_SECIIN_MODE_OFFSET 0
622 #define GCI_SECIIN_GCIGPIO_OFFSET 4
623 #define GCI_SECIIN_RXID2IP_OFFSET 8
624
625 #define GCI_SECIOUT_MODE_OFFSET 0
626 #define GCI_SECIOUT_GCIGPIO_OFFSET 4
627 #define GCI_SECIOUT_LOOPBACK_OFFSET 8
628 #define GCI_SECIOUT_SECIINRELATED_OFFSET 16
629
630 #define GCI_SECIAUX_RXENABLE_OFFSET 0
631 #define GCI_SECIFIFO_RXENABLE_OFFSET 16
632
633 #define GCI_SECITX_ENABLE_OFFSET 0
634
635 #define GCI_GPIOCTL_INEN_OFFSET 0
636 #define GCI_GPIOCTL_OUTEN_OFFSET 1
637 #define GCI_GPIOCTL_PDN_OFFSET 4
638
639 #define GCI_GPIOIDX_OFFSET 16
640
641 #define GCI_LTECX_SECI_ID 0 /**< SECI port for LTECX */
642
643 /* To access per GCI bit registers */
644 #define GCI_REG_WIDTH 32
645
646 /* GCI bit positions */
647 /* GCI [127:000] = WLAN [127:0] */
648 #define GCI_WLAN_IP_ID 0
649 #define GCI_WLAN_BEGIN 0
650 #define GCI_WLAN_PRIO_POS (GCI_WLAN_BEGIN + 4)
651 #define GCI_WLAN_PERST_POS (GCI_WLAN_BEGIN + 15)
652
653 /* GCI [639:512] = LTE [127:0] */
654 #define GCI_LTE_IP_ID 4
655 #define GCI_LTE_BEGIN 512
656 #define GCI_LTE_FRAMESYNC_POS (GCI_LTE_BEGIN + 0)
657 #define GCI_LTE_RX_POS (GCI_LTE_BEGIN + 1)
658 #define GCI_LTE_TX_POS (GCI_LTE_BEGIN + 2)
659 #define GCI_LTE_WCI2TYPE_POS (GCI_LTE_BEGIN + 48)
660 #define GCI_LTE_WCI2TYPE_MASK 7
661 #define GCI_LTE_AUXRXDVALID_POS (GCI_LTE_BEGIN + 56)
662
663 /* Reg Index corresponding to ECI bit no x of ECI space */
664 #define GCI_REGIDX(x) ((x)/GCI_REG_WIDTH)
665 /* Bit offset of ECI bit no x in 32-bit words */
666 #define GCI_BITOFFSET(x) ((x)%GCI_REG_WIDTH)
667
668 /* End - GCI Macros */
669
670 #ifdef REROUTE_OOBINT
671 #define CC_OOB 0x0
672 #define M2MDMA_OOB 0x1
673 #define PMU_OOB 0x2
674 #define D11_OOB 0x3
675 #define SDIOD_OOB 0x4
676 #define WLAN_OOB 0x5
677 #define PMU_OOB_BIT 0x12
678 #endif /* REROUTE_OOBINT */
679
680 #define GCI_REG(si, offset, mask, val) \
681 (AOB_ENAB(si) ? \
682 si_corereg(si, si_findcoreidx(si, GCI_CORE_ID, 0), \
683 offset, mask, val): \
684 si_corereg(si, SI_CC_IDX, offset, mask, val))
685
686 extern void si_pll_sr_reinit(si_t *sih);
687 extern void si_pll_closeloop(si_t *sih);
688 void si_config_4364_d11_oob(si_t *sih, uint coreid);
689 extern void si_update_macclk_mul_fact(si_t *sih, uint mul_fact);
690 extern uint32 si_get_macclk_mul_fact(si_t *sih);
691 extern void si_gci_set_femctrl(si_t *sih, osl_t *osh, bool set);
692 extern void si_gci_set_femctrl_mask_ant01(si_t *sih, osl_t *osh, bool set);
693 extern uint si_num_slaveports(si_t *sih, uint coreid);
694 extern uint32 si_get_slaveport_addr(si_t *sih, uint asidx, uint core_id, uint coreunit);
695 extern uint32 si_get_d11_slaveport_addr(si_t *sih, uint asidx, uint coreunit);
696 uint si_introff(si_t *sih);
697 void si_intrrestore(si_t *sih, uint intr_val);
698 void si_nvram_res_masks(si_t *sih, uint32 *min_mask, uint32 *max_mask);
699 uint32 si_xtalfreq(si_t *sih);
700 extern uint32 si_wrapper_dump_buf_size(si_t *sih);
701 extern uint32 si_wrapper_dump_binary(si_t *sih, uchar *p);
702
703 /* SR Power Control */
704 extern uint32 si_srpwr_request(si_t *sih, uint32 mask, uint32 val);
705 extern uint32 si_srpwr_stat_spinwait(si_t *sih, uint32 mask, uint32 val);
706 extern uint32 si_srpwr_stat(si_t *sih);
707 extern uint32 si_srpwr_domain(si_t *sih);
708
709 /* SR Power Control */
710 #ifdef BCMSRPWR
711 /* No capabilities bit so using chipid for now */
712 #define SRPWR_CAP(sih) (\
713 (CHIPID(sih->chip) == BCM4347_CHIP_ID) || \
714 (0))
715
716 extern bool _bcmsrpwr;
717 #if defined(WL_ENAB_RUNTIME_CHECK) || !defined(DONGLEBUILD)
718 #define SRPWR_ENAB() (_bcmsrpwr)
719 #elif defined(BCMSRPWR_DISABLED)
720 #define SRPWR_ENAB() (0)
721 #else
722 #define SRPWR_ENAB() (1)
723 #endif
724 #else
725 #define SRPWR_CAP(sih) (0)
726 #define SRPWR_ENAB() (0)
727 #endif /* BCMSRPWR */
728
729 #endif /* _siutils_h_ */
730