1 /*
2 * Firmware I/O implementation for XRadio drivers
3 *
4 * Copyright (c) 2013
5 * Xradio Technology Co., Ltd. <www.xradiotech.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/init.h>
13 #include <linux/vmalloc.h>
14 #include <linux/sched.h>
15 #include <linux/firmware.h>
16
17 #include "xradio.h"
18 #include "fwio.h"
19 #include "hwio.h"
20 #include "sbus.h"
21 #include "bh.h"
22
23 /* Macroses are local. */
24 #define APB_WRITE(reg, val) \
25 do { \
26 ret = xradio_apb_write_32(hw_priv, APB_ADDR(reg), (val)); \
27 if (ret < 0) { \
28 xradio_dbg(XRADIO_DBG_ERROR, \
29 "%s: can't write %s at line %d.\n", \
30 __func__, #reg, __LINE__); \
31 goto error; \
32 } \
33 } while (0)
34 #define APB_READ(reg, val) \
35 do { \
36 ret = xradio_apb_read_32(hw_priv, APB_ADDR(reg), &(val)); \
37 if (ret < 0) { \
38 xradio_dbg(XRADIO_DBG_ERROR, \
39 "%s: can't read %s at line %d.\n", \
40 __func__, #reg, __LINE__); \
41 goto error; \
42 } \
43 } while (0)
44 #define REG_WRITE(reg, val) \
45 do { \
46 ret = xradio_reg_write_32(hw_priv, (reg), (val)); \
47 if (ret < 0) { \
48 xradio_dbg(XRADIO_DBG_ERROR, \
49 "%s: can't write %s at line %d.\n", \
50 __func__, #reg, __LINE__); \
51 goto error; \
52 } \
53 } while (0)
54 #define REG_READ(reg, val) \
55 do { \
56 ret = xradio_reg_read_32(hw_priv, (reg), &(val)); \
57 if (ret < 0) { \
58 xradio_dbg(XRADIO_DBG_ERROR, \
59 "%s: can't read %s at line %d.\n", \
60 __func__, #reg, __LINE__); \
61 goto error; \
62 } \
63 } while (0)
64
xradio_get_hw_type(u32 config_reg_val,int * major_revision)65 static int xradio_get_hw_type(u32 config_reg_val, int *major_revision)
66 {
67 int hw_type = -1;
68 u32 hif_type = (config_reg_val >> 24) & 0x4;
69 /*u32 hif_vers = (config_reg_val >> 31) & 0x1;*/
70
71 /* Check if we have XRADIO */
72 if (hif_type == 0x4) {
73 *major_revision = 0x4;
74 hw_type = HIF_HW_TYPE_XRADIO;
75 } else {
76 /*hw type unknown.*/
77 *major_revision = 0x0;
78 }
79 return hw_type;
80 }
81
82 /*
83 * This function is called to Parse the SDD file
84 * to extract some informations
85 */
xradio_parse_sdd(struct xradio_common * hw_priv,u32 * dpll)86 static int xradio_parse_sdd(struct xradio_common *hw_priv, u32 *dpll)
87 {
88 int ret = 0;
89 const char *sdd_path = NULL;
90 struct xradio_sdd *pElement = NULL;
91 int parsedLength = 0;
92
93 sta_printk(XRADIO_DBG_TRC, "%s\n", __func__);
94 SYS_BUG(hw_priv->sdd != NULL);
95
96 /* select and load sdd file depend on hardware version. */
97 switch (hw_priv->hw_revision) {
98 case XR829_HW_REV0:
99 sdd_path = XR829_SDD_FILE;
100 #ifdef CONFIG_XRADIO_ETF
101 if (etf_is_connect())
102 sdd_path = etf_get_sddpath();
103 #endif
104 break;
105 default:
106 xradio_dbg(XRADIO_DBG_ERROR,
107 "%s: unknown hardware version.\n", __func__);
108 return ret;
109 }
110
111 ret = request_firmware(&hw_priv->sdd, sdd_path, hw_priv->pdev);
112 if (unlikely(ret)) {
113 xradio_dbg(XRADIO_DBG_ERROR, "%s: can't load sdd file %s.\n",
114 __func__, sdd_path);
115 return ret;
116 }
117
118 /*parse SDD config.*/
119 hw_priv->is_BT_Present = false;
120 pElement = (struct xradio_sdd *)hw_priv->sdd->data;
121 parsedLength += (FIELD_OFFSET(struct xradio_sdd, data) + \
122 pElement->length);
123 pElement = FIND_NEXT_ELT(pElement);
124
125 while (parsedLength < hw_priv->sdd->size) {
126 switch (pElement->id) {
127 case SDD_PTA_CFG_ELT_ID:
128 hw_priv->conf_listen_interval =
129 (*((u16 *) pElement->data + 1) >> 7) & 0x1F;
130 hw_priv->is_BT_Present = true;
131 xradio_dbg(XRADIO_DBG_NIY,
132 "PTA element found.Listen Interval %d\n",
133 hw_priv->conf_listen_interval);
134 break;
135 case SDD_REFERENCE_FREQUENCY_ELT_ID:
136 switch (*((uint16_t *) pElement->data)) {
137 case 0x32C8:
138 *dpll = 0x1D89D241;
139 break;
140 case 0x3E80:
141 *dpll = 0x1E1;
142 break;
143 case 0x41A0:
144 *dpll = 0x124931C1;
145 break;
146 case 0x4B00:
147 *dpll = 0x191;
148 break;
149 case 0x5DC0:
150 *dpll = 0x141;
151 break;
152 case 0x6590:
153 *dpll = 0x0EC4F121;
154 break;
155 case 0x8340:
156 *dpll = 0x92490E1;
157 break;
158 case 0x9600:
159 *dpll = 0x100010C1;
160 break;
161 case 0x9C40:
162 *dpll = 0xC1;
163 break;
164 case 0xBB80:
165 *dpll = 0xA1;
166 break;
167 case 0xCB20:
168 *dpll = 0x7627091;
169 break;
170 default:
171 *dpll = DPLL_INIT_VAL_XRADIO;
172 xradio_dbg(XRADIO_DBG_WARN,
173 "Unknown Reference clock frequency."
174 "Use default DPLL value=0x%08x.",
175 DPLL_INIT_VAL_XRADIO);
176 break;
177 }
178 xradio_dbg(XRADIO_DBG_NIY,
179 "Reference clock=%uKHz, DPLL value=0x%08x.\n",
180 *((uint16_t *) pElement->data), *dpll);
181 default:
182 break;
183 }
184 parsedLength += (FIELD_OFFSET(struct xradio_sdd, data) + \
185 pElement->length);
186 pElement = FIND_NEXT_ELT(pElement);
187 }
188
189 xradio_dbg(XRADIO_DBG_MSG, "sdd size=%zu parse len=%d.\n",
190 hw_priv->sdd->size, parsedLength);
191
192
193 if (hw_priv->is_BT_Present == false) {
194 hw_priv->conf_listen_interval = 0;
195 xradio_dbg(XRADIO_DBG_NIY, "PTA element NOT found.\n");
196 }
197 return ret;
198 }
199
xradio_update_dpllctrl(struct xradio_common * hw_priv,u32 dpll_update)200 int xradio_update_dpllctrl(struct xradio_common *hw_priv, u32 dpll_update)
201 {
202 int ret = 0;
203 u32 val32 = 0;
204 u32 dpll_read = 0;
205 int i = 0;
206
207 xradio_ahb_read_32(hw_priv, PWRCTRL_WLAN_START_CFG, &val32);
208 do {
209 ret = xradio_ahb_read_32(hw_priv, PWRCTRL_WLAN_COMMON_CFG, &val32);
210 /*Check DPLL, return success if sync finish*/
211 if (val32 & PWRCTRL_COMMON_REG_DONE) {
212 xradio_ahb_read_32(hw_priv, PWRCTRL_WLAN_DPLL_CTRL, &dpll_read);
213 if (dpll_update == dpll_read) {
214 xradio_dbg(XRADIO_DBG_NIY, "%s: dpll sync ok=0x%08x.\n",
215 __func__, dpll_read);
216 break;
217 } else {
218 xradio_dbg(XRADIO_DBG_ERROR, "%s: dpll is incorrect, " \
219 "dpll_read=0x%08x, dpll_update=0x%08x.\n",
220 __func__, dpll_read, dpll_update);
221 /*dpll_ctrl need to be corrected it by follow procedure.*/
222 }
223 }
224
225 /*correct dpll_ctrl if wlan is accessible.*/
226 if ((val32 & PWRCTRL_COMMON_REG_ARBT) && /*wait for arbit end.*/
227 !(val32 & PWRCTRL_COMMON_REG_BT)) { /*wlan is accessible.*/
228 xradio_ahb_read_32(hw_priv, PWRCTRL_WLAN_DPLL_CTRL, &dpll_read);
229 if (dpll_update != dpll_read) {
230 xradio_dbg(XRADIO_DBG_WARN,
231 "%s:dpll_read=0x%08x, new dpll_ctrl=0x%08x.\n",
232 __func__, dpll_read, dpll_update);
233 xradio_ahb_write_32(hw_priv,
234 PWRCTRL_WLAN_DPLL_CTRL, (dpll_update|0x1));
235 msleep(5); /*wait for it stable after change DPLL config. */
236 } else {
237 xradio_dbg(XRADIO_DBG_ALWY, "%s: DPLL_CTRL Sync=0x%08x.\n",
238 __func__, dpll_read);
239 }
240 xradio_ahb_write_32(hw_priv, PWRCTRL_WLAN_COMMON_CFG,
241 PWRCTRL_COMMON_REG_DONE); /*set done*/
242 break;
243 } else if (i < 100) {
244 xradio_dbg(XRADIO_DBG_WARN, "%s: COMMON_REG=0x%08x.\n",
245 __func__, val32);
246 msleep(i);
247 ++i;
248 } else {
249 xradio_dbg(XRADIO_DBG_ERROR, "%s:DPLL access timeout=0x%08x.\n",
250 __func__, val32);
251 ret = -ETIMEDOUT;
252 break;
253 }
254 } while (!ret);
255 xradio_ahb_write_32(hw_priv, PWRCTRL_WLAN_START_CFG, 0);
256 return ret;
257 }
258
xradio_firmware(struct xradio_common * hw_priv)259 static int xradio_firmware(struct xradio_common *hw_priv)
260 {
261 int ret, block, num_blocks;
262 unsigned i;
263 u32 val32;
264 u32 put = 0, get = 0;
265 u8 *buf = NULL;
266 const char *fw_path;
267 const struct firmware *firmware = NULL;
268 xradio_dbg(XRADIO_DBG_TRC, "%s\n", __func__);
269
270 switch (hw_priv->hw_revision) {
271 case XR829_HW_REV0:
272 fw_path = XR829_FIRMWARE;
273 #ifdef CONFIG_XRADIO_ETF
274 if (etf_is_connect())
275 fw_path = etf_get_fwpath();
276 #endif
277 break;
278 default:
279 xradio_dbg(XRADIO_DBG_ERROR, "%s: invalid silicon revision %d.\n",
280 __func__, hw_priv->hw_revision);
281 return -EINVAL;
282 }
283
284 /* Initialize common registers */
285 APB_WRITE(DOWNLOAD_IMAGE_SIZE_REG, DOWNLOAD_ARE_YOU_HERE);
286 APB_WRITE(DOWNLOAD_PUT_REG, 0);
287 APB_WRITE(DOWNLOAD_GET_REG, 0);
288 APB_WRITE(DOWNLOAD_STATUS_REG, DOWNLOAD_PENDING);
289 APB_WRITE(DOWNLOAD_FLAGS_REG, 0);
290
291 /* Release CPU from RESET */
292 xradio_reg_bit_operate(hw_priv, HIF_CONFIG_REG_ID,
293 0, HIF_CONFIG_CPU_RESET_BIT);
294 /* Enable Clock */
295 xradio_reg_bit_operate(hw_priv, HIF_CONFIG_REG_ID,
296 0, HIF_CONFIG_CPU_CLK_DIS_BIT);
297
298 /* Load a firmware file */
299 ret = request_firmware(&firmware, fw_path, hw_priv->pdev);
300 if (ret) {
301 xradio_dbg(XRADIO_DBG_ERROR, "%s: can't load firmware file %s.\n",
302 __func__, fw_path);
303 goto error;
304 }
305 SYS_BUG(!firmware->data);
306
307 buf = xr_kmalloc(DOWNLOAD_BLOCK_SIZE, true);
308 if (!buf) {
309 xradio_dbg(XRADIO_DBG_ERROR,
310 "%s: can't allocate firmware buffer.\n", __func__);
311 ret = -ENOMEM;
312 goto error;
313 }
314
315 /* Check if the bootloader is ready */
316 for (i = 0; i < 100; i++ /*= 1 + i / 2*/) {
317 APB_READ(DOWNLOAD_IMAGE_SIZE_REG, val32);
318 if (val32 == DOWNLOAD_I_AM_HERE)
319 break;
320 mdelay(10);
321 } /* End of for loop */
322 if (val32 != DOWNLOAD_I_AM_HERE) {
323 xradio_dbg(XRADIO_DBG_ERROR, "%s: bootloader is not ready.\n",
324 __func__);
325 #ifdef BOOT_NOT_READY_FIX
326 hw_priv->boot_not_ready_cnt++;
327 hw_priv->boot_not_ready = 1;
328 #endif
329 ret = -ETIMEDOUT;
330 goto error;
331 }
332
333 /* Calculcate number of download blocks */
334 num_blocks = (firmware->size - 1) / DOWNLOAD_BLOCK_SIZE + 1;
335
336 /* Updating the length in Download Ctrl Area */
337 val32 = firmware->size; /* Explicit cast from size_t to u32 */
338 APB_WRITE(DOWNLOAD_IMAGE_SIZE_REG, val32);
339
340 /*
341 * DOWNLOAD_BLOCK_SIZE must be divided exactly by sdio blocksize,
342 * otherwise it may cause bootloader error.
343 */
344 val32 = hw_priv->sbus_ops->get_block_size(hw_priv->sbus_priv);
345 if (val32 > DOWNLOAD_BLOCK_SIZE || DOWNLOAD_BLOCK_SIZE%val32) {
346 xradio_dbg(XRADIO_DBG_WARN,
347 "%s:change blocksize(%d->%d) during download fw.\n",
348 __func__, val32, DOWNLOAD_BLOCK_SIZE>>1);
349 hw_priv->sbus_ops->lock(hw_priv->sbus_priv);
350 ret = hw_priv->sbus_ops->set_block_size(hw_priv->sbus_priv,
351 DOWNLOAD_BLOCK_SIZE>>1);
352 if (ret)
353 xradio_dbg(XRADIO_DBG_ERROR,
354 "%s: set blocksize error(%d).\n", __func__, ret);
355 hw_priv->sbus_ops->unlock(hw_priv->sbus_priv);
356 }
357
358 /* Firmware downloading loop */
359 for (block = 0; block < num_blocks; block++) {
360 size_t tx_size;
361 size_t block_size;
362
363 /* check the download status */
364 APB_READ(DOWNLOAD_STATUS_REG, val32);
365 if (val32 != DOWNLOAD_PENDING) {
366 xradio_dbg(XRADIO_DBG_ERROR,
367 "%s: bootloader reported error %d.\n",
368 __func__, val32);
369 ret = -EIO;
370 goto error;
371 }
372
373 /* calculate the block size */
374 tx_size = block_size = min((size_t)(firmware->size - put),
375 (size_t)DOWNLOAD_BLOCK_SIZE);
376 memcpy(buf, &firmware->data[put], block_size);
377 if (block_size < DOWNLOAD_BLOCK_SIZE) {
378 memset(&buf[block_size], 0, DOWNLOAD_BLOCK_SIZE - block_size);
379 tx_size = DOWNLOAD_BLOCK_SIZE;
380 }
381
382 /* loop until put - get <= 24K */
383 for (i = 0; i < 100; i++) {
384 APB_READ(DOWNLOAD_GET_REG, get);
385 if ((put - get) <= (DOWNLOAD_FIFO_SIZE - DOWNLOAD_BLOCK_SIZE))
386 break;
387 mdelay(i);
388 }
389
390 if ((put - get) > (DOWNLOAD_FIFO_SIZE - DOWNLOAD_BLOCK_SIZE)) {
391 xradio_dbg(XRADIO_DBG_ERROR, "%s: Timeout waiting for FIFO.\n",
392 __func__);
393 ret = -ETIMEDOUT;
394 goto error;
395 }
396
397 /* send the block to sram */
398 ret = xradio_apb_write(hw_priv, APB_ADDR(DOWNLOAD_FIFO_OFFSET + \
399 (put & (DOWNLOAD_FIFO_SIZE - 1))),
400 buf, tx_size);
401 if (ret < 0) {
402 xradio_dbg(XRADIO_DBG_ERROR,
403 "%s: can't write block at line %d.\n",
404 __func__, __LINE__);
405 goto error;
406 }
407
408 /* update the put register */
409 put += block_size;
410 APB_WRITE(DOWNLOAD_PUT_REG, put);
411 } /* End of firmware download loop */
412
413 /* Wait for the download completion */
414 for (i = 0; i < 300; i += 1 + i / 2) {
415 APB_READ(DOWNLOAD_STATUS_REG, val32);
416 if (val32 != DOWNLOAD_PENDING)
417 break;
418 mdelay(i);
419 }
420 if (val32 != DOWNLOAD_SUCCESS) {
421 xradio_dbg(XRADIO_DBG_ERROR,
422 "%s: wait for download completion failed. " \
423 "Read: 0x%.8X\n", __func__, val32);
424 ret = -ETIMEDOUT;
425 goto error;
426 } else {
427 xradio_dbg(XRADIO_DBG_ALWY, "Firmware completed.\n");
428 ret = 0;
429 }
430
431 error:
432 if (buf)
433 kfree(buf);
434 if (firmware) {
435 release_firmware(firmware);
436 }
437 return ret;
438 }
439
xradio_bootloader(struct xradio_common * hw_priv)440 static int xradio_bootloader(struct xradio_common *hw_priv)
441 {
442 int ret = -1;
443 u32 i = 0;
444 const char *bl_path = XR829_BOOTLOADER;
445 u32 addr = AHB_MEMORY_ADDRESS;
446 u32 *data = NULL;
447 const struct firmware *bootloader = NULL;
448 xradio_dbg(XRADIO_DBG_TRC, "%s\n", __func__);
449
450 /* Load a bootloader file */
451 ret = request_firmware(&bootloader, bl_path, hw_priv->pdev);
452 if (ret) {
453 xradio_dbg(XRADIO_DBG_ERROR,
454 "%s: can't load bootloader file %s.\n",
455 __func__, bl_path);
456 goto error;
457 }
458
459 xradio_dbg(XRADIO_DBG_NIY, "%s: bootloader size = %zu, loopcount = %zu\n",
460 __func__, bootloader->size, (bootloader->size) / 4);
461
462 /* Down bootloader. */
463 data = (u32 *)bootloader->data;
464 for (i = 0; i < (bootloader->size)/4; i++) {
465 ret = xradio_ahb_write_32(hw_priv, addr, data[i]);
466 if (ret < 0) {
467 sbus_printk(XRADIO_DBG_ERROR, "%s: xradio_ahb_write failed.\n", __func__);
468 goto error;
469 }
470 if (i == 100 || i == 200 || i == 300 || i == 400 || i == 500 || i == 600)
471 xradio_dbg(XRADIO_DBG_NIY, "%s: addr = 0x%x, data = 0x%x\n", __func__, addr, data[i]);
472 addr += 4;
473 }
474 xradio_dbg(XRADIO_DBG_ALWY, "Bootloader complete\n");
475
476 error:
477 if (bootloader) {
478 release_firmware(bootloader);
479 }
480 return ret;
481 }
482
483 #if (DBG_XRADIO_HIF)
484
485 extern u16 hif_test_rw; /*0: nothing to do; 1: write only; 2: write and read*/
486 extern u16 hif_test_data_mode; /* hif test data mode, such as 0x55, 0xff etc*/
487 extern u16 hif_test_data_len; /* hif test data len, every data len pre round*/
488 extern u16 hif_test_data_round;
489 extern u16 hif_test_oper_delta; /* hif test operation delta time, give more time to analyze data tranx*/
HIF_R_W_TEST(struct xradio_common * hw_priv)490 int HIF_R_W_TEST(struct xradio_common *hw_priv)
491 {
492 int time;
493 int i;
494 struct timespec64 start; //linux5.4 commit 33e26418193f58d1895f2f968e1953b1caf8deb7
495 struct timespec64 end;
496 unsigned int addr;
497 char *write_buf;
498 char *read_buf;
499 write_buf = kmalloc(hif_test_data_len * 4, GFP_KERNEL);
500 if (!write_buf)
501 return 0xff;
502 read_buf = kmalloc(hif_test_data_len * 4, GFP_KERNEL);
503 if (!read_buf) {
504 kfree(write_buf);
505 return 0xff;
506 }
507
508 xr_do_gettimeofday(&start);
509 printk(KERN_ERR"[HIF test] --- <write> --- begin~~\n");
510 addr = PAS_RAM_START_ADDR;
511 memset(write_buf, hif_test_data_mode, hif_test_data_len * 4);
512 i = 0;
513 while (i < hif_test_data_round) {
514 xradio_apb_write(hw_priv, addr, write_buf, hif_test_data_len * 4);
515 msleep(hif_test_oper_delta);
516 i++;
517 if (0 == hif_test_rw)
518 goto err;
519 }
520
521 if (1 == hif_test_rw) { // means write only
522 kfree(write_buf);
523 kfree(read_buf);
524 printk(KERN_ERR"[HIF test] --- <write> --- end and return~~\n");
525 return 0;
526 }
527
528 msleep(hif_test_oper_delta * 5);
529 printk(KERN_ERR"[HIF test] --- <read> --- begin~~\n");
530
531 addr = PAS_RAM_START_ADDR;
532 memset(write_buf, hif_test_data_mode, hif_test_data_len * 4);
533 i = 0;
534 while (i < hif_test_data_round) {
535 xradio_apb_read(hw_priv, addr, read_buf, hif_test_data_len * 4);
536 msleep(hif_test_oper_delta);
537 i++;
538 if (0 == hif_test_rw)
539 goto err;
540 }
541
542 printk(KERN_ERR"[HIF test] --- <read> --- end~~\n");
543 xr_do_gettimeofday(&end);
544 time = 1000 * (end.tv_sec - start.tv_sec) + (end.tv_nsec - start.tv_nsec) / 1000000;
545 kfree(write_buf);
546 kfree(read_buf);
547 return 0;
548 err:
549 kfree(write_buf);
550 kfree(read_buf);
551 return 1;
552 }
553
554 #endif
555
xradio_load_firmware(struct xradio_common * hw_priv)556 int xradio_load_firmware(struct xradio_common *hw_priv)
557 {
558 int ret;
559 int i;
560 u32 val32 = 0;
561 u16 val16 = 0;
562 u32 dpll = 0;
563 int major_revision;
564
565 xradio_dbg(XRADIO_DBG_TRC, "%s\n", __func__);
566 SYS_BUG(!hw_priv);
567 /* Read CONFIG Register Value - We will read 32 bits */
568
569 ret = xradio_reg_read_32(hw_priv, HIF_CONFIG_REG_ID, &val32);
570 if (ret < 0) {
571 xradio_dbg(XRADIO_DBG_ERROR,
572 "%s: can't read config register, err=%d.\n",
573 __func__, ret);
574 return ret;
575 }
576
577 /*check hardware type and revision.*/
578 hw_priv->hw_type = xradio_get_hw_type(val32, &major_revision);
579 switch (hw_priv->hw_type) {
580 case HIF_HW_TYPE_XRADIO:
581 xradio_dbg(XRADIO_DBG_NIY, "%s: HW_TYPE_XRADIO detected.\n",
582 __func__);
583 break;
584 default:
585 xradio_dbg(XRADIO_DBG_ERROR, "%s: Unknown hardware: %d.\n",
586 __func__, hw_priv->hw_type);
587 return -ENOTSUPP;
588 }
589 if (major_revision == 4) {
590 hw_priv->hw_revision = XR829_HW_REV0;
591 xradio_dbg(XRADIO_DBG_ALWY, "XRADIO_HW_REV 1.0 detected.\n");
592 } else {
593 xradio_dbg(XRADIO_DBG_ERROR, "%s: Unsupported major revision %d.\n",
594 __func__, major_revision);
595 return -ENOTSUPP;
596 }
597
598 /*load sdd file, and get config from it.*/
599 ret = xradio_parse_sdd(hw_priv, &dpll);
600 if (ret < 0) {
601 return ret;
602 }
603
604 /*set dpll initial value and check.*/
605 ret = xradio_reg_write_32(hw_priv, HIF_TSET_GEN_R_W_REG_ID, dpll);
606 if (ret < 0) {
607 xradio_dbg(XRADIO_DBG_ERROR, "%s: can't write DPLL register.\n",
608 __func__);
609 goto out;
610 }
611 msleep(5);
612 ret = xradio_reg_read_32(hw_priv, HIF_TSET_GEN_R_W_REG_ID, &val32);
613 if (ret < 0) {
614 xradio_dbg(XRADIO_DBG_ERROR, "%s: can't read DPLL register.\n",
615 __func__);
616 goto out;
617 }
618 if (val32 != dpll) {
619 xradio_dbg(XRADIO_DBG_ERROR, "%s: unable to initialise " \
620 "DPLL register. Wrote 0x%.8X, read 0x%.8X.\n",
621 __func__, dpll, val32);
622 ret = -EIO;
623 goto out;
624 }
625
626 /* Set wakeup bit in device */
627 ret = xradio_reg_bit_operate(hw_priv, HIF_CONTROL_REG_ID, HIF_CTRL_WUP_BIT, 0);
628 if (ret < 0) {
629 xradio_dbg(XRADIO_DBG_ERROR, "%s: device wake up failed.\n", __func__);
630 hw_priv->hw_cant_wakeup = true;
631 goto out;
632 }
633
634 /* Wait for wakeup */
635 for (i = 0 ; i < 300 ; i += 1 + i / 2) {
636 ret = xradio_reg_read_16(hw_priv, HIF_CONTROL_REG_ID, &val16);
637 if (ret < 0) {
638 xradio_dbg(XRADIO_DBG_ERROR, "%s: Wait_for_wakeup: "
639 "can't read control register.\n", __func__);
640 goto out;
641 }
642 if (val16 & HIF_CTRL_RDY_BIT) {
643 break;
644 }
645 msleep(i);
646 }
647 if ((val16 & HIF_CTRL_RDY_BIT) == 0) {
648 xradio_dbg(XRADIO_DBG_ERROR, "%s: Wait for wakeup:"
649 "device is not responding.\n", __func__);
650 hw_priv->hw_cant_wakeup = true;
651 #ifdef BOOT_NOT_READY_FIX
652 hw_priv->boot_not_ready_cnt++;
653 hw_priv->boot_not_ready = 1;
654 xradio_dbg(XRADIO_DBG_ERROR, "Device will restart at %d times!\n",
655 hw_priv->boot_not_ready_cnt);
656 #ifdef ERROR_HANG_DRIVER
657 if (hw_priv->boot_not_ready_cnt >= 6) {
658 xradio_dbg(XRADIO_DBG_ERROR, "Boot not ready and device restart \
659 more than 6, hang the driver.\n");
660 error_hang_driver = 1;
661 }
662 #endif
663 #endif
664 ret = -ETIMEDOUT;
665 goto out;
666 } else {
667 xradio_dbg(XRADIO_DBG_NIY, "WLAN device is ready.\n");
668 hw_priv->hw_cant_wakeup = false;
669 }
670
671 /* Checking for access mode and download firmware. */
672 ret = xradio_reg_bit_operate(hw_priv, HIF_CONFIG_REG_ID,
673 HIF_CONFIG_ACCESS_MODE_BIT, 0);
674 if (ret < 0) {
675 xradio_dbg(XRADIO_DBG_ERROR, "%s: check_access_mode: "
676 "can't read config register.\n", __func__);
677 goto out;
678 }
679
680 #ifdef SUPPORT_DPLL_CHECK
681 /*Checking DPLL value and correct it if need.*/
682 xradio_update_dpllctrl(hw_priv, xradio_dllctrl_convert(dpll));
683 #else
684 xradio_dbg(XRADIO_DBG_ALWY, "%s: not need check dpll.\n", __func__);
685 #endif
686
687 #if (DBG_XRADIO_HIF)
688
689 if (hif_test_rw) {
690 ret = HIF_R_W_TEST(hw_priv);
691 if (0 == ret) {
692 printk(KERN_ERR "HIF Test OK!\n");
693 } else if (1 == ret) {
694 printk(KERN_ERR "HIF Test faied!\n");
695 } else {
696 printk(KERN_ERR "Unkmow error!\n");
697 }
698 }
699
700 #endif
701
702 /* Down bootloader. */
703 ret = xradio_bootloader(hw_priv);
704 if (ret < 0) {
705 xradio_dbg(XRADIO_DBG_ERROR, "%s: can't download bootloader.\n", __func__);
706 goto out;
707 }
708 /* Down firmware. */
709 ret = xradio_firmware(hw_priv);
710 if (ret < 0) {
711 xradio_dbg(XRADIO_DBG_ERROR, "%s: can't download firmware.\n", __func__);
712 goto out;
713 }
714
715 /* Register Interrupt Handler */
716 ret = hw_priv->sbus_ops->irq_subscribe(hw_priv->sbus_priv,
717 (sbus_irq_handler)xradio_irq_handler,
718 hw_priv);
719 if (ret < 0) {
720 xradio_dbg(XRADIO_DBG_ERROR, "%s: can't register IRQ handler.\n",
721 __func__);
722 goto out;
723 }
724
725 if (HIF_HW_TYPE_XRADIO == hw_priv->hw_type) {
726 /* If device is XRADIO the IRQ enable/disable bits
727 * are in CONFIG register */
728 ret = xradio_reg_bit_operate(hw_priv, HIF_CONFIG_REG_ID,
729 HIF_CONF_IRQ_RDY_ENABLE, 0);
730 if (ret < 0) {
731 xradio_dbg(XRADIO_DBG_ERROR, "%s: enable_irq: can't read " \
732 "config register.\n", __func__);
733 goto unsubscribe;
734 }
735 } else {
736 /* Enable device interrupts - Both DATA_RDY and WLAN_RDY */
737 ret = xradio_reg_bit_operate(hw_priv, HIF_CONTROL_REG_ID,
738 HIF_CTRL_IRQ_RDY_ENABLE, 0);
739 if (ret < 0) {
740 xradio_dbg(XRADIO_DBG_ERROR, "%s: enable_irq: can't read " \
741 "control register.\n", __func__);
742 goto unsubscribe;
743 }
744 }
745
746 /* Configure device for MESSSAGE MODE */
747 ret = xradio_reg_bit_operate(hw_priv, HIF_CONFIG_REG_ID,
748 0, HIF_CONFIG_ACCESS_MODE_BIT);
749 if (ret < 0) {
750 xradio_dbg(XRADIO_DBG_ERROR, "%s: set_mode: can't read config register.\n",
751 __func__);
752 goto unsubscribe;
753 }
754
755 /* Unless we read the CONFIG Register we are
756 * not able to get an interrupt */
757 mdelay(10);
758 xradio_reg_read_32(hw_priv, HIF_CONFIG_REG_ID, &val32);
759 return 0;
760
761 unsubscribe:
762 hw_priv->sbus_ops->irq_unsubscribe(hw_priv->sbus_priv);
763 out:
764 if (hw_priv->sdd) {
765 release_firmware(hw_priv->sdd);
766 hw_priv->sdd = NULL;
767 }
768 return ret;
769 }
770
xradio_dev_deinit(struct xradio_common * hw_priv)771 int xradio_dev_deinit(struct xradio_common *hw_priv)
772 {
773 hw_priv->sbus_ops->irq_unsubscribe(hw_priv->sbus_priv);
774 if (hw_priv->sdd) {
775 release_firmware(hw_priv->sdd);
776 hw_priv->sdd = NULL;
777 }
778 return 0;
779 }
780
781 #undef APB_WRITE
782 #undef APB_READ
783 #undef REG_WRITE
784 #undef REG_READ
785