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1 // SPDX-License-Identifier: (GPL-2.0+ or MIT)
2 /*
3  * Copyright(c) 2012-2016 Allwinnertech Co., Ltd.
4  * Author: huangshuosheng <huangshuosheng@allwinnertech.com>
5  */
6 
7 #include <linux/module.h>
8 #include <linux/platform_device.h>
9 #include <linux/of.h>
10 #include <linux/of_device.h>
11 #include <linux/pinctrl/pinctrl.h>
12 
13 #include "pinctrl-sunxi.h"
14 
15 static const struct sunxi_desc_pin sun50iw10p1_r_pins[] = {
16 	//Register Name: PL_CFG0
17 	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
18 		SUNXI_FUNCTION(0x0, "gpio_in"),
19 		SUNXI_FUNCTION(0x1, "gpio_out"),
20 		SUNXI_FUNCTION(0x2, "s_twi0"),		/* SCK */
21 		SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0),
22 		SUNXI_FUNCTION(0x7, "io_disabled")),
23 	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
24 		SUNXI_FUNCTION(0x0, "gpio_in"),
25 		SUNXI_FUNCTION(0x1, "gpio_out"),
26 		SUNXI_FUNCTION(0x2, "s_twi0"),		/* SDA */
27 		SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1),
28 		SUNXI_FUNCTION(0x7, "io_disabled")),
29 	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
30 		SUNXI_FUNCTION(0x0, "gpio_in"),
31 		SUNXI_FUNCTION(0x1, "gpio_out"),
32 		SUNXI_FUNCTION(0x2, "s_uart0"),		/* TX */
33 		SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2),
34 		SUNXI_FUNCTION(0x7, "io_disabled")),
35 	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
36 		SUNXI_FUNCTION(0x0, "gpio_in"),
37 		SUNXI_FUNCTION(0x1, "gpio_out"),
38 		SUNXI_FUNCTION(0x2, "s_uart0"),		/* RX */
39 		SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3),
40 		SUNXI_FUNCTION(0x7, "io_disabled")),
41 	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
42 		SUNXI_FUNCTION(0x0, "gpio_in"),
43 		SUNXI_FUNCTION(0x1, "gpio_out"),
44 		SUNXI_FUNCTION(0x2, "s_jtag0"),		/* MS */
45 		SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4),
46 		SUNXI_FUNCTION(0x7, "io_disabled")),
47 	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
48 		SUNXI_FUNCTION(0x0, "gpio_in"),
49 		SUNXI_FUNCTION(0x1, "gpio_out"),
50 		SUNXI_FUNCTION(0x2, "s_jtag0"),		/* CK */
51 		SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5),
52 		SUNXI_FUNCTION(0x7, "io_disabled")),
53 	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
54 		SUNXI_FUNCTION(0x0, "gpio_in"),
55 		SUNXI_FUNCTION(0x1, "gpio_out"),
56 		SUNXI_FUNCTION(0x2, "s_jtag0"),		/* DO */
57 		SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6),
58 		SUNXI_FUNCTION(0x7, "io_disabled")),
59 	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
60 		SUNXI_FUNCTION(0x0, "gpio_in"),
61 		SUNXI_FUNCTION(0x1, "gpio_out"),
62 		SUNXI_FUNCTION(0x2, "s_jtag0"),		/* DI */
63 		SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7),
64 		SUNXI_FUNCTION(0x7, "io_disabled")),
65 	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
66 		SUNXI_FUNCTION(0x0, "gpio_in"),
67 		SUNXI_FUNCTION(0x1, "gpio_out"),
68 		SUNXI_FUNCTION(0x2, "s_twi1"),		/* SCK */
69 		SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8),
70 		SUNXI_FUNCTION(0x7, "io_disabled")),
71 	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
72 		SUNXI_FUNCTION(0x0, "gpio_in"),
73 		SUNXI_FUNCTION(0x1, "gpio_out"),
74 		SUNXI_FUNCTION(0x2, "s_twi1"),		/* SDA */
75 		SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9),
76 		SUNXI_FUNCTION(0x7, "io_disabled")),
77 	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10),
78 		SUNXI_FUNCTION(0x0, "gpio_in"),
79 		SUNXI_FUNCTION(0x1, "gpio_out"),
80 		SUNXI_FUNCTION(0x2, "s_pwm0"),		/* S_PWM0 */
81 		SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10),
82 		SUNXI_FUNCTION(0x7, "io_disabled")),
83 	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 11),
84 		SUNXI_FUNCTION(0x0, "gpio_in"),
85 		SUNXI_FUNCTION(0x1, "gpio_out"),
86 		SUNXI_FUNCTION(0x2, "s_cpu0"),		/* CUR_W */
87 		SUNXI_FUNCTION(0x3, "s_cir0"),		/* IN */
88 		SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11),
89 		SUNXI_FUNCTION(0x7, "io_disabled")),
90 };
91 
92 static const struct sunxi_pinctrl_desc sun50iw10p1_r_pinctrl_data = {
93 	.pins = sun50iw10p1_r_pins,
94 	.npins = ARRAY_SIZE(sun50iw10p1_r_pins),
95 	.pin_base = SUNXI_PIN_BASE('L'),
96 	.irq_banks = 1,
97 	.hw_type = SUNXI_PCTL_HW_TYPE_0,
98 };
99 
sun50iw10p1_r_pinctrl_probe(struct platform_device * pdev)100 static int sun50iw10p1_r_pinctrl_probe(struct platform_device *pdev)
101 {
102 #if IS_ENABLED(CONFIG_PINCTRL_SUNXI_DEBUGFS)
103 	dev_set_name(&pdev->dev, "r_pio");
104 #endif
105 	return sunxi_bsp_pinctrl_init(pdev, &sun50iw10p1_r_pinctrl_data);
106 }
107 
108 static struct of_device_id sun50iw10p1_r_pinctrl_match[] = {
109 	{ .compatible = "allwinner,sun50iw10p1-r-pinctrl", },
110 	{}
111 };
112 MODULE_DEVICE_TABLE(of, sun50iw10p1_r_pinctrl_match);
113 
114 static struct platform_driver sun50iw10p1_r_pinctrl_driver = {
115 	.probe	= sun50iw10p1_r_pinctrl_probe,
116 	.driver	= {
117 		.name		= "sun50iw10p1-r-pinctrl",
118 		.of_match_table	= sun50iw10p1_r_pinctrl_match,
119 	},
120 };
121 
sun50iw10p1_r_pio_init(void)122 static int __init sun50iw10p1_r_pio_init(void)
123 {
124 	return platform_driver_register(&sun50iw10p1_r_pinctrl_driver);
125 }
126 postcore_initcall(sun50iw10p1_r_pio_init);
127 
128 MODULE_AUTHOR("Huangshuosheng<huangshuosheng@allwinnertech.com>");
129 MODULE_DESCRIPTION("Allwinner sun50iw10p1 R_PIO pinctrl driver");
130 MODULE_LICENSE("GPL");
131 MODULE_VERSION("1.0.0");
132