1 // SPDX-License-Identifier: (GPL-2.0+ or MIT)
2 /*
3 * Copyright (c) 2020 frank@allwinnertech.com
4 */
5
6 #include <linux/module.h>
7 #include <linux/platform_device.h>
8 #include <linux/of.h>
9 #include <linux/of_device.h>
10 #include <linux/pinctrl/pinctrl.h>
11
12 #include "pinctrl-sunxi.h"
13
14 static const struct sunxi_desc_pin sun50iw9_pins[] = {
15 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
16 SUNXI_FUNCTION(0x0, "gpio_in"),
17 SUNXI_FUNCTION(0x1, "gpio_out"),
18 SUNXI_FUNCTION(0x2, "gmac1"), /* RXD1 */
19 SUNXI_FUNCTION(0x4, "twi0"), /* SCK */
20 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),
21 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
22 SUNXI_FUNCTION(0x0, "gpio_in"),
23 SUNXI_FUNCTION(0x1, "gpio_out"),
24 SUNXI_FUNCTION(0x2, "gmac1"), /* RXD0 */
25 SUNXI_FUNCTION(0x4, "twi0"), /* SDA */
26 SUNXI_FUNCTION(0x5, "Vdevice"), /* XXX For Test */
27 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),
28 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
29 SUNXI_FUNCTION(0x0, "gpio_in"),
30 SUNXI_FUNCTION(0x1, "gpio_out"),
31 SUNXI_FUNCTION(0x2, "gmac1"), /* CRTS_DV */
32 SUNXI_FUNCTION(0x4, "twi1"), /* SCK */
33 SUNXI_FUNCTION(0x5, "Vdevice"), /* XXX For Test */
34 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),
35 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
36 SUNXI_FUNCTION(0x0, "gpio_in"),
37 SUNXI_FUNCTION(0x1, "gpio_out"),
38 SUNXI_FUNCTION(0x2, "gmac1"), /* RXER */
39 SUNXI_FUNCTION(0x4, "twi1"), /* SDA */
40 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),
41 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
42 SUNXI_FUNCTION(0x0, "gpio_in"),
43 SUNXI_FUNCTION(0x1, "gpio_out"),
44 SUNXI_FUNCTION(0x2, "gmac1"), /* TXD1*/
45 SUNXI_FUNCTION(0x4, "ac_adcy"),
46 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),
47 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
48 SUNXI_FUNCTION(0x0, "gpio_in"),
49 SUNXI_FUNCTION(0x1, "gpio_out"),
50 SUNXI_FUNCTION(0x2, "gmac1"), /* TXD0 */
51 SUNXI_FUNCTION(0x3, "i2s0"), /* DOUT0 */
52 SUNXI_FUNCTION(0x4, "ac_adcx"),
53 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),
54 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
55 SUNXI_FUNCTION(0x0, "gpio_in"),
56 SUNXI_FUNCTION(0x1, "gpio_out"),
57 SUNXI_FUNCTION(0x2, "gmac1"), /* TXCK */
58 SUNXI_FUNCTION(0x3, "i2s0"), /* MCLK */
59 SUNXI_FUNCTION(0x4, "ac_mclk"),
60 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),
61 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
62 SUNXI_FUNCTION(0x0, "gpio_in"),
63 SUNXI_FUNCTION(0x1, "gpio_out"),
64 SUNXI_FUNCTION(0x2, "gmac1"), /* TXEN */
65 SUNXI_FUNCTION(0x3, "i2s0"), /* BCLK */
66 SUNXI_FUNCTION(0x4, "ac_sync"),
67 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),
68 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
69 SUNXI_FUNCTION(0x0, "gpio_in"),
70 SUNXI_FUNCTION(0x1, "gpio_out"),
71 SUNXI_FUNCTION(0x2, "gmac1"), /* MDC */
72 SUNXI_FUNCTION(0x3, "i2s0"), /* LRCK */
73 SUNXI_FUNCTION(0x4, "ac_adcl"),
74 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),
75 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
76 SUNXI_FUNCTION(0x0, "gpio_in"),
77 SUNXI_FUNCTION(0x1, "gpio_out"),
78 SUNXI_FUNCTION(0x2, "gmac1"), /* MDIO */
79 SUNXI_FUNCTION(0x3, "i2s0"), /* DIN0 */
80 SUNXI_FUNCTION(0x4, "ac_adcr"),
81 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),
82 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
83 SUNXI_FUNCTION(0x0, "gpio_in"),
84 SUNXI_FUNCTION(0x1, "gpio_out"),
85 SUNXI_FUNCTION(0x2, "twi3"), /* SCK */
86 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)),
87 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
88 SUNXI_FUNCTION(0x0, "gpio_in"),
89 SUNXI_FUNCTION(0x1, "gpio_out"),
90 SUNXI_FUNCTION(0x2, "twi3"), /* SDA */
91 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)),
92 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
93 SUNXI_FUNCTION(0x0, "gpio_in"),
94 SUNXI_FUNCTION(0x1, "gpio_out"),
95 SUNXI_FUNCTION(0x2, "pwm5"),
96 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)),
97 /* HOLE */
98 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
99 SUNXI_FUNCTION(0x0, "gpio_in"),
100 SUNXI_FUNCTION(0x1, "gpio_out"),
101 SUNXI_FUNCTION(0x2, "nand0"), /* WE */
102 SUNXI_FUNCTION(0x3, "sdc2"), /* DS */
103 SUNXI_FUNCTION(0x4, "spi0"), /* CLK */
104 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)),
105 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
106 SUNXI_FUNCTION(0x0, "gpio_in"),
107 SUNXI_FUNCTION(0x1, "gpio_out"),
108 SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
109 SUNXI_FUNCTION(0x3, "sdc2"), /* RST */
110 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)),
111 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
112 SUNXI_FUNCTION(0x0, "gpio_in"),
113 SUNXI_FUNCTION(0x1, "gpio_out"),
114 SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
115 SUNXI_FUNCTION(0x4, "spi0"), /* MOSI */
116 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)),
117 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
118 SUNXI_FUNCTION(0x0, "gpio_in"),
119 SUNXI_FUNCTION(0x1, "gpio_out"),
120 SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */
121 SUNXI_FUNCTION(0x4, "spi0"), /* CS0 */
122 SUNXI_FUNCTION(0x5, "boot"), /* SEL1 */
123 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)),
124 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
125 SUNXI_FUNCTION(0x0, "gpio_in"),
126 SUNXI_FUNCTION(0x1, "gpio_out"),
127 SUNXI_FUNCTION(0x2, "nand0"), /* CE0 */
128 SUNXI_FUNCTION(0x4, "spi0"), /* MISO */
129 SUNXI_FUNCTION(0x5, "boot"), /* SEL2 */
130 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)),
131 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
132 SUNXI_FUNCTION(0x0, "gpio_in"),
133 SUNXI_FUNCTION(0x1, "gpio_out"),
134 SUNXI_FUNCTION(0x2, "nand0"), /* RE */
135 SUNXI_FUNCTION(0x3, "sdc2"), /* CLK */
136 SUNXI_FUNCTION(0x5, "boot"), /* SEL3 */
137 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)),
138 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
139 SUNXI_FUNCTION(0x0, "gpio_in"),
140 SUNXI_FUNCTION(0x1, "gpio_out"),
141 SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
142 SUNXI_FUNCTION(0x3, "sdc2"), /* CMD */
143 SUNXI_FUNCTION(0x5, "boot"), /* SEL4 */
144 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)),
145 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
146 SUNXI_FUNCTION(0x0, "gpio_in"),
147 SUNXI_FUNCTION(0x1, "gpio_out"),
148 SUNXI_FUNCTION(0x2, "nand0"), /* RB1 */
149 SUNXI_FUNCTION(0x4, "spi0"), /* CS1 */
150 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)),
151 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
152 SUNXI_FUNCTION(0x0, "gpio_in"),
153 SUNXI_FUNCTION(0x1, "gpio_out"),
154 SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
155 SUNXI_FUNCTION(0x3, "sdc2"), /* D3 */
156 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)),
157 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
158 SUNXI_FUNCTION(0x0, "gpio_in"),
159 SUNXI_FUNCTION(0x1, "gpio_out"),
160 SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
161 SUNXI_FUNCTION(0x3, "sdc2"), /* D4 */
162 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)),
163 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
164 SUNXI_FUNCTION(0x0, "gpio_in"),
165 SUNXI_FUNCTION(0x1, "gpio_out"),
166 SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
167 SUNXI_FUNCTION(0x3, "sdc2"), /* D0 */
168 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)),
169 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
170 SUNXI_FUNCTION(0x0, "gpio_in"),
171 SUNXI_FUNCTION(0x1, "gpio_out"),
172 SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
173 SUNXI_FUNCTION(0x3, "sdc2"), /* D5 */
174 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)),
175 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
176 SUNXI_FUNCTION(0x0, "gpio_in"),
177 SUNXI_FUNCTION(0x1, "gpio_out"),
178 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
179 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)),
180 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
181 SUNXI_FUNCTION(0x0, "gpio_in"),
182 SUNXI_FUNCTION(0x1, "gpio_out"),
183 SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
184 SUNXI_FUNCTION(0x3, "sdc2"), /* D1 */
185 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)),
186 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
187 SUNXI_FUNCTION(0x0, "gpio_in"),
188 SUNXI_FUNCTION(0x1, "gpio_out"),
189 SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
190 SUNXI_FUNCTION(0x3, "sdc2"), /* D6 */
191 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 14)),
192 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
193 SUNXI_FUNCTION(0x0, "gpio_in"),
194 SUNXI_FUNCTION(0x1, "gpio_out"),
195 SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
196 SUNXI_FUNCTION(0x3, "sdc2"), /* D2 */
197 SUNXI_FUNCTION(0x4, "spi0"), /* WP */
198 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 15)),
199 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
200 SUNXI_FUNCTION(0x0, "gpio_in"),
201 SUNXI_FUNCTION(0x1, "gpio_out"),
202 SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
203 SUNXI_FUNCTION(0x3, "sdc2"), /* D7 */
204 SUNXI_FUNCTION(0x4, "spi0"), /* HOLD */
205 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 16)),
206 /* HOLE */
207 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
208 SUNXI_FUNCTION(0x0, "gpio_in"),
209 SUNXI_FUNCTION(0x1, "gpio_out"),
210 SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
211 SUNXI_FUNCTION(0x3, "lvds0"), /* VP0 */
212 SUNXI_FUNCTION(0x4, "ts0"), /* CLK */
213 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)),
214 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
215 SUNXI_FUNCTION(0x0, "gpio_in"),
216 SUNXI_FUNCTION(0x1, "gpio_out"),
217 SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
218 SUNXI_FUNCTION(0x3, "lvds0"), /* VN0 */
219 SUNXI_FUNCTION(0x4, "ts0"), /* ERR */
220 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)),
221 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
222 SUNXI_FUNCTION(0x0, "gpio_in"),
223 SUNXI_FUNCTION(0x1, "gpio_out"),
224 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
225 SUNXI_FUNCTION(0x3, "lvds0"), /* VP1 */
226 SUNXI_FUNCTION(0x4, "ts0"), /* SYNC */
227 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)),
228 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
229 SUNXI_FUNCTION(0x0, "gpio_in"),
230 SUNXI_FUNCTION(0x1, "gpio_out"),
231 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
232 SUNXI_FUNCTION(0x3, "lvds0"), /* VN1 */
233 SUNXI_FUNCTION(0x4, "ts0"), /* DVLD */
234 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)),
235 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
236 SUNXI_FUNCTION(0x0, "gpio_in"),
237 SUNXI_FUNCTION(0x1, "gpio_out"),
238 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
239 SUNXI_FUNCTION(0x3, "lvds0"), /* VP2 */
240 SUNXI_FUNCTION(0x4, "ts0"), /* D0 */
241 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)),
242 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
243 SUNXI_FUNCTION(0x0, "gpio_in"),
244 SUNXI_FUNCTION(0x1, "gpio_out"),
245 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
246 SUNXI_FUNCTION(0x3, "lvds0"), /* VN2 */
247 SUNXI_FUNCTION(0x4, "ts0"), /* D1 */
248 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)),
249 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
250 SUNXI_FUNCTION(0x0, "gpio_in"),
251 SUNXI_FUNCTION(0x1, "gpio_out"),
252 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
253 SUNXI_FUNCTION(0x3, "lvds0"), /* VPC */
254 SUNXI_FUNCTION(0x4, "ts0"), /* D2 */
255 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)),
256 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
257 SUNXI_FUNCTION(0x0, "gpio_in"),
258 SUNXI_FUNCTION(0x1, "gpio_out"),
259 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
260 SUNXI_FUNCTION(0x3, "lvds0"), /* VNC */
261 SUNXI_FUNCTION(0x4, "ts0"), /* D3 */
262 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)),
263 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
264 SUNXI_FUNCTION(0x0, "gpio_in"),
265 SUNXI_FUNCTION(0x1, "gpio_out"),
266 SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
267 SUNXI_FUNCTION(0x3, "lvds0"), /* VP3 */
268 SUNXI_FUNCTION(0x4, "ts0"), /* D4 */
269 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)),
270 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
271 SUNXI_FUNCTION(0x0, "gpio_in"),
272 SUNXI_FUNCTION(0x1, "gpio_out"),
273 SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
274 SUNXI_FUNCTION(0x3, "lvds0"), /* VN3 */
275 SUNXI_FUNCTION(0x4, "ts0"), /* D5 */
276 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)),
277 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
278 SUNXI_FUNCTION(0x0, "gpio_in"),
279 SUNXI_FUNCTION(0x1, "gpio_out"),
280 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
281 SUNXI_FUNCTION(0x3, "lvds1"), /* VP0 */
282 SUNXI_FUNCTION(0x4, "ts0"), /* D6 */
283 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)),
284 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
285 SUNXI_FUNCTION(0x0, "gpio_in"),
286 SUNXI_FUNCTION(0x1, "gpio_out"),
287 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
288 SUNXI_FUNCTION(0x3, "lvds1"), /* VN0 */
289 SUNXI_FUNCTION(0x4, "ts0"), /* D7 */
290 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)),
291 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
292 SUNXI_FUNCTION(0x0, "gpio_in"),
293 SUNXI_FUNCTION(0x1, "gpio_out"),
294 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
295 SUNXI_FUNCTION(0x3, "lvds1"), /* VP1 */
296 SUNXI_FUNCTION(0x4, "sim0"), /* VPPEN */
297 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)),
298 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
299 SUNXI_FUNCTION(0x0, "gpio_in"),
300 SUNXI_FUNCTION(0x1, "gpio_out"),
301 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
302 SUNXI_FUNCTION(0x3, "lvds1"), /* VN1 */
303 SUNXI_FUNCTION(0x4, "sim0"), /* VPPPP */
304 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)),
305 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
306 SUNXI_FUNCTION(0x0, "gpio_in"),
307 SUNXI_FUNCTION(0x1, "gpio_out"),
308 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
309 SUNXI_FUNCTION(0x3, "lvds1"), /* VP2 */
310 SUNXI_FUNCTION(0x4, "sim0"), /* PWREN */
311 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)),
312 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
313 SUNXI_FUNCTION(0x0, "gpio_in"),
314 SUNXI_FUNCTION(0x1, "gpio_out"),
315 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
316 SUNXI_FUNCTION(0x3, "lvds1"), /* VN2 */
317 SUNXI_FUNCTION(0x4, "sim0"), /* CLK */
318 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)),
319 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
320 SUNXI_FUNCTION(0x0, "gpio_in"),
321 SUNXI_FUNCTION(0x1, "gpio_out"),
322 SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
323 SUNXI_FUNCTION(0x3, "lvds1"), /* VPC */
324 SUNXI_FUNCTION(0x4, "sim0"), /* DATA */
325 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 16)),
326 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
327 SUNXI_FUNCTION(0x0, "gpio_in"),
328 SUNXI_FUNCTION(0x1, "gpio_out"),
329 SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
330 SUNXI_FUNCTION(0x3, "lvds1"), /* VNC */
331 SUNXI_FUNCTION(0x4, "sim0"), /* RST */
332 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 17)),
333 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
334 SUNXI_FUNCTION(0x0, "gpio_in"),
335 SUNXI_FUNCTION(0x1, "gpio_out"),
336 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
337 SUNXI_FUNCTION(0x3, "lvds1"), /* VP3 */
338 SUNXI_FUNCTION(0x4, "sim0"), /* DET */
339 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 18)),
340 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
341 SUNXI_FUNCTION(0x0, "gpio_in"),
342 SUNXI_FUNCTION(0x1, "gpio_out"),
343 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
344 SUNXI_FUNCTION(0x3, "lvds1"), /* VN3 */
345 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 19)),
346 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
347 SUNXI_FUNCTION(0x0, "gpio_in"),
348 SUNXI_FUNCTION(0x1, "gpio_out"),
349 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
350 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 20)),
351 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
352 SUNXI_FUNCTION(0x0, "gpio_in"),
353 SUNXI_FUNCTION(0x1, "gpio_out"),
354 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
355 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 21)),
356 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
357 SUNXI_FUNCTION(0x0, "gpio_in"),
358 SUNXI_FUNCTION(0x1, "gpio_out"),
359 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
360 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 22)),
361 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
362 SUNXI_FUNCTION(0x0, "gpio_in"),
363 SUNXI_FUNCTION(0x1, "gpio_out"),
364 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
365 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 23)),
366 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
367 SUNXI_FUNCTION(0x0, "gpio_in"),
368 SUNXI_FUNCTION(0x1, "gpio_out"),
369 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
370 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 24)),
371 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
372 SUNXI_FUNCTION(0x0, "gpio_in"),
373 SUNXI_FUNCTION(0x1, "gpio_out"),
374 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
375 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 25)),
376 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
377 SUNXI_FUNCTION(0x0, "gpio_in"),
378 SUNXI_FUNCTION(0x1, "gpio_out"),
379 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
380 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 26)),
381 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
382 SUNXI_FUNCTION(0x0, "gpio_in"),
383 SUNXI_FUNCTION(0x1, "gpio_out"),
384 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
385 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 27)),
386 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 28),
387 SUNXI_FUNCTION(0x0, "gpio_in"),
388 SUNXI_FUNCTION(0x1, "gpio_out"),
389 SUNXI_FUNCTION(0x2, "pwm0"),
390 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 28)),
391 /* HOLE */
392 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
393 SUNXI_FUNCTION(0x0, "gpio_in"),
394 SUNXI_FUNCTION(0x1, "gpio_out"),
395 SUNXI_FUNCTION(0x2, "csi1"), /* CLK */
396 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)),
397 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
398 SUNXI_FUNCTION(0x0, "gpio_in"),
399 SUNXI_FUNCTION(0x1, "gpio_out"),
400 SUNXI_FUNCTION(0x2, "csi_mclk1"), /* MCLK */
401 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)),
402 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
403 SUNXI_FUNCTION(0x0, "gpio_in"),
404 SUNXI_FUNCTION(0x1, "gpio_out"),
405 SUNXI_FUNCTION(0x2, "csi1"), /* HSYNC */
406 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)),
407 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
408 SUNXI_FUNCTION(0x0, "gpio_in"),
409 SUNXI_FUNCTION(0x1, "gpio_out"),
410 SUNXI_FUNCTION(0x2, "csi1"), /* VSYNC */
411 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)),
412 SUNXI_PIN (SUNXI_PINCTRL_PIN(E, 4),
413 SUNXI_FUNCTION(0x0, "gpio_in"),
414 SUNXI_FUNCTION(0x1, "gpio_out"),
415 SUNXI_FUNCTION(0x2, "csi1"), /* D0 */
416 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)),
417 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
418 SUNXI_FUNCTION(0x0, "gpio_in"),
419 SUNXI_FUNCTION(0x1, "gpio_out"),
420 SUNXI_FUNCTION(0x2, "csi1"), /* D1 */
421 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)),
422 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
423 SUNXI_FUNCTION(0x0, "gpio_in"),
424 SUNXI_FUNCTION(0x1, "gpio_out"),
425 SUNXI_FUNCTION(0x2, "csi1"), /* D2 */
426 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)),
427 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
428 SUNXI_FUNCTION(0x0, "gpio_in"),
429 SUNXI_FUNCTION(0x1, "gpio_out"),
430 SUNXI_FUNCTION(0x2, "csi1"), /* D3 */
431 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)),
432 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
433 SUNXI_FUNCTION(0x0, "gpio_in"),
434 SUNXI_FUNCTION(0x1, "gpio_out"),
435 SUNXI_FUNCTION(0x2, "csi1"), /* D4 */
436 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)),
437 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
438 SUNXI_FUNCTION(0x0, "gpio_in"),
439 SUNXI_FUNCTION(0x1, "gpio_out"),
440 SUNXI_FUNCTION(0x2, "csi1"), /* D5 */
441 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)),
442 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
443 SUNXI_FUNCTION(0x0, "gpio_in"),
444 SUNXI_FUNCTION(0x1, "gpio_out"),
445 SUNXI_FUNCTION(0x2, "csi1"), /* D6 */
446 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 10)),
447 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
448 SUNXI_FUNCTION(0x0, "gpio_in"),
449 SUNXI_FUNCTION(0x1, "gpio_out"),
450 SUNXI_FUNCTION(0x2, "csi1"), /* D7 */
451 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 11)),
452 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
453 SUNXI_FUNCTION(0x0, "gpio_in"),
454 SUNXI_FUNCTION(0x1, "gpio_out"),
455 SUNXI_FUNCTION(0x2, "csi1"), /* D8 */
456 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 12)),
457 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
458 SUNXI_FUNCTION(0x0, "gpio_in"),
459 SUNXI_FUNCTION(0x1, "gpio_out"),
460 SUNXI_FUNCTION(0x2, "csi1"), /* D9 */
461 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 13)),
462 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
463 SUNXI_FUNCTION(0x0, "gpio_in"),
464 SUNXI_FUNCTION(0x1, "gpio_out"),
465 SUNXI_FUNCTION(0x2, "csi1"), /* D10 */
466 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 14)),
467 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
468 SUNXI_FUNCTION(0x0, "gpio_in"),
469 SUNXI_FUNCTION(0x1, "gpio_out"),
470 SUNXI_FUNCTION(0x2, "csi1"), /* D11 */
471 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 15)),
472 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
473 SUNXI_FUNCTION(0x0, "gpio_in"),
474 SUNXI_FUNCTION(0x1, "gpio_out"),
475 SUNXI_FUNCTION(0x2, "csi1"), /* D12 */
476 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 16)),
477 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17),
478 SUNXI_FUNCTION(0x0, "gpio_in"),
479 SUNXI_FUNCTION(0x1, "gpio_out"),
480 SUNXI_FUNCTION(0x2, "csi1"), /* D13 */
481 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 17)),
482 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 18),
483 SUNXI_FUNCTION(0x0, "gpio_in"),
484 SUNXI_FUNCTION(0x1, "gpio_out"),
485 SUNXI_FUNCTION(0x2, "csi1"), /* D14 */
486 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 18)),
487 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 19),
488 SUNXI_FUNCTION(0x0, "gpio_in"),
489 SUNXI_FUNCTION(0x1, "gpio_out"),
490 SUNXI_FUNCTION(0x2, "csi1"), /* D15 */
491 SUNXI_FUNCTION(0x3, "jtag"), /* MS */
492 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 19)),
493 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 20),
494 SUNXI_FUNCTION(0x0, "gpio_in"),
495 SUNXI_FUNCTION(0x1, "gpio_out"),
496 SUNXI_FUNCTION(0x2, "csi_cci1"), /* SCK */
497 SUNXI_FUNCTION(0x3, "jtag"), /* CK */
498 SUNXI_FUNCTION(0x5, "twi2"), /* SCK */
499 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 20)),
500 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 21),
501 SUNXI_FUNCTION(0x0, "gpio_in"),
502 SUNXI_FUNCTION(0x1, "gpio_out"),
503 SUNXI_FUNCTION(0x2, "csi_cci1"), /* SDA */
504 SUNXI_FUNCTION(0x3, "jtag"), /* DO */
505 SUNXI_FUNCTION(0x5, "twi2"), /* SDA */
506 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 21)),
507 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 22),
508 SUNXI_FUNCTION(0x0, "gpio_in"),
509 SUNXI_FUNCTION(0x1, "gpio_out"),
510 SUNXI_FUNCTION(0x2, "ncsi_fsin0"), /* FSIN0 */
511 SUNXI_FUNCTION(0x3, "jtag"), /* DI */
512 SUNXI_FUNCTION(0x4, "TCON"), /* TRIG0 */
513 SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 22)),
514 /* HOLE */
515 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
516 SUNXI_FUNCTION(0x0, "gpio_in"),
517 SUNXI_FUNCTION(0x1, "gpio_out"),
518 SUNXI_FUNCTION(0x2, "sdc0"), /* D1 */
519 SUNXI_FUNCTION(0x3, "jtag"), /* MS1 */
520 SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 0)),
521 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
522 SUNXI_FUNCTION(0x0, "gpio_in"),
523 SUNXI_FUNCTION(0x1, "gpio_out"),
524 SUNXI_FUNCTION(0x2, "sdc0"), /* D0 */
525 SUNXI_FUNCTION(0x3, "jtag"), /* DI1 */
526 SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 1)),
527 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
528 SUNXI_FUNCTION(0x0, "gpio_in"),
529 SUNXI_FUNCTION(0x1, "gpio_out"),
530 SUNXI_FUNCTION(0x2, "sdc0"), /* CLK */
531 SUNXI_FUNCTION(0x3, "uart0"), /* TX */
532 SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 2)),
533 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
534 SUNXI_FUNCTION(0x0, "gpio_in"),
535 SUNXI_FUNCTION(0x1, "gpio_out"),
536 SUNXI_FUNCTION(0x2, "sdc0"), /* CMD */
537 SUNXI_FUNCTION(0x3, "jtag"), /* DO1 */
538 SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 3)),
539 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
540 SUNXI_FUNCTION(0x0, "gpio_in"),
541 SUNXI_FUNCTION(0x1, "gpio_out"),
542 SUNXI_FUNCTION(0x2, "sdc0"), /* D3 */
543 SUNXI_FUNCTION(0x3, "uart0"), /* RX */
544 SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 4)),
545 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
546 SUNXI_FUNCTION(0x0, "gpio_in"),
547 SUNXI_FUNCTION(0x1, "gpio_out"),
548 SUNXI_FUNCTION(0x2, "sdc0"), /* D2 */
549 SUNXI_FUNCTION(0x3, "jtag"), /* CK1 */
550 SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 5)),
551 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
552 SUNXI_FUNCTION(0x0, "gpio_in"),
553 SUNXI_FUNCTION(0x1, "gpio_out"),
554 SUNXI_FUNCTION(0x2, "jtag"), /* SEL */
555 SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 6)),
556 /* HOLE */
557 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
558 SUNXI_FUNCTION(0x0, "gpio_in"),
559 SUNXI_FUNCTION(0x1, "gpio_out"),
560 SUNXI_FUNCTION(0x2, "sdc1"), /* CLK */
561 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 0)),
562 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
563 SUNXI_FUNCTION(0x0, "gpio_in"),
564 SUNXI_FUNCTION(0x1, "gpio_out"),
565 SUNXI_FUNCTION(0x2, "sdc1"), /* CMD */
566 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 1)),
567 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
568 SUNXI_FUNCTION(0x0, "gpio_in"),
569 SUNXI_FUNCTION(0x1, "gpio_out"),
570 SUNXI_FUNCTION(0x2, "sdc1"), /* D0 */
571 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 2)),
572 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
573 SUNXI_FUNCTION(0x0, "gpio_in"),
574 SUNXI_FUNCTION(0x1, "gpio_out"),
575 SUNXI_FUNCTION(0x2, "sdc1"), /* D1 */
576 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 3)),
577 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
578 SUNXI_FUNCTION(0x0, "gpio_in"),
579 SUNXI_FUNCTION(0x1, "gpio_out"),
580 SUNXI_FUNCTION(0x2, "sdc1"), /* D2 */
581 SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 4)),
582 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
583 SUNXI_FUNCTION(0x0, "gpio_in"),
584 SUNXI_FUNCTION(0x1, "gpio_out"),
585 SUNXI_FUNCTION(0x2, "sdc1"), /* D3 */
586 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 5)),
587 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
588 SUNXI_FUNCTION(0x0, "gpio_in"),
589 SUNXI_FUNCTION(0x1, "gpio_out"),
590 SUNXI_FUNCTION(0x2, "uart1"), /* TX */
591 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 6)),
592 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
593 SUNXI_FUNCTION(0x0, "gpio_in"),
594 SUNXI_FUNCTION(0x1, "gpio_out"),
595 SUNXI_FUNCTION(0x2, "uart1"), /* RX */
596 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 7)),
597 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
598 SUNXI_FUNCTION(0x0, "gpio_in"),
599 SUNXI_FUNCTION(0x1, "gpio_out"),
600 SUNXI_FUNCTION(0x2, "uart1"), /* RTS */
601 SUNXI_FUNCTION(0x3, "pll0"), /* STA_DB */
602 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 8)),
603 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
604 SUNXI_FUNCTION(0x0, "gpio_in"),
605 SUNXI_FUNCTION(0x1, "gpio_out"),
606 SUNXI_FUNCTION(0x2, "uart1"), /* CTS */
607 SUNXI_FUNCTION(0x3, "pll0"), /* TEST_GPIO */
608 SUNXI_FUNCTION(0x5, "ac"), /* ADCY */
609 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 9)),
610 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
611 SUNXI_FUNCTION(0x0, "gpio_in"),
612 SUNXI_FUNCTION(0x1, "gpio_out"),
613 SUNXI_FUNCTION(0x2, "i2s2"), /* MCLK */
614 SUNXI_FUNCTION(0x3, "x32kfout"),
615 SUNXI_FUNCTION(0x5, "ac"), /* MCLK */
616 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 10)),
617 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
618 SUNXI_FUNCTION(0x0, "gpio_in"),
619 SUNXI_FUNCTION(0x1, "gpio_out"),
620 SUNXI_FUNCTION(0x2, "i2s2"), /* BCLK */
621 SUNXI_FUNCTION(0x5, "ac"), /* SYNC */
622 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 11)),
623 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
624 SUNXI_FUNCTION(0x0, "gpio_in"),
625 SUNXI_FUNCTION(0x1, "gpio_out"),
626 SUNXI_FUNCTION(0x2, "i2s2"), /* LRLK */
627 SUNXI_FUNCTION(0x4, "bist0"), /* RESULT1 */
628 SUNXI_FUNCTION(0x5, "ac"), /* ADCL */
629 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 12)),
630 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
631 SUNXI_FUNCTION(0x0, "gpio_in"),
632 SUNXI_FUNCTION(0x1, "gpio_out"),
633 SUNXI_FUNCTION(0x2, "i2s2_dout0"), /* DOUT0 */
634 SUNXI_FUNCTION(0x3, "i2s2_din1"), /* DIN1 */
635 SUNXI_FUNCTION(0x4, "bist0"), /* RESULT2 */
636 SUNXI_FUNCTION(0x5, "ac"), /* ADCR */
637 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 13)),
638 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14),
639 SUNXI_FUNCTION(0x0, "gpio_in"),
640 SUNXI_FUNCTION(0x1, "gpio_out"),
641 SUNXI_FUNCTION(0x2, "i2s2_din0"), /* DIN0 */
642 SUNXI_FUNCTION(0x3, "i2s2_dout1"), /* DOUT1 */
643 SUNXI_FUNCTION(0x4, "bist0"), /* RESULT3 */
644 SUNXI_FUNCTION(0x5, "ac"), /* ADCX */
645 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 14)),
646 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 15),
647 SUNXI_FUNCTION(0x0, "gpio_in"),
648 SUNXI_FUNCTION(0x1, "gpio_out"),
649 SUNXI_FUNCTION(0x2, "uart2"), /* TX */
650 SUNXI_FUNCTION(0x5, "twi4"), /* SCK */
651 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 15)),
652 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 16),
653 SUNXI_FUNCTION(0x0, "gpio_in"),
654 SUNXI_FUNCTION(0x1, "gpio_out"),
655 SUNXI_FUNCTION(0x2, "uart2"), /* RX */
656 SUNXI_FUNCTION(0x5, "twi4"), /* SDA */
657 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 16)),
658 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 17),
659 SUNXI_FUNCTION(0x0, "gpio_in"),
660 SUNXI_FUNCTION(0x1, "gpio_out"),
661 SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
662 SUNXI_FUNCTION(0x3, "csi_cci0"), /* SCK */
663 SUNXI_FUNCTION(0x5, "twi3"), /* SCK */
664 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 17)),
665 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 18),
666 SUNXI_FUNCTION(0x0, "gpio_in"),
667 SUNXI_FUNCTION(0x1, "gpio_out"),
668 SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
669 SUNXI_FUNCTION(0x3, "csi_cci0"), /* SDA */
670 SUNXI_FUNCTION(0x5, "twi3"), /* SDA */
671 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 18)),
672 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 19),
673 SUNXI_FUNCTION(0x0, "gpio_in"),
674 SUNXI_FUNCTION(0x1, "gpio_out"),
675 SUNXI_FUNCTION(0x3, "csi_mclk0"), /* MCLK */
676 SUNXI_FUNCTION(0x4, "pwm1"),
677 SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 19)),
678 /* HOLE */
679 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
680 SUNXI_FUNCTION(0x0, "gpio_in"),
681 SUNXI_FUNCTION(0x1, "gpio_out"),
682 SUNXI_FUNCTION(0x2, "uart0"), /* TX */
683 SUNXI_FUNCTION(0x3, "can0"), /* TX */
684 SUNXI_FUNCTION(0x4, "pwm3"),
685 SUNXI_FUNCTION(0x5, "twi1"), /* SCK */
686 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 0)),
687 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
688 SUNXI_FUNCTION(0x0, "gpio_in"),
689 SUNXI_FUNCTION(0x1, "gpio_out"),
690 SUNXI_FUNCTION(0x2, "uart0"), /* RX */
691 SUNXI_FUNCTION(0x3, "can0"), /* RX */
692 SUNXI_FUNCTION(0x4, "pwm4"),
693 SUNXI_FUNCTION(0x5, "twi1"), /* SDA */
694 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 1)),
695 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
696 SUNXI_FUNCTION(0x0, "gpio_in"),
697 SUNXI_FUNCTION(0x1, "gpio_out"),
698 SUNXI_FUNCTION(0x2, "uart5"), /* TX */
699 SUNXI_FUNCTION(0x3, "spdif"), /* CLK */
700 SUNXI_FUNCTION(0x4, "pwm2"),
701 SUNXI_FUNCTION(0x5, "twi2"), /* SCK */
702 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 2)),
703 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
704 SUNXI_FUNCTION(0x0, "gpio_in"),
705 SUNXI_FUNCTION(0x1, "gpio_out"),
706 SUNXI_FUNCTION(0x2, "uart5"), /* RX */
707 SUNXI_FUNCTION(0x3, "spdif"), /* IN */
708 SUNXI_FUNCTION(0x4, "pwm1"),
709 SUNXI_FUNCTION(0x5, "twi2"), /* SDA */
710 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 3)),
711 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
712 SUNXI_FUNCTION(0x0, "gpio_in"),
713 SUNXI_FUNCTION(0x1, "gpio_out"),
714 SUNXI_FUNCTION(0x3, "spdif"), /* OUT */
715 SUNXI_FUNCTION(0x5, "twi3"), /* SCK */
716 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 4)),
717 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
718 SUNXI_FUNCTION(0x0, "gpio_in"),
719 SUNXI_FUNCTION(0x1, "gpio_out"),
720 SUNXI_FUNCTION(0x2, "uart2"), /* TX */
721 SUNXI_FUNCTION(0x3, "i2s3"), /* MCLK */
722 SUNXI_FUNCTION(0x4, "spi1"), /* CS0 */
723 SUNXI_FUNCTION(0x5, "twi3"), /* SDA */
724 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 5)),
725 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
726 SUNXI_FUNCTION(0x0, "gpio_in"),
727 SUNXI_FUNCTION(0x1, "gpio_out"),
728 SUNXI_FUNCTION(0x2, "uart2"), /* RX */
729 SUNXI_FUNCTION(0x3, "i2s3"), /* BCLK */
730 SUNXI_FUNCTION(0x4, "spi1"), /* CLK */
731 SUNXI_FUNCTION(0x5, "twi4"), /* SCK */
732 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 6)),
733 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
734 SUNXI_FUNCTION(0x0, "gpio_in"),
735 SUNXI_FUNCTION(0x1, "gpio_out"),
736 SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
737 SUNXI_FUNCTION(0x3, "i2s3"), /* LRLK */
738 SUNXI_FUNCTION(0x4, "spi1"), /* MOSI */
739 SUNXI_FUNCTION(0x5, "twi4"), /* SDA */
740 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 7)),
741 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
742 SUNXI_FUNCTION(0x0, "gpio_in"),
743 SUNXI_FUNCTION(0x1, "gpio_out"),
744 SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
745 SUNXI_FUNCTION(0x3, "i2s3_dout0"), /* DOUT0 */
746 SUNXI_FUNCTION(0x4, "spi1"), /* MISO */
747 SUNXI_FUNCTION(0x5, "i2s3_din1"), /* DIN1 */
748 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 8)),
749 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
750 SUNXI_FUNCTION(0x0, "gpio_in"),
751 SUNXI_FUNCTION(0x1, "gpio_out"),
752 SUNXI_FUNCTION(0x3, "i2s3_din0"), /* DIN0 */
753 SUNXI_FUNCTION(0x4, "spi1"), /* CS1 */
754 SUNXI_FUNCTION(0x5, "i2s3_dout1"), /* DOUT1 */
755 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 9)),
756 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
757 SUNXI_FUNCTION(0x0, "gpio_in"),
758 SUNXI_FUNCTION(0x1, "gpio_out"),
759 SUNXI_FUNCTION(0x3, "ir"), /* RX */
760 SUNXI_FUNCTION(0x4, "tcon"), /* TRIG1 */
761 SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 10)),
762 /* HOLE */
763 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 0),
764 SUNXI_FUNCTION(0x0, "gpio_in"),
765 SUNXI_FUNCTION(0x1, "gpio_out"),
766 SUNXI_FUNCTION(0x2, "emac0"), /* RXD3 / RMII_NULL */
767 SUNXI_FUNCTION(0x3, "dmic"), /* CLK */
768 SUNXI_FUNCTION(0x4, "i2s0"), /* MCLK */
769 SUNXI_FUNCTION(0x5, "hdmi"), /* SCL */
770 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 0)),
771 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 1),
772 SUNXI_FUNCTION(0x0, "gpio_in"),
773 SUNXI_FUNCTION(0x1, "gpio_out"),
774 SUNXI_FUNCTION(0x2, "emac0"), /* RXD2 / RMII_NULL */
775 SUNXI_FUNCTION(0x3, "dmic"), /* DATA0 */
776 SUNXI_FUNCTION(0x4, "i2s0"), /* BCLK */
777 SUNXI_FUNCTION(0x5, "hdmi"), /* SDA */
778 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 1)),
779 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 2),
780 SUNXI_FUNCTION(0x0, "gpio_in"),
781 SUNXI_FUNCTION(0x1, "gpio_out"),
782 SUNXI_FUNCTION(0x2, "emac0"), /* RXD1 / RMII_RXD1 */
783 SUNXI_FUNCTION(0x3, "dmic"), /* DATA1 */
784 SUNXI_FUNCTION(0x4, "i2s0"), /* LRLK */
785 SUNXI_FUNCTION(0x5, "hdmi"), /* CEC */
786 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 2)),
787 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 3),
788 SUNXI_FUNCTION(0x0, "gpio_in"),
789 SUNXI_FUNCTION(0x1, "gpio_out"),
790 SUNXI_FUNCTION(0x2, "emac0"), /* RXD0 / RMII_RXD0 */
791 SUNXI_FUNCTION(0x3, "dmic"), /* DATA2 */
792 SUNXI_FUNCTION(0x4, "i2s0_dout0"), /* DOUT0 */
793 SUNXI_FUNCTION(0x5, "i2s0_din1"), /* DIN1 */
794 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 3)),
795 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 4),
796 SUNXI_FUNCTION(0x0, "gpio_in"),
797 SUNXI_FUNCTION(0x1, "gpio_out"),
798 SUNXI_FUNCTION(0x2, "emac0"), /* RXCK / RMII_NULL */
799 SUNXI_FUNCTION(0x3, "dmic"), /* DATA3 */
800 SUNXI_FUNCTION(0x4, "i2s0_din0"), /* DIN0 */
801 SUNXI_FUNCTION(0x5, "i2s0_dout1"), /* DOUT1 */
802 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 4)),
803 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 5),
804 SUNXI_FUNCTION(0x0, "gpio_in"),
805 SUNXI_FUNCTION(0x1, "gpio_out"),
806 SUNXI_FUNCTION(0x2, "emac0"), /* RXCT / RMII_CRS_DV */
807 SUNXI_FUNCTION(0x3, "uart2"), /* TX */
808 SUNXI_FUNCTION(0x4, "ts0"), /* CLK */
809 SUNXI_FUNCTION(0x5, "twi0"), /* SCK */
810 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 5)),
811 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 6),
812 SUNXI_FUNCTION(0x0, "gpio_in"),
813 SUNXI_FUNCTION(0x1, "gpio_out"),
814 SUNXI_FUNCTION(0x2, "emac0"), /* NULL / RMII_RXER */
815 SUNXI_FUNCTION(0x3, "uart2"), /* RX */
816 SUNXI_FUNCTION(0x4, "ts0"), /* ERR */
817 SUNXI_FUNCTION(0x5, "twi0"), /* SDA */
818 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 6)),
819 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 7),
820 SUNXI_FUNCTION(0x0, "gpio_in"),
821 SUNXI_FUNCTION(0x1, "gpio_out"),
822 SUNXI_FUNCTION(0x2, "emac0"), /* TXD3 / RMII_NULL */
823 SUNXI_FUNCTION(0x3, "uart2"), /* RTS */
824 SUNXI_FUNCTION(0x4, "ts0"), /* SYNC */
825 SUNXI_FUNCTION(0x5, "twi1"), /* SCK */
826 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 7)),
827 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 8),
828 SUNXI_FUNCTION(0x0, "gpio_in"),
829 SUNXI_FUNCTION(0x1, "gpio_out"),
830 SUNXI_FUNCTION(0x2, "emac0"), /* TXD2 / RMII_NULL */
831 SUNXI_FUNCTION(0x3, "uart2"), /* RTS */
832 SUNXI_FUNCTION(0x4, "ts0"), /* DVLD */
833 SUNXI_FUNCTION(0x5, "twi1"), /* SDA */
834 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 8)),
835 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 9),
836 SUNXI_FUNCTION(0x0, "gpio_in"),
837 SUNXI_FUNCTION(0x1, "gpio_out"),
838 SUNXI_FUNCTION(0x2, "emac0"), /* TXD1 / RMII_TXD1 */
839 SUNXI_FUNCTION(0x3, "uart3"), /* TX */
840 SUNXI_FUNCTION(0x4, "ts0"), /* D0 */
841 SUNXI_FUNCTION(0x5, "twi2"), /* SCK */
842 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 9)),
843 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 10),
844 SUNXI_FUNCTION(0x0, "gpio_in"),
845 SUNXI_FUNCTION(0x1, "gpio_out"),
846 SUNXI_FUNCTION(0x2, "emac0"), /* TXD0 / RMII_TXD0 */
847 SUNXI_FUNCTION(0x3, "uart3"), /* RX */
848 SUNXI_FUNCTION(0x4, "ts0"), /* D1 */
849 SUNXI_FUNCTION(0x5, "twi2"), /* SDA */
850 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 10)),
851 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 11),
852 SUNXI_FUNCTION(0x0, "gpio_in"),
853 SUNXI_FUNCTION(0x1, "gpio_out"),
854 SUNXI_FUNCTION(0x2, "emac0"), /* TXCK / RMII_TXCK */
855 SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
856 SUNXI_FUNCTION(0x4, "ts0"), /* D2 */
857 SUNXI_FUNCTION(0x5, "pwm1"), /* SCK */
858 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 11)),
859 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 12),
860 SUNXI_FUNCTION(0x0, "gpio_in"),
861 SUNXI_FUNCTION(0x1, "gpio_out"),
862 SUNXI_FUNCTION(0x2, "emac0"), /* TXCTL / RMII_TXEN */
863 SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
864 SUNXI_FUNCTION(0x4, "twi3"), /* SDA */
865 SUNXI_FUNCTION(0x5, "pwm2"), /* SCK */
866 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 12)),
867 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 13),
868 SUNXI_FUNCTION(0x0, "gpio_in"),
869 SUNXI_FUNCTION(0x1, "gpio_out"),
870 SUNXI_FUNCTION(0x2, "emac0"), /* CLKIN / RMII_NULL */
871 SUNXI_FUNCTION(0x3, "uart4"), /* TX */
872 SUNXI_FUNCTION(0x4, "ts0"), /* D4 */
873 SUNXI_FUNCTION(0x5, "pwm3"),
874 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 13)),
875 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 14),
876 SUNXI_FUNCTION(0x0, "gpio_in"),
877 SUNXI_FUNCTION(0x1, "gpio_out"),
878 SUNXI_FUNCTION(0x2, "emac0"),
879 SUNXI_FUNCTION(0x3, "uart4"), /* RX */
880 SUNXI_FUNCTION(0x4, "ts0"), /* D5 */
881 SUNXI_FUNCTION(0x5, "pwm4"),
882 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 14)),
883 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 15),
884 SUNXI_FUNCTION(0x0, "gpio_in"),
885 SUNXI_FUNCTION(0x1, "gpio_out"),
886 SUNXI_FUNCTION(0x2, "emac0"),
887 SUNXI_FUNCTION(0x3, "uart4"), /* RTS */
888 SUNXI_FUNCTION(0x4, "ts0"), /* D6 */
889 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 15)),
890 SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 16),
891 SUNXI_FUNCTION(0x0, "gpio_in"),
892 SUNXI_FUNCTION(0x1, "gpio_out"),
893 SUNXI_FUNCTION(0x2, "emac0"),
894 SUNXI_FUNCTION(0x3, "uart4"), /* CTS */
895 SUNXI_FUNCTION(0x4, "ts0"), /* D7 */
896 SUNXI_FUNCTION(0x5, "x32kfout"),
897 SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 16)),
898 };
899
900 static const unsigned int sun50iw9_irq_bank_map[] = {
901 SUNXI_BANK_OFFSET('A', 'A'),
902 SUNXI_BANK_OFFSET('C', 'A'),
903 SUNXI_BANK_OFFSET('D', 'A'),
904 SUNXI_BANK_OFFSET('E', 'A'),
905 SUNXI_BANK_OFFSET('F', 'A'),
906 SUNXI_BANK_OFFSET('G', 'A'),
907 SUNXI_BANK_OFFSET('H', 'A'),
908 SUNXI_BANK_OFFSET('I', 'A'),
909 };
910
911 static const struct sunxi_pinctrl_desc sun50iw9_pinctrl_data = {
912 .pins = sun50iw9_pins,
913 .npins = ARRAY_SIZE(sun50iw9_pins),
914 .irq_banks = ARRAY_SIZE(sun50iw9_irq_bank_map),
915 .irq_bank_map = sun50iw9_irq_bank_map,
916 .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_CTL,
917 .pf_power_source_switch = true,
918 .hw_type = SUNXI_PCTL_HW_TYPE_0,
919 };
920
921 static void *mem;
922 static int mem_size;
923
sun50iw9_pinctrl_probe(struct platform_device * pdev)924 static int sun50iw9_pinctrl_probe(struct platform_device *pdev)
925 {
926 struct resource *res;
927
928 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
929 if (!res)
930 return -EINVAL;
931 mem_size = resource_size(res);
932
933 mem = devm_kzalloc(&pdev->dev, mem_size, GFP_KERNEL);
934 if (!mem)
935 return -ENOMEM;
936
937 return sunxi_bsp_pinctrl_init(pdev, &sun50iw9_pinctrl_data);
938 }
939
sun50iw9_pinctrl_suspend_noirq(struct device * dev)940 static int __maybe_unused sun50iw9_pinctrl_suspend_noirq(struct device *dev)
941 {
942 struct sunxi_pinctrl *pctl = dev_get_drvdata(dev);
943 unsigned long flags;
944
945 raw_spin_lock_irqsave(&pctl->lock, flags);
946 memcpy(mem, pctl->membase, mem_size);
947 raw_spin_unlock_irqrestore(&pctl->lock, flags);
948
949 return 0;
950 }
951
sun50iw9_pinctrl_resume_noirq(struct device * dev)952 static int __maybe_unused sun50iw9_pinctrl_resume_noirq(struct device *dev)
953 {
954 struct sunxi_pinctrl *pctl = dev_get_drvdata(dev);
955 unsigned long flags;
956
957 raw_spin_lock_irqsave(&pctl->lock, flags);
958 memcpy(pctl->membase, mem, mem_size);
959 raw_spin_unlock_irqrestore(&pctl->lock, flags);
960
961 return 0;
962 }
963
964 static struct of_device_id sun50iw9_pinctrl_match[] = {
965 { .compatible = "allwinner,sun50iw9-pinctrl", },
966 {}
967 };
968 MODULE_DEVICE_TABLE(of, sun50iw9_pinctrl_match);
969
970 static const struct dev_pm_ops sun50iw9_pinctrl_pm_ops = {
971 .suspend_noirq = sun50iw9_pinctrl_suspend_noirq,
972 .resume_noirq = sun50iw9_pinctrl_resume_noirq,
973 };
974
975 static struct platform_driver sun50iw9_pinctrl_driver = {
976 .probe = sun50iw9_pinctrl_probe,
977 .driver = {
978 .name = "sun50iw9-pinctrl",
979 .pm = &sun50iw9_pinctrl_pm_ops,
980 .of_match_table = sun50iw9_pinctrl_match,
981 },
982 };
983
sun50iw9_pio_init(void)984 static int __init sun50iw9_pio_init(void)
985 {
986 return platform_driver_register(&sun50iw9_pinctrl_driver);
987 }
988 postcore_initcall(sun50iw9_pio_init);
989
990 MODULE_DESCRIPTION("Allwinner sun50iw9 pio pinctrl driver");
991 MODULE_LICENSE("GPL");
992 MODULE_VERSION("1.0.0");
993