1 /*
2 * Allwinner A1X SoCs pinctrl driver.
3 *
4 * Copyright (C) 2012 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13 #ifndef __PINCTRL_SUNXI_H
14 #define __PINCTRL_SUNXI_H
15
16 #include <linux/kernel.h>
17 #include <linux/spinlock.h>
18 #include <linux/pinctrl/pinconf-generic.h>
19
20 #define SUNXI_BANK_OFFSET(bank, bankbase) ((bank) - (bankbase))
21 #define SUNXI_PIN_BASE(bank) (SUNXI_BANK_OFFSET(bank, 'A') * 32)
22
23 #define PA_BASE SUNXI_PIN_BASE('A')
24 #define PB_BASE SUNXI_PIN_BASE('B')
25 #define PC_BASE SUNXI_PIN_BASE('C')
26 #define PD_BASE SUNXI_PIN_BASE('D')
27 #define PE_BASE SUNXI_PIN_BASE('E')
28 #define PF_BASE SUNXI_PIN_BASE('F')
29 #define PG_BASE SUNXI_PIN_BASE('G')
30 #define PH_BASE SUNXI_PIN_BASE('H')
31 #define PI_BASE SUNXI_PIN_BASE('I')
32 #define PJ_BASE SUNXI_PIN_BASE('J')
33 #define PL_BASE SUNXI_PIN_BASE('L')
34 #define PM_BASE SUNXI_PIN_BASE('M')
35 #define PN_BASE SUNXI_PIN_BASE('N')
36
37 #define SUNXI_PINCTRL_PIN(bank, pin) \
38 PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)
39
40 #define SUNXI_PIN_NAME_MAX_LEN 5
41
42 #define MUX_REGS_OFFSET 0x0
43 #define DATA_REGS_OFFSET 0x10
44 #define DLEVEL_REGS_OFFSET 0x14
45
46 #define PINS_PER_BANK 32
47 #define MUX_PINS_PER_REG 8
48 #define MUX_PINS_BITS 4
49 #define MUX_PINS_MASK 0x0f
50 #define DATA_PINS_PER_REG 32
51 #define DATA_PINS_BITS 1
52 #define DATA_PINS_MASK 0x01
53 #define PULL_PINS_PER_REG 16
54 #define PULL_PINS_BITS 2
55 #define PULL_PINS_MASK 0x03
56
57 #define IRQ_PER_BANK 32
58
59 #define IRQ_CFG_REG 0x200
60 #define IRQ_CFG_IRQ_PER_REG 8
61 #define IRQ_CFG_IRQ_BITS 4
62 #define IRQ_CFG_IRQ_MASK ((1 << IRQ_CFG_IRQ_BITS) - 1)
63 #define IRQ_CTRL_REG 0x210
64 #define IRQ_CTRL_IRQ_PER_REG 32
65 #define IRQ_CTRL_IRQ_BITS 1
66 #define IRQ_CTRL_IRQ_MASK ((1 << IRQ_CTRL_IRQ_BITS) - 1)
67 #define IRQ_STATUS_REG 0x214
68 #define IRQ_STATUS_IRQ_PER_REG 32
69 #define IRQ_STATUS_IRQ_BITS 1
70 #define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1)
71
72 #define IRQ_DEBOUNCE_REG 0x218
73
74 #define IRQ_MEM_SIZE 0x20
75
76 #define IRQ_EDGE_RISING 0x00
77 #define IRQ_EDGE_FALLING 0x01
78 #define IRQ_LEVEL_HIGH 0x02
79 #define IRQ_LEVEL_LOW 0x03
80 #define IRQ_EDGE_BOTH 0x04
81
82 #define GRP_CFG_REG 0x300
83
84 #define IO_BIAS_MASK GENMASK(3, 0)
85
86 #define SUN4I_FUNC_INPUT 0
87
88 #define PINCTRL_SUN5I_A10S BIT(1)
89 #define PINCTRL_SUN5I_A13 BIT(2)
90 #define PINCTRL_SUN5I_GR8 BIT(3)
91 #define PINCTRL_SUN6I_A31 BIT(4)
92 #define PINCTRL_SUN6I_A31S BIT(5)
93 #define PINCTRL_SUN4I_A10 BIT(6)
94 #define PINCTRL_SUN7I_A20 BIT(7)
95 #define PINCTRL_SUN8I_R40 BIT(8)
96 #define PINCTRL_SUN8I_V3 BIT(9)
97 #define PINCTRL_SUN8I_V3S BIT(10)
98
99 #define PIO_POW_MOD_SEL_REG 0x340
100 #define PIO_POW_MOD_CTL_REG 0x344
101 #define PIO_POW_CTL_REG 0x350
102
103 #define POWER_SOURCE_MASK 0x01
104
105 #if IS_ENABLED(CONFIG_PINCTRL_SUNXI_DEBUGFS)
106 #define SUNXI_PINCFG_TYPE_FUNC (PIN_CONFIG_END - 2)
107 #define SUNXI_PINCFG_TYPE_DAT (PIN_CONFIG_END - 1)
108 #endif
109 enum sunxi_desc_bias_voltage {
110 BIAS_VOLTAGE_NONE,
111 /*
112 * Bias voltage configuration is done through
113 * Pn_GRP_CONFIG registers, as seen on A80 SoC.
114 */
115 BIAS_VOLTAGE_GRP_CONFIG,
116 /*
117 * Bias voltage is set through PIO_POW_MOD_SEL_REG
118 * register, as seen on H6 SoC, for example.
119 */
120 BIAS_VOLTAGE_PIO_POW_MODE_SEL,
121 /*
122 * Bias voltage is set through PIO_POW_MOD_SEL_REG
123 * and PIO_POW_MOD_CTL_REG register, as seen on
124 * A100 SoC, for example.
125 */
126 BIAS_VOLTAGE_PIO_POW_MODE_CTL,
127 };
128
129 enum sunxi_pinctrl_hw_type {
130 SUNXI_PCTL_HW_TYPE_0, /* Older chips */
131 SUNXI_PCTL_HW_TYPE_1, /* Newer chips: sun8iw20, sun20iw1, sun50iw12 */
132 /* Add new types here ... */
133 SUNXI_PCTL_HW_TYPE_CNT,
134 };
135
136 /* Reference <Port_Controller_Spec: Port Register List> for the information below: */
137 struct sunxi_pinctrl_hw_info {
138 u8 bank_mem_size; /* Size of the basic registers (including CFG/DAT/DRV/PUL) of any bank */
139 u8 pull_regs_offset; /* Pull Register's offset */
140 u8 dlevel_pins_per_reg; /* How many pins does a 'Multi-Driving Register' contain? */
141 u8 dlevel_pins_bits; /* How many bits does a 'Multi-Driving Register' use for a pin? */
142 u8 dlevel_pins_mask; /* Bit mask for 'dlevel_pins_bits' */
143 u8 irq_mux_val; /* Mux value for IRQ function */
144 };
145
146 /* Indexed by `enum sunxi_pinctrl_hw_type` */
147 extern struct sunxi_pinctrl_hw_info sunxi_pinctrl_hw_info[SUNXI_PCTL_HW_TYPE_CNT];
148
149 struct sunxi_desc_function {
150 unsigned long variant;
151 const char *name;
152 u8 muxval;
153 u8 irqbank;
154 u8 irqnum;
155 };
156
157 struct sunxi_desc_pin {
158 struct pinctrl_pin_desc pin;
159 unsigned long variant;
160 struct sunxi_desc_function *functions;
161 };
162
163 struct sunxi_pinctrl_desc {
164 const struct sunxi_desc_pin *pins;
165 int npins;
166 unsigned pin_base;
167 unsigned irq_banks;
168 const unsigned int *irq_bank_map;
169 bool irq_read_needs_mux;
170 bool disable_strict_mode;
171 enum sunxi_desc_bias_voltage io_bias_cfg_variant;
172 bool pf_power_source_switch;
173 enum sunxi_pinctrl_hw_type hw_type;
174 };
175
176 struct sunxi_pinctrl_function {
177 const char *name;
178 const char **groups;
179 unsigned ngroups;
180 };
181
182 struct sunxi_pinctrl_group {
183 const char *name;
184 unsigned pin;
185 };
186
187 struct sunxi_pinctrl_regulator {
188 struct regulator *regulator;
189 struct regulator *regulator_optional;
190 refcount_t refcount;
191 };
192
193 struct sunxi_pinctrl {
194 void __iomem *membase;
195 struct gpio_chip *chip;
196 const struct sunxi_pinctrl_desc *desc;
197 struct device *dev;
198 struct sunxi_pinctrl_regulator regulators[9];
199 struct irq_domain *domain;
200 struct sunxi_pinctrl_function *functions;
201 unsigned nfunctions;
202 struct sunxi_pinctrl_group *groups;
203 unsigned ngroups;
204 int *irq;
205 unsigned *irq_array;
206 raw_spinlock_t lock;
207 struct pinctrl_dev *pctl_dev;
208 unsigned long variant;
209 };
210
211 #define SUNXI_PIN(_pin, ...) \
212 { \
213 .pin = _pin, \
214 .functions = (struct sunxi_desc_function[]){ \
215 __VA_ARGS__, { } }, \
216 }
217
218 #define SUNXI_PIN_VARIANT(_pin, _variant, ...) \
219 { \
220 .pin = _pin, \
221 .variant = _variant, \
222 .functions = (struct sunxi_desc_function[]){ \
223 __VA_ARGS__, { } }, \
224 }
225
226 #define SUNXI_FUNCTION(_val, _name) \
227 { \
228 .name = _name, \
229 .muxval = _val, \
230 }
231
232 #define SUNXI_FUNCTION_VARIANT(_val, _name, _variant) \
233 { \
234 .name = _name, \
235 .muxval = _val, \
236 .variant = _variant, \
237 }
238
239 #define SUNXI_FUNCTION_IRQ(_val, _irq) \
240 { \
241 .name = "irq", \
242 .muxval = _val, \
243 .irqnum = _irq, \
244 }
245
246 #define SUNXI_FUNCTION_IRQ_BANK(_val, _bank, _irq) \
247 { \
248 .name = "irq", \
249 .muxval = _val, \
250 .irqbank = _bank, \
251 .irqnum = _irq, \
252 }
253
254 /*
255 * The sunXi PIO registers are organized as is:
256 * 0x00 - 0x0c Muxing values.
257 * 8 pins per register, each pin having a 4bits value
258 * 0x10 Pin values
259 * 32 bits per register, each pin corresponding to one bit
260 * 0x14 - 0x18 Drive level
261 * 16 pins per register, each pin having a 2bits value
262 * 0x1c - 0x20 Pull-Up values
263 * 16 pins per register, each pin having a 2bits value
264 *
265 * This is for the first bank. Each bank will have the same layout,
266 * with an offset being a multiple of 0x24.
267 *
268 * The following functions calculate from the pin number the register
269 * and the bit offset that we should access.
270 */
sunxi_mux_reg(u16 pin,enum sunxi_pinctrl_hw_type hw_type)271 static inline u32 sunxi_mux_reg(u16 pin, enum sunxi_pinctrl_hw_type hw_type)
272 {
273 u8 bank = pin / PINS_PER_BANK;
274 u32 offset = bank * sunxi_pinctrl_hw_info[hw_type].bank_mem_size;
275 offset += MUX_REGS_OFFSET;
276 offset += pin % PINS_PER_BANK / MUX_PINS_PER_REG * 0x04;
277 return round_down(offset, 4);
278 }
279
sunxi_mux_offset(u16 pin)280 static inline u32 sunxi_mux_offset(u16 pin)
281 {
282 u32 pin_num = pin % MUX_PINS_PER_REG;
283 return pin_num * MUX_PINS_BITS;
284 }
285
sunxi_data_reg(u16 pin,enum sunxi_pinctrl_hw_type hw_type)286 static inline u32 sunxi_data_reg(u16 pin, enum sunxi_pinctrl_hw_type hw_type)
287 {
288 u8 bank = pin / PINS_PER_BANK;
289 u32 offset = bank * sunxi_pinctrl_hw_info[hw_type].bank_mem_size;
290 offset += DATA_REGS_OFFSET;
291 offset += pin % PINS_PER_BANK / DATA_PINS_PER_REG * 0x04;
292 return round_down(offset, 4);
293 }
294
sunxi_data_offset(u16 pin)295 static inline u32 sunxi_data_offset(u16 pin)
296 {
297 u32 pin_num = pin % DATA_PINS_PER_REG;
298 return pin_num * DATA_PINS_BITS;
299 }
300
sunxi_dlevel_reg(u16 pin,enum sunxi_pinctrl_hw_type hw_type)301 static inline u32 sunxi_dlevel_reg(u16 pin, enum sunxi_pinctrl_hw_type hw_type)
302 {
303 u8 bank = pin / PINS_PER_BANK;
304 u32 offset = bank * sunxi_pinctrl_hw_info[hw_type].bank_mem_size;
305 offset += DLEVEL_REGS_OFFSET;
306 offset += pin % PINS_PER_BANK / sunxi_pinctrl_hw_info[hw_type].dlevel_pins_per_reg * 0x04;
307 return round_down(offset, 4);
308 }
309
sunxi_dlevel_offset(u16 pin,enum sunxi_pinctrl_hw_type hw_type)310 static inline u32 sunxi_dlevel_offset(u16 pin, enum sunxi_pinctrl_hw_type hw_type)
311 {
312 u32 pin_num = pin % sunxi_pinctrl_hw_info[hw_type].dlevel_pins_per_reg;
313 return pin_num * sunxi_pinctrl_hw_info[hw_type].dlevel_pins_bits;
314 }
315
sunxi_pull_reg(u16 pin,enum sunxi_pinctrl_hw_type hw_type)316 static inline u32 sunxi_pull_reg(u16 pin, enum sunxi_pinctrl_hw_type hw_type)
317 {
318 u8 bank = pin / PINS_PER_BANK;
319 u32 offset = bank * sunxi_pinctrl_hw_info[hw_type].bank_mem_size;
320 offset += sunxi_pinctrl_hw_info[hw_type].pull_regs_offset;
321 offset += pin % PINS_PER_BANK / PULL_PINS_PER_REG * 0x04;
322 return round_down(offset, 4);
323 }
324
sunxi_pull_offset(u16 pin)325 static inline u32 sunxi_pull_offset(u16 pin)
326 {
327 u32 pin_num = pin % PULL_PINS_PER_REG;
328 return pin_num * PULL_PINS_BITS;
329 }
330
sunxi_irq_hw_bank_num(const struct sunxi_pinctrl_desc * desc,u8 bank)331 static inline u32 sunxi_irq_hw_bank_num(const struct sunxi_pinctrl_desc *desc, u8 bank)
332 {
333 BUG_ON(bank >= desc->irq_banks);
334 if (!desc->irq_bank_map)
335 return bank;
336 else
337 return desc->irq_bank_map[bank];
338 }
339
sunxi_irq_cfg_reg(const struct sunxi_pinctrl_desc * desc,u16 irq)340 static inline u32 sunxi_irq_cfg_reg(const struct sunxi_pinctrl_desc *desc,
341 u16 irq)
342 {
343 u8 bank = irq / IRQ_PER_BANK;
344 u8 reg = (irq % IRQ_PER_BANK) / IRQ_CFG_IRQ_PER_REG * 0x04;
345
346 return IRQ_CFG_REG +
347 sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE + reg;
348 }
349
sunxi_irq_cfg_offset(u16 irq)350 static inline u32 sunxi_irq_cfg_offset(u16 irq)
351 {
352 u32 irq_num = irq % IRQ_CFG_IRQ_PER_REG;
353 return irq_num * IRQ_CFG_IRQ_BITS;
354 }
355
sunxi_irq_ctrl_reg_from_bank(const struct sunxi_pinctrl_desc * desc,u8 bank)356 static inline u32 sunxi_irq_ctrl_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
357 {
358 return IRQ_CTRL_REG + sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
359 }
360
sunxi_irq_ctrl_reg(const struct sunxi_pinctrl_desc * desc,u16 irq)361 static inline u32 sunxi_irq_ctrl_reg(const struct sunxi_pinctrl_desc *desc,
362 u16 irq)
363 {
364 u8 bank = irq / IRQ_PER_BANK;
365
366 return sunxi_irq_ctrl_reg_from_bank(desc, bank);
367 }
368
sunxi_irq_ctrl_offset(u16 irq)369 static inline u32 sunxi_irq_ctrl_offset(u16 irq)
370 {
371 u32 irq_num = irq % IRQ_CTRL_IRQ_PER_REG;
372 return irq_num * IRQ_CTRL_IRQ_BITS;
373 }
374
sunxi_irq_debounce_reg_from_bank(const struct sunxi_pinctrl_desc * desc,u8 bank)375 static inline u32 sunxi_irq_debounce_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
376 {
377 return IRQ_DEBOUNCE_REG +
378 sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
379 }
380
sunxi_irq_status_reg_from_bank(const struct sunxi_pinctrl_desc * desc,u8 bank)381 static inline u32 sunxi_irq_status_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
382 {
383 return IRQ_STATUS_REG +
384 sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
385 }
386
sunxi_irq_status_reg(const struct sunxi_pinctrl_desc * desc,u16 irq)387 static inline u32 sunxi_irq_status_reg(const struct sunxi_pinctrl_desc *desc,
388 u16 irq)
389 {
390 u8 bank = irq / IRQ_PER_BANK;
391
392 return sunxi_irq_status_reg_from_bank(desc, bank);
393 }
394
sunxi_irq_status_offset(u16 irq)395 static inline u32 sunxi_irq_status_offset(u16 irq)
396 {
397 u32 irq_num = irq % IRQ_STATUS_IRQ_PER_REG;
398 return irq_num * IRQ_STATUS_IRQ_BITS;
399 }
400
sunxi_grp_config_reg(u16 pin)401 static inline u32 sunxi_grp_config_reg(u16 pin)
402 {
403 u8 bank = pin / PINS_PER_BANK;
404
405 return GRP_CFG_REG + bank * 0x4;
406 }
407
408 int sunxi_bsp_pinctrl_init_with_variant(struct platform_device *pdev,
409 const struct sunxi_pinctrl_desc *desc,
410 unsigned long variant);
411
412 #define sunxi_bsp_pinctrl_init(_dev, _desc) \
413 sunxi_bsp_pinctrl_init_with_variant(_dev, _desc, 0)
414
415 #endif /* __PINCTRL_SUNXI_H */
416