1 /*
2 * drivers/pwm/pwm-sunxi.c
3 *
4 * Allwinnertech pulse-width-modulation controller driver
5 *
6 * Copyright (C) 2015 AllWinner
7 *
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13 //#define DEBUG
14 #include <linux/types.h>
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/cdev.h>
18 #include <linux/pwm.h>
19 #include <linux/platform_device.h>
20 #include <linux/slab.h>
21 #include <linux/err.h>
22 #include <linux/fs.h>
23 #include <linux/device.h>
24 #include <linux/gpio.h>
25 #include <linux/pinctrl/pinconf.h>
26 #include <linux/pinctrl/consumer.h>
27 #include <linux/of_irq.h>
28 #include <linux/of_address.h>
29 #include <linux/of_iommu.h>
30 #include <linux/of_device.h>
31 #include <linux/of_platform.h>
32 #include <linux/io.h>
33 #include <linux/clk.h>
34 #include <linux/reset.h>
35 #include "pwm-sunxi.h"
36
37 #define PWM_DEBUG 0
38 #define PWM_NUM_MAX 4
39 #define PWM_BIND_NUM 2
40 #define PWM_PIN_STATE_ACTIVE "active"
41 #define PWM_PIN_STATE_SLEEP "sleep"
42
43 #define SETMASK(width, shift) ((width?((-1U) >> (32-width)):0) << (shift))
44 #define CLRMASK(width, shift) (~(SETMASK(width, shift)))
45 #define GET_BITS(shift, width, reg) \
46 (((reg) & SETMASK(width, shift)) >> (shift))
47 #define SET_BITS(shift, width, reg, val) \
48 (((reg) & CLRMASK(width, shift)) | (val << (shift)))
49
50 #if PWM_DEBUG
51 #define pwm_debug(fmt, arg...) \
52 pr_info("%s()%d - "fmt, __func__, __LINE__, ##arg)
53 #else
54 #define pwm_debug(msg...)
55 #endif
56
57 struct sunxi_pwm_config {
58 unsigned int dead_time;
59 unsigned int bind_pwm;
60 };
61
62 struct group_pwm_config {
63 unsigned int group_channel;
64 unsigned int group_run_count;
65 unsigned int pwm_polarity;
66 int pwm_period;
67 };
68
69 struct sunxi_pwm_hw_data {
70 u32 pdzcr01_offset; /* PWM dead zone control register 01*/
71 u32 pdzcr23_offset; /* PWM dead zone control register 23*/
72 u32 pdzcr45_offset; /* PWM dead zone control register 45*/
73 u32 per_offset; /* PWM enable register */
74 u32 cer_offset; /* PWM capture enable register */
75 u32 ver_reg_offset; /* PWM version register */
76 u32 pcr_base_offset; /* PWM control register */
77 u32 ppr_base_offset; /* PWM period register */
78 u32 pcntr_base_offset; /* PWM counter register */
79 u32 ccr_base_offset; /* PWM capture control register */
80 u32 crlr_base_offset; /* PWM capture rise lock register */
81 u32 cflr_base_offset; /* PWM capture fall lock register */
82 int pm_regs_num; /* PWM pm related register length */
83 bool clk_gating_separate; /* PWM clk gating register whether to separate */
84 };
85
86 struct sunxi_pwm_chip {
87 struct pinctrl *pctl;
88 struct pwm_chip chip;
89 struct sunxi_pwm_hw_data *data;
90 struct sunxi_pwm_config *config;
91 struct clk *pwm_clk;
92 struct reset_control *pwm_rst_clk;
93 void __iomem *base;
94 unsigned int g_channel;
95 unsigned int g_polarity;
96 unsigned int start_count;
97 unsigned int g_period;
98 u32 *regs_backup;
99 u32 *pm_regs_offset;
100 };
101
102 static struct sunxi_pwm_hw_data sunxi_pwm_v100_data = {
103 .pdzcr01_offset = 0x0030,
104 .pdzcr23_offset = 0x0034,
105 .pdzcr45_offset = 0x0038,
106 .per_offset = 0x0040,
107 .cer_offset = 0x0044,
108 .ver_reg_offset = 0x0050,
109 .pcr_base_offset = 0x0060,
110 .ppr_base_offset = 0x0060 + 0x0004,
111 .pcntr_base_offset = 0x0060 + 0x0008,
112 .ccr_base_offset = 0x0060 + 0x000c,
113 .crlr_base_offset = 0x0060 + 0x0010,
114 .cflr_base_offset = 0x0060 + 0x0014,
115 .clk_gating_separate = 0,
116 .pm_regs_num = 4,
117 };
118
119 static struct sunxi_pwm_hw_data sunxi_pwm_v200_data = {
120 .pdzcr01_offset = 0x0060,
121 .pdzcr23_offset = 0x0064,
122 .pdzcr45_offset = 0x0068,
123 .per_offset = 0x0080,
124 .cer_offset = 0x00c0,
125 .ver_reg_offset = 0x0050,
126 .pcr_base_offset = 0x0100,
127 .ppr_base_offset = 0x0100 + 0x0004,
128 .pcntr_base_offset = 0x0100 + 0x0008,
129 .ccr_base_offset = 0x0100 + 0x0010,
130 .crlr_base_offset = 0x0100 + 0x0014,
131 .cflr_base_offset = 0x0100 + 0x0018,
132 .clk_gating_separate = 1,
133 .pm_regs_num = 5,
134 };
135
sunxi_pwm_save_regs(struct sunxi_pwm_chip * chip)136 static inline void sunxi_pwm_save_regs(struct sunxi_pwm_chip *chip)
137 {
138 int i;
139
140 for (i = 0; i < chip->data->pm_regs_num; i++)
141 chip->regs_backup[i] = readl(chip->base + chip->pm_regs_offset[i]);
142 }
143
sunxi_pwm_restore_regs(struct sunxi_pwm_chip * chip)144 static inline void sunxi_pwm_restore_regs(struct sunxi_pwm_chip *chip)
145 {
146 int i;
147
148 for (i = 0; i < chip->data->pm_regs_num; i++)
149 writel(chip->regs_backup[i], chip->base + chip->pm_regs_offset[i]);
150 }
151
to_sunxi_pwm_chip(struct pwm_chip * chip)152 static inline struct sunxi_pwm_chip *to_sunxi_pwm_chip(struct pwm_chip *chip)
153 {
154 return container_of(chip, struct sunxi_pwm_chip, chip);
155 }
156
sunxi_pwm_readl(struct pwm_chip * chip,u32 offset)157 static inline u32 sunxi_pwm_readl(struct pwm_chip *chip, u32 offset)
158 {
159 struct sunxi_pwm_chip *pc = to_sunxi_pwm_chip(chip);
160 u32 value = 0;
161
162 value = readl(pc->base + offset);
163
164 return value;
165 }
166
sunxi_pwm_writel(struct pwm_chip * chip,u32 offset,u32 value)167 static inline u32 sunxi_pwm_writel(struct pwm_chip *chip, u32 offset, u32 value)
168 {
169 struct sunxi_pwm_chip *pc = to_sunxi_pwm_chip(chip);
170
171 writel(value, pc->base + offset);
172
173 return 0;
174 }
175
sunxi_pwm_pin_set_state(struct device * dev,char * name)176 static int sunxi_pwm_pin_set_state(struct device *dev, char *name)
177 {
178 struct pinctrl *pctl;
179 struct pinctrl_state *state = NULL;
180 int ret;
181
182 pctl = devm_pinctrl_get(dev);
183 if (IS_ERR(pctl)) {
184 dev_err(dev, "pinctrl_get failed\n");
185 ret = PTR_ERR(pctl);
186 return ret;
187 }
188
189 state = pinctrl_lookup_state(pctl, name);
190 if (IS_ERR(state)) {
191 dev_err(dev, "pinctrl_lookup_state(%s) failed\n", name);
192 ret = PTR_ERR(state);
193 goto exit;
194 }
195
196 ret = pinctrl_select_state(pctl, state);
197 if (ret) {
198 dev_err(dev, "pinctrl_select_state(%s) failed\n", name);
199 goto exit;
200 }
201
202 exit:
203 devm_pinctrl_put(pctl);
204 return ret;
205
206 }
207
sunxi_pwm_get_config(struct platform_device * pdev,struct sunxi_pwm_config * config)208 static int sunxi_pwm_get_config(struct platform_device *pdev,
209 struct sunxi_pwm_config *config)
210 {
211 struct device_node *np = pdev->dev.of_node;
212 int ret = 0;
213
214 ret = of_property_read_u32(np, "bind_pwm", &config->bind_pwm);
215 if (ret < 0) {
216 /*if there is no bind pwm,set 255, dual pwm invalid!*/
217 config->bind_pwm = 255;
218 ret = 0;
219 }
220
221 ret = of_property_read_u32(np, "dead_time", &config->dead_time);
222 if (ret < 0) {
223 /*if there is bind pwm, but not set dead time,set bind pwm 255,dual pwm invalid!*/
224 config->bind_pwm = 255;
225 ret = 0;
226 }
227
228 of_node_put(np);
229
230 return ret;
231 }
232
sunxi_pwm_set_polarity_single(struct pwm_chip * chip,struct pwm_device * pwm,enum pwm_polarity polarity)233 static int sunxi_pwm_set_polarity_single(struct pwm_chip *chip,
234 struct pwm_device *pwm,
235 enum pwm_polarity polarity)
236 {
237 u32 temp;
238 unsigned int reg_offset, reg_shift, reg_width;
239 u32 sel = 0;
240 struct sunxi_pwm_chip *pc = to_sunxi_pwm_chip(chip);
241
242 sel = pwm->pwm - chip->base;
243 reg_offset = pc->data->pcr_base_offset + sel * PWM_REG_UNIFORM_OFFSET;
244 reg_shift = PWM_ACT_STA_SHIFT;
245 reg_width = PWM_ACT_STA_WIDTH;
246 temp = sunxi_pwm_readl(chip, reg_offset);
247 if (polarity == PWM_POLARITY_NORMAL) /* set single polarity*/
248 temp = SET_BITS(reg_shift, reg_width, temp, 1);
249 else
250 temp = SET_BITS(reg_shift, reg_width, temp, 0);
251
252 sunxi_pwm_writel(chip, reg_offset, temp);
253
254 return 0;
255 }
256
sunxi_pwm_set_polarity_dual(struct pwm_chip * chip,struct pwm_device * pwm,enum pwm_polarity polarity,int bind_num)257 static int sunxi_pwm_set_polarity_dual(struct pwm_chip *chip,
258 struct pwm_device *pwm,
259 enum pwm_polarity polarity,
260 int bind_num)
261 {
262 u32 temp[2];
263 unsigned int reg_offset[2], reg_shift[2], reg_width[2];
264 u32 sel[2] = {0};
265 struct sunxi_pwm_chip *pc = to_sunxi_pwm_chip(chip);
266
267 sel[0] = pwm->pwm - chip->base;
268 sel[1] = bind_num - chip->base;
269 /* config current pwm*/
270 reg_offset[0] = pc->data->pcr_base_offset + sel[0] * PWM_REG_UNIFORM_OFFSET;
271 reg_shift[0] = PWM_ACT_STA_SHIFT;
272 reg_width[0] = PWM_ACT_STA_WIDTH;
273 temp[0] = sunxi_pwm_readl(chip, reg_offset[0]);
274 if (polarity == PWM_POLARITY_NORMAL)
275 temp[0] = SET_BITS(reg_shift[0], 1, temp[0], 1);
276 else
277 temp[0] = SET_BITS(reg_shift[0], 1, temp[0], 0);
278 /* config bind pwm*/
279 reg_offset[1] = pc->data->pcr_base_offset + sel[1] * PWM_REG_UNIFORM_OFFSET;
280 reg_shift[1] = PWM_ACT_STA_SHIFT;
281 reg_width[1] = PWM_ACT_STA_WIDTH;
282 temp[1] = sunxi_pwm_readl(chip, reg_offset[1]);
283
284 /*bind pwm's polarity is reverse compare with the current pwm*/
285 if (polarity == PWM_POLARITY_NORMAL)
286 temp[1] = SET_BITS(reg_shift[0], 1, temp[1], 1);
287 else
288 temp[1] = SET_BITS(reg_shift[0], 1, temp[1], 0);
289 /*config register at the same time*/
290 sunxi_pwm_writel(chip, reg_offset[0], temp[0]);
291 sunxi_pwm_writel(chip, reg_offset[1], temp[1]);
292
293 return 0;
294 }
295
sunxi_pwm_set_polarity(struct pwm_chip * chip,struct pwm_device * pwm,enum pwm_polarity polarity)296 static int sunxi_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
297 enum pwm_polarity polarity)
298 {
299 int bind_num;
300 struct sunxi_pwm_chip *pc = to_sunxi_pwm_chip(chip);
301
302 bind_num = pc->config[pwm->pwm - chip->base].bind_pwm;
303 if (bind_num == 255)
304 sunxi_pwm_set_polarity_single(chip, pwm, polarity);
305 else
306 sunxi_pwm_set_polarity_dual(chip, pwm, polarity, bind_num);
307
308 return 0;
309 }
310
311
get_pccr_reg_offset(u32 sel,u32 * reg_offset)312 static u32 get_pccr_reg_offset(u32 sel, u32 *reg_offset)
313 {
314 switch (sel) {
315 case 0:
316 case 1:
317 *reg_offset = PWM_PCCR01;
318 break;
319 case 2:
320 case 3:
321 *reg_offset = PWM_PCCR23;
322 break;
323 case 4:
324 case 5:
325 *reg_offset = PWM_PCCR45;
326 break;
327 case 6:
328 case 7:
329 *reg_offset = PWM_PCCR67;
330 break;
331 case 8:
332 case 9:
333 *reg_offset = PWM_PCCR89;
334 break;
335 case 10:
336 case 11:
337 *reg_offset = PWM_PCCRAB;
338 break;
339 case 12:
340 case 13:
341 *reg_offset = PWM_PCCRCD;
342 break;
343 case 14:
344 case 15:
345 *reg_offset = PWM_PCCREF;
346 break;
347 default:
348 pr_err("%s:Not supported!\n", __func__);
349 break;
350 }
351 return 0;
352 }
353
get_pdzcr_reg_offset(struct sunxi_pwm_chip * chip,u32 sel,u32 * reg_offset)354 static u32 get_pdzcr_reg_offset(struct sunxi_pwm_chip *chip, u32 sel, u32 *reg_offset)
355 {
356 switch (sel) {
357 case 0:
358 case 1:
359 *reg_offset = chip->data->pdzcr01_offset;
360 break;
361 case 2:
362 case 3:
363 *reg_offset = chip->data->pdzcr23_offset;
364 break;
365 case 4:
366 case 5:
367 *reg_offset = chip->data->pdzcr45_offset;
368 break;
369 case 6:
370 case 7:
371 *reg_offset = PWM_PDZCR67;
372 break;
373 case 8:
374 case 9:
375 *reg_offset = PWM_PDZCR89;
376 break;
377 case 10:
378 case 11:
379 *reg_offset = PWM_PDZCRAB;
380 break;
381 case 12:
382 case 13:
383 *reg_offset = PWM_PDZCRCD;
384 break;
385 case 14:
386 case 15:
387 *reg_offset = PWM_PDZCREF;
388 break;
389 default:
390 pr_err("%s:Not supported!\n", __func__);
391 break;
392 }
393 return 0;
394 }
395
396 #define PRESCALE_MAX 256
397
sunxi_pwm_config_single(struct pwm_chip * chip,struct pwm_device * pwm,int duty_ns,int period_ns)398 static int sunxi_pwm_config_single(struct pwm_chip *chip, struct pwm_device *pwm,
399 int duty_ns, int period_ns)
400 {
401 unsigned int temp;
402 unsigned long long c = 0;
403 unsigned long entire_cycles = 256, active_cycles = 192;
404 unsigned int reg_offset, reg_shift, reg_width;
405 unsigned int reg_bypass_shift/*, group_reg_offset*/;
406 unsigned int reg_clk_src_shift, reg_clk_src_width;
407 unsigned int reg_div_m_shift, reg_div_m_width, value;
408 unsigned int pre_scal_id = 0, div_m = 0, prescale = 0;
409 unsigned int reg_clk_gating_shift, reg_clk_gating_width;
410 u32 sel = 0;
411 u32 pre_scal[][2] = {
412
413 /* reg_value clk_pre_div */
414 {0, 1},
415 {1, 2},
416 {2, 4},
417 {3, 8},
418 {4, 16},
419 {5, 32},
420 {6, 64},
421 {7, 128},
422 {8, 256},
423 };
424
425 struct sunxi_pwm_chip *pc = to_sunxi_pwm_chip(chip);
426 unsigned int pwm_run_count = 0;
427
428 if (pwm->chip_data) {
429 pwm_run_count = ((struct group_pwm_config *)pwm->chip_data)->group_run_count;
430 pc->g_channel = ((struct group_pwm_config *)pwm->chip_data)->group_channel;
431 pc->g_polarity = ((struct group_pwm_config *)pwm->chip_data)->pwm_polarity;
432 pc->g_period = ((struct group_pwm_config *)
433 pwm->chip_data)->pwm_period;
434 }
435
436 if (pc->g_channel) {
437 reg_offset = pc->data->per_offset;
438 value = sunxi_pwm_readl(chip, reg_offset);
439 value &= ~((0xf) << 4*(pc->g_channel - 1));
440 sunxi_pwm_writel(chip, reg_offset, value);
441 }
442
443 sel = pwm->pwm - chip->base;
444 get_pccr_reg_offset(sel, ®_offset);
445
446 /*src clk reg*/
447 reg_clk_src_shift = PWM_CLK_SRC_SHIFT;
448 reg_clk_src_width = PWM_CLK_SRC_WIDTH;
449
450 if (pc->g_channel) {
451 /* group_mode used the apb1 clk*/
452 temp = sunxi_pwm_readl(chip, reg_offset);
453 temp = SET_BITS(reg_clk_src_shift, reg_clk_src_width, temp, 0);
454 sunxi_pwm_writel(chip, reg_offset, temp);
455 } else {
456 if (period_ns > 0 && period_ns <= 10) {
457 /* if freq lt 100M, then direct output 100M clock,set by pass. */
458 c = 100000000;
459 /* config bypass */
460 if (!pc->data->clk_gating_separate) {
461 if ((sel % 2) == 0)
462 reg_bypass_shift = PWM_BYPASS_SHIFT;
463 else
464 reg_bypass_shift = PWM_BYPASS_SHIFT + 1;
465 temp = sunxi_pwm_readl(chip, reg_offset);
466 temp = SET_BITS(reg_bypass_shift, PWM_BYPASS_WIDTH, temp, 1); /*sun50iw9 bypass set */
467 sunxi_pwm_writel(chip, reg_offset, temp);
468 } else {
469 reg_bypass_shift = sel;
470 temp = sunxi_pwm_readl(chip, PCGR);
471 temp = SET_BITS(reg_bypass_shift, PWM_BYPASS_WIDTH, temp, 1); /* bypass set */
472 sunxi_pwm_writel(chip, PCGR, temp);
473 }
474
475 /*clk_src_reg*/
476 temp = sunxi_pwm_readl(chip, reg_offset);
477 temp = SET_BITS(reg_clk_src_shift, reg_clk_src_width, temp, 1);/*clock source*/
478 sunxi_pwm_writel(chip, reg_offset, temp);
479
480 return 0;
481 } else if (period_ns > 10 && period_ns <= 334) {
482 /* if freq between 3M~100M, then select 100M as clock */
483 c = 100000000;
484 /*clk_src_reg*/
485 temp = sunxi_pwm_readl(chip, reg_offset);
486 temp = SET_BITS(reg_clk_src_shift, reg_clk_src_width, temp, 1);
487 sunxi_pwm_writel(chip, reg_offset, temp);
488
489 } else if (period_ns > 334) {
490 /* if freq < 3M, then select 24M clock */
491 c = 24000000;
492 /*clk_src_reg*/
493 temp = sunxi_pwm_readl(chip, reg_offset);
494 temp = SET_BITS(reg_clk_src_shift, reg_clk_src_width, temp, 0);
495 sunxi_pwm_writel(chip, reg_offset, temp);
496 }
497 pwm_debug("duty_ns=%d period_ns=%d c =%llu.\n", duty_ns, period_ns, c);
498
499 c = c * period_ns;
500 do_div(c, 1000000000);
501 entire_cycles = (unsigned long)c;
502
503 for (pre_scal_id = 0; pre_scal_id < 9; pre_scal_id++) {
504 if (entire_cycles <= 65536)
505 break;
506 for (prescale = 0; prescale < PRESCALE_MAX+1; prescale++) {
507 entire_cycles = ((unsigned long)c/pre_scal[pre_scal_id][1])/(prescale + 1);
508 if (entire_cycles <= 65536) {
509 div_m = pre_scal[pre_scal_id][0];
510 break;
511 }
512 }
513 }
514 c = (unsigned long long)entire_cycles * duty_ns;
515 do_div(c, period_ns);
516 active_cycles = c;
517 if (entire_cycles == 0)
518 entire_cycles++;
519 }
520
521 /* config clk div_m*/
522 reg_div_m_shift = PWM_DIV_M_SHIFT;
523 reg_div_m_width = PWM_DIV_M_WIDTH;
524 temp = sunxi_pwm_readl(chip, reg_offset);
525 if (pc->g_channel)
526 temp = SET_BITS(reg_div_m_shift, reg_div_m_width, temp, 0);
527 else
528 temp = SET_BITS(reg_div_m_shift, reg_div_m_width, temp, div_m);
529 sunxi_pwm_writel(chip, reg_offset, temp);
530
531 /* config clk gating */
532 if (!pc->data->clk_gating_separate) {
533 get_pccr_reg_offset(sel, ®_offset);
534 reg_clk_gating_shift = PWM_CLK_GATING_SHIFT;
535 reg_clk_gating_width = PWM_CLK_GATING_WIDTH;
536 temp = sunxi_pwm_readl(chip, reg_offset);
537 temp = SET_BITS(reg_clk_gating_shift, reg_clk_gating_width, temp, 1);
538 sunxi_pwm_writel(chip, reg_offset, temp);
539 } else {
540 reg_shift = sel;
541 value = sunxi_pwm_readl(chip, PCGR);
542 value = SET_BITS(reg_shift, 1, value, 1);/* set gating */
543 sunxi_pwm_writel(chip, PCGR, value);
544 }
545
546 #if defined(CONFIG_ARCH_SUN50IW9) && defined(CONFIG_MFD_ACX00)
547 /* use pwm5 as phy(ac300,gmac) clk */
548 if (sel == 5) {
549 reg_shift = sel + 1;
550 value = sunxi_pwm_readl(chip, PWM_PCCR45);
551 value = SET_BITS(reg_shift, 1, value, 1);
552 sunxi_pwm_writel(chip, PWM_PCCR45, value);
553
554 reg_shift = sel - 1;
555 value = sunxi_pwm_readl(chip, PWM_PCCR45);
556 value = SET_BITS(reg_shift, 1, value, 1);
557 sunxi_pwm_writel(chip, PWM_PCCR45, value);
558 }
559 #endif
560
561 /* config prescal */
562 reg_offset = pc->data->pcr_base_offset + PWM_REG_UNIFORM_OFFSET * sel;
563 reg_shift = PWM_PRESCAL_SHIFT;
564 reg_width = PWM_PRESCAL_WIDTH;
565 temp = sunxi_pwm_readl(chip, reg_offset);
566 if (pc->g_channel)
567 temp = SET_BITS(reg_shift, reg_width, temp, 0xef);
568 else
569 temp = SET_BITS(reg_shift, reg_width, temp, prescale);
570 sunxi_pwm_writel(chip, reg_offset, temp);
571
572 if (pc->g_channel) {
573 /* group set */
574 reg_offset = PGR0 + 0x04 * (pc->g_channel - 1);
575 reg_shift = sel;
576 reg_width = 1;
577 temp = sunxi_pwm_readl(chip, reg_offset);
578 temp = SET_BITS(reg_shift, reg_width, temp, 1); /* set group0_cs */
579 sunxi_pwm_writel(chip, reg_offset, temp);
580
581 /* pwm pulse mode */
582 reg_offset = pc->data->pcr_base_offset + sel * PWM_REG_UNIFORM_OFFSET;
583 reg_shift = PWM_MODE_ACTS_SHIFT;
584 reg_width = PWM_MODE_ACTS_WIDTH;
585 temp = sunxi_pwm_readl(chip, reg_offset);
586 temp = SET_BITS(reg_shift, reg_width, temp, 0x3); /* pwm pulse mode and active */
587 /* pwm output pulse num */
588 reg_shift = PWM_PUL_NUM_SHIFT;
589 reg_width = PWM_PUL_NUM_WIDTH;
590 temp = SET_BITS(reg_shift, reg_width, temp, pwm_run_count); /* pwm output pulse num */
591 sunxi_pwm_writel(chip, reg_offset, temp);
592 }
593
594 /* config active cycles */
595 reg_offset = pc->data->ppr_base_offset + PWM_REG_UNIFORM_OFFSET * sel;
596 reg_shift = PWM_ACT_CYCLES_SHIFT;
597 reg_width = PWM_ACT_CYCLES_WIDTH;
598 temp = sunxi_pwm_readl(chip, reg_offset);
599 if (pc->g_channel)
600 temp = SET_BITS(reg_shift, reg_width, temp,
601 (unsigned int)(pc->g_period*3/8));
602 else
603 temp = SET_BITS(reg_shift, reg_width, temp, active_cycles);
604 sunxi_pwm_writel(chip, reg_offset, temp);
605
606 /* config period cycles */
607 reg_offset = pc->data->ppr_base_offset + PWM_REG_UNIFORM_OFFSET * sel;
608 reg_shift = PWM_PERIOD_CYCLES_SHIFT;
609 reg_width = PWM_PERIOD_CYCLES_WIDTH;
610 temp = sunxi_pwm_readl(chip, reg_offset);
611 if (pc->g_channel) {
612 temp = SET_BITS(reg_shift, reg_width, temp, pc->g_period);
613 pc->g_channel = 0;
614 } else
615 temp = SET_BITS(reg_shift, reg_width, temp, (entire_cycles - 1));
616 sunxi_pwm_writel(chip, reg_offset, temp);
617
618 pwm_debug("active_cycles=%lu entire_cycles=%lu prescale=%u div_m=%u\n",
619 active_cycles, entire_cycles, prescale, div_m);
620 return 0;
621 }
622
sunxi_pwm_config_dual(struct pwm_chip * chip,struct pwm_device * pwm,int duty_ns,int period_ns,int bind_num)623 static int sunxi_pwm_config_dual(struct pwm_chip *chip, struct pwm_device *pwm,
624 int duty_ns, int period_ns, int bind_num)
625 {
626 u32 value[2] = {0};
627 unsigned int temp;
628 unsigned long long c = 0, clk = 0, clk_temp = 0;
629 unsigned long entire_cycles = 256, active_cycles = 192;
630 unsigned int reg_offset[2], reg_shift[2], reg_width[2];
631 unsigned int reg_bypass_shift;
632 unsigned int reg_dz_en_offset[2], reg_dz_en_shift[2], reg_dz_en_width[2];
633 unsigned int pre_scal_id = 0, div_m = 0, prescale = 0;
634 int src_clk_sel = 0;
635 int i = 0;
636 unsigned int dead_time = 0, duty = 0;
637 u32 pre_scal[][2] = {
638
639 /* reg_value clk_pre_div */
640 {0, 1},
641 {1, 2},
642 {2, 4},
643 {3, 8},
644 {4, 16},
645 {5, 32},
646 {6, 64},
647 {7, 128},
648 {8, 256},
649 };
650 unsigned int pwm_index[2] = {0};
651 struct sunxi_pwm_chip *pc = to_sunxi_pwm_chip(chip);
652
653 pwm_index[0] = pwm->pwm - chip->base;
654 pwm_index[1] = bind_num - chip->base;
655
656 /* if duty time < dead time,it is wrong. */
657 dead_time = pc->config[pwm_index[0]].dead_time;
658 duty = (unsigned int)duty_ns;
659 /* judge if the pwm eanble dead zone */
660 get_pdzcr_reg_offset(pc, pwm_index[0], ®_dz_en_offset[0]);
661 reg_dz_en_shift[0] = PWM_DZ_EN_SHIFT;
662 reg_dz_en_width[0] = PWM_DZ_EN_WIDTH;
663
664 value[0] = sunxi_pwm_readl(chip, reg_dz_en_offset[0]);
665 value[0] = SET_BITS(reg_dz_en_shift[0], reg_dz_en_width[0], value[0], 1);
666 sunxi_pwm_writel(chip, reg_dz_en_offset[0], value[0]);
667 temp = sunxi_pwm_readl(chip, reg_dz_en_offset[0]);
668 temp &= (1u << reg_dz_en_shift[0]);
669 if (duty < dead_time || temp == 0) {
670 pr_err("[PWM]duty time or dead zone error.\n");
671 return -EINVAL;
672 }
673
674 for (i = 0; i < PWM_BIND_NUM; i++) {
675 if ((i % 2) == 0)
676 reg_bypass_shift = 0x5;
677 else
678 reg_bypass_shift = 0x6;
679 get_pccr_reg_offset(pwm_index[i], ®_offset[i]);
680 reg_shift[i] = reg_bypass_shift;
681 reg_width[i] = PWM_BYPASS_WIDTH;
682 }
683
684 if (period_ns > 0 && period_ns <= 10) {
685 /* if freq lt 100M, then direct output 100M clock,set by pass */
686 clk = 100000000;
687 src_clk_sel = 1;
688
689 /* config the two pwm bypass */
690 for (i = 0; i < PWM_BIND_NUM; i++) {
691 temp = sunxi_pwm_readl(chip, reg_offset[i]);
692 temp = SET_BITS(reg_shift[i], reg_width[i], temp, 1);
693 sunxi_pwm_writel(chip, reg_offset[i], temp);
694
695 reg_shift[i] = PWM_CLK_SRC_SHIFT;
696 reg_width[i] = PWM_CLK_SRC_WIDTH;
697 temp = sunxi_pwm_readl(chip, reg_offset[i]);
698 temp = SET_BITS(reg_shift[i], reg_width[i], temp, 1);
699 sunxi_pwm_writel(chip, reg_offset[i], temp);
700 }
701
702 return 0;
703 } else if (period_ns > 10 && period_ns <= 334) {
704 clk = 100000000;
705 src_clk_sel = 1;
706 } else if (period_ns > 334) {
707 /* if freq < 3M, then select 24M clock */
708 clk = 24000000;
709 src_clk_sel = 0;
710 }
711
712 for (i = 0; i < PWM_BIND_NUM; i++) {
713 reg_shift[i] = PWM_CLK_SRC_SHIFT;
714 reg_width[i] = PWM_CLK_SRC_WIDTH;
715
716 temp = sunxi_pwm_readl(chip, reg_offset[i]);
717 temp = SET_BITS(reg_shift[i], reg_width[i], temp, src_clk_sel);
718 sunxi_pwm_writel(chip, reg_offset[i], temp);
719 }
720
721 c = clk;
722 c *= period_ns;
723 do_div(c, 1000000000);
724 entire_cycles = (unsigned long)c;
725
726 /* get div_m and prescale,which satisfy: deat_val <= 256, entire <= 65536 */
727 for (pre_scal_id = 0; pre_scal_id < 9; pre_scal_id++) {
728 for (prescale = 0; prescale < PRESCALE_MAX+1; prescale++) {
729 entire_cycles = ((unsigned long)c/pre_scal[pre_scal_id][1])/(prescale + 1);
730 clk_temp = clk;
731 do_div(clk_temp, pre_scal[pre_scal_id][1] * (prescale + 1));
732 clk_temp *= dead_time;
733 do_div(clk_temp, 1000000000);
734 if (entire_cycles <= 65536 && clk_temp <= 256) {
735 div_m = pre_scal[pre_scal_id][0];
736 break;
737 }
738 }
739 if (entire_cycles <= 65536 && clk_temp <= 256)
740 break;
741 else {
742 pr_err("%s:config dual err.entire_cycles=%lu, dead_zone_val=%llu",
743 __func__, entire_cycles, clk_temp);
744 return -EINVAL;
745 }
746 }
747
748 c = (unsigned long long)entire_cycles * duty_ns;
749 do_div(c, period_ns);
750 active_cycles = c;
751 if (entire_cycles == 0)
752 entire_cycles++;
753
754 /* config clk div_m*/
755 for (i = 0; i < PWM_BIND_NUM; i++) {
756 reg_shift[i] = PWM_DIV_M_SHIFT;
757 reg_width[i] = PWM_DIV_M_SHIFT;
758 temp = sunxi_pwm_readl(chip, reg_offset[i]);
759 temp = SET_BITS(reg_shift[i], reg_width[i], temp, div_m);
760 sunxi_pwm_writel(chip, reg_offset[i], temp);
761 }
762
763 /* config prescal */
764 for (i = 0; i < PWM_BIND_NUM; i++) {
765 reg_offset[i] = pc->data->pcr_base_offset + PWM_REG_UNIFORM_OFFSET * pwm_index[i];
766 reg_shift[i] = PWM_PRESCAL_SHIFT;
767 reg_width[i] = PWM_PRESCAL_WIDTH;
768 temp = sunxi_pwm_readl(chip, reg_offset[i]);
769 temp = SET_BITS(reg_shift[i], reg_width[i], temp, prescale);
770 sunxi_pwm_writel(chip, reg_offset[i], temp);
771 }
772
773 /* config active cycles */
774 for (i = 0; i < PWM_BIND_NUM; i++) {
775 reg_offset[i] = pc->data->ppr_base_offset + PWM_REG_UNIFORM_OFFSET * pwm_index[i];
776 reg_shift[i] = PWM_ACT_CYCLES_SHIFT;
777 reg_width[i] = PWM_ACT_CYCLES_WIDTH;
778 temp = sunxi_pwm_readl(chip, reg_offset[i]);
779 temp = SET_BITS(reg_shift[i], reg_width[i], temp, active_cycles);
780 sunxi_pwm_writel(chip, reg_offset[i], temp);
781 }
782
783 /* config period cycles */
784 for (i = 0; i < PWM_BIND_NUM; i++) {
785 reg_offset[i] = pc->data->ppr_base_offset + PWM_REG_UNIFORM_OFFSET * pwm_index[i];
786 reg_shift[i] = PWM_PERIOD_CYCLES_SHIFT;
787 reg_width[i] = PWM_PERIOD_CYCLES_WIDTH;
788 temp = sunxi_pwm_readl(chip, reg_offset[i]);
789 temp = SET_BITS(reg_shift[i], reg_width[i], temp, (entire_cycles - 1));
790 sunxi_pwm_writel(chip, reg_offset[i], temp);
791 }
792
793 pwm_debug("active_cycles=%lu entire_cycles=%lu prescale=%u div_m=%u\n",
794 active_cycles, entire_cycles, prescale, div_m);
795
796 /* config dead zone, one config for two pwm */
797 reg_offset[0] = reg_dz_en_offset[0];
798 reg_shift[0] = PWM_PDZINTV_SHIFT;
799 reg_width[0] = PWM_PDZINTV_WIDTH;
800 temp = sunxi_pwm_readl(chip, reg_offset[0]);
801 temp = SET_BITS(reg_shift[0], reg_width[0], temp, (unsigned int)clk_temp);
802 sunxi_pwm_writel(chip, reg_offset[0], temp);
803
804 return 0;
805 }
806
sunxi_pwm_config(struct pwm_chip * chip,struct pwm_device * pwm,int duty_ns,int period_ns)807 static int sunxi_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
808 int duty_ns, int period_ns)
809 {
810 int bind_num;
811
812 struct sunxi_pwm_chip *pc = to_sunxi_pwm_chip(chip);
813
814 bind_num = pc->config[pwm->pwm - chip->base].bind_pwm;
815 if (bind_num == 255)
816 sunxi_pwm_config_single(chip, pwm, duty_ns, period_ns);
817 else
818 sunxi_pwm_config_dual(chip, pwm, duty_ns, period_ns, bind_num);
819
820 return 0;
821 }
822
sunxi_pwm_enable_single(struct pwm_chip * chip,struct pwm_device * pwm)823 static int sunxi_pwm_enable_single(struct pwm_chip *chip, struct pwm_device *pwm)
824 {
825 unsigned int value = 0, index = 0;
826 unsigned int reg_offset, reg_shift, reg_width, group_reg_offset;
827 unsigned int temp;
828 struct device_node *sub_np;
829 struct platform_device *pwm_pdevice;
830 static unsigned int enable_num;
831 unsigned int pwm_start_count, i;
832 int pwm_period = 0;
833 int ret;
834
835 struct sunxi_pwm_chip *pc = to_sunxi_pwm_chip(chip);
836
837 index = pwm->pwm - chip->base;
838 sub_np = of_parse_phandle(chip->dev->of_node, "sunxi-pwms", index);
839 if (IS_ERR_OR_NULL(sub_np)) {
840 pr_err("%s: can't parse \"sunxi-pwms\" property\n", __func__);
841 return -ENODEV;
842 }
843 pwm_pdevice = of_find_device_by_node(sub_np);
844 if (IS_ERR_OR_NULL(pwm_pdevice)) {
845 pr_err("%s: can't parse pwm device\n", __func__);
846 return -ENODEV;
847 }
848 ret = sunxi_pwm_pin_set_state(&pwm_pdevice->dev, PWM_PIN_STATE_ACTIVE);
849 if (ret != 0)
850 return ret;
851
852 if (pwm->chip_data) {
853 pc->g_channel = ((struct group_pwm_config *)pwm->chip_data)->group_channel;
854 pwm_period = ((struct group_pwm_config *)
855 pwm->chip_data)->pwm_period;
856 }
857
858 if (pc->g_channel)
859 enable_num++;
860
861 /* enable pwm controller pwm can be used */
862 if (!pc->g_channel) {
863 reg_offset = pc->data->per_offset;
864 reg_shift = index;
865 value = sunxi_pwm_readl(chip, reg_offset);
866 value = SET_BITS(reg_shift, 1, value, 1);
867 sunxi_pwm_writel(chip, reg_offset, value);
868
869 /* config clk gating */
870 if (!pc->data->clk_gating_separate) {
871 get_pccr_reg_offset(index, ®_offset);
872 reg_shift = PWM_CLK_GATING_SHIFT;
873 reg_width = PWM_CLK_GATING_WIDTH;
874 } else {
875 reg_offset = PCGR;
876 reg_shift = index;
877 reg_width = 0x1;
878 }
879 value = sunxi_pwm_readl(chip, reg_offset);
880 value = SET_BITS(reg_shift, reg_width, value, 1);
881 sunxi_pwm_writel(chip, reg_offset, value);
882 }
883
884 if (pc->g_channel && enable_num == 4) {
885 if (pc->g_polarity)
886 pwm_start_count = (unsigned int)pwm_period*6/8;
887 else
888 pwm_start_count = 0;
889
890 for (i = 4*(pc->g_channel - 1); i < 4*pc->g_channel; i++) {
891 /* start count set */
892 reg_offset = pc->data->pcntr_base_offset + PWM_REG_UNIFORM_OFFSET * i;
893 reg_shift = PWM_COUNTER_START_SHIFT;
894 reg_width = PWM_COUNTER_START_WIDTH;
895
896 temp = pwm_start_count << reg_shift;
897 sunxi_pwm_writel(chip, reg_offset, temp);
898 if (pc->g_polarity)
899 pwm_start_count = pwm_start_count -
900 ((unsigned int)pwm_period*2/8);
901 else
902 pwm_start_count = pwm_start_count +
903 ((unsigned int)pwm_period*2/8);
904 }
905
906 reg_offset = pc->data->per_offset;
907 reg_shift = index;
908 value = sunxi_pwm_readl(chip, reg_offset);
909 value |= ((0xf) << 4*(pc->g_channel - 1));
910 sunxi_pwm_writel(chip, reg_offset, value);
911
912 group_reg_offset = PGR0 + 0x04 * (pc->g_channel - 1);
913
914 enable_num = 0;
915 pwm_start_count = 0;
916 /* group en and start */
917 reg_shift = PWMG_EN_SHIFT;
918 value = sunxi_pwm_readl(chip, group_reg_offset);
919 value = SET_BITS(reg_shift, 1, value, 1);/* enable group0 enable */
920 sunxi_pwm_writel(chip, group_reg_offset, value);
921
922 reg_shift = PWMG_START_SHIFT;
923 value = sunxi_pwm_readl(chip, group_reg_offset);
924 value = SET_BITS(reg_shift, 1, value, 1);/* group0 start */
925 sunxi_pwm_writel(chip, group_reg_offset, value);
926
927 pc->g_channel = 0;
928 }
929
930 return 0;
931 }
932
sunxi_pwm_enable_dual(struct pwm_chip * chip,struct pwm_device * pwm,int bind_num)933 static int sunxi_pwm_enable_dual(struct pwm_chip *chip, struct pwm_device *pwm, int bind_num)
934 {
935 u32 value[2] = {0};
936 unsigned int reg_offset[2], reg_shift[2], reg_width[2];
937 struct device_node *sub_np[2];
938 struct platform_device *pwm_pdevice[2];
939 int i = 0, ret = 0;
940 unsigned int pwm_index[2] = {0};
941 struct sunxi_pwm_chip *pc = to_sunxi_pwm_chip(chip);
942
943 pwm_index[0] = pwm->pwm - chip->base;
944 pwm_index[1] = bind_num - chip->base;
945
946 /*set current pwm pin state*/
947 sub_np[0] = of_parse_phandle(chip->dev->of_node, "sunxi-pwms", pwm_index[0]);
948 if (IS_ERR_OR_NULL(sub_np[0])) {
949 pr_err("%s: can't parse \"sunxi-pwms\" property\n", __func__);
950 return -ENODEV;
951 }
952 pwm_pdevice[0] = of_find_device_by_node(sub_np[0]);
953 if (IS_ERR_OR_NULL(pwm_pdevice[0])) {
954 pr_err("%s: can't parse pwm device\n", __func__);
955 return -ENODEV;
956 }
957
958 /*set bind pwm pin state*/
959 sub_np[1] = of_parse_phandle(chip->dev->of_node, "sunxi-pwms", pwm_index[1]);
960 if (IS_ERR_OR_NULL(sub_np[1])) {
961 pr_err("%s: can't parse \"sunxi-pwms\" property\n", __func__);
962 return -ENODEV;
963 }
964 pwm_pdevice[1] = of_find_device_by_node(sub_np[1]);
965 if (IS_ERR_OR_NULL(pwm_pdevice[1])) {
966 pr_err("%s: can't parse pwm device\n", __func__);
967 return -ENODEV;
968 }
969
970 ret = sunxi_pwm_pin_set_state(&pwm_pdevice[0]->dev, PWM_PIN_STATE_ACTIVE);
971 if (ret != 0)
972 return ret;
973 ret = sunxi_pwm_pin_set_state(&pwm_pdevice[1]->dev, PWM_PIN_STATE_ACTIVE);
974 if (ret != 0)
975 return ret;
976
977 /* enable clk for pwm controller */
978 for (i = 0; i < PWM_BIND_NUM; i++) {
979 get_pccr_reg_offset(pwm_index[i], ®_offset[i]);
980 reg_shift[i] = PWM_CLK_GATING_SHIFT;
981 reg_width[i] = PWM_CLK_GATING_WIDTH;
982 value[i] = sunxi_pwm_readl(chip, reg_offset[i]);
983 value[i] = SET_BITS(reg_shift[i], reg_width[i], value[i], 1);
984 sunxi_pwm_writel(chip, reg_offset[i], value[i]);
985 }
986
987 /* enable pwm controller */
988 for (i = 0; i < PWM_BIND_NUM; i++) {
989 reg_offset[i] = pc->data->per_offset;
990 reg_shift[i] = pwm_index[i];
991 reg_width[i] = 0x1;
992 value[i] = sunxi_pwm_readl(chip, reg_offset[i]);
993 value[i] = SET_BITS(reg_shift[i], reg_width[i], value[i], 1);
994 sunxi_pwm_writel(chip, reg_offset[i], value[i]);
995 }
996
997 return 0;
998 }
999
sunxi_pwm_enable(struct pwm_chip * chip,struct pwm_device * pwm)1000 static int sunxi_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
1001 {
1002 int bind_num;
1003 int ret = 0;
1004 struct sunxi_pwm_chip *pc = to_sunxi_pwm_chip(chip);
1005
1006 bind_num = pc->config[pwm->pwm - chip->base].bind_pwm;
1007 if (bind_num == 255)
1008 ret = sunxi_pwm_enable_single(chip, pwm);
1009 else
1010 ret = sunxi_pwm_enable_dual(chip, pwm, bind_num);
1011
1012 return ret;
1013 }
1014
1015
sunxi_pwm_disable_single(struct pwm_chip * chip,struct pwm_device * pwm)1016 static void sunxi_pwm_disable_single(struct pwm_chip *chip, struct pwm_device *pwm)
1017 {
1018 u32 value = 0, index = 0;
1019 unsigned int reg_offset, reg_shift, reg_width, group_reg_offset;
1020 struct device_node *sub_np;
1021 struct platform_device *pwm_pdevice;
1022
1023 static int disable_num;
1024 struct sunxi_pwm_chip *pc = to_sunxi_pwm_chip(chip);
1025 index = pwm->pwm - chip->base;
1026
1027 if (pwm->chip_data) {
1028 pc->g_channel = ((struct group_pwm_config *)pwm->chip_data)->group_channel;
1029 }
1030 /* disable pwm controller */
1031 if (pc->g_channel) {
1032 if (disable_num == 0) {
1033 reg_offset = pc->data->per_offset;
1034 reg_width = 0x4;
1035 value = sunxi_pwm_readl(chip, reg_offset);
1036 value &= ~((0xf) << 4*(pc->g_channel - 1));
1037 sunxi_pwm_writel(chip, reg_offset, value);
1038 /* config clk gating */
1039 if (!pc->data->clk_gating_separate) {
1040 get_pccr_reg_offset(index, ®_offset);
1041 reg_shift = PWM_CLK_GATING_SHIFT;
1042 reg_width = PWM_CLK_GATING_WIDTH;
1043 } else {
1044 reg_offset = PCGR;
1045 reg_shift = index;
1046 reg_width = 0x1;
1047 }
1048 value = sunxi_pwm_readl(chip, reg_offset);
1049 value &= ~((0xf) << 4*(pc->g_channel - 1));
1050 // value = SET_BITS(reg_shift, reg_width, value, 0);
1051 sunxi_pwm_writel(chip, reg_offset, value);
1052 }
1053 } else {
1054 reg_offset = pc->data->per_offset;
1055 reg_shift = index;
1056 reg_width = 0x1;
1057 value = sunxi_pwm_readl(chip, reg_offset);
1058 value = SET_BITS(reg_shift, reg_width, value, 0);
1059 sunxi_pwm_writel(chip, reg_offset, value);
1060
1061 /* config clk gating */
1062 if (!pc->data->clk_gating_separate) {
1063 get_pccr_reg_offset(index, ®_offset);
1064 reg_shift = PWM_CLK_GATING_SHIFT;
1065 reg_width = PWM_CLK_GATING_WIDTH;
1066 } else {
1067 reg_offset = PCGR;
1068 reg_shift = index;
1069 reg_width = 0x1;
1070 }
1071 value = sunxi_pwm_readl(chip, reg_offset);
1072 value = SET_BITS(reg_shift, reg_width, value, 0);
1073 sunxi_pwm_writel(chip, reg_offset, value);
1074 }
1075
1076 if (pc->g_channel)
1077 disable_num++;
1078
1079 sub_np = of_parse_phandle(chip->dev->of_node, "sunxi-pwms", index);
1080 if (IS_ERR_OR_NULL(sub_np)) {
1081 pr_err("%s: can't parse \"sunxi-pwms\" property\n", __func__);
1082 return;
1083 }
1084 pwm_pdevice = of_find_device_by_node(sub_np);
1085 if (IS_ERR_OR_NULL(pwm_pdevice)) {
1086 pr_err("%s: can't parse pwm device\n", __func__);
1087 return;
1088 }
1089 sunxi_pwm_pin_set_state(&pwm_pdevice->dev, PWM_PIN_STATE_SLEEP);
1090
1091 if (pc->g_channel) {
1092 group_reg_offset = PGR0 + 0x04 * (pc->g_channel - 1);
1093 /* group end */
1094 reg_shift = PWMG_START_SHIFT;
1095 value = sunxi_pwm_readl(chip, group_reg_offset);
1096 value = SET_BITS(reg_shift, 1, value, 0);/* group end */
1097 sunxi_pwm_writel(chip, group_reg_offset, value);
1098
1099 /* group disable */
1100 reg_shift = PWMG_EN_SHIFT;
1101 value = sunxi_pwm_readl(chip, group_reg_offset);
1102 value = SET_BITS(reg_shift, 1, value, 0);/* group disable */
1103 sunxi_pwm_writel(chip, group_reg_offset, value);
1104
1105 pc->g_channel = 0;
1106 }
1107 }
1108
sunxi_pwm_disable_dual(struct pwm_chip * chip,struct pwm_device * pwm,int bind_num)1109 static void sunxi_pwm_disable_dual(struct pwm_chip *chip, struct pwm_device *pwm, int bind_num)
1110 {
1111 u32 value[2] = {0};
1112 unsigned int reg_offset[2], reg_shift[2], reg_width[2];
1113 struct device_node *sub_np[2];
1114 struct platform_device *pwm_pdevice[2];
1115 int i = 0;
1116 unsigned int pwm_index[2] = {0};
1117 struct sunxi_pwm_chip *pc = to_sunxi_pwm_chip(chip);
1118
1119 pwm_index[0] = pwm->pwm - chip->base;
1120 pwm_index[1] = bind_num - chip->base;
1121
1122 /* get current index pwm device */
1123 sub_np[0] = of_parse_phandle(chip->dev->of_node, "sunxi-pwms", pwm_index[0]);
1124 if (IS_ERR_OR_NULL(sub_np[0])) {
1125 pr_err("%s: can't parse \"sunxi-pwms\" property\n", __func__);
1126 return;
1127 }
1128 pwm_pdevice[0] = of_find_device_by_node(sub_np[0]);
1129 if (IS_ERR_OR_NULL(pwm_pdevice[0])) {
1130 pr_err("%s: can't parse pwm device\n", __func__);
1131 return;
1132 }
1133 /* get bind pwm device */
1134 sub_np[1] = of_parse_phandle(chip->dev->of_node, "sunxi-pwms", pwm_index[1]);
1135 if (IS_ERR_OR_NULL(sub_np[1])) {
1136 pr_err("%s: can't parse \"sunxi-pwms\" property\n", __func__);
1137 return;
1138 }
1139 pwm_pdevice[1] = of_find_device_by_node(sub_np[1]);
1140 if (IS_ERR_OR_NULL(pwm_pdevice[1])) {
1141 pr_err("%s: can't parse pwm device\n", __func__);
1142 return;
1143 }
1144
1145 /* disable pwm controller */
1146 for (i = 0; i < PWM_BIND_NUM; i++) {
1147 reg_offset[i] = pc->data->per_offset;
1148 reg_shift[i] = pwm_index[i];
1149 reg_width[i] = 0x1;
1150 value[i] = sunxi_pwm_readl(chip, reg_offset[i]);
1151 value[i] = SET_BITS(reg_shift[i], reg_width[i], value[i], 0);
1152 sunxi_pwm_writel(chip, reg_offset[i], value[i]);
1153 }
1154
1155 /* disable pwm clk gating */
1156 for (i = 0; i < PWM_BIND_NUM; i++) {
1157 get_pccr_reg_offset(pwm_index[i], ®_offset[i]);
1158 reg_shift[i] = PWM_CLK_GATING_SHIFT;
1159 reg_width[i] = 0x1;
1160 value[i] = sunxi_pwm_readl(chip, reg_offset[i]);
1161 value[i] = SET_BITS(reg_shift[i], reg_width[i], value[i], 0);
1162 sunxi_pwm_writel(chip, reg_offset[i], value[i]);
1163 }
1164
1165 /* disable pwm dead zone,one for the two pwm */
1166 get_pdzcr_reg_offset(pc, pwm_index[0], ®_offset[0]);
1167 reg_shift[0] = PWM_DZ_EN_SHIFT;
1168 reg_width[0] = PWM_DZ_EN_WIDTH;
1169 value[0] = sunxi_pwm_readl(chip, reg_offset[0]);
1170 value[0] = SET_BITS(reg_shift[0], reg_width[0], value[0], 0);
1171 sunxi_pwm_writel(chip, reg_offset[0], value[0]);
1172
1173 /* config pin sleep */
1174 sunxi_pwm_pin_set_state(&pwm_pdevice[0]->dev, PWM_PIN_STATE_SLEEP);
1175 sunxi_pwm_pin_set_state(&pwm_pdevice[1]->dev, PWM_PIN_STATE_SLEEP);
1176 }
1177
sunxi_pwm_disable(struct pwm_chip * chip,struct pwm_device * pwm)1178 static void sunxi_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
1179 {
1180 int bind_num;
1181 struct sunxi_pwm_chip *pc = to_sunxi_pwm_chip(chip);
1182
1183 bind_num = pc->config[pwm->pwm - chip->base].bind_pwm;
1184 if (bind_num == 255)
1185 sunxi_pwm_disable_single(chip, pwm);
1186 else
1187 sunxi_pwm_disable_dual(chip, pwm, bind_num);
1188 }
1189
1190 //TODO: use pwm interrupt
1191 /* Some soc have not interruput soure.
1192 * So,use CPU polling pwm capture interrupt status
1193 * default:24MHz
1194 * max input pwm period:2.7ms
1195 * min input pwm period:2.7us
1196 */
sunxi_pwm_capture(struct pwm_chip * chip,struct pwm_device * pwm,struct pwm_capture * result,unsigned long timeout)1197 static int sunxi_pwm_capture(struct pwm_chip *chip, struct pwm_device *pwm,
1198 struct pwm_capture *result, unsigned long timeout)
1199 {
1200 unsigned long long pwm_clk = 0, temp_clk;
1201 unsigned int pwm_div;
1202 unsigned int i = 0;
1203 /* spinlock_t pwm_lock; */
1204 /* unsigned long flags; */
1205 int cap_time[3];
1206 unsigned int value = 0, temp = 0, irq_num = 0;
1207 unsigned int reg_offset, reg_shift;
1208 struct device_node *sub_np;
1209 struct platform_device *pwm_pdevice;
1210 int index = pwm->pwm - chip->base;
1211 u32 pre_scal[][2] = {
1212 /* reg_value clk_pre_div */
1213 {0, 1},
1214 {1, 2},
1215 {2, 4},
1216 {3, 8},
1217 {4, 16},
1218 {5, 32},
1219 {6, 64},
1220 {7, 128},
1221 {8, 256},
1222 };
1223 struct sunxi_pwm_chip *pc = to_sunxi_pwm_chip(chip);
1224
1225 sub_np = of_parse_phandle(chip->dev->of_node, "sunxi-pwms", index);
1226 if (IS_ERR_OR_NULL(sub_np)) {
1227 pr_err("%s: can't parse \"pwms\" property\n", __func__);
1228 return -ENODEV;
1229 }
1230 pwm_pdevice = of_find_device_by_node(sub_np);
1231 if (IS_ERR_OR_NULL(pwm_pdevice)) {
1232 pr_err("%s: can't parse pwm device\n", __func__);
1233 return -ENODEV;
1234 }
1235 sunxi_pwm_pin_set_state(&pwm_pdevice->dev, PWM_PIN_STATE_ACTIVE);
1236
1237 /* enable clk for pwm controller */
1238 get_pccr_reg_offset(index, ®_offset);
1239 reg_shift = PWM_CLK_GATING_SHIFT;
1240 value = sunxi_pwm_readl(chip, reg_offset);
1241 value = SET_BITS(reg_shift, 1, value, 1);
1242 sunxi_pwm_writel(chip, reg_offset, value);
1243
1244 get_pccr_reg_offset(index, ®_offset);
1245 temp = sunxi_pwm_readl(chip, reg_offset);
1246 pwm_div = pre_scal[temp & (0x000f)][1];
1247 if (temp & (0x01 << PWM_CLK_SRC_SHIFT))
1248 pwm_clk = 100;//100M
1249 else
1250 pwm_clk = 24;//24M
1251
1252 /* spin_lock_init(&pwm_lock); */
1253 /* spin_lock_irqsave(&pwm_lock, flags); */
1254
1255 /* enable rise interrupt */
1256 temp = sunxi_pwm_readl(chip, PWM_CIER);
1257 temp = SET_BITS(index * 0x2, 0x1, temp, 0x1);
1258 sunxi_pwm_writel(chip, PWM_CIER, temp);
1259 /* Enable capture */
1260 temp = sunxi_pwm_readl(chip, pc->data->cer_offset);
1261 temp = SET_BITS(index, 0x1, temp, 0x1);
1262 sunxi_pwm_writel(chip, pc->data->cer_offset, temp);
1263 /* Clean capture rise status*/
1264 temp = sunxi_pwm_readl(chip, PWM_CISR);
1265 temp = SET_BITS(index * 0x2, 0x1, temp, 0x1);
1266 sunxi_pwm_writel(chip, PWM_CISR, temp);
1267
1268 sunxi_pwm_writel(chip, pc->data->ccr_base_offset + index * PWM_REG_UNIFORM_OFFSET, 0x6);
1269
1270 printk("time out is %ld\n", timeout);
1271 while (--timeout) {
1272 for (i = 0; i < 65535; i++) {
1273 /*
1274 * Capture input:
1275 * _______ _______
1276 * | | | |
1277 * ________| |_____________| |________
1278 *irq_num ^0 ^1 ^2
1279 *
1280 * Capture start by the first available rising edge.
1281 */
1282 temp = sunxi_pwm_readl(chip, PWM_CISR);
1283 if ((temp & (0x1 << (index * 0x2))) &&
1284 (temp & (0x2 << (index * 0x2)))) {
1285 pr_err("input signal is constant of greater than Hz\n");
1286 goto err;
1287 }
1288 if (temp & (0x1 << (index * 0x2))) {
1289 if (irq_num == 1) {
1290 pr_err("pwm high time too short,can not capture,index:%d\n",
1291 irq_num);
1292 goto err;
1293 }
1294 cap_time[irq_num] = sunxi_pwm_readl(chip,
1295 pc->data->crlr_base_offset + index * PWM_REG_UNIFORM_OFFSET);
1296 irq_num++;
1297
1298 /* clean irq status*/
1299 temp = sunxi_pwm_readl(chip, PWM_CISR);
1300 temp = SET_BITS(index * 0x2, 0x1, temp, 0x1);
1301 sunxi_pwm_writel(chip, PWM_CISR, temp);
1302 /* clean capture crlf */
1303 sunxi_pwm_writel(chip,
1304 pc->data->ccr_base_offset + index * PWM_REG_UNIFORM_OFFSET, 0x6);
1305
1306 /* enable fail interrupt */
1307 temp = sunxi_pwm_readl(chip, PWM_CIER);
1308 temp = SET_BITS(1 + index * 0x2, 0x1, temp, 0x1);
1309 sunxi_pwm_writel(chip, PWM_CIER, temp);
1310 } else if (temp & (0x2 << (index * 0x2))) {
1311 if (irq_num == 0 || irq_num == 2) {
1312 pr_err("pwm low time too short,can not capture, index:%d\n",
1313 irq_num);
1314 goto err;
1315 }
1316 cap_time[irq_num] = sunxi_pwm_readl(chip,
1317 pc->data->cflr_base_offset + index * PWM_REG_UNIFORM_OFFSET);
1318 irq_num++;
1319
1320 /* clean irq status*/
1321 temp = sunxi_pwm_readl(chip, PWM_CISR);
1322 temp = SET_BITS(1 + index * 0x2, 0x1, temp, 0x1);
1323 sunxi_pwm_writel(chip, PWM_CISR, temp);
1324 /* clean capture cflf */
1325 sunxi_pwm_writel(chip,
1326 pc->data->ccr_base_offset + index * PWM_REG_UNIFORM_OFFSET, 0x2);
1327 }
1328 if (irq_num > 2) {
1329 err:
1330 /* spin_unlock_irqrestore(&pwm_lock, flags); */
1331 /* disable fail interrupt */
1332 temp = sunxi_pwm_readl(chip, PWM_CIER);
1333 temp = SET_BITS(1 + index * 0x2, 0x1, temp, 0x0);
1334 sunxi_pwm_writel(chip, PWM_CIER, temp);
1335
1336 /* disable capture */
1337 temp = sunxi_pwm_readl(chip, pc->data->cer_offset);
1338 temp = SET_BITS(index, 0x1, temp, 0x0);
1339 sunxi_pwm_writel(chip, pc->data->cer_offset, temp);
1340 goto end;
1341 }
1342 }
1343 }
1344 end:
1345 temp_clk = (cap_time[1] + cap_time[2]) * 1000 * pwm_div;
1346 do_div(temp_clk, pwm_clk);
1347 result->period = (unsigned int)temp_clk;
1348 temp_clk = cap_time[1] * 1000 * pwm_div;
1349 do_div(temp_clk, pwm_clk);
1350 result->duty_cycle = (unsigned int)temp_clk;
1351
1352 reg_shift = index;
1353 value = sunxi_pwm_readl(chip, pc->data->per_offset);
1354 /*
1355 * 0 , 1 --> 0
1356 * 2 , 3 --> 2
1357 * 4 , 5 --> 4
1358 * 6 , 7 --> 6
1359 */
1360 reg_shift &= ~(1);
1361 if (GET_BITS(reg_shift, 2, value) == 0) {
1362 value = sunxi_pwm_readl(chip, pc->data->cer_offset);
1363 if (GET_BITS(reg_shift, 2, value) == 0) {
1364 /* disable clk for pwm controller. */
1365 get_pccr_reg_offset(index, ®_offset);
1366 reg_shift = PWM_CLK_GATING_SHIFT;
1367 value = sunxi_pwm_readl(chip, reg_offset);
1368 value = SET_BITS(reg_shift, 0x1, value, 0);
1369 sunxi_pwm_writel(chip, reg_offset, value);
1370 }
1371 }
1372 sunxi_pwm_pin_set_state(&pwm_pdevice->dev, PWM_PIN_STATE_SLEEP);
1373
1374 if (timeout <= 0) {
1375 pr_err("%s: pwm capture timeout !\n", __func__);
1376 return -1;
1377 }
1378 return 0;
1379 }
1380
sunxi_pwm_get_state(struct pwm_chip * chip,struct pwm_device * pwm,struct pwm_state * state)1381 static void sunxi_pwm_get_state(struct pwm_chip *chip,
1382 struct pwm_device *pwm,
1383 struct pwm_state *state)
1384 {
1385 unsigned int reg_offset;
1386 u32 val, sel;
1387 struct sunxi_pwm_chip *pc = to_sunxi_pwm_chip(chip);
1388
1389 sel = pwm->pwm - chip->base;
1390 reg_offset = pc->data->pcr_base_offset + sel * PWM_REG_UNIFORM_OFFSET;
1391
1392 val = sunxi_pwm_readl(chip, reg_offset);
1393 if (val & BIT_MASK(8)) {
1394 state->polarity = PWM_POLARITY_NORMAL;
1395 } else {
1396 state->polarity = PWM_POLARITY_INVERSED;
1397 }
1398
1399 }
1400
1401 static struct pwm_ops sunxi_pwm_ops = {
1402 .config = sunxi_pwm_config,
1403 .enable = sunxi_pwm_enable,
1404 .disable = sunxi_pwm_disable,
1405 .set_polarity = sunxi_pwm_set_polarity,
1406 .capture = sunxi_pwm_capture,
1407 .get_state = sunxi_pwm_get_state,
1408 .owner = THIS_MODULE,
1409 };
1410
1411 static const struct of_device_id sunxi_pwm_match[] = {
1412 { .compatible = "allwinner,sunxi-pwm", .data = &sunxi_pwm_v200_data},
1413 { .compatible = "allwinner,sunxi-s_pwm", .data = &sunxi_pwm_v200_data},
1414 { .compatible = "allwinner,sunxi-pwm-v100", .data = &sunxi_pwm_v100_data},
1415 { /* sentinel */ },
1416 };
1417 MODULE_DEVICE_TABLE(of, sunxi_pwm_match);
1418
sunxi_pwm_fill_hw_data(struct sunxi_pwm_chip * pwm)1419 static int sunxi_pwm_fill_hw_data(struct sunxi_pwm_chip *pwm)
1420 {
1421 size_t size;
1422 const struct of_device_id *of_id;
1423
1424 /* get hw data from match table*/
1425 of_id = of_match_device(sunxi_pwm_match, pwm->chip.dev);
1426 if (!of_id) {
1427 dev_err(pwm->chip.dev, "of_match_device() failed\n");
1428 return -EINVAL;
1429 }
1430
1431 pwm->data = (struct sunxi_pwm_hw_data *)(of_id->data);
1432
1433 size = sizeof(u32) * pwm->data->pm_regs_num;
1434 pwm->pm_regs_offset = devm_kzalloc(pwm->chip.dev, size, GFP_KERNEL);
1435 pwm->regs_backup = devm_kzalloc(pwm->chip.dev, size, GFP_KERNEL);
1436
1437 /* Configure the registers that need to be saved for wake-up from sleep */
1438 pwm->pm_regs_offset[0] = PWM_PIER;
1439 pwm->pm_regs_offset[1] = PWM_CIER;
1440 pwm->pm_regs_offset[2] = pwm->data->per_offset;
1441 pwm->pm_regs_offset[3] = pwm->data->cer_offset;
1442 if (pwm->data->clk_gating_separate)
1443 pwm->pm_regs_offset[4] = PCGR;
1444
1445 return 0;
1446 }
1447
sunxi_pwm_probe(struct platform_device * pdev)1448 static int sunxi_pwm_probe(struct platform_device *pdev)
1449 {
1450 int ret;
1451 struct sunxi_pwm_chip *pwm;
1452 struct device_node *np = pdev->dev.of_node;
1453 int i;
1454 struct platform_device *pwm_pdevice;
1455 struct device_node *sub_np;
1456
1457 pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
1458
1459 if (IS_ERR_OR_NULL(pwm))
1460 return -ENOMEM;
1461
1462 platform_set_drvdata(pdev, pwm);
1463 pwm->chip.dev = &pdev->dev;
1464
1465 ret = sunxi_pwm_fill_hw_data(pwm);
1466 if (ret) {
1467 dev_err(&pdev->dev, "unable to get hw_data\n");
1468 return ret;
1469 }
1470
1471 /* io map pwm base */
1472 pwm->base = (void __iomem *)of_iomap(pdev->dev.of_node, 0);
1473 if (!pwm->base) {
1474 dev_err(&pdev->dev, "unable to map pwm registers\n");
1475 ret = -EINVAL;
1476 goto err_iomap;
1477 }
1478
1479 /* read property pwm-number */
1480 ret = of_property_read_u32(np, "pwm-number", &pwm->chip.npwm);
1481 if (ret < 0) {
1482 dev_err(&pdev->dev, "failed to get pwm number: %d, force to one!\n", ret);
1483 /* force to one pwm if read property fail */
1484 pwm->chip.npwm = 1;
1485 goto err_iomap;
1486 }
1487
1488 /* read property pwm-base */
1489 ret = of_property_read_u32(np, "pwm-base", &pwm->chip.base);
1490 if (ret < 0) {
1491 dev_err(&pdev->dev, "failed to get pwm-base: %d, force to -1 !\n", ret);
1492 /* force to one pwm if read property fail */
1493 pwm->chip.base = -1;
1494 }
1495
1496 pwm->chip.ops = &sunxi_pwm_ops;
1497 pwm->chip.of_xlate = of_pwm_xlate_with_flags;
1498 pwm->chip.of_pwm_n_cells = 3;
1499
1500 /* add pwm chip to pwm-core */
1501 ret = pwmchip_add(&pwm->chip);
1502 if (ret < 0) {
1503 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
1504 goto err_add;
1505 }
1506
1507 pwm->config = devm_kzalloc(&pdev->dev, sizeof(*pwm->config) * pwm->chip.npwm, GFP_KERNEL);
1508 if (!pwm->config) {
1509 dev_err(&pdev->dev, "failed to allocate memory!\n");
1510 goto err_alloc;
1511 }
1512
1513 for (i = 0; i < pwm->chip.npwm; i++) {
1514 sub_np = of_parse_phandle(np, "sunxi-pwms", i);
1515 if (IS_ERR_OR_NULL(sub_np)) {
1516 pr_err("%s: can't parse \"sunxi-pwms\" property\n", __func__);
1517 return -EINVAL;
1518 }
1519
1520 pwm_pdevice = of_find_device_by_node(sub_np);
1521 /* it may be the program is error or the status of pwm%d is disabled */
1522 if (!pwm_pdevice) {
1523 pr_debug("%s:fail to find device for pwm%d, continue!\n", __func__, i);
1524 continue;
1525 }
1526 ret = sunxi_pwm_get_config(pwm_pdevice, &pwm->config[i]);
1527 if (ret) {
1528 pr_err("Get config failed,exit!\n");
1529 goto err_get_config;
1530 }
1531 }
1532
1533 pwm->pwm_clk = of_clk_get(pdev->dev.of_node, 0);
1534 if (IS_ERR_OR_NULL(pwm->pwm_clk)) {
1535 pr_err("%s: can't get pwm clk\n", __func__);
1536 return -EINVAL;
1537 }
1538 pwm->pwm_rst_clk = devm_reset_control_get(&pdev->dev, NULL);
1539 if (IS_ERR_OR_NULL(pwm->pwm_rst_clk)) {
1540 pr_err("%s: can't get pwm reset clk\n", __func__);
1541 return -EINVAL;
1542 }
1543 reset_control_deassert(pwm->pwm_rst_clk);
1544 clk_prepare_enable(pwm->pwm_clk);
1545
1546 return 0;
1547
1548 err_get_config:
1549 err_alloc:
1550 pwmchip_remove(&pwm->chip);
1551 err_add:
1552 iounmap(pwm->base);
1553 err_iomap:
1554 return ret;
1555 }
1556
sunxi_pwm_remove(struct platform_device * pdev)1557 static int sunxi_pwm_remove(struct platform_device *pdev)
1558 {
1559 struct sunxi_pwm_chip *pwm = platform_get_drvdata(pdev);
1560 clk_disable(pwm->pwm_clk);
1561 reset_control_assert(pwm->pwm_rst_clk);
1562 return pwmchip_remove(&pwm->chip);
1563 }
1564
1565 #if IS_ENABLED(CONFIG_PM)
1566
sunxi_pwm_stop_work(struct sunxi_pwm_chip * pwm)1567 static void sunxi_pwm_stop_work(struct sunxi_pwm_chip *pwm)
1568 {
1569 int i;
1570 bool pwm_state;
1571
1572 for (i = 0; i < pwm->chip.npwm; i++) {
1573 pwm_state = pwm->chip.pwms[i].state.enabled;
1574 pwm_disable(&pwm->chip.pwms[i]);
1575 pwm->chip.pwms[i].state.enabled = pwm_state;
1576 }
1577 }
1578
sunxi_pwm_start_work(struct sunxi_pwm_chip * pwm)1579 static void sunxi_pwm_start_work(struct sunxi_pwm_chip *pwm)
1580 {
1581 int i;
1582 struct pwm_state state;
1583
1584 for (i = 0; i < pwm->chip.npwm; i++) {
1585 pwm_get_state(&pwm->chip.pwms[i], &state);
1586 pwm->chip.pwms[i].state.period = 0;
1587 pwm->chip.pwms[i].state.duty_cycle = 0;
1588 pwm->chip.pwms[i].state.polarity = PWM_POLARITY_NORMAL;
1589 pwm_apply_state(&pwm->chip.pwms[i], &state);
1590 if (pwm_is_enabled(&pwm->chip.pwms[i])) {
1591 pwm->chip.pwms[i].state.enabled = false;
1592 pwm_enable(&pwm->chip.pwms[i]);
1593 }
1594 }
1595 }
1596
sunxi_pwm_suspend(struct device * dev)1597 static int sunxi_pwm_suspend(struct device *dev)
1598 {
1599 struct platform_device *pdev = container_of(dev,
1600 struct platform_device, dev);
1601 struct sunxi_pwm_chip *pwm = platform_get_drvdata(pdev);
1602
1603 sunxi_pwm_stop_work(pwm);
1604
1605 sunxi_pwm_save_regs(pwm);
1606
1607 clk_disable_unprepare(pwm->pwm_clk);
1608
1609 reset_control_assert(pwm->pwm_rst_clk);
1610
1611 return 0;
1612 }
1613
sunxi_pwm_resume(struct device * dev)1614 static int sunxi_pwm_resume(struct device *dev)
1615 {
1616 struct platform_device *pdev = container_of(dev,
1617 struct platform_device, dev);
1618 struct sunxi_pwm_chip *pwm = platform_get_drvdata(pdev);
1619 int ret = 0;
1620
1621 ret = reset_control_deassert(pwm->pwm_rst_clk);
1622 if (ret) {
1623 pr_err("reset_control_deassert() failed\n");
1624 return 0;
1625 }
1626
1627 ret = clk_prepare_enable(pwm->pwm_clk);
1628 if (ret) {
1629 pr_err("clk_prepare_enable() failed\n");
1630 return 0;
1631 }
1632
1633 sunxi_pwm_restore_regs(pwm);
1634
1635 sunxi_pwm_start_work(pwm);
1636
1637 return 0;
1638 }
1639
1640 static const struct dev_pm_ops pwm_pm_ops = {
1641 .suspend_late = sunxi_pwm_suspend,
1642 .resume_early = sunxi_pwm_resume,
1643 };
1644 #else
1645 static const struct dev_pm_ops pwm_pm_ops;
1646 #endif
1647
1648
1649
1650 static struct platform_driver sunxi_pwm_driver = {
1651 .probe = sunxi_pwm_probe,
1652 .remove = sunxi_pwm_remove,
1653 .driver = {
1654 .name = "sunxi_pwm",
1655 .owner = THIS_MODULE,
1656 .of_match_table = sunxi_pwm_match,
1657 .pm = &pwm_pm_ops,
1658 },
1659 };
1660
pwm_module_init(void)1661 static int __init pwm_module_init(void)
1662 {
1663 int ret = 0;
1664
1665 pr_info("pwm module init!\n");
1666
1667 #if !IS_ENABLED(CONFIG_OF)
1668 ret = platform_device_register(&sunxi_pwm_device);
1669 #endif
1670 if (ret == 0) {
1671 ret = platform_driver_register(&sunxi_pwm_driver);
1672 }
1673
1674 return ret;
1675 }
1676
pwm_module_exit(void)1677 static void __exit pwm_module_exit(void)
1678 {
1679 pr_info("pwm module exit!\n");
1680
1681 platform_driver_unregister(&sunxi_pwm_driver);
1682 #if !IS_ENABLED(CONFIG_OF)
1683 platform_device_unregister(&sunxi_pwm_device);
1684 #endif
1685 }
1686
1687 subsys_initcall_sync(pwm_module_init);
1688 module_exit(pwm_module_exit);
1689
1690 MODULE_AUTHOR("lihuaxing");
1691 MODULE_DESCRIPTION("pwm driver");
1692 MODULE_LICENSE("GPL");
1693 MODULE_ALIAS("platform:sunxi-pwm");
1694 MODULE_VERSION("1.1.1");
1695
1696