1 /*
2 * (C) Copyright 2007-2013
3 * Reuuimlla Technology Co., Ltd. <www.reuuimllatech.com>
4 * Aaron.Maoye <leafy.myeh@reuuimllatech.com>
5 *
6 * Driver of Allwinner UART controller.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * 2013.6.6 Mintow <duanmintao@allwinnertech.com>
14 * Adapt to support sun8i/sun9i of Allwinner.
15 */
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/io.h>
19 #include <linux/irq.h>
20 #include <linux/clk.h>
21 #include <linux/gpio.h>
22 #include <linux/delay.h>
23 #include <linux/ctype.h>
24 #include <linux/slab.h>
25 #include <linux/proc_fs.h>
26 #include <linux/platform_device.h>
27 #include <linux/pinctrl/consumer.h>
28
29 #include <linux/console.h>
30 #include <linux/tty.h>
31 #include <linux/tty_flip.h>
32 #include <linux/serial_core.h>
33 #include <linux/serial.h>
34
35 #include <linux/clk.h>
36 #include <linux/clk-provider.h>
37
38 #include <linux/dmaengine.h>
39 #include <linux/dma-mapping.h>
40
41 #include <linux/of.h>
42 #include <linux/of_irq.h>
43 #include <linux/of_address.h>
44 #include "sunxi-uart.h"
45
46 #if defined(CONFIG_AW_SERIAL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
47 #define SUPPORT_SYSRQ
48 #endif
49
50
51 /* #define CONFIG_SW_UART_DUMP_DATA */
52 /*
53 * ********************* Note **********************
54 * CONFIG_SW_UART_DUMP_DATA may cause some problems
55 * with some commands of 'dmesg', 'logcat', and
56 * 'cat /proc/kmsg' in the console. This problem may
57 * cause kernel to dead. These commands will work fine
58 * in the adb shell. So you must be very clear with
59 * this problem if you want define this macro to debug.
60 */
61
62 /* debug control */
63 #define SERIAL_DBG(fmt, arg...) \
64 do { \
65 if (sw_uport->port.line != 0) \
66 pr_debug("%s()%d - "fmt, __func__, __LINE__, ##arg); \
67 } while (0)
68 #define SERIAL_MSG(fmt, arg...) pr_warn("%s()%d - "fmt, __func__, __LINE__, ##arg)
69
70 #define TX_DMA 1
71 #define RX_DMA 2
72 #define DMA_SERIAL_BUFFER_SIZE (PAGE_SIZE)
73 #define SERIAL_CIRC_CNT_TO_END(xmit) \
74 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE)
75
76 enum uart_time_use {
77 UART_NO_USE_TIMER = 0,
78 UART_USE_TIMER,
79 };
80
81 #if IS_ENABLED(CONFIG_AW_SERIAL_DMA)
82 static void sw_uart_stop_dma_tx(struct sw_uart_port *sw_uport);
83 static void sw_uart_release_dma_tx(struct sw_uart_port *sw_uport);
84 static int sw_uart_init_dma_tx(struct sw_uart_port *sw_uport);
85 static void dma_tx_callback(void *data);
86 static int sw_uart_start_dma_tx(struct sw_uart_port *sw_uport);
87 static void sw_uart_stop_dma_tx(struct sw_uart_port *sw_uport);
88 static void sw_uart_release_dma_rx(struct sw_uart_port *sw_uport);
89 static int sw_uart_init_dma_rx(struct sw_uart_port *sw_uport);
90 static int sw_uart_start_dma_rx(struct sw_uart_port *sw_uport);
91 static void sw_uart_update_rb_addr(struct sw_uart_port *sw_uport);
92 static enum hrtimer_restart sw_uart_report_dma_rx(struct hrtimer *rx_hrtimer);
93 #endif
94
95 #if IS_ENABLED(CONFIG_SW_UART_DUMP_DATA)
sw_uart_dump_data(struct sw_uart_port * sw_uport,char * prompt)96 static void sw_uart_dump_data(struct sw_uart_port *sw_uport, char *prompt)
97 {
98 int i, j;
99 int head = 0;
100 char *buf = sw_uport->dump_buff;
101 u32 len = sw_uport->dump_len;
102 static char pbuff[128];
103 u32 idx = 0;
104
105 BUG_ON(sw_uport->dump_len > MAX_DUMP_SIZE);
106 BUG_ON(!sw_uport->dump_buff);
107 #define MAX_DUMP_PER_LINE (16)
108 #define MAX_DUMP_PER_LINE_HALF (MAX_DUMP_PER_LINE >> 1)
109 printk(KERN_DEBUG "%s len %d\n", prompt, len);
110 for (i = 0; i < len;) {
111 if ((i & (MAX_DUMP_PER_LINE-1)) == 0) {
112 idx += sprintf(&pbuff[idx], "%04x: ", i);
113 head = i;
114 }
115 idx += sprintf(&pbuff[idx], "%02x ", buf[i]&0xff);
116 if ((i & (MAX_DUMP_PER_LINE-1)) == MAX_DUMP_PER_LINE-1 || i == len-1) {
117 for (j = i-head+1; j < MAX_DUMP_PER_LINE; j++)
118 idx += sprintf(&pbuff[idx], " ");
119 idx += sprintf(&pbuff[idx], " |");
120 for (j = head; j <= i; j++) {
121 if (isascii(buf[j]) && isprint(buf[j]))
122 idx += sprintf(&pbuff[idx], "%c", buf[j]);
123 else
124 idx += sprintf(&pbuff[idx], ".");
125 }
126 idx += sprintf(&pbuff[idx], "|\n");
127 pbuff[idx] = '\0';
128 printk(KERN_DEBUG "%s", pbuff);
129 idx = 0;
130 }
131 i++;
132 }
133 sw_uport->dump_len = 0;
134 }
135 #define SERIAL_DUMP(up, ...) do { \
136 if (DEBUG_CONDITION) \
137 sw_uart_dump_data(up, __VA_ARGS__); \
138 } while (0)
139 #else
140 #define SERIAL_DUMP(up, ...) { up->dump_len = 0; }
141 #endif
142
143 #define UART_TO_SPORT(port) ((struct sw_uart_port *)port)
144
serial_in(struct uart_port * port,int offs)145 static inline unsigned char serial_in(struct uart_port *port, int offs)
146 {
147 return readb_relaxed(port->membase + offs);
148 }
149
serial_out(struct uart_port * port,unsigned char value,int offs)150 static inline void serial_out(struct uart_port *port, unsigned char value, int offs)
151 {
152 writeb_relaxed(value, port->membase + offs);
153 }
154
sw_is_console_port(struct uart_port * port)155 static inline bool sw_is_console_port(struct uart_port *port)
156 {
157 return port->cons && port->cons->index == port->line;
158 }
159
sw_uart_reset(struct sw_uart_port * sw_uport)160 static inline void sw_uart_reset(struct sw_uart_port *sw_uport)
161 {
162 #if IS_ENABLED(CONFIG_AW_IC_BOARD)
163 int ret;
164 ret = reset_control_assert(sw_uport->reset);
165 ret = reset_control_deassert(sw_uport->reset);
166 #endif
167 }
168
sw_uart_enable_ier_thri(struct uart_port * port)169 static inline void sw_uart_enable_ier_thri(struct uart_port *port)
170 {
171 struct sw_uart_port *sw_uport = UART_TO_SPORT(port);
172
173 if (!(sw_uport->ier & SUNXI_UART_IER_THRI)) {
174 sw_uport->ier |= SUNXI_UART_IER_THRI;
175 SERIAL_DBG("start tx, ier %x\n", sw_uport->ier);
176 serial_out(port, sw_uport->ier, SUNXI_UART_IER);
177 }
178 }
179
sw_uart_disable_ier_thri(struct uart_port * port)180 static inline void sw_uart_disable_ier_thri(struct uart_port *port)
181 {
182 struct sw_uart_port *sw_uport = UART_TO_SPORT(port);
183
184 if (sw_uport->ier & SUNXI_UART_IER_THRI) {
185 sw_uport->ier &= ~SUNXI_UART_IER_THRI;
186 SERIAL_DBG("stop tx, ier %x\n", sw_uport->ier);
187 serial_out(port, sw_uport->ier, SUNXI_UART_IER);
188 }
189 }
190
sw_uart_handle_rx(struct sw_uart_port * sw_uport,unsigned int lsr)191 static unsigned int sw_uart_handle_rx(struct sw_uart_port *sw_uport, unsigned int lsr)
192 {
193 unsigned char ch = 0;
194 int max_count = 256;
195 char flag;
196
197 #if IS_ENABLED(CONFIG_AW_SERIAL_DMA)
198 if ((sw_uport->dma->use_dma & RX_DMA)) {
199 if (lsr & SUNXI_UART_LSR_RXFIFOE) {
200 dev_info(sw_uport->port.dev, "error:lsr=0x%x\n", lsr);
201 lsr = serial_in(&sw_uport->port, SUNXI_UART_LSR);
202 return lsr;
203 }
204 }
205 #endif
206 do {
207 if (likely(lsr & SUNXI_UART_LSR_DR)) {
208 ch = serial_in(&sw_uport->port, SUNXI_UART_RBR);
209 #if IS_ENABLED(CONFIG_SW_UART_DUMP_DATA)
210 sw_uport->dump_buff[sw_uport->dump_len++] = ch;
211 #endif
212 } else
213 ch = 0;
214
215 flag = TTY_NORMAL;
216 sw_uport->port.icount.rx++;
217
218 if (unlikely(lsr & SUNXI_UART_LSR_BRK_ERROR_BITS)) {
219 /*
220 * For statistics only
221 */
222 if (lsr & SUNXI_UART_LSR_BI) {
223 lsr &= ~(SUNXI_UART_LSR_FE | SUNXI_UART_LSR_PE);
224 sw_uport->port.icount.brk++;
225 /*
226 * We do the SysRQ and SAK checking
227 * here because otherwise the break
228 * may get masked by ignore_status_mask
229 * or read_status_mask.
230 */
231 if (!ch && uart_handle_break(&sw_uport->port))
232 goto ignore_char;
233 } else if (lsr & SUNXI_UART_LSR_PE)
234 sw_uport->port.icount.parity++;
235 else if (lsr & SUNXI_UART_LSR_FE)
236 sw_uport->port.icount.frame++;
237 if (lsr & SUNXI_UART_LSR_OE)
238 sw_uport->port.icount.overrun++;
239
240 /*
241 * Mask off conditions which should be ignored.
242 */
243 lsr &= sw_uport->port.read_status_mask;
244 #if IS_ENABLED(CONFIG_AW_SERIAL_CONSOLE)
245 if (sw_is_console_port(&sw_uport->port)) {
246 /* Recover the break flag from console xmit */
247 lsr |= sw_uport->lsr_break_flag;
248 }
249 #endif
250 if (lsr & SUNXI_UART_LSR_BI)
251 flag = TTY_BREAK;
252 else if (lsr & SUNXI_UART_LSR_PE)
253 flag = TTY_PARITY;
254 else if (lsr & SUNXI_UART_LSR_FE)
255 flag = TTY_FRAME;
256 }
257 if (uart_handle_sysrq_char(&sw_uport->port, ch))
258 goto ignore_char;
259 uart_insert_char(&sw_uport->port, lsr, SUNXI_UART_LSR_OE, ch, flag);
260 ignore_char:
261 lsr = serial_in(&sw_uport->port, SUNXI_UART_LSR);
262 } while ((lsr & (SUNXI_UART_LSR_DR | SUNXI_UART_LSR_BI)) && (max_count-- > 0));
263
264 SERIAL_DUMP(sw_uport, "Rx");
265 spin_unlock(&sw_uport->port.lock);
266 tty_flip_buffer_push(&sw_uport->port.state->port);
267 spin_lock(&sw_uport->port.lock);
268
269 return lsr;
270 }
271
sw_uart_stop_tx(struct uart_port * port)272 static void sw_uart_stop_tx(struct uart_port *port)
273 {
274 #if IS_ENABLED(CONFIG_AW_SERIAL_DMA)
275 struct sw_uart_port *sw_uport = UART_TO_SPORT(port);
276 struct sw_uart_dma *uart_dma = sw_uport->dma;
277
278 if (uart_dma->use_dma & TX_DMA)
279 sw_uart_stop_dma_tx(sw_uport);
280 #endif
281 sw_uart_disable_ier_thri(port);
282 }
283
sw_uart_start_tx(struct uart_port * port)284 static void sw_uart_start_tx(struct uart_port *port)
285 {
286 #if IS_ENABLED(CONFIG_AW_SERIAL_DMA)
287 struct sw_uart_port *sw_uport = UART_TO_SPORT(port);
288
289 if (!((sw_uport->dma->use_dma & TX_DMA) && sw_uport->dma->tx_dma_used))
290 #endif
291 sw_uart_enable_ier_thri(port);
292 }
293
sw_uart_handle_tx(struct sw_uart_port * sw_uport)294 static void sw_uart_handle_tx(struct sw_uart_port *sw_uport)
295 {
296 struct circ_buf *xmit = &sw_uport->port.state->xmit;
297 int count;
298
299 if (sw_uport->port.x_char) {
300 serial_out(&sw_uport->port, sw_uport->port.x_char, SUNXI_UART_THR);
301 sw_uport->port.icount.tx++;
302 sw_uport->port.x_char = 0;
303 #if IS_ENABLED(CONFIG_SW_UART_DUMP_DATA)
304 sw_uport->dump_buff[sw_uport->dump_len++] = sw_uport->port.x_char;
305 SERIAL_DUMP(sw_uport, "Tx");
306 #endif
307 return;
308 }
309 if (uart_circ_empty(xmit) || uart_tx_stopped(&sw_uport->port)) {
310 sw_uart_stop_tx(&sw_uport->port);
311 return;
312 }
313
314 #if IS_ENABLED(CONFIG_AW_SERIAL_DMA)
315 if (sw_uport->dma->use_dma & TX_DMA) {
316 if (SERIAL_CIRC_CNT_TO_END(xmit) >= (sw_uport->port.fifosize / 2)) {
317 sw_uart_start_dma_tx(sw_uport);
318 return;
319 }
320 }
321 #endif
322
323 count = sw_uport->port.fifosize / 2;
324 do {
325 #if IS_ENABLED(CONFIG_SW_UART_DUMP_DATA)
326 sw_uport->dump_buff[sw_uport->dump_len++] = xmit->buf[xmit->tail];
327 #endif
328 serial_out(&sw_uport->port, xmit->buf[xmit->tail], SUNXI_UART_THR);
329 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
330 sw_uport->port.icount.tx++;
331 if (uart_circ_empty(xmit)) {
332 break;
333 }
334 } while (--count > 0);
335
336 SERIAL_DUMP(sw_uport, "Tx");
337 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
338 spin_unlock(&sw_uport->port.lock);
339 uart_write_wakeup(&sw_uport->port);
340 spin_lock(&sw_uport->port.lock);
341 }
342 if (uart_circ_empty(xmit))
343 sw_uart_stop_tx(&sw_uport->port);
344 }
345
sw_uart_modem_status(struct sw_uart_port * sw_uport)346 static unsigned int sw_uart_modem_status(struct sw_uart_port *sw_uport)
347 {
348 unsigned int status = serial_in(&sw_uport->port, SUNXI_UART_MSR);
349
350 status |= sw_uport->msr_saved_flags;
351 sw_uport->msr_saved_flags = 0;
352
353 if (status & SUNXI_UART_MSR_ANY_DELTA && sw_uport->ier & SUNXI_UART_IER_MSI &&
354 sw_uport->port.state != NULL) {
355 if (status & SUNXI_UART_MSR_TERI)
356 sw_uport->port.icount.rng++;
357 if (status & SUNXI_UART_MSR_DDSR)
358 sw_uport->port.icount.dsr++;
359 if (status & SUNXI_UART_MSR_DDCD)
360 uart_handle_dcd_change(&sw_uport->port, status & SUNXI_UART_MSR_DCD);
361 if (!(sw_uport->mcr & SUNXI_UART_MCR_AFE) && status & SUNXI_UART_MSR_DCTS)
362 uart_handle_cts_change(&sw_uport->port, status & SUNXI_UART_MSR_CTS);
363
364 wake_up_interruptible(&sw_uport->port.state->port.delta_msr_wait);
365 }
366
367 SERIAL_DBG("modem status: %x\n", status);
368 return status;
369 }
370
sw_uart_force_lcr(struct sw_uart_port * sw_uport,unsigned msecs)371 static void sw_uart_force_lcr(struct sw_uart_port *sw_uport, unsigned msecs)
372 {
373 unsigned long expire = jiffies + msecs_to_jiffies(msecs);
374 struct uart_port *port = &sw_uport->port;
375
376 /* hold tx so that uart will update lcr and baud in the gap of rx */
377 serial_out(port, SUNXI_UART_HALT_HTX|SUNXI_UART_HALT_FORCECFG, SUNXI_UART_HALT);
378 serial_out(port, sw_uport->lcr|SUNXI_UART_LCR_DLAB, SUNXI_UART_LCR);
379 serial_out(port, sw_uport->dll, SUNXI_UART_DLL);
380 serial_out(port, sw_uport->dlh, SUNXI_UART_DLH);
381 serial_out(port, SUNXI_UART_HALT_HTX|SUNXI_UART_HALT_FORCECFG|SUNXI_UART_HALT_LCRUP, SUNXI_UART_HALT);
382 while (time_before(jiffies, expire) && (serial_in(port, SUNXI_UART_HALT) & SUNXI_UART_HALT_LCRUP))
383 ;
384
385 /*
386 * In fact there are two DLABs(DLAB and DLAB_BAK) in the hardware implementation.
387 * The DLAB_BAK is sellected only when SW_UART_HALT_FORCECFG is set to 1,
388 * and this bit can be access no matter uart is busy or not.
389 * So we select the DLAB_BAK always by leaving SW_UART_HALT_FORCECFG to be 1.
390 */
391 serial_out(port, sw_uport->lcr, SUNXI_UART_LCR);
392 serial_out(port, SUNXI_UART_HALT_FORCECFG, SUNXI_UART_HALT);
393 }
394
sw_uart_force_idle(struct sw_uart_port * sw_uport)395 static void sw_uart_force_idle(struct sw_uart_port *sw_uport)
396 {
397 struct uart_port *port = &sw_uport->port;
398
399 if (sw_uport->fcr & SUNXI_UART_FCR_FIFO_EN) {
400 serial_out(port, SUNXI_UART_FCR_FIFO_EN, SUNXI_UART_FCR);
401 serial_out(port, SUNXI_UART_FCR_TXFIFO_RST
402 | SUNXI_UART_FCR_RXFIFO_RST
403 | SUNXI_UART_FCR_FIFO_EN, SUNXI_UART_FCR);
404 serial_out(port, 0, SUNXI_UART_FCR);
405 }
406
407 serial_out(port, sw_uport->fcr, SUNXI_UART_FCR);
408 (void)serial_in(port, SUNXI_UART_FCR);
409 }
410
411 /*
412 * We should clear busy interupt, busy state and reset lcr,
413 * but we should be careful not to introduce a new busy interrupt.
414 */
sw_uart_handle_busy(struct sw_uart_port * sw_uport)415 static void sw_uart_handle_busy(struct sw_uart_port *sw_uport)
416 {
417 struct uart_port *port = &sw_uport->port;
418
419 (void)serial_in(port, SUNXI_UART_USR);
420
421 /*
422 * Before reseting lcr, we should ensure than uart is not in busy
423 * state. Otherwise, a new busy interrupt will be introduced.
424 * It is wise to set uart into loopback mode, since it can cut down the
425 * serial in, then we should reset fifo(in my test, busy state
426 * (SUNXI_UART_USR_BUSY) can't be cleard until the fifo is empty).
427 */
428 serial_out(port, sw_uport->mcr | SUNXI_UART_MCR_LOOP, SUNXI_UART_MCR);
429 sw_uart_force_idle(sw_uport);
430 serial_out(port, sw_uport->lcr, SUNXI_UART_LCR);
431 serial_out(port, sw_uport->mcr, SUNXI_UART_MCR);
432 }
433
434 #if IS_ENABLED(CONFIG_AW_SERIAL_DMA)
sw_uart_stop_dma_tx(struct sw_uart_port * sw_uport)435 static void sw_uart_stop_dma_tx(struct sw_uart_port *sw_uport)
436 {
437 struct sw_uart_dma *uart_dma = sw_uport->dma;
438
439 if (uart_dma && uart_dma->tx_dma_used) {
440 dmaengine_terminate_all(uart_dma->dma_chan_tx);
441 uart_dma->tx_dma_used = 0;
442 }
443 }
444
sw_uart_release_dma_tx(struct sw_uart_port * sw_uport)445 static void sw_uart_release_dma_tx(struct sw_uart_port *sw_uport)
446 {
447 struct sw_uart_dma *uart_dma = sw_uport->dma;
448
449 if (uart_dma && uart_dma->tx_dma_inited) {
450 sw_uart_stop_dma_tx(sw_uport);
451 dma_free_coherent(sw_uport->port.dev, sw_uport->dma->tb_size,
452 sw_uport->dma->tx_buffer, sw_uport->dma->tx_phy_addr);
453 sw_uport->port.state->xmit.buf = NULL;
454 dma_release_channel(uart_dma->dma_chan_tx);
455 uart_dma->dma_chan_tx = NULL;
456 uart_dma->tx_dma_inited = 0;
457 }
458 }
459
sw_uart_init_dma_tx(struct sw_uart_port * sw_uport)460 static int sw_uart_init_dma_tx(struct sw_uart_port *sw_uport)
461 {
462 struct dma_slave_config slave_config;
463 struct uart_port *port = &sw_uport->port;
464 struct sw_uart_dma *uart_dma = sw_uport->dma;
465 int ret;
466
467 if (!uart_dma) {
468 dev_info(sw_uport->port.dev, "sw_uart_init_dma_tx fail\n");
469 return -1;
470 }
471
472 if (uart_dma->tx_dma_inited)
473 return 0;
474
475 uart_dma->dma_chan_tx = dma_request_chan(sw_uport->port.dev, "tx");
476 if (!uart_dma->dma_chan_tx) {
477 dev_err(port->dev, "cannot get the TX DMA channel!\n");
478 ret = -EINVAL;
479 }
480
481 slave_config.direction = DMA_MEM_TO_DEV;
482 slave_config.dst_addr = port->mapbase + SUNXI_UART_THR;
483 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
484 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
485 slave_config.src_maxburst = 1;
486 slave_config.dst_maxburst = 1;
487 ret = dmaengine_slave_config(uart_dma->dma_chan_tx, &slave_config);
488 if (ret) {
489 dev_err(port->dev, "error in TX dma configuration.");
490 return ret;
491 }
492
493 uart_dma->tx_dma_inited = 1;
494 dev_info(port->dev, "sw_uart_init_dma_tx sucess\n");
495 return 0;
496 }
497
dma_tx_callback(void * data)498 static void dma_tx_callback(void *data)
499 {
500 struct uart_port *port = data;
501 struct sw_uart_port *sw_uport = container_of(port,
502 struct sw_uart_port, port);
503 struct circ_buf *xmit = &port->state->xmit;
504 struct sw_uart_dma *uart_dma = sw_uport->dma;
505 struct scatterlist *sgl = &uart_dma->tx_sgl;
506
507 dma_unmap_sg(sw_uport->port.dev, sgl, 1, DMA_TO_DEVICE);
508
509 xmit->tail = (xmit->tail + uart_dma->tx_bytes) & (UART_XMIT_SIZE - 1);
510 port->icount.tx += uart_dma->tx_bytes;
511 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
512 uart_write_wakeup(port);
513
514 uart_dma->tx_dma_used = 0;
515 sw_uart_enable_ier_thri(port);
516 }
517
sw_uart_start_dma_tx(struct sw_uart_port * sw_uport)518 static int sw_uart_start_dma_tx(struct sw_uart_port *sw_uport)
519 {
520 int count = 0;
521 struct uart_port *port = &sw_uport->port;
522 struct circ_buf *xmit = &port->state->xmit;
523 struct sw_uart_dma *uart_dma = sw_uport->dma;
524 struct scatterlist *sgl = &uart_dma->tx_sgl;
525 struct dma_async_tx_descriptor *desc;
526 int ret;
527
528 if (!uart_dma->use_dma)
529 goto err_out;
530
531 if (-1 == sw_uart_init_dma_tx(sw_uport))
532 goto err_out;
533
534 if (1 == uart_dma->tx_dma_used)
535 return 1;
536
537 /**********************************/
538 /* mask the stop now */
539 sw_uart_disable_ier_thri(port);
540
541 count = SERIAL_CIRC_CNT_TO_END(xmit);
542 uart_dma->tx_bytes = count;
543 sg_init_one(sgl, phys_to_virt(uart_dma->tx_phy_addr) + xmit->tail, count);
544 ret = dma_map_sg(port->dev, sgl, 1, DMA_TO_DEVICE);
545
546 if (ret == 0) {
547 dev_err(port->dev, "DMA mapping error for TX.\n");
548 return -1;
549 }
550 desc = dmaengine_prep_slave_sg(uart_dma->dma_chan_tx, sgl, 1,
551 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
552
553 if (!desc) {
554 dev_err(port->dev, "We cannot prepare for the TX slave dma!\n");
555 return -1;
556 }
557 desc->callback = dma_tx_callback;
558 desc->callback_param = port;
559 dmaengine_submit(desc);
560 dma_async_issue_pending(uart_dma->dma_chan_tx);
561 uart_dma->tx_dma_used = 1;
562 return 1;
563 err_out:
564 dev_info(sw_uport->port.dev, "-sw_uart_start_dma_tx-error-\n");
565 return -1;
566 }
567
sw_uart_stop_dma_rx(struct sw_uart_port * sw_uport)568 static void sw_uart_stop_dma_rx(struct sw_uart_port *sw_uport)
569 {
570 struct sw_uart_dma *uart_dma = sw_uport->dma;
571
572 if (uart_dma && uart_dma->rx_dma_used) {
573 hrtimer_cancel(&sw_uport->rx_hrtimer);
574 dmaengine_terminate_all(uart_dma->dma_chan_rx);
575 uart_dma->rb_tail = 0;
576 uart_dma->rx_dma_used = 0;
577 }
578 }
579
sw_uart_release_dma_rx(struct sw_uart_port * sw_uport)580 static void sw_uart_release_dma_rx(struct sw_uart_port *sw_uport)
581 {
582 struct sw_uart_dma *uart_dma = sw_uport->dma;
583
584 if (uart_dma && uart_dma->rx_dma_inited) {
585 sw_uart_stop_dma_rx(sw_uport);
586 dma_free_coherent(sw_uport->port.dev, sw_uport->dma->rb_size,
587 sw_uport->dma->rx_buffer, sw_uport->dma->rx_phy_addr);
588 dma_release_channel(uart_dma->dma_chan_rx);
589 uart_dma->dma_chan_rx = NULL;
590 uart_dma->rx_dma_inited = 0;
591 }
592 }
593
sw_uart_init_dma_rx(struct sw_uart_port * sw_uport)594 static int sw_uart_init_dma_rx(struct sw_uart_port *sw_uport)
595 {
596 int ret;
597 struct uart_port *port = &sw_uport->port;
598 struct dma_slave_config slave_config;
599 struct sw_uart_dma *uart_dma = sw_uport->dma;
600
601 if (!uart_dma) {
602 dev_info(port->dev, "sw_uart_init_dma_rx: port fail\n");
603 return -1;
604 }
605
606 if (uart_dma->rx_dma_inited)
607 return 0;
608
609 uart_dma->dma_chan_tx = dma_request_chan(sw_uport->port.dev, "rx");
610 if (!uart_dma->dma_chan_rx) {
611 dev_err(port->dev, "cannot get the DMA channel.\n");
612 return -1;
613 }
614
615 slave_config.direction = DMA_DEV_TO_MEM;
616 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
617 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
618 slave_config.src_maxburst = 1;
619 slave_config.dst_maxburst = 1;
620 slave_config.src_addr = port->mapbase + SUNXI_UART_RBR;
621
622 ret = dmaengine_slave_config(uart_dma->dma_chan_rx, &slave_config);
623 if (ret) {
624 dev_err(port->dev, "error in RX dma configuration.\n");
625 return ret;
626 }
627
628 uart_dma->rx_dma_inited = 1;
629 dev_info(port->dev, "sw_uart_init_dma_rx sucess\n");
630 return 0;
631 }
632
sw_uart_start_dma_rx(struct sw_uart_port * sw_uport)633 static int sw_uart_start_dma_rx(struct sw_uart_port *sw_uport)
634 {
635 struct uart_port *port = &sw_uport->port;
636 struct sw_uart_dma *uart_dma = sw_uport->dma;
637 struct dma_async_tx_descriptor *desc;
638
639 if (!uart_dma->use_dma)
640 return 0;
641
642 if (uart_dma->rx_dma_used == 1)
643 return 0;
644
645 if (-1 == sw_uart_init_dma_rx(sw_uport)) {
646 dev_info(sw_uport->port.dev, "sw_uart_init_dma_rx error!\n");
647 return -1;
648 }
649 desc = dmaengine_prep_dma_cyclic(uart_dma->dma_chan_rx,
650 uart_dma->rx_phy_addr, uart_dma->rb_size, 1,
651 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
652
653 if (!desc) {
654 dev_err(port->dev, "get rx dma descriptor failed!\n");
655 return -EINVAL;
656 }
657
658 dev_dbg(port->dev, "RX: prepare for the DMA.\n");
659 uart_dma->rx_cookie = dmaengine_submit(desc);
660 dma_async_issue_pending(uart_dma->dma_chan_rx);
661
662 uart_dma->rx_dma_used = 1;
663 if (uart_dma->use_timer == 1) {
664 hrtimer_start(&sw_uport->rx_hrtimer,
665 ns_to_ktime(uart_dma->rx_timeout), HRTIMER_MODE_REL);
666 }
667 return 1;
668 }
669
sw_uart_update_rb_addr(struct sw_uart_port * sw_uport)670 static void sw_uart_update_rb_addr(struct sw_uart_port *sw_uport)
671 {
672 struct sw_uart_dma *uart_dma = sw_uport->dma;
673 struct dma_tx_state state;
674 uart_dma->rx_size = 0;
675 if (uart_dma->rx_dma_used == 1) {
676 dmaengine_tx_status(uart_dma->dma_chan_rx, uart_dma->rx_cookie,
677 &state);
678 if ((uart_dma->rb_size - state.residue) !=
679 sw_uport->rx_last_pos) {
680 uart_dma->rb_head = uart_dma->rb_size - state.residue;
681 sw_uport->rx_last_pos = uart_dma->rb_head;
682 }
683 }
684 }
685
sw_uart_report_dma_rx(struct hrtimer * rx_hrtimer)686 static enum hrtimer_restart sw_uart_report_dma_rx(struct hrtimer *rx_hrtimer)
687 {
688 int count, flip = 0;
689 struct sw_uart_port *sw_uport = container_of(rx_hrtimer,
690 struct sw_uart_port, rx_hrtimer);
691 struct uart_port *port = &sw_uport->port;
692 struct sw_uart_dma *uart_dma = sw_uport->dma;
693
694 if (!uart_dma->rx_dma_used || !port->state->port.tty)
695 return HRTIMER_NORESTART;
696
697 sw_uart_update_rb_addr(sw_uport);
698 while (1) {
699 count = CIRC_CNT_TO_END(uart_dma->rb_head, uart_dma->rb_tail,
700 uart_dma->rb_size);
701 if (count <= 0)
702 break;
703 port->icount.rx += count;
704 flip = tty_insert_flip_string(&port->state->port,
705 uart_dma->rx_buffer + uart_dma->rb_tail, count);
706 tty_flip_buffer_push(&port->state->port);
707 uart_dma->rb_tail =
708 (uart_dma->rb_tail + count) & (uart_dma->rb_size - 1);
709 }
710
711 if (uart_dma->use_timer == 1) {
712 hrtimer_forward_now(&sw_uport->rx_hrtimer,
713 ns_to_ktime(uart_dma->rx_timeout));
714 }
715
716 return HRTIMER_RESTART;
717 }
718
719 #endif
720
sw_uart_irq(int irq,void * dev_id)721 static irqreturn_t sw_uart_irq(int irq, void *dev_id)
722 {
723 struct uart_port *port = dev_id;
724 struct sw_uart_port *sw_uport = UART_TO_SPORT(port);
725 unsigned int iir = 0, lsr = 0;
726 unsigned long flags;
727
728 spin_lock_irqsave(&port->lock, flags);
729
730 iir = serial_in(port, SUNXI_UART_IIR) & SUNXI_UART_IIR_IID_MASK;
731 lsr = serial_in(port, SUNXI_UART_LSR);
732 SERIAL_DBG("irq: iir %x lsr %x\n", iir, lsr);
733
734 if (iir == SUNXI_UART_IIR_IID_BUSBSY) {
735 sw_uart_handle_busy(sw_uport);
736 } else {
737 if (lsr & (SUNXI_UART_LSR_DR | SUNXI_UART_LSR_BI))
738 lsr = sw_uart_handle_rx(sw_uport, lsr);
739 /* has charto irq but no dr lsr? just read and ignore */
740 else if (iir & SUNXI_UART_IIR_IID_CHARTO)
741 serial_in(&sw_uport->port, SUNXI_UART_RBR);
742 sw_uart_modem_status(sw_uport);
743 #if IS_ENABLED(CONFIG_SW_UART_PTIME_MODE)
744 if (iir == SUNXI_UART_IIR_IID_THREMP)
745 #else
746 if (lsr & SUNXI_UART_LSR_THRE)
747 #endif
748 sw_uart_handle_tx(sw_uport);
749 }
750
751 spin_unlock_irqrestore(&port->lock, flags);
752
753 return IRQ_HANDLED;
754 }
755
756 /*
757 * uart buadrate and apb2 clock config selection
758 * We should select an apb2 clock as low as possible
759 * for lower power comsumpition, which can satisfy the
760 * different baudrates of different ttyS applications.
761 *
762 * the reference table as follows:
763 * pll6 600M
764 * apb2div 0 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5
765 * apbclk 24000000 30000000 31578947 33333333 35294117 37500000 40000000 42857142 46153846 50000000 54545454 60000000 66666666 75000000 85714285 100000000 120000000
766 * 115200 * * * * * * * * * * * * * * * * *
767 * 230400 * * * * * * * * * * * * * * * *
768 * 380400 * * * * * * * * * * * * * * *
769 * 460800 * * * * * * * * * * * *
770 * 921600 * * * * * * * *
771 * 1000000 * * * * * *
772 * 1500000 * * * * * *
773 * 1750000 * *
774 * 2000000 * * * *
775 * 2500000 * *
776 * 3000000 * * *
777 * 3250000 * *
778 * 3500000 *
779 * 4000000 *
780 */
781 struct baudset {
782 u32 baud;
783 u32 uartclk_min;
784 u32 uartclk_max;
785 };
786
sw_uart_check_baudset(struct uart_port * port,unsigned int baud)787 static inline int sw_uart_check_baudset(struct uart_port *port, unsigned int baud)
788 {
789 struct sw_uart_port *sw_uport = UART_TO_SPORT(port);
790 static struct baudset baud_set[] = {
791 {115200, 24000000, 120000000},
792 {230400, 30000000, 120000000},
793 {380400, 24000000, 120000000},
794 {460800, 30000000, 120000000},
795 {921600, 30000000, 120000000},
796 {1000000, 31000000, 120000000}, /* 31578947 */
797 {1500000, 24000000, 120000000},
798 {1750000, 54000000, 120000000}, /* 54545454 */
799 {2000000, 31000000, 120000000}, /* 31578947 */
800 {2500000, 40000000, 120000000}, /* 40000000 */
801 {3000000, 46000000, 120000000}, /* 46153846 */
802 {3250000, 54000000, 120000000}, /* 54545454 */
803 {3500000, 54000000, 120000000}, /* 54545454 */
804 {4000000, 66000000, 120000000}, /* 66666666 */
805 };
806 struct baudset *setsel;
807 int i;
808
809 if (baud < 115200) {
810 if (port->uartclk < 24000000) {
811 SERIAL_MSG("uart%d, uartclk(%d) too small for baud %d\n",
812 sw_uport->id, port->uartclk, baud);
813 return -1;
814 }
815 } else {
816 for (i = 0; i < ARRAY_SIZE(baud_set); i++) {
817 if (baud == baud_set[i].baud)
818 break;
819 }
820
821 if (i == ARRAY_SIZE(baud_set)) {
822 SERIAL_MSG("uart%d, baud %d beyond rance\n", sw_uport->id, baud);
823 return -1;
824 }
825
826 setsel = &baud_set[i];
827 if (port->uartclk < setsel->uartclk_min
828 || port->uartclk > setsel->uartclk_max) {
829 SERIAL_MSG("uart%d, select set %d, baud %d, uartclk %d beyond rance[%d, %d]\n",
830 sw_uport->id, i, baud, port->uartclk,
831 setsel->uartclk_min, setsel->uartclk_max);
832 return -1;
833 }
834 }
835 return 0;
836 }
837
838 #define BOTH_EMPTY (SUNXI_UART_LSR_TEMT | SUNXI_UART_LSR_THRE)
wait_for_xmitr(struct sw_uart_port * sw_uport)839 static inline void wait_for_xmitr(struct sw_uart_port *sw_uport)
840 {
841 unsigned int status, tmout = 10000;
842 #if IS_ENABLED(CONFIG_SW_UART_PTIME_MODE)
843 unsigned int offs = SUNXI_UART_USR;
844 unsigned char mask = SUNXI_UART_USR_TFNF;
845 #else
846 unsigned int offs = SUNXI_UART_LSR;
847 unsigned char mask = BOTH_EMPTY;
848 #endif
849
850 /* Wait up to 10ms for the character(s) to be sent. */
851 do {
852 status = serial_in(&sw_uport->port, offs);
853 if (serial_in(&sw_uport->port, SUNXI_UART_LSR) & SUNXI_UART_LSR_BI)
854 sw_uport->lsr_break_flag = SUNXI_UART_LSR_BI;
855 if (--tmout == 0)
856 break;
857 udelay(1);
858 } while ((status & mask) != mask);
859
860 /* CTS is unsupported by the 2-line UART, so ignore it. */
861 if (sw_uport->pdata->io_num == 2)
862 return;
863
864 /* Wait up to 500ms for flow control if necessary */
865 if (sw_uport->port.flags & UPF_CONS_FLOW) {
866 tmout = 500000;
867 for (tmout = 1000000; tmout; tmout--) {
868 unsigned int msr = serial_in(&sw_uport->port, SUNXI_UART_MSR);
869
870 sw_uport->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
871 if (msr & SUNXI_UART_MSR_CTS)
872 break;
873
874 udelay(1);
875 }
876 }
877 }
878
879 /* Enable or disable the RS485 support */
sw_uart_config_rs485(struct uart_port * port,struct serial_rs485 * rs485conf)880 static void sw_uart_config_rs485(struct uart_port *port, struct serial_rs485 *rs485conf)
881 {
882 struct sw_uart_port *sw_uport = UART_TO_SPORT(port);
883
884 sw_uport->rs485conf = *rs485conf;
885
886 sw_uport->mcr &= ~SUNXI_UART_MCR_MODE_MASK;
887 if (rs485conf->flags & SER_RS485_ENABLED) {
888 SERIAL_DBG("setting to rs485\n");
889 sw_uport->mcr |= SUNXI_UART_MCR_MODE_RS485;
890
891 /*
892 * In NMM mode and no 9th bit(default RS485 mode), uart receive
893 * all the bytes into FIFO before receveing an address byte
894 */
895 sw_uport->rs485 |= SUNXI_UART_RS485_RXBFA;
896 } else {
897 SERIAL_DBG("setting to uart\n");
898 sw_uport->mcr |= SUNXI_UART_MCR_MODE_UART;
899 sw_uport->rs485 = 0;
900 }
901
902 serial_out(port, sw_uport->mcr, SUNXI_UART_MCR);
903 serial_out(port, sw_uport->rs485, SUNXI_UART_RS485);
904 }
905
sw_uart_tx_empty(struct uart_port * port)906 static unsigned int sw_uart_tx_empty(struct uart_port *port)
907 {
908 struct sw_uart_port *sw_uport = UART_TO_SPORT(port);
909 unsigned long flags = 0;
910 unsigned int ret = 0;
911
912 spin_lock_irqsave(&sw_uport->port.lock, flags);
913 ret = (serial_in(port, SUNXI_UART_USR) & SUNXI_UART_USR_TFE) ? TIOCSER_TEMT : 0;
914 spin_unlock_irqrestore(&sw_uport->port.lock, flags);
915 return ret;
916 }
917
sw_uart_set_mctrl(struct uart_port * port,unsigned int mctrl)918 static void sw_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
919 {
920 struct sw_uart_port *sw_uport = UART_TO_SPORT(port);
921 unsigned int mcr = 0;
922
923 if (mctrl & TIOCM_RTS)
924 mcr |= SUNXI_UART_MCR_RTS;
925 if (mctrl & TIOCM_DTR)
926 mcr |= SUNXI_UART_MCR_DTR;
927 if (mctrl & TIOCM_LOOP)
928 mcr |= SUNXI_UART_MCR_LOOP;
929 sw_uport->mcr &= ~(SUNXI_UART_MCR_RTS|SUNXI_UART_MCR_DTR|SUNXI_UART_MCR_LOOP);
930 sw_uport->mcr |= mcr;
931 SERIAL_DBG("set mcr %x\n", mcr);
932 serial_out(port, sw_uport->mcr, SUNXI_UART_MCR);
933 }
934
sw_uart_get_mctrl(struct uart_port * port)935 static unsigned int sw_uart_get_mctrl(struct uart_port *port)
936 {
937 struct sw_uart_port *sw_uport = UART_TO_SPORT(port);
938 unsigned int msr;
939 unsigned int ret = 0;
940
941 msr = sw_uart_modem_status(sw_uport);
942 if (msr & SUNXI_UART_MSR_DCD)
943 ret |= TIOCM_CAR;
944 if (msr & SUNXI_UART_MSR_RI)
945 ret |= TIOCM_RNG;
946 if (msr & SUNXI_UART_MSR_DSR)
947 ret |= TIOCM_DSR;
948 if (msr & SUNXI_UART_MSR_CTS)
949 ret |= TIOCM_CTS;
950 SERIAL_DBG("get msr %x\n", msr);
951 return ret;
952 }
953
sw_uart_stop_rx(struct uart_port * port)954 static void sw_uart_stop_rx(struct uart_port *port)
955 {
956 struct sw_uart_port *sw_uport = UART_TO_SPORT(port);
957
958 #if IS_ENABLED(CONFIG_AW_SERIAL_DMA)
959 struct sw_uart_dma *uart_dma = sw_uport->dma;
960 if (uart_dma->use_dma & RX_DMA) {
961 sw_uart_stop_dma_rx(sw_uport);
962 }
963 #endif
964 if (sw_uport->ier & SUNXI_UART_IER_RLSI) {
965 sw_uport->ier &= ~SUNXI_UART_IER_RLSI;
966 SERIAL_DBG("stop rx, ier %x\n", sw_uport->ier);
967 sw_uport->port.read_status_mask &= ~SUNXI_UART_LSR_DR;
968 serial_out(port, sw_uport->ier, SUNXI_UART_IER);
969 }
970 }
971
sw_uart_enable_ms(struct uart_port * port)972 static void sw_uart_enable_ms(struct uart_port *port)
973 {
974 struct sw_uart_port *sw_uport = UART_TO_SPORT(port);
975
976 if (!(sw_uport->ier & SUNXI_UART_IER_MSI)) {
977 sw_uport->ier |= SUNXI_UART_IER_MSI;
978 SERIAL_DBG("en msi, ier %x\n", sw_uport->ier);
979 serial_out(port, sw_uport->ier, SUNXI_UART_IER);
980 }
981 }
982
sw_uart_break_ctl(struct uart_port * port,int break_state)983 static void sw_uart_break_ctl(struct uart_port *port, int break_state)
984 {
985 struct sw_uart_port *sw_uport = UART_TO_SPORT(port);
986 unsigned long flags;
987
988 spin_lock_irqsave(&port->lock, flags);
989 if (break_state == -1)
990 sw_uport->lcr |= SUNXI_UART_LCR_SBC;
991 else
992 sw_uport->lcr &= ~SUNXI_UART_LCR_SBC;
993 serial_out(port, sw_uport->lcr, SUNXI_UART_LCR);
994 spin_unlock_irqrestore(&port->lock, flags);
995 }
996
sw_uart_startup(struct uart_port * port)997 static int sw_uart_startup(struct uart_port *port)
998 {
999 struct sw_uart_port *sw_uport = UART_TO_SPORT(port);
1000 int ret;
1001
1002 SERIAL_DBG("start up ...\n");
1003
1004 ret = request_irq(port->irq, sw_uart_irq, 0, sw_uport->name, port);
1005 if (unlikely(ret)) {
1006 SERIAL_MSG("uart%d cannot get irq %d\n", sw_uport->id, port->irq);
1007 return ret;
1008 }
1009
1010 sw_uport->msr_saved_flags = 0;
1011 /*
1012 * PTIME mode to select the THRE trigger condition:
1013 * if PTIME=1(IER[7]), the THRE interrupt will be generated when the
1014 * the water level of the TX FIFO is lower than the threshold of the
1015 * TX FIFO. and if PTIME=0, the THRE interrupt will be generated when
1016 * the TX FIFO is empty.
1017 * In addition, when PTIME=1, the THRE bit of the LSR register will not
1018 * be set when the THRE interrupt is generated. You must check the
1019 * interrupt id of the IIR register to decide whether some data need to
1020 * send.
1021 */
1022
1023 #if IS_ENABLED(CONFIG_AW_SERIAL_DMA)
1024 if (sw_uport->dma->use_dma & TX_DMA) {
1025 if (sw_uport->port.state->xmit.buf !=
1026 sw_uport->dma->tx_buffer){
1027 free_page((unsigned long)sw_uport->port.state->xmit.buf);
1028 sw_uport->port.state->xmit.buf =
1029 sw_uport->dma->tx_buffer;
1030 }
1031 } else
1032 #endif
1033 {
1034 sw_uport->ier = 0;
1035 serial_out(port, sw_uport->ier, SUNXI_UART_IER);
1036 }
1037
1038 sw_uart_config_rs485(port, &sw_uport->rs485conf);
1039
1040 return 0;
1041 }
1042
sw_uart_shutdown(struct uart_port * port)1043 static void sw_uart_shutdown(struct uart_port *port)
1044 {
1045 struct sw_uart_port *sw_uport = UART_TO_SPORT(port);
1046
1047 SERIAL_DBG("shut down ...\n");
1048 #if IS_ENABLED(CONFIG_AW_SERIAL_DMA)
1049 if (sw_uport->dma->use_dma & TX_DMA)
1050 sw_uport->port.state->xmit.buf = NULL;
1051 #endif
1052 sw_uport->ier = 0;
1053 sw_uport->lcr = 0;
1054 sw_uport->mcr = 0;
1055 sw_uport->fcr = 0;
1056 serial_out(port, sw_uport->ier, SUNXI_UART_IER);
1057 free_irq(port->irq, port);
1058 }
1059
sw_uart_flush_buffer(struct uart_port * port)1060 static void sw_uart_flush_buffer(struct uart_port *port)
1061 {
1062 struct sw_uart_port *sw_uport = UART_TO_SPORT(port);
1063
1064 SERIAL_DBG("flush buffer...\n");
1065 serial_out(port, sw_uport->fcr|SUNXI_UART_FCR_TXFIFO_RST, SUNXI_UART_FCR);
1066 }
1067
sw_uart_filter_lsr_err(struct uart_port * port)1068 static void sw_uart_filter_lsr_err(struct uart_port *port)
1069 {
1070 struct sw_uart_port *sw_uport = UART_TO_SPORT(port);
1071 static bool uart_lb[SUNXI_UART_NUM] = {false};
1072 /*note:For some memory fifo, first receive data,LSR will error make data abnormal.
1073 *UART config loopback mode self-receiving data can filter this exception.
1074 *Only need to config loopback mode once.
1075 */
1076 if (sw_uport->port.line != 0 && !uart_lb[sw_uport->port.line]) {
1077 uart_lb[sw_uport->port.line] = true;
1078 /* set loopback mode*/
1079 serial_out(port, sw_uport->mcr | SUNXI_UART_MCR_LOOP,
1080 SUNXI_UART_MCR);
1081 serial_out(&sw_uport->port, 0xff, SUNXI_UART_THR);//write 0xff
1082 sw_uart_start_tx(port);
1083 serial_in(&sw_uport->port, SUNXI_UART_RBR);//read 0xff
1084 sw_uart_stop_tx(port);
1085 /* disabled loopback mode*/
1086 serial_out(port, sw_uport->mcr, SUNXI_UART_MCR);
1087 }
1088 }
1089
sw_uart_set_termios(struct uart_port * port,struct ktermios * termios,struct ktermios * old)1090 static void sw_uart_set_termios(struct uart_port *port, struct ktermios *termios,
1091 struct ktermios *old)
1092 {
1093 struct sw_uart_port *sw_uport = UART_TO_SPORT(port);
1094 unsigned long flags;
1095 unsigned int baud, quot, lcr = 0, dll, dlh;
1096
1097 #if IS_ENABLED(CONFIG_AW_SERIAL_DMA)
1098 /* stop dma tx, which might make the uart be busy while some
1099 * registers are set
1100 */
1101 if (sw_uport->dma->tx_dma_used)
1102 sw_uart_stop_dma_tx(sw_uport);
1103 #endif
1104 SERIAL_DBG("set termios ...\n");
1105 switch (termios->c_cflag & CSIZE) {
1106 case CS5:
1107 lcr |= SUNXI_UART_LCR_WLEN5;
1108 break;
1109 case CS6:
1110 lcr |= SUNXI_UART_LCR_WLEN6;
1111 break;
1112 case CS7:
1113 lcr |= SUNXI_UART_LCR_WLEN7;
1114 break;
1115 case CS8:
1116 default:
1117 lcr |= SUNXI_UART_LCR_WLEN8;
1118 break;
1119 }
1120
1121 if (termios->c_cflag & CSTOPB)
1122 lcr |= SUNXI_UART_LCR_STOP;
1123 if (termios->c_cflag & PARENB)
1124 lcr |= SUNXI_UART_LCR_PARITY;
1125 if (!(termios->c_cflag & PARODD))
1126 lcr |= SUNXI_UART_LCR_EPAR;
1127
1128 /* set buadrate */
1129 baud = uart_get_baud_rate(port, termios, old,
1130 port->uartclk / 16 / 0xffff,
1131 port->uartclk / 16);
1132 sw_uart_check_baudset(port, baud);
1133 quot = uart_get_divisor(port, baud);
1134 dll = quot & 0xff;
1135 dlh = quot >> 8;
1136 SERIAL_DBG("set baudrate %d, quot %d\n", baud, quot);
1137
1138 spin_lock_irqsave(&port->lock, flags);
1139 uart_update_timeout(port, termios->c_cflag, baud);
1140
1141 /* Update the per-port timeout. */
1142 port->read_status_mask = SUNXI_UART_LSR_OE | SUNXI_UART_LSR_THRE | SUNXI_UART_LSR_DR;
1143 if (termios->c_iflag & INPCK)
1144 port->read_status_mask |= SUNXI_UART_LSR_FE | SUNXI_UART_LSR_PE;
1145 if (termios->c_iflag & (BRKINT | PARMRK))
1146 port->read_status_mask |= SUNXI_UART_LSR_BI;
1147
1148 /* Characteres to ignore */
1149 port->ignore_status_mask = 0;
1150 if (termios->c_iflag & IGNPAR)
1151 port->ignore_status_mask |= SUNXI_UART_LSR_PE | SUNXI_UART_LSR_FE;
1152 if (termios->c_iflag & IGNBRK) {
1153 port->ignore_status_mask |= SUNXI_UART_LSR_BI;
1154 /*
1155 * If we're ignoring parity and break indicators,
1156 * ignore overruns too (for real raw support).
1157 */
1158 if (termios->c_iflag & IGNPAR)
1159 port->ignore_status_mask |= SUNXI_UART_LSR_OE;
1160 }
1161
1162 /*
1163 * ignore all characters if CREAD is not set
1164 */
1165 if ((termios->c_cflag & CREAD) == 0)
1166 port->ignore_status_mask |= SUNXI_UART_LSR_DR;
1167
1168 /*
1169 * reset controller
1170 */
1171 sw_uart_reset(sw_uport);
1172
1173 if (baud <= 9600)
1174 sw_uport->fcr = SUNXI_UART_FCR_RXTRG_1CH
1175 | SUNXI_UART_FCR_TXTRG_1_2
1176 | SUNXI_UART_FCR_FIFO_EN;
1177 else
1178 sw_uport->fcr = SUNXI_UART_FCR_RXTRG_1_2
1179 | SUNXI_UART_FCR_TXTRG_1_2
1180 | SUNXI_UART_FCR_FIFO_EN;
1181
1182 serial_out(port, sw_uport->fcr, SUNXI_UART_FCR);
1183
1184
1185 sw_uport->lcr = lcr;
1186 sw_uport->dll = dll;
1187 sw_uport->dlh = dlh;
1188 sw_uart_force_lcr(sw_uport, 50);
1189
1190 /* clear rxfifo after set lcr & baud to discard redundant data */
1191 serial_out(port, sw_uport->fcr|SUNXI_UART_FCR_RXFIFO_RST, SUNXI_UART_FCR);
1192 port->ops->set_mctrl(port, port->mctrl);
1193
1194 sw_uport->ier = SUNXI_UART_IER_RLSI | SUNXI_UART_IER_RDI;
1195 #if IS_ENABLED(CONFIG_SW_UART_PTIME_MODE)
1196 sw_uport->ier |= SUNXI_UART_IER_PTIME;
1197 #endif
1198 #if IS_ENABLED(CONFIG_AW_SERIAL_DMA)
1199 if (sw_uport->dma->use_dma & TX_DMA)
1200 serial_out(port, SUNXI_UART_HALT_PTE | serial_in(port, SUNXI_UART_HALT), SUNXI_UART_HALT);
1201
1202 if (sw_uport->dma->use_dma & RX_DMA) {
1203 /* disable the receive data interrupt */
1204 sw_uport->ier &= ~SUNXI_UART_IER_RDI;
1205 sw_uart_start_dma_rx(sw_uport);
1206 }
1207 #endif
1208 /* flow control */
1209 sw_uport->mcr &= ~SUNXI_UART_MCR_AFE;
1210 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
1211 if (termios->c_cflag & CRTSCTS) {
1212 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
1213 sw_uport->mcr |= SUNXI_UART_MCR_AFE;
1214 }
1215 serial_out(port, sw_uport->mcr, SUNXI_UART_MCR);
1216
1217 /*
1218 * CTS flow control flag and modem status interrupts
1219 */
1220 sw_uport->ier &= ~SUNXI_UART_IER_MSI;
1221 if (UART_ENABLE_MS(port, termios->c_cflag))
1222 sw_uport->ier |= SUNXI_UART_IER_MSI;
1223 serial_out(port, sw_uport->ier, SUNXI_UART_IER);
1224 /* Must save the current config for the resume of console(no tty user). */
1225 if (sw_is_console_port(port))
1226 port->cons->cflag = termios->c_cflag;
1227
1228 spin_unlock_irqrestore(&port->lock, flags);
1229
1230 /* Don't rewrite B0 */
1231 if (tty_termios_baud_rate(termios))
1232 tty_termios_encode_baud_rate(termios, baud, baud);
1233 SERIAL_DBG("termios lcr 0x%x fcr 0x%x mcr 0x%x dll 0x%x dlh 0x%x\n",
1234 sw_uport->lcr, sw_uport->fcr, sw_uport->mcr,
1235 sw_uport->dll, sw_uport->dlh);
1236
1237 sw_uart_filter_lsr_err(port);
1238 }
1239
sw_uart_type(struct uart_port * port)1240 static const char *sw_uart_type(struct uart_port *port)
1241 {
1242 return "SUNXI";
1243 }
1244
sw_uart_select_gpio_state(struct pinctrl * pctrl,char * name,u32 no)1245 static int sw_uart_select_gpio_state(struct pinctrl *pctrl, char *name, u32 no)
1246 {
1247 int ret = 0;
1248 struct pinctrl_state *pctrl_state = NULL;
1249
1250 pctrl_state = pinctrl_lookup_state(pctrl, name);
1251 if (IS_ERR(pctrl_state)) {
1252 SERIAL_MSG("UART%d pinctrl_lookup_state(%s) failed! return %p \n", no, name, pctrl_state);
1253 return -1;
1254 }
1255
1256 ret = pinctrl_select_state(pctrl, pctrl_state);
1257 if (ret < 0)
1258 SERIAL_MSG("UART%d pinctrl_select_state(%s) failed! return %d \n", no, name, ret);
1259
1260 return ret;
1261 }
1262
sw_uart_request_gpio(struct sw_uart_port * sw_uport)1263 static int sw_uart_request_gpio(struct sw_uart_port *sw_uport)
1264 {
1265 if (sw_uport->card_print)
1266 return 0;
1267
1268 sw_uport->pctrl = devm_pinctrl_get(sw_uport->port.dev);
1269
1270 if (IS_ERR_OR_NULL(sw_uport->pctrl)) {
1271 SERIAL_MSG("UART%d devm_pinctrl_get() failed! return %ld\n", sw_uport->id, PTR_ERR(sw_uport->pctrl));
1272 return -1;
1273 }
1274
1275 return sw_uart_select_gpio_state(sw_uport->pctrl, PINCTRL_STATE_DEFAULT, sw_uport->id);
1276 }
1277
sw_uart_release_gpio(struct sw_uart_port * sw_uport)1278 static void sw_uart_release_gpio(struct sw_uart_port *sw_uport)
1279 {
1280 if (sw_uport->card_print)
1281 return;
1282
1283 devm_pinctrl_put(sw_uport->pctrl);
1284 sw_uport->pctrl = NULL;
1285 }
1286
sw_uart_release_port(struct uart_port * port)1287 static void sw_uart_release_port(struct uart_port *port)
1288 {
1289 struct sw_uart_port *sw_uport = UART_TO_SPORT(port);
1290 struct platform_device *pdev;
1291 struct resource *mem_res;
1292
1293 SERIAL_DBG("release port(iounmap & release io)\n");
1294
1295 pdev = to_platform_device(port->dev);
1296 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1297 if (mem_res == NULL) {
1298 SERIAL_MSG("uart%d, get MEM resource failed\n", sw_uport->id);
1299 return;
1300 }
1301
1302 /* release memory resource */
1303 release_mem_region(mem_res->start, resource_size(mem_res));
1304 iounmap(port->membase);
1305 port->membase = NULL;
1306
1307 /* release io resource */
1308 sw_uart_release_gpio(sw_uport);
1309 }
1310
sw_uart_request_port(struct uart_port * port)1311 static int sw_uart_request_port(struct uart_port *port)
1312 {
1313 struct sw_uart_port *sw_uport = UART_TO_SPORT(port);
1314 struct platform_device *pdev;
1315 struct resource *mem_res;
1316 int ret;
1317
1318 SERIAL_DBG("request port(ioremap & request io) %d\n", sw_uport->id);
1319
1320 pdev = to_platform_device(port->dev);
1321 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1322 if (mem_res == NULL) {
1323 SERIAL_MSG("uart%d, get MEM resource failed\n", sw_uport->id);
1324 ret = -ENXIO;
1325 }
1326
1327 /* request memory resource */
1328 if (!request_mem_region(mem_res->start, resource_size(mem_res), SUNXI_UART_DEV_NAME)) {
1329 SERIAL_MSG("uart%d, request mem region failed\n", sw_uport->id);
1330 return -EBUSY;
1331 }
1332
1333 port->membase = ioremap(mem_res->start, resource_size(mem_res));
1334 if (!port->membase) {
1335 SERIAL_MSG("uart%d, ioremap failed\n", sw_uport->id);
1336 release_mem_region(mem_res->start, resource_size(mem_res));
1337 return -EBUSY;
1338 }
1339
1340 /* request io resource */
1341 ret = sw_uart_request_gpio(sw_uport);
1342 if (ret < 0) {
1343 release_mem_region(mem_res->start, resource_size(mem_res));
1344 return ret;
1345 }
1346
1347 return 0;
1348 }
1349
sw_uart_config_port(struct uart_port * port,int flags)1350 static void sw_uart_config_port(struct uart_port *port, int flags)
1351 {
1352 int ret;
1353
1354 if (flags & UART_CONFIG_TYPE) {
1355 port->type = PORT_SUNXI;
1356 ret = sw_uart_request_port(port);
1357 if (ret)
1358 return;
1359 }
1360 }
1361
sw_uart_verify_port(struct uart_port * port,struct serial_struct * ser)1362 static int sw_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
1363 {
1364 if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_SUNXI))
1365 return -EINVAL;
1366 if (unlikely(port->irq != ser->irq))
1367 return -EINVAL;
1368 return 0;
1369 }
1370
sw_uart_ioctl(struct uart_port * port,unsigned int cmd,unsigned long arg)1371 static int sw_uart_ioctl(struct uart_port *port, unsigned int cmd,
1372 unsigned long arg)
1373 {
1374 struct serial_rs485 rs485conf;
1375 unsigned long flags = 0;
1376
1377 switch (cmd) {
1378 case TIOCSRS485:
1379 if (copy_from_user(&rs485conf, (struct serial_rs485 *)arg,
1380 sizeof(rs485conf)))
1381 return -EFAULT;
1382
1383 spin_lock_irqsave(&port->lock, flags);
1384 sw_uart_config_rs485(port, &rs485conf);
1385 spin_unlock_irqrestore(&port->lock, flags);
1386 break;
1387
1388 case TIOCGRS485:
1389 if (copy_to_user((struct serial_rs485 *) arg,
1390 &(UART_TO_SPORT(port)->rs485conf),
1391 sizeof(rs485conf)))
1392 return -EFAULT;
1393 break;
1394
1395 default:
1396 return -ENOIOCTLCMD;
1397 }
1398
1399 return 0;
1400 }
1401
sw_uart_pm(struct uart_port * port,unsigned int state,unsigned int oldstate)1402 static void sw_uart_pm(struct uart_port *port, unsigned int state,
1403 unsigned int oldstate)
1404 {
1405 #if IS_ENABLED(CONFIG_AW_IC_BOARD)
1406 int ret;
1407 struct sw_uart_port *sw_uport = UART_TO_SPORT(port);
1408
1409 SERIAL_DBG("PM state %d -> %d\n", oldstate, state);
1410
1411 switch (state) {
1412 case UART_PM_STATE_ON: /* Power up */
1413 ret = clk_prepare_enable(sw_uport->mclk);
1414 if (ret) {
1415 SERIAL_MSG("uart%d release reset failed\n", sw_uport->id);
1416 }
1417 break;
1418 case UART_PM_STATE_OFF: /* Power down */
1419 clk_disable_unprepare(sw_uport->mclk);
1420 break;
1421 default:
1422 SERIAL_MSG("uart%d, Unknown PM state %d\n", sw_uport->id, state);
1423 }
1424 #endif
1425 }
1426
1427 #if IS_ENABLED(CONFIG_CONSOLE_POLL)
1428 /*
1429 * Console polling routines for writing and reading from the uart while
1430 * in an interrupt or debug context.
1431 */
1432
sw_get_poll_char(struct uart_port * port)1433 static int sw_get_poll_char(struct uart_port *port)
1434 {
1435 struct sw_uart_port *sw_uport = UART_TO_SPORT(port);
1436 unsigned int lsr = serial_in(port, SUNXI_UART_LSR);
1437
1438 if (!(lsr & SUNXI_UART_LSR_DR)) {
1439 return NO_POLL_CHAR;
1440 }
1441
1442 return serial_in(port, SUNXI_UART_RBR);
1443 }
1444
1445
sw_put_poll_char(struct uart_port * port,unsigned char c)1446 static void sw_put_poll_char(struct uart_port *port,
1447 unsigned char c)
1448 {
1449 unsigned int ier;
1450 struct sw_uart_port *sw_uport = UART_TO_SPORT(port);
1451
1452 /*
1453 * First save the IER then disable the interrupts.
1454 */
1455 ier = serial_in(port, SUNXI_UART_IER);
1456
1457 serial_out(port, 0, SUNXI_UART_IER);
1458 wait_for_xmitr(sw_uport);
1459
1460 serial_out(port, c, SUNXI_UART_THR);
1461 if (c == 10) {
1462 wait_for_xmitr(sw_uport);
1463 serial_out(port, 13, SUNXI_UART_THR);
1464 }
1465 /*
1466 * Finally, wait for transmitter to become empty
1467 * and restore the IER
1468 */
1469 wait_for_xmitr(sw_uport);
1470 serial_out(port, ier, SUNXI_UART_IER);
1471 }
1472
1473 #endif /* CONFIG_CONSOLE_POLL */
1474
1475 /* Disable receive interrupts to throttle receive data, which could
1476 * avoid receive data overrun*/
sw_uart_throttle(struct uart_port * port)1477 static void sw_uart_throttle(struct uart_port *port)
1478 {
1479 struct sw_uart_port *sw_uport = UART_TO_SPORT(port);
1480 unsigned long flags;
1481
1482 spin_lock_irqsave(&port->lock, flags);
1483 sw_uport->ier &= ~(SUNXI_UART_IER_RLSI | SUNXI_UART_IER_RDI);
1484 serial_out(port, sw_uport->ier, SUNXI_UART_IER);
1485 sw_uport->throttled = true;
1486 spin_unlock_irqrestore(&port->lock, flags);
1487 }
1488
sw_uart_unthrottle(struct uart_port * port)1489 static void sw_uart_unthrottle(struct uart_port *port)
1490 {
1491 struct sw_uart_port *sw_uport = UART_TO_SPORT(port);
1492 unsigned long flags;
1493
1494 spin_lock_irqsave(&port->lock, flags);
1495 sw_uport->ier |= SUNXI_UART_IER_RLSI | SUNXI_UART_IER_RDI;
1496 serial_out(port, sw_uport->ier, SUNXI_UART_IER);
1497 sw_uport->throttled = false;
1498 spin_unlock_irqrestore(&port->lock, flags);
1499 }
1500
1501 static struct uart_ops sw_uart_ops = {
1502 .tx_empty = sw_uart_tx_empty,
1503 .set_mctrl = sw_uart_set_mctrl,
1504 .get_mctrl = sw_uart_get_mctrl,
1505 .stop_tx = sw_uart_stop_tx,
1506 .start_tx = sw_uart_start_tx,
1507 .stop_rx = sw_uart_stop_rx,
1508 .enable_ms = sw_uart_enable_ms,
1509 .break_ctl = sw_uart_break_ctl,
1510 .startup = sw_uart_startup,
1511 .shutdown = sw_uart_shutdown,
1512 .flush_buffer = sw_uart_flush_buffer,
1513 .set_termios = sw_uart_set_termios,
1514 .type = sw_uart_type,
1515 .release_port = sw_uart_release_port,
1516 .request_port = sw_uart_request_port,
1517 .config_port = sw_uart_config_port,
1518 .verify_port = sw_uart_verify_port,
1519 .ioctl = sw_uart_ioctl,
1520 .pm = sw_uart_pm,
1521 #if IS_ENABLED(CONFIG_CONSOLE_POLL)
1522 .poll_get_char = sw_get_poll_char,
1523 .poll_put_char = sw_put_poll_char,
1524 #endif
1525 .throttle = sw_uart_throttle,
1526 .unthrottle = sw_uart_unthrottle,
1527 };
1528
sw_uart_regulator_request(struct sw_uart_port * sw_uport,struct sw_uart_pdata * pdata,struct device * dev)1529 static int sw_uart_regulator_request(struct sw_uart_port *sw_uport, struct sw_uart_pdata *pdata,
1530 struct device *dev)
1531 {
1532 struct regulator *regu = NULL;
1533
1534 /* Consider "n***" as nocare. Support "none", "nocare", "null", "" etc. */
1535 if ((pdata->regulator_id[0] == 'n') || (pdata->regulator_id[0] == 0)) {
1536 /* if regulator_id not exist, use dt way to get regulator */
1537 regu = regulator_get(dev, "uart");
1538 if (IS_ERR(regu)) {
1539 dev_warn(dev, "get regulator by dt way failed!\n");
1540 return 0;
1541 }
1542 pdata->regulator = regu;
1543 return 0;
1544 }
1545
1546 regu = regulator_get(NULL, pdata->regulator_id);
1547 if (IS_ERR(regu)) {
1548 SERIAL_MSG("get regulator %s failed!\n", pdata->regulator_id);
1549 return -1;
1550 }
1551 pdata->regulator = regu;
1552 return 0;
1553 }
1554
sw_uart_regulator_release(struct sw_uart_pdata * pdata)1555 static void sw_uart_regulator_release(struct sw_uart_pdata *pdata)
1556 {
1557 if (pdata->regulator == NULL)
1558 return;
1559
1560 regulator_put(pdata->regulator);
1561 pdata->regulator = NULL;
1562 }
1563
sw_uart_regulator_enable(struct sw_uart_pdata * pdata)1564 static int sw_uart_regulator_enable(struct sw_uart_pdata *pdata)
1565 {
1566 if (pdata->regulator == NULL)
1567 return 0;
1568
1569 if (regulator_enable(pdata->regulator) != 0)
1570 return -1;
1571
1572 return 0;
1573 }
1574
sw_uart_regulator_disable(struct sw_uart_pdata * pdata)1575 static int sw_uart_regulator_disable(struct sw_uart_pdata *pdata)
1576 {
1577 if (pdata->regulator == NULL)
1578 return 0;
1579
1580 if (regulator_disable(pdata->regulator) != 0)
1581 return -1;
1582
1583 return 0;
1584 }
1585
1586 static struct sw_uart_port sw_uart_ports[SUNXI_UART_NUM];
1587 static struct sw_uart_pdata sw_uport_pdata[SUNXI_UART_NUM];
1588
sunxi_uart_dev_info_show(struct device * dev,struct device_attribute * attr,char * buf)1589 static ssize_t sunxi_uart_dev_info_show(struct device *dev,
1590 struct device_attribute *attr, char *buf)
1591 {
1592 struct uart_port *port = dev_get_drvdata(dev);
1593 struct sw_uart_port *sw_uport = UART_TO_SPORT(port);
1594 struct sw_uart_pdata *pdata = (struct sw_uart_pdata *)dev->platform_data;
1595
1596 return snprintf(buf, PAGE_SIZE,
1597 "id = %u \n"
1598 "name = %s \n"
1599 "irq = %u \n"
1600 "io_num = %u \n"
1601 "port->mapbase = %pa \n"
1602 "port->membase = 0x%p \n"
1603 "port->iobase = 0x%08lx \n"
1604 "port->fifosize = %d\n"
1605 "pdata->regulator = 0x%p \n"
1606 "pdata->regulator_id = %s \n",
1607 sw_uport->id, sw_uport->name, port->irq,
1608 sw_uport->pdata->io_num,
1609 &port->mapbase, port->membase, port->iobase,
1610 port->fifosize, pdata->regulator, pdata->regulator_id);
1611 }
1612
1613 static struct device_attribute sunxi_uart_dev_info_attr =
1614 __ATTR(dev_info, S_IRUGO, sunxi_uart_dev_info_show, NULL);
1615
sunxi_uart_status_show(struct device * dev,struct device_attribute * attr,char * buf)1616 static ssize_t sunxi_uart_status_show(struct device *dev,
1617 struct device_attribute *attr, char *buf)
1618 {
1619 struct uart_port *port = dev_get_drvdata(dev);
1620
1621 return snprintf(buf, PAGE_SIZE,
1622 "uartclk = %d \n"
1623 "The Uart controller register[Base: 0x%p]: \n"
1624 "[RTX] 0x%02x = 0x%08x, [IER] 0x%02x = 0x%08x, [FCR] 0x%02x = 0x%08x \n"
1625 "[LCR] 0x%02x = 0x%08x, [MCR] 0x%02x = 0x%08x, [LSR] 0x%02x = 0x%08x \n"
1626 "[MSR] 0x%02x = 0x%08x, [SCH] 0x%02x = 0x%08x, [USR] 0x%02x = 0x%08x \n"
1627 "[TFL] 0x%02x = 0x%08x, [RFL] 0x%02x = 0x%08x, [HALT] 0x%02x = 0x%08x \n",
1628 port->uartclk, port->membase,
1629 SUNXI_UART_RBR, readl(port->membase + SUNXI_UART_RBR),
1630 SUNXI_UART_IER, readl(port->membase + SUNXI_UART_IER),
1631 SUNXI_UART_FCR, readl(port->membase + SUNXI_UART_FCR),
1632 SUNXI_UART_LCR, readl(port->membase + SUNXI_UART_LCR),
1633 SUNXI_UART_MCR, readl(port->membase + SUNXI_UART_MCR),
1634 SUNXI_UART_LSR, readl(port->membase + SUNXI_UART_LSR),
1635 SUNXI_UART_MSR, readl(port->membase + SUNXI_UART_MSR),
1636 SUNXI_UART_SCH, readl(port->membase + SUNXI_UART_SCH),
1637 SUNXI_UART_USR, readl(port->membase + SUNXI_UART_USR),
1638 SUNXI_UART_TFL, readl(port->membase + SUNXI_UART_TFL),
1639 SUNXI_UART_RFL, readl(port->membase + SUNXI_UART_RFL),
1640 SUNXI_UART_HALT, readl(port->membase + SUNXI_UART_HALT));
1641 }
1642 static struct device_attribute sunxi_uart_status_attr =
1643 __ATTR(status, S_IRUGO, sunxi_uart_status_show, NULL);
1644
sunxi_uart_loopback_show(struct device * dev,struct device_attribute * attr,char * buf)1645 static ssize_t sunxi_uart_loopback_show(struct device *dev,
1646 struct device_attribute *attr, char *buf)
1647 {
1648 int mcr = 0;
1649 struct uart_port *port = dev_get_drvdata(dev);
1650
1651 mcr = readl(port->membase + SUNXI_UART_MCR);
1652 return snprintf(buf, PAGE_SIZE,
1653 "MCR: 0x%08x, Loopback: %d\n", mcr, mcr&SUNXI_UART_MCR_LOOP ? 1 : 0);
1654 }
1655
sunxi_uart_loopback_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1656 static ssize_t sunxi_uart_loopback_store(struct device *dev,
1657 struct device_attribute *attr,
1658 const char *buf, size_t count)
1659 {
1660 int mcr = 0;
1661 int enable = 0;
1662 struct uart_port *port = dev_get_drvdata(dev);
1663
1664 if (!strncmp(buf, "enable", 6))
1665 enable = 1;
1666
1667 pr_debug("Set loopback: %d \n", enable);
1668
1669 mcr = readl(port->membase + SUNXI_UART_MCR);
1670 if (enable)
1671 writel(mcr|SUNXI_UART_MCR_LOOP, port->membase + SUNXI_UART_MCR);
1672 else
1673 writel(mcr&(~SUNXI_UART_MCR_LOOP), port->membase + SUNXI_UART_MCR);
1674
1675 return count;
1676 }
1677 static struct device_attribute sunxi_uart_loopback_attr =
1678 __ATTR(loopback, S_IRUGO|S_IWUSR, sunxi_uart_loopback_show, sunxi_uart_loopback_store);
1679
sunxi_uart_ctrl_info_show(struct device * dev,struct device_attribute * attr,char * buf)1680 static ssize_t sunxi_uart_ctrl_info_show(struct device *dev,
1681 struct device_attribute *attr, char *buf)
1682 {
1683 struct uart_port *port = dev_get_drvdata(dev);
1684 struct sw_uart_port *sw_uport = UART_TO_SPORT(port);
1685 u32 dl = (u32)sw_uport->dlh << 8 | (u32)sw_uport->dll;
1686
1687 if (dl == 0)
1688 dl = 1000;
1689
1690 return snprintf(buf, PAGE_SIZE,
1691 " ier : 0x%02x\n"
1692 " lcr : 0x%02x\n"
1693 " mcr : 0x%02x\n"
1694 " fcr : 0x%02x\n"
1695 " dll : 0x%02x\n"
1696 " dlh : 0x%02x\n"
1697 " last baud : %d (dl = %d)\n\n"
1698 "TxRx Statistics:\n"
1699 " tx : %d\n"
1700 " rx : %d\n"
1701 " parity : %d\n"
1702 " frame : %d\n"
1703 " overrun: %d\n"
1704 " throttled: %d\n",
1705 sw_uport->ier, sw_uport->lcr, sw_uport->mcr,
1706 sw_uport->fcr, sw_uport->dll, sw_uport->dlh,
1707 (sw_uport->port.uartclk>>4)/dl, dl,
1708 sw_uport->port.icount.tx,
1709 sw_uport->port.icount.rx,
1710 sw_uport->port.icount.parity,
1711 sw_uport->port.icount.frame,
1712 sw_uport->port.icount.overrun,
1713 sw_uport->throttled);
1714 }
1715 static struct device_attribute sunxi_uart_ctrl_info_attr =
1716 __ATTR(ctrl_info, S_IRUGO, sunxi_uart_ctrl_info_show, NULL);
1717
sunxi_uart_sysfs(struct platform_device * _pdev)1718 static void sunxi_uart_sysfs(struct platform_device *_pdev)
1719 {
1720 device_create_file(&_pdev->dev, &sunxi_uart_dev_info_attr);
1721 device_create_file(&_pdev->dev, &sunxi_uart_status_attr);
1722 device_create_file(&_pdev->dev, &sunxi_uart_loopback_attr);
1723 device_create_file(&_pdev->dev, &sunxi_uart_ctrl_info_attr);
1724 }
1725
1726 #if IS_ENABLED(CONFIG_AW_SERIAL_CONSOLE)
sw_console_get_port(struct console * co)1727 static struct uart_port *sw_console_get_port(struct console *co)
1728 {
1729 struct uart_port *port = NULL;
1730 int i, used;
1731
1732 for (i = 0; i < SUNXI_UART_NUM; i++) {
1733 used = sw_uport_pdata[i].used;
1734 port = &sw_uart_ports[i].port;
1735 if ((used == 1) && (port->line == co->index)) {
1736 break;
1737 }
1738 }
1739 return port;
1740 }
1741
sw_console_putchar(struct uart_port * port,int c)1742 static void sw_console_putchar(struct uart_port *port, int c)
1743 {
1744 struct sw_uart_port *sw_uport = UART_TO_SPORT(port);
1745
1746 wait_for_xmitr(sw_uport);
1747 serial_out(port, c, SUNXI_UART_THR);
1748 }
1749
sw_console_write(struct console * co,const char * s,unsigned int count)1750 static void sw_console_write(struct console *co, const char *s,
1751 unsigned int count)
1752 {
1753 struct uart_port *port = NULL;
1754 struct sw_uart_port *sw_uport;
1755 unsigned long flags;
1756 unsigned int ier;
1757 int locked = 1;
1758
1759 BUG_ON(co->index < 0 || co->index >= SUNXI_UART_NUM);
1760
1761 port = sw_console_get_port(co);
1762 if (port == NULL)
1763 return;
1764 sw_uport = UART_TO_SPORT(port);
1765
1766 if (port->sysrq || oops_in_progress)
1767 locked = spin_trylock_irqsave(&port->lock, flags);
1768 else
1769 spin_lock_irqsave(&port->lock, flags);
1770
1771 ier = serial_in(port, SUNXI_UART_IER);
1772 serial_out(port, 0, SUNXI_UART_IER);
1773
1774 uart_console_write(port, s, count, sw_console_putchar);
1775 wait_for_xmitr(sw_uport);
1776 serial_out(port, ier, SUNXI_UART_IER);
1777
1778 if (locked)
1779 spin_unlock_irqrestore(&port->lock, flags);
1780 }
1781
sw_console_setup(struct console * co,char * options)1782 static int sw_console_setup(struct console *co, char *options)
1783 {
1784 struct uart_port *port = NULL;
1785 struct sw_uart_port *sw_uport;
1786 int baud = 115200;
1787 int bits = 8;
1788 int parity = 'n';
1789 int flow = 'n';
1790
1791 if (unlikely(co->index >= SUNXI_UART_NUM || co->index < 0))
1792 return -ENXIO;
1793
1794 port = sw_console_get_port(co);
1795 if (port == NULL)
1796 return -ENODEV;
1797 sw_uport = UART_TO_SPORT(port);
1798 if (!port->iobase && !port->membase)
1799 return -ENODEV;
1800
1801 if (options)
1802 uart_parse_options(options, &baud, &parity, &bits, &flow);
1803
1804 SERIAL_MSG("console setup baud %d parity %c bits %d, flow %c\n",
1805 baud, parity, bits, flow);
1806 return uart_set_options(port, co, baud, parity, bits, flow);
1807 }
1808
1809 static struct uart_driver sw_uart_driver;
1810 static struct console sw_console = {
1811 #if IS_ENABLED(CONFIG_SERIAL_8250)
1812 .name = "ttyAS",
1813 #else
1814 .name = "ttyS",
1815 #endif
1816 .write = sw_console_write,
1817 .device = uart_console_device,
1818 .setup = sw_console_setup,
1819 .flags = CON_PRINTBUFFER,
1820 .index = -1,
1821 .data = &sw_uart_driver,
1822 };
1823
1824 #define SW_CONSOLE (&sw_console)
1825 #else
1826 #define SW_CONSOLE NULL
1827 #endif
1828
1829 static struct uart_driver sw_uart_driver = {
1830 .owner = THIS_MODULE,
1831 .driver_name = SUNXI_UART_DEV_NAME,
1832 #if IS_ENABLED(CONFIG_SERIAL_8250)
1833 .dev_name = "ttyAS",
1834 #else
1835 .dev_name = "ttyS",
1836 #endif
1837 .nr = SUNXI_UART_NUM,
1838 .cons = SW_CONSOLE,
1839 };
1840
sw_uart_request_resource(struct sw_uart_port * sw_uport,struct sw_uart_pdata * pdata,struct device * dev)1841 static int sw_uart_request_resource(struct sw_uart_port *sw_uport, struct sw_uart_pdata *pdata,
1842 struct device *dev)
1843 {
1844 SERIAL_DBG("get system resource(clk & IO)\n");
1845
1846 if (sw_uart_regulator_request(sw_uport, pdata, dev) < 0) {
1847 SERIAL_MSG("uart%d request regulator failed!\n", sw_uport->id);
1848 return -ENXIO;
1849 }
1850 sw_uart_regulator_enable(pdata);
1851
1852 #if IS_ENABLED(CONFIG_SW_UART_DUMP_DATA)
1853 sw_uport->dump_buff = (char *)kmalloc(MAX_DUMP_SIZE, GFP_KERNEL);
1854 if (!sw_uport->dump_buff) {
1855 SERIAL_MSG("uart%d fail to alloc dump buffer\n", sw_uport->id);
1856 }
1857 #endif
1858
1859 return 0;
1860 }
1861
sw_uart_release_resource(struct sw_uart_port * sw_uport,struct sw_uart_pdata * pdata)1862 static int sw_uart_release_resource(struct sw_uart_port *sw_uport, struct sw_uart_pdata *pdata)
1863 {
1864 SERIAL_DBG("put system resource(clk & IO)\n");
1865
1866 #if IS_ENABLED(CONFIG_SW_UART_DUMP_DATA)
1867 kfree(sw_uport->dump_buff);
1868 sw_uport->dump_buff = NULL;
1869 sw_uport->dump_len = 0;
1870 #endif
1871
1872 clk_disable_unprepare(sw_uport->mclk);
1873 clk_put(sw_uport->mclk);
1874
1875 sw_uart_regulator_disable(pdata);
1876 sw_uart_regulator_release(pdata);
1877
1878 return 0;
1879 }
1880
sw_uart_get_pdev(int uart_id)1881 struct platform_device *sw_uart_get_pdev(int uart_id)
1882 {
1883 if (sw_uart_ports[uart_id].port.dev)
1884 return to_platform_device(sw_uart_ports[uart_id].port.dev);
1885 else
1886 return NULL;
1887 }
1888
1889 #if IS_ENABLED(CONFIG_AW_SERIAL_EARLYCON)
1890
1891 #define SUNXI_UART_USR_NF 0x02 /* Tansmit fifo not full */
1892
sunxi_serial_console_putchar(struct uart_port * port,int ch)1893 static void sunxi_serial_console_putchar(struct uart_port *port, int ch)
1894 {
1895 int value = 0;
1896
1897 do {
1898 value = readl_relaxed(port->membase + SUNXI_UART_USR);
1899 } while (!(value & SUNXI_UART_USR_NF));
1900
1901 writel_relaxed(ch, port->membase + SUNXI_UART_THR);
1902 }
1903
sunxi_early_serial_write(struct console * con,const char * s,unsigned int n)1904 static __init void sunxi_early_serial_write(struct console *con, const char *s,
1905 unsigned int n)
1906 {
1907 struct earlycon_device *dev = con->data;
1908
1909 uart_console_write(&dev->port, s, n, sunxi_serial_console_putchar);
1910 }
1911
sunxi_early_console_setup(struct earlycon_device * dev,const char * opt)1912 static int __init sunxi_early_console_setup(struct earlycon_device *dev,
1913 const char *opt)
1914 {
1915 if (!dev->port.membase)
1916 return -ENODEV;
1917 dev->con->write = sunxi_early_serial_write;
1918 return 0;
1919 }
1920 OF_EARLYCON_DECLARE(uart0, "", sunxi_early_console_setup);
1921 #endif /* CONFIG_AW_SERIAL_EARLYCON */
1922
sw_uart_probe(struct platform_device * pdev)1923 static int sw_uart_probe(struct platform_device *pdev)
1924 {
1925 struct device_node *np = pdev->dev.of_node;
1926 struct uart_port *port;
1927 struct sw_uart_port *sw_uport;
1928 struct sw_uart_pdata *pdata;
1929 struct resource *res;
1930 char uart_para[16] = {0};
1931 const char *uart_string;
1932 int ret = -1;
1933 struct device_node *apk_np = of_find_node_by_name(NULL, "auto_print");
1934 const char *apk_sta = NULL;
1935 #if IS_ENABLED(CONFIG_AW_SERIAL_DMA)
1936 int use_dma = 0;
1937 #endif
1938
1939 pdev->id = of_alias_get_id(np, "serial");
1940 if (pdev->id < 0 || pdev->id >= SUNXI_UART_NUM) {
1941 SERIAL_MSG("get alias id err or exceed supported uart controllers\n");
1942 return -EINVAL;
1943 }
1944
1945 port = &sw_uart_ports[pdev->id].port;
1946 port->dev = &pdev->dev;
1947 pdata = &sw_uport_pdata[pdev->id];
1948 sw_uport = UART_TO_SPORT(port);
1949 sw_uport->pdata = pdata;
1950 sw_uport->id = pdev->id;
1951 sw_uport->ier = 0;
1952 sw_uport->lcr = 0;
1953 sw_uport->mcr = 0;
1954 sw_uport->fcr = 0;
1955 sw_uport->dll = 0;
1956 sw_uport->dlh = 0;
1957 snprintf(sw_uport->name, 16, SUNXI_UART_DEV_NAME"%d", pdev->id);
1958 pdev->dev.init_name = sw_uport->name;
1959 pdev->dev.platform_data = sw_uport->pdata;
1960
1961 snprintf(uart_para, sizeof(uart_para), "uart%d_regulator", pdev->id);
1962 ret = of_property_read_string(np, uart_para, &uart_string);
1963 if (!ret)
1964 strncpy(pdata->regulator_id, uart_string, 16);
1965
1966 /* request system resource and init them */
1967 ret = sw_uart_request_resource(sw_uport, pdev->dev.platform_data, &pdev->dev);
1968 if (unlikely(ret)) {
1969 SERIAL_MSG("uart%d error to get resource\n", pdev->id);
1970 return -ENXIO;
1971 }
1972
1973
1974 #if IS_ENABLED(CONFIG_AW_IC_BOARD)
1975 sw_uport->reset = devm_reset_control_get(&pdev->dev, NULL);
1976 if (IS_ERR(sw_uport->reset)) {
1977 printk("get reset clk error\n");
1978 return -EINVAL;
1979 }
1980 sw_uport->mclk = of_clk_get(np, 0);
1981 if (IS_ERR(sw_uport->mclk)) {
1982 SERIAL_MSG("uart%d error to get clk\n", pdev->id);
1983 return -EINVAL;
1984 }
1985
1986 ret = reset_control_deassert(sw_uport->reset);
1987 if (ret) {
1988 printk("deassert clk error, ret:%d\n", ret);
1989 return ret;
1990 }
1991
1992 /* uart clk come from apb2, apb2 default clk is hosc. if change rate
1993 * needed, must switch apb2's source clk first and then set its rate
1994 * */
1995 sw_uport->sclk = of_clk_get(np, 1);
1996 if (!IS_ERR(sw_uport->sclk)) {
1997 sw_uport->pclk = of_clk_get(np, 2);
1998 port->uartclk = clk_get_rate(sw_uport->sclk);
1999 /*config a fixed divider before switch source clk for apb2 */
2000 clk_set_rate(sw_uport->sclk, port->uartclk/6);
2001 /* switch source clock for apb2 */
2002 clk_set_parent(sw_uport->sclk, sw_uport->pclk);
2003 ret = of_property_read_u32(np, "clock-frequency",
2004 &port->uartclk);
2005 if (ret) {
2006 SERIAL_MSG("uart%d get clock-freq failed\n", pdev->id);
2007 return -EINVAL;
2008 }
2009 /* set apb2 clock frequency now */
2010 clk_set_rate(sw_uport->sclk, port->uartclk);
2011 }
2012
2013 port->uartclk = clk_get_rate(sw_uport->mclk);
2014 #else
2015 port->uartclk = 24000000;
2016 #endif
2017
2018 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2019 if (res == NULL) {
2020 dev_err(&pdev->dev, "uart%d error to get MEM resource\n", pdev->id);
2021 return -EINVAL;
2022 }
2023 port->mapbase = res->start;
2024
2025
2026 #if IS_ENABLED(CONFIG_AW_SERIAL_DMA)
2027 sw_uport->dma = devm_kzalloc(&pdev->dev, sizeof(struct sw_uart_dma), GFP_KERNEL);
2028 if (!sw_uport->dma) {
2029 dev_err(&pdev->dev, "unable to allocate mem\n");
2030 return -ENOMEM;
2031 }
2032 ret = of_property_read_u32(np, "use_dma", &use_dma);
2033 if (ret)
2034 use_dma = 0;
2035 sw_uport->dma->use_dma = use_dma;
2036 sw_uport->dma->rx_dma_inited = 0;
2037 sw_uport->dma->rx_dma_used = 0;
2038 sw_uport->dma->tx_dma_inited = 0;
2039 sw_uport->dma->tx_dma_used = 0;
2040 #endif
2041
2042 port->irq = platform_get_irq(pdev, 0);
2043 if (port->irq < 0) {
2044 dev_err(&pdev->dev, "uart%d error to get irq\n", pdev->id);
2045 return -EINVAL;
2046 }
2047
2048
2049 snprintf(uart_para, sizeof(uart_para), "uart%d_port", pdev->id);
2050 ret = of_property_read_u32(np, uart_para, &port->line);
2051 if (ret) {
2052 dev_err(&pdev->dev, "uart%d error to get port property\n", pdev->id);
2053 return -EINVAL;
2054 }
2055
2056
2057 snprintf(uart_para, sizeof(uart_para), "uart%d_type", pdev->id);
2058 ret = of_property_read_u32(np, uart_para, &pdata->io_num);
2059 if (ret) {
2060 dev_err(&pdev->dev, "uart%d error to get type property\n", pdev->id);
2061 return -EINVAL;
2062 }
2063
2064
2065 if (of_property_read_bool(np, "linux,rs485-enabled-at-boot-time"))
2066 sw_uport->rs485conf.flags |= SER_RS485_ENABLED;
2067
2068 if (apk_np && !of_property_read_string(apk_np, "status", &apk_sta)
2069 && !strcmp(apk_sta, "okay"))
2070 sw_uport->card_print = true;
2071 else
2072 sw_uport->card_print = false;
2073
2074 pdata->used = 1;
2075 port->iotype = UPIO_MEM;
2076 port->type = PORT_SUNXI;
2077 port->flags = UPF_BOOT_AUTOCONF;
2078 port->ops = &sw_uart_ops;
2079
2080 ret = of_property_read_u32(np, "sunxi,uart-fifosize", &port->fifosize);
2081 if (ret) {
2082 dev_err(&pdev->dev, "uart%d error to get fifo size property\n", pdev->id);
2083 port->fifosize = SUNXI_UART_FIFO_SIZE;
2084 }
2085
2086 platform_set_drvdata(pdev, port);
2087
2088 #if IS_ENABLED(CONFIG_AW_SERIAL_DMA)
2089 /* set dma config */
2090 pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
2091 if (sw_uport->dma->use_dma & RX_DMA) {
2092 /* timer */
2093 sw_uport->dma->use_timer = UART_USE_TIMER;
2094 sw_uport->dma->rx_timeout = 2000000;
2095 hrtimer_init(&sw_uport->rx_hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2096 sw_uport->rx_hrtimer.function = sw_uart_report_dma_rx;
2097
2098 /* rx buffer */
2099 sw_uport->dma->rb_size = DMA_SERIAL_BUFFER_SIZE;
2100 sw_uport->dma->rx_buffer = dma_alloc_coherent(
2101 sw_uport->port.dev, sw_uport->dma->rb_size,
2102 &sw_uport->dma->rx_phy_addr, GFP_KERNEL);
2103 sw_uport->dma->rb_tail = 0;
2104
2105 if (!sw_uport->dma->rx_buffer) {
2106 dev_err(sw_uport->port.dev,
2107 "dmam_alloc_coherent dma_rx_buffer fail\n");
2108 return -ENOMEM;
2109 } else {
2110 dev_info(sw_uport->port.dev,
2111 "dma_rx_buffer %p\n", sw_uport->dma->rx_buffer);
2112 dev_info(sw_uport->port.dev,
2113 "dma_rx_phy 0x%08x\n", (unsigned)sw_uport->dma->rx_phy_addr);
2114 }
2115 sw_uart_init_dma_rx(sw_uport);
2116 }
2117
2118 if (sw_uport->dma->use_dma & TX_DMA) {
2119 /* tx buffer */
2120 sw_uport->dma->tb_size = UART_XMIT_SIZE;
2121 sw_uport->dma->tx_buffer = dma_alloc_coherent(
2122 sw_uport->port.dev, sw_uport->dma->tb_size,
2123 &sw_uport->dma->tx_phy_addr, GFP_KERNEL);
2124 if (!sw_uport->dma->tx_buffer) {
2125 dev_info(sw_uport->port.dev,
2126 "dmam_alloc_coherent dma_tx_buffer fail\n");
2127 } else {
2128 dev_info(sw_uport->port.dev, "dma_tx_buffer %p\n",
2129 sw_uport->dma->tx_buffer);
2130 dev_info(sw_uport->port.dev, "dma_tx_phy 0x%08x\n",
2131 (unsigned) sw_uport->dma->tx_phy_addr);
2132 }
2133 sw_uart_init_dma_tx(sw_uport);
2134 }
2135
2136 #endif
2137
2138 sunxi_uart_sysfs(pdev);
2139
2140 SERIAL_DBG("add uart%d port, port_type %d, uartclk %d\n",
2141 pdev->id, port->type, port->uartclk);
2142 return uart_add_one_port(&sw_uart_driver, port);
2143 }
2144
sw_uart_remove(struct platform_device * pdev)2145 static int sw_uart_remove(struct platform_device *pdev)
2146 {
2147 struct sw_uart_port *sw_uport = platform_get_drvdata(pdev);
2148
2149 SERIAL_DBG("release uart%d port\n", sw_uport->id);
2150 #if IS_ENABLED(CONFIG_AW_SERIAL_DMA)
2151 sw_uart_release_dma_tx(sw_uport);
2152 sw_uart_release_dma_rx(sw_uport);
2153 #endif
2154 sw_uart_release_resource(sw_uport, pdev->dev.platform_data);
2155 return 0;
2156 }
2157
2158 /* UART power management code */
2159 #if IS_ENABLED(CONFIG_PM_SLEEP)
2160
2161 #define SW_UART_NEED_SUSPEND(port) \
2162 ((sw_is_console_port(port) && (console_suspend_enabled)) \
2163 || !sw_is_console_port(port))
2164
sw_uart_suspend(struct device * dev)2165 static int sw_uart_suspend(struct device *dev)
2166 {
2167 struct uart_port *port = dev_get_drvdata(dev);
2168 struct sw_uart_port *sw_uport = UART_TO_SPORT(port);
2169
2170 if (port) {
2171 SERIAL_MSG("uart%d suspend\n", sw_uport->id);
2172 uart_suspend_port(&sw_uart_driver, port);
2173
2174 if (SW_UART_NEED_SUSPEND(port)) {
2175 if (!sw_uport->card_print)
2176 sw_uart_select_gpio_state(sw_uport->pctrl,
2177 PINCTRL_STATE_SLEEP, sw_uport->id);
2178 sw_uart_regulator_disable(dev->platform_data);
2179 }
2180 }
2181
2182 return 0;
2183 }
2184
sw_uart_resume(struct device * dev)2185 static int sw_uart_resume(struct device *dev)
2186 {
2187 struct uart_port *port = dev_get_drvdata(dev);
2188 struct sw_uart_port *sw_uport = UART_TO_SPORT(port);
2189
2190 if (port) {
2191 if (SW_UART_NEED_SUSPEND(port)) {
2192 sw_uart_regulator_enable(dev->platform_data);
2193 if (!sw_uport->card_print)
2194 sw_uart_select_gpio_state(sw_uport->pctrl,
2195 PINCTRL_STATE_DEFAULT, sw_uport->id);
2196 }
2197 uart_resume_port(&sw_uart_driver, port);
2198 SERIAL_MSG("uart%d resume. DLH: %d, DLL: %d. \n", sw_uport->id, sw_uport->dlh, sw_uport->dll);
2199 }
2200
2201 return 0;
2202 }
2203
2204 static const struct dev_pm_ops sw_uart_pm_ops = {
2205 .suspend = sw_uart_suspend,
2206 .resume = sw_uart_resume,
2207 };
2208 #define SERIAL_SW_PM_OPS (&sw_uart_pm_ops)
2209
2210 #else /* !CONFIG_PM_SLEEP */
2211
2212 #define SERIAL_SW_PM_OPS NULL
2213 #endif /* CONFIG_PM_SLEEP */
2214
2215 static const struct of_device_id sunxi_uart_match[] = {
2216 { .compatible = "allwinner,sun8i-uart", },
2217 { .compatible = "allwinner,sun50i-uart", },
2218 { .compatible = "allwinner,sun20i-uart", },
2219 {},
2220 };
2221 MODULE_DEVICE_TABLE(of, sunxi_uart_match);
2222
2223
2224 static struct platform_driver sw_uport_platform_driver = {
2225 .probe = sw_uart_probe,
2226 .remove = sw_uart_remove,
2227 .driver = {
2228 .name = SUNXI_UART_DEV_NAME,
2229 .pm = SERIAL_SW_PM_OPS,
2230 .owner = THIS_MODULE,
2231 .of_match_table = sunxi_uart_match,
2232 },
2233 };
2234
sunxi_uart_init(void)2235 static int __init sunxi_uart_init(void)
2236 {
2237 int ret;
2238
2239 ret = uart_register_driver(&sw_uart_driver);
2240 if (unlikely(ret)) {
2241 SERIAL_MSG("driver initializied\n");
2242 return ret;
2243 }
2244
2245 return platform_driver_register(&sw_uport_platform_driver);
2246 }
2247
sunxi_uart_exit(void)2248 static void __exit sunxi_uart_exit(void)
2249 {
2250 SERIAL_MSG("driver exit\n");
2251 #if IS_ENABLED(CONFIG_AW_SERIAL_CONSOLE)
2252 unregister_console(&sw_console);
2253 #endif
2254 platform_driver_unregister(&sw_uport_platform_driver);
2255 uart_unregister_driver(&sw_uart_driver);
2256 }
2257
2258 module_init(sunxi_uart_init);
2259 module_exit(sunxi_uart_exit);
2260
2261 MODULE_AUTHOR("Aaron<leafy.myeh@allwinnertech.com>");
2262 MODULE_DESCRIPTION("Driver for Allwinner UART controller");
2263 MODULE_LICENSE("GPL");
2264
2265 MODULE_VERSION("1.0.2");
2266