1 /**
2 * drivers/usb/host/sunxi-hci.c
3 * (C) Copyright 2010-2015
4 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
5 * yangnaitian, 2011-5-24, create this file
6 * javen, 2011-7-18, add clock and power switch
7 *
8 * sunxi HCI Driver
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 */
16
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/delay.h>
20 #include <linux/ioport.h>
21 #include <linux/sched.h>
22 #include <linux/slab.h>
23 #include <linux/errno.h>
24 #include <linux/init.h>
25 #include <linux/timer.h>
26 #include <linux/list.h>
27 #include <linux/interrupt.h>
28 #include <linux/platform_device.h>
29 #include <linux/clk.h>
30 #include <linux/reset.h>
31 #include <linux/gpio.h>
32
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/dma-mapping.h>
36
37 #include <asm/byteorder.h>
38 #include <asm/io.h>
39 #include <asm/unaligned.h>
40 #include <linux/regulator/consumer.h>
41 #include <linux/of.h>
42 #include <linux/of_address.h>
43 #include <linux/of_device.h>
44 #include <sunxi-sid.h>
45
46 #include "sunxi-hci.h"
47
48 #define DRIVER_DESC "SUNXI HCI driver"
49 #define SUNXI_HCI_NAME "sunxi-hci"
50 static const char hci_name[] = SUNXI_HCI_NAME;
51
52 static u64 sunxi_hci_dmamask = ~0ULL; // DMA_BIT_MASK(64); /* Avoid Clang waring: shift count >= width of type */
53 static DEFINE_MUTEX(usb_passby_lock);
54 static DEFINE_MUTEX(usb_vbus_lock);
55 static DEFINE_MUTEX(usb_clock_lock);
56 static DEFINE_MUTEX(usb_standby_lock);
57
58 #ifndef CONFIG_OF
59 static char *usbc_name[4] = {"usbc0", "usbc1", "usbc2", "usbc3"};
60 #endif
61
62 static struct sunxi_hci_hcd sunxi_ohci0;
63 static struct sunxi_hci_hcd sunxi_ohci1;
64 static struct sunxi_hci_hcd sunxi_ohci2;
65 static struct sunxi_hci_hcd sunxi_ohci3;
66 static struct sunxi_hci_hcd sunxi_ehci0;
67 static struct sunxi_hci_hcd sunxi_ehci1;
68 static struct sunxi_hci_hcd sunxi_ehci2;
69 static struct sunxi_hci_hcd sunxi_ehci3;
70 static struct sunxi_hci_hcd sunxi_xhci;
71
72 #define USBPHYC_REG_o_PHYCTL 0x0404
73
74 atomic_t usb1_enable_passly_cnt = ATOMIC_INIT(0);
75 atomic_t usb2_enable_passly_cnt = ATOMIC_INIT(0);
76 atomic_t usb3_enable_passly_cnt = ATOMIC_INIT(0);
77 atomic_t usb4_enable_passly_cnt = ATOMIC_INIT(0);
78
79 atomic_t usb_standby_cnt = ATOMIC_INIT(0);
request_usb_regulator_io(struct sunxi_hci_hcd * sunxi_hci)80 static s32 request_usb_regulator_io(struct sunxi_hci_hcd *sunxi_hci)
81 {
82 if (sunxi_hci->hsic_flag) {
83 if (sunxi_hci->hsic_regulator_io != NULL) {
84 sunxi_hci->hsic_regulator_io_hdle =
85 regulator_get(NULL, sunxi_hci->hsic_regulator_io);
86 if (IS_ERR(sunxi_hci->hsic_regulator_io_hdle)) {
87 DMSG_PANIC("ERR: some error happen, %s, hsic_regulator_io_hdle fail to get regulator!", sunxi_hci->hci_name);
88 sunxi_hci->hsic_regulator_io_hdle = NULL;
89 return 0;
90 }
91 }
92 }
93
94 return 0;
95 }
96
release_usb_regulator_io(struct sunxi_hci_hcd * sunxi_hci)97 static s32 release_usb_regulator_io(struct sunxi_hci_hcd *sunxi_hci)
98 {
99 if (sunxi_hci->hsic_flag) {
100 if (sunxi_hci->hsic_regulator_io != NULL)
101 regulator_put(sunxi_hci->hsic_regulator_io_hdle);
102 }
103
104 return 0;
105 }
106
usb_phy_csr_add(struct sunxi_hci_hcd * sunxi_hci)107 void __iomem *usb_phy_csr_add(struct sunxi_hci_hcd *sunxi_hci)
108 {
109 return (sunxi_hci->otg_vbase + SUNXI_OTG_PHY_CTRL);
110 }
111
usb_phy_csr_read(struct sunxi_hci_hcd * sunxi_hci)112 void __iomem *usb_phy_csr_read(struct sunxi_hci_hcd *sunxi_hci)
113 {
114 switch (sunxi_hci->usbc_no) {
115 case 0:
116 return sunxi_hci->otg_vbase + SUNXI_OTG_PHY_STATUS;
117
118 case 1:
119 return sunxi_hci->usb_vbase + SUNXI_HCI_UTMI_PHY_STATUS;
120
121 case 2:
122 return sunxi_hci->usb_vbase + SUNXI_HCI_UTMI_PHY_STATUS;
123
124 case 3:
125 return sunxi_hci->usb_vbase + SUNXI_HCI_UTMI_PHY_STATUS;
126
127 default:
128 DMSG_PANIC("usb_phy_csr_read is failed in %d index\n",
129 sunxi_hci->usbc_no);
130 break;
131 }
132
133 return NULL;
134 }
135
usb_phy_csr_write(struct sunxi_hci_hcd * sunxi_hci)136 void __iomem *usb_phy_csr_write(struct sunxi_hci_hcd *sunxi_hci)
137 {
138 switch (sunxi_hci->usbc_no) {
139 case 0:
140 return sunxi_hci->otg_vbase + SUNXI_OTG_PHY_CTRL;
141
142 case 1:
143 return sunxi_hci->usb_vbase + SUNXI_HCI_PHY_CTRL;
144
145 case 2:
146 return sunxi_hci->usb_vbase + SUNXI_HCI_PHY_CTRL;
147
148 case 3:
149 return sunxi_hci->usb_vbase + SUNXI_HCI_PHY_CTRL;
150
151 default:
152 DMSG_PANIC("usb_phy_csr_write is failed in %d index\n",
153 sunxi_hci->usbc_no);
154 break;
155 }
156
157 return NULL;
158 }
159
usb_phyx_tp_write(struct sunxi_hci_hcd * sunxi_hci,int addr,int data,int len)160 int usb_phyx_tp_write(struct sunxi_hci_hcd *sunxi_hci,
161 int addr, int data, int len)
162 {
163 int temp = 0;
164 int j = 0;
165 int reg_value = 0;
166 int reg_temp = 0;
167 int dtmp = 0;
168
169 if (sunxi_hci->otg_vbase == NULL) {
170 DMSG_PANIC("%s,otg_vbase is null\n", __func__);
171 return -1;
172 }
173
174 if (usb_phy_csr_add(sunxi_hci) == NULL) {
175 DMSG_PANIC("%s,phy_csr_add is null\n", __func__);
176 return -1;
177 }
178
179 if (usb_phy_csr_write(sunxi_hci) == NULL) {
180
181 DMSG_PANIC("%s,phy_csr_write is null\n", __func__);
182 return -1;
183 }
184
185 reg_value = USBC_Readl(sunxi_hci->otg_vbase + SUNXI_OTG_PHY_CFG);
186 reg_temp = reg_value;
187 reg_value |= 0x01;
188 USBC_Writel(reg_value, (sunxi_hci->otg_vbase + SUNXI_OTG_PHY_CFG));
189
190 dtmp = data;
191 for (j = 0; j < len; j++) {
192 USBC_Writeb(addr + j, usb_phy_csr_add(sunxi_hci) + 1);
193
194 temp = USBC_Readb(usb_phy_csr_write(sunxi_hci));
195 temp &= ~(0x1 << 0);
196 USBC_Writeb(temp, usb_phy_csr_write(sunxi_hci));
197
198 temp = USBC_Readb(usb_phy_csr_add(sunxi_hci));
199 temp &= ~(0x1 << 7);
200 temp |= (dtmp & 0x1) << 7;
201 USBC_Writeb(temp, usb_phy_csr_add(sunxi_hci));
202
203 temp = USBC_Readb(usb_phy_csr_write(sunxi_hci));
204 temp |= (0x1 << 0);
205 USBC_Writeb(temp, usb_phy_csr_write(sunxi_hci));
206
207 temp = USBC_Readb(usb_phy_csr_write(sunxi_hci));
208 temp &= ~(0x1 << 0);
209 USBC_Writeb(temp, usb_phy_csr_write(sunxi_hci));
210
211 dtmp >>= 1;
212 }
213
214 USBC_Writel(reg_temp, (sunxi_hci->otg_vbase + SUNXI_OTG_PHY_CFG));
215
216 return 0;
217 }
218 EXPORT_SYMBOL(usb_phyx_tp_write);
219
usb_phyx_write(struct sunxi_hci_hcd * sunxi_hci,int data)220 int usb_phyx_write(struct sunxi_hci_hcd *sunxi_hci, int data)
221 {
222 int reg_value = 0;
223 int temp = 0;
224 int dtmp = 0;
225 int ptmp = 0;
226
227 temp = data;
228 dtmp = data;
229 ptmp = data;
230
231 reg_value = USBC_Readl(sunxi_hci->usb_vbase + SUNXI_HCI_PHY_TUNE);
232
233 /*TXVREFTUNE + TXRISETUNE + TXPREEMPAMPTUNE + TXRESTUNE*/
234 reg_value &= ~((0xf << 8) | (0x3 << 4) | (0xf << 0));
235 temp &= ~((0xf << 4) | (0x3 << 8));
236 reg_value |= temp << 8;
237 dtmp &= ~((0xf << 6) | (0xf << 0));
238 reg_value |= dtmp;
239 data &= ~((0x3 << 4) | (0xf << 0));
240 reg_value |= data >> 6;
241
242 USBC_Writel(reg_value, (sunxi_hci->usb_vbase + SUNXI_HCI_PHY_TUNE));
243
244 return 0;
245 }
246 EXPORT_SYMBOL(usb_phyx_write);
247
usb_phyx_read(struct sunxi_hci_hcd * sunxi_hci)248 int usb_phyx_read(struct sunxi_hci_hcd *sunxi_hci)
249 {
250 int reg_value = 0;
251 int temp = 0;
252 int ptmp = 0;
253 int ret = 0;
254
255 reg_value = USBC_Readl(sunxi_hci->usb_vbase + SUNXI_HCI_PHY_TUNE);
256 reg_value &= 0xf3f;
257 ptmp = reg_value;
258
259 temp = reg_value >> 8;
260 ptmp &= ~((0xf << 8) | (0xf << 4));
261 ptmp <<= 6;
262 reg_value &= ~((0xf << 8) | (0xf << 0));
263
264 ret = reg_value | ptmp | temp;
265
266 DMSG_INFO("bit[3:0]VREF = 0x%x; bit[5:4]RISE = 0x%x; bit[7:6]PREEMPAMP = 0x%x; bit[9:8]RES = 0x%x\n",
267 temp, reg_value >> 4, (ptmp >> 6) & 0x3,
268 ((ptmp >> 6) & 0xc) >> 2);
269
270 return ret;
271 }
272 EXPORT_SYMBOL(usb_phyx_read);
273
usb_phyx_tp_read(struct sunxi_hci_hcd * sunxi_hci,int addr,int len)274 int usb_phyx_tp_read(struct sunxi_hci_hcd *sunxi_hci, int addr, int len)
275 {
276 int temp = 0;
277 int i = 0;
278 int j = 0;
279 int ret = 0;
280 int reg_value = 0;
281 int reg_temp = 0;
282
283 if (sunxi_hci->otg_vbase == NULL) {
284 DMSG_PANIC("%s,otg_vbase is null\n", __func__);
285 return -1;
286 }
287
288 if (usb_phy_csr_add(sunxi_hci) == NULL) {
289 DMSG_PANIC("%s,phy_csr_add is null\n", __func__);
290 return -1;
291 }
292
293 if (usb_phy_csr_read(sunxi_hci) == NULL) {
294 DMSG_PANIC("%s,phy_csr_read is null\n", __func__);
295 return -1;
296 }
297
298 reg_value = USBC_Readl(sunxi_hci->otg_vbase + SUNXI_OTG_PHY_CFG);
299 reg_temp = reg_value;
300 reg_value |= 0x01;
301 USBC_Writel(reg_value, (sunxi_hci->otg_vbase + SUNXI_OTG_PHY_CFG));
302
303 for (j = len; j > 0; j--) {
304 USBC_Writeb((addr + j - 1), usb_phy_csr_add(sunxi_hci) + 1);
305
306 for (i = 0; i < 0x4; i++)
307 ;
308
309 temp = USBC_Readb(usb_phy_csr_read(sunxi_hci));
310 ret <<= 1;
311 ret |= (temp & 0x1);
312 }
313
314 USBC_Writel(reg_temp, (sunxi_hci->otg_vbase + SUNXI_OTG_PHY_CFG));
315
316 return ret;
317 }
318 EXPORT_SYMBOL(usb_phyx_tp_read);
319
320 #if defined(CONFIG_ARCH_SUN8IW20) || defined(CONFIG_ARCH_SUN20IW1)
321 /*for new phy*/
usb_new_phyx_tp_write(struct sunxi_hci_hcd * sunxi_hci,int addr,int data,int len)322 static int usb_new_phyx_tp_write(struct sunxi_hci_hcd *sunxi_hci,
323 int addr, int data, int len)
324 {
325 int temp = 0;
326 int j = 0;
327 int dtmp = 0;
328 void __iomem *base;
329
330 if (sunxi_hci->otg_vbase == NULL) {
331 DMSG_PANIC("%s,otg_vbase is null\n", __func__);
332 return -1;
333 }
334
335 if (usb_phy_csr_add(sunxi_hci) == NULL) {
336 DMSG_PANIC("%s,phy_csr_add is null\n", __func__);
337 return -1;
338 }
339
340 if (usb_phy_csr_write(sunxi_hci) == NULL) {
341
342 DMSG_PANIC("%s,phy_csr_write is null\n", __func__);
343 return -1;
344 }
345 /*device: 0x410(phy_ctl)*/
346 base = sunxi_hci->usb_vbase;
347 dtmp = data;
348 for (j = 0; j < len; j++) {
349 temp = USBC_Readb(base + SUNXI_HCI_PHY_CTRL);
350 temp |= (0x1 << 1);
351 USBC_Writeb(temp, base + SUNXI_HCI_PHY_CTRL);
352
353 USBC_Writeb(addr + j, base + SUNXI_HCI_PHY_CTRL + 1);
354
355 temp = USBC_Readb(base + SUNXI_HCI_PHY_CTRL);
356 temp &= ~(0x1 << 0);
357 USBC_Writeb(temp, base + SUNXI_HCI_PHY_CTRL);
358
359 temp = USBC_Readb(base + SUNXI_HCI_PHY_CTRL);
360 temp &= ~(0x1 << 7);
361 temp |= (dtmp & 0x1) << 7;
362 USBC_Writeb(temp, base + SUNXI_HCI_PHY_CTRL);
363
364 temp |= (0x1 << 0);
365 USBC_Writeb(temp, base + SUNXI_HCI_PHY_CTRL);
366
367 temp &= ~(0x1 << 0);
368 USBC_Writeb(temp, base + SUNXI_HCI_PHY_CTRL);
369
370 temp = USBC_Readb(base + SUNXI_HCI_PHY_CTRL);
371 temp &= ~(0x1 << 1);
372 USBC_Writeb(temp, base + SUNXI_HCI_PHY_CTRL);
373
374 dtmp >>= 1;
375 }
376
377 return 0;
378 }
379
usb_new_phyx_tp_read(struct sunxi_hci_hcd * sunxi_hci,int addr,int len)380 static int usb_new_phyx_tp_read(struct sunxi_hci_hcd *sunxi_hci, int addr, int len)
381 {
382 int temp = 0;
383 int i = 0;
384 int j = 0;
385 int ret = 0;
386 void __iomem *base;
387
388 if (sunxi_hci->otg_vbase == NULL) {
389 DMSG_PANIC("%s,otg_vbase is null\n", __func__);
390 return -1;
391 }
392
393 if (usb_phy_csr_add(sunxi_hci) == NULL) {
394 DMSG_PANIC("%s,phy_csr_add is null\n", __func__);
395 return -1;
396 }
397
398 if (usb_phy_csr_read(sunxi_hci) == NULL) {
399 DMSG_PANIC("%s,phy_csr_read is null\n", __func__);
400 return -1;
401 }
402
403 base = sunxi_hci->usb_vbase;
404
405 temp = USBC_Readb(base + SUNXI_HCI_PHY_CTRL);
406 temp |= (0x1 << 1);
407 USBC_Writeb(temp, base + SUNXI_HCI_PHY_CTRL);
408
409 for (j = len; j > 0; j--) {
410 USBC_Writeb((addr + j - 1), base + SUNXI_HCI_PHY_CTRL + 1);
411
412 for (i = 0; i < 0x4; i++)
413 ;
414
415 temp = USBC_Readb(base + SUNXI_HCI_UTMI_PHY_STATUS);
416 ret <<= 1;
417 ret |= (temp & 0x1);
418 }
419
420 temp = USBC_Readb(base + SUNXI_HCI_PHY_CTRL);
421 temp &= ~(0x1 << 1);
422 USBC_Writeb(temp, base + SUNXI_HCI_PHY_CTRL);
423
424 return ret;
425 }
426
usb_new_phy_init(struct sunxi_hci_hcd * sunxi_hci)427 static void usb_new_phy_init(struct sunxi_hci_hcd *sunxi_hci)
428 {
429 int value = 0;
430 u32 efuse_val = 0;
431
432 pr_debug("addr:%x,len:%x,value:%x\n", 0x03, 0x06,
433 usb_new_phyx_tp_read(sunxi_hci, 0x03, 0x06));
434
435 //pll_prediv
436 pr_debug("addr:%x,len:%x,value:%x\n", 0x16, 0x03,
437 usb_new_phyx_tp_read(sunxi_hci, 0x16, 0x03));
438
439 //usbc_new_phyx_tp_write(regs, 0x1c, 0x07, 0x03);
440 //pll_n
441 pr_debug("addr:%x,len:%x,value:%x\n", 0x0b, 0x08,
442 usb_new_phyx_tp_read(sunxi_hci, 0x0b, 0x08));
443
444 //usbc_new_phyx_tp_write(regs, 0x30, 0x0f, 0x0d);
445 //pll_sts
446 pr_debug("addr:%x,len:%x,value:%x\n", 0x09, 0x03,
447 usb_new_phyx_tp_read(sunxi_hci, 0x09, 0x03));
448
449 sunxi_get_module_param_from_sid(&efuse_val, EFUSE_OFFSET, 4);
450 pr_debug("efuse_val:0x%x\n", efuse_val);
451
452 usb_new_phyx_tp_write(sunxi_hci, 0x1c, 0x0, 0x03);
453 pr_debug("addr:%x,len:%x,value:%x\n", 0x1c, 0x03,
454 usb_new_phyx_tp_read(sunxi_hci, 0x1c, 0x03));
455
456 if (efuse_val & SUNXI_HCI_PHY_EFUSE_ADJUST) {
457 if (efuse_val & SUNXI_HCI_PHY_EFUSE_MODE) {
458 /* iref mode */
459 usb_new_phyx_tp_write(sunxi_hci, 0x60, 0x1, 0x01);
460
461 switch (sunxi_hci->usbc_no) {
462 case 0:
463 value = (efuse_val & SUNXI_HCI_PHY_EFUSE_USB0TX) >> 22;
464 usb_new_phyx_tp_write(sunxi_hci, 0x61, value, 0x03);
465 break;
466
467 case 1:
468 value = (efuse_val & SUNXI_HCI_PHY_EFUSE_USB0TX) >> 25;
469 usb_new_phyx_tp_write(sunxi_hci, 0x61, value, 0x03);
470 break;
471
472 default:
473 pr_err("usb %d not exist!\n", sunxi_hci->usbc_no);
474 break;
475 }
476
477 value = (efuse_val & SUNXI_HCI_PHY_EFUSE_RES) >> 18;
478 usb_new_phyx_tp_write(sunxi_hci, 0x44, value, 0x04);
479
480 pr_debug("addr:%x,len:%x,value:%x\n", 0x61, 0x03,
481 usb_new_phyx_tp_read(sunxi_hci, 0x61, 0x03));
482 pr_debug("addr:%x,len:%x,value:%x\n", 0x44, 0x04,
483 usb_new_phyx_tp_read(sunxi_hci, 0x44, 0x04));
484 } else {
485 /* vref mode */
486 usb_new_phyx_tp_write(sunxi_hci, 0x60, 0x0, 0x01);
487
488 value = (efuse_val & SUNXI_HCI_PHY_EFUSE_RES) >> 18;
489 usb_new_phyx_tp_write(sunxi_hci, 0x44, value, 0x04);
490
491 value = (efuse_val & SUNXI_HCI_PHY_EFUSE_COM) >> 22;
492 usb_new_phyx_tp_write(sunxi_hci, 0x36, value, 0x03);
493
494
495 pr_debug("addr:%x,len:%x,value:%x\n", 0x60, 0x01,
496 usb_new_phyx_tp_read(sunxi_hci, 0x60, 0x01));
497 pr_debug("addr:%x,len:%x,value:%x\n", 0x44, 0x04,
498 usb_new_phyx_tp_read(sunxi_hci, 0x44, 0x04));
499 pr_debug("addr:%x,len:%x,value:%x\n", 0x36, 0x03,
500 usb_new_phyx_tp_read(sunxi_hci, 0x36, 0x03));
501 }
502 }
503
504 pr_debug("addr:%x,len:%x,value:%x\n", 0x03, 0x06,
505 usb_new_phyx_tp_read(sunxi_hci, 0x03, 0x06));
506 pr_debug("addr:%x,len:%x,value:%x\n", 0x16, 0x03,
507 usb_new_phyx_tp_read(sunxi_hci, 0x16, 0x03));
508 pr_debug("addr:%x,len:%x,value:%x\n", 0x0b, 0x08,
509 usb_new_phyx_tp_read(sunxi_hci, 0x0b, 0x08));
510 pr_debug("addr:%x,len:%x,value:%x\n", 0x09, 0x03,
511 usb_new_phyx_tp_read(sunxi_hci, 0x09, 0x03));
512 }
513
514 #endif
515
516 #if defined(CONFIG_ARCH_SUN8IW7) || defined(CONFIG_ARCH_SUN8IW12) \
517 || defined(CONFIG_ARCH_SUN8IW15) || defined(CONFIG_ARCH_SUN50IW3) \
518 || defined(CONFIG_ARCH_SUN50IW6) || defined(CONFIG_ARCH_SUN50IW9) \
519 || defined(CONFIG_ARCH_SUN8IW18)
usb_hci_utmi_phy_tune(struct sunxi_hci_hcd * sunxi_hci,int mask,int offset,int val)520 static void usb_hci_utmi_phy_tune(struct sunxi_hci_hcd *sunxi_hci, int mask,
521 int offset, int val)
522 {
523 int reg_value = 0;
524
525 reg_value = USBC_Readl(sunxi_hci->usb_vbase + SUNXI_HCI_PHY_TUNE);
526 reg_value &= ~mask;
527 val = val << offset;
528 val &= mask;
529 reg_value |= val;
530 USBC_Writel(reg_value, (sunxi_hci->usb_vbase + SUNXI_HCI_PHY_TUNE));
531 }
532 #endif
533
USBC_SelectPhyToHci(struct sunxi_hci_hcd * sunxi_hci)534 static void USBC_SelectPhyToHci(struct sunxi_hci_hcd *sunxi_hci)
535 {
536 int reg_value = 0;
537
538 reg_value = USBC_Readl(sunxi_hci->otg_vbase + SUNXI_OTG_PHY_CFG);
539 reg_value &= ~(0x01);
540 USBC_Writel(reg_value, (sunxi_hci->otg_vbase + SUNXI_OTG_PHY_CFG));
541 }
542
USBC_Clean_SIDDP(struct sunxi_hci_hcd * sunxi_hci)543 static void USBC_Clean_SIDDP(struct sunxi_hci_hcd *sunxi_hci)
544 {
545 int reg_value = 0;
546
547 reg_value = USBC_Readl(sunxi_hci->usb_vbase + SUNXI_HCI_PHY_CTRL);
548 reg_value &= ~(0x01 << SUNXI_HCI_PHY_CTRL_SIDDQ);
549 USBC_Writel(reg_value, (sunxi_hci->usb_vbase + SUNXI_HCI_PHY_CTRL));
550 }
551
552 #if defined(CONFIG_ARCH_SUN50IW10)
553 /*for common circuit*/
sunxi_hci_common_set_rc_clk(struct sunxi_hci_hcd * sunxi_hci,int is_on)554 void sunxi_hci_common_set_rc_clk(struct sunxi_hci_hcd *sunxi_hci, int is_on)
555 {
556 int reg_value = 0;
557 reg_value = USBC_Readl(sunxi_hci->usb_common_phy_config
558 + SUNXI_USB_PMU_IRQ_ENABLE);
559 if (is_on)
560 reg_value |= 0x01 << SUNXI_HCI_RC16M_CLK_ENBALE;
561 else
562 reg_value &= ~(0x01 << SUNXI_HCI_RC16M_CLK_ENBALE);
563 USBC_Writel(reg_value, (sunxi_hci->usb_common_phy_config
564 + SUNXI_USB_PMU_IRQ_ENABLE));
565 }
sunxi_hci_common_switch_clk(struct sunxi_hci_hcd * sunxi_hci,int is_on)566 void sunxi_hci_common_switch_clk(struct sunxi_hci_hcd *sunxi_hci, int is_on)
567 {
568 int reg_value = 0;
569 reg_value = USBC_Readl(sunxi_hci->usb_common_phy_config
570 + SUNXI_USB_PMU_IRQ_ENABLE);
571 if (is_on)
572 reg_value |= 0x01 << 31;
573 else
574 reg_value &= ~(0x01 << 31);
575 USBC_Writel(reg_value, (sunxi_hci->usb_common_phy_config
576 + SUNXI_USB_PMU_IRQ_ENABLE));
577 }
sunxi_hci_common_set_rcgating(struct sunxi_hci_hcd * sunxi_hci,int is_on)578 void sunxi_hci_common_set_rcgating(struct sunxi_hci_hcd *sunxi_hci, int is_on)
579 {
580 int reg_value = 0;
581 reg_value = USBC_Readl(sunxi_hci->usb_common_phy_config
582 + SUNXI_USB_PMU_IRQ_ENABLE);
583 if (is_on)
584 reg_value |= 0x01 << 3;
585 else
586 reg_value &= ~(0x01 << 3);
587 USBC_Writel(reg_value, (sunxi_hci->usb_common_phy_config
588 + SUNXI_USB_PMU_IRQ_ENABLE));
589 }
sunxi_hci_switch_clk(struct sunxi_hci_hcd * sunxi_hci,int is_on)590 void sunxi_hci_switch_clk(struct sunxi_hci_hcd *sunxi_hci, int is_on)
591 {
592 int val = 0;
593 val = USBC_Readl(sunxi_hci->usb_vbase + SUNXI_USB_PMU_IRQ_ENABLE);
594 if (is_on)
595 val |= 0x01 << 31;
596 else
597 val &= ~(0x01 << 31);
598 USBC_Writel(val, (sunxi_hci->usb_vbase + SUNXI_USB_PMU_IRQ_ENABLE));
599 }
sunxi_hci_set_rcgating(struct sunxi_hci_hcd * sunxi_hci,int is_on)600 void sunxi_hci_set_rcgating(struct sunxi_hci_hcd *sunxi_hci, int is_on)
601 {
602 int val = 0;
603 val = USBC_Readl(sunxi_hci->usb_vbase + SUNXI_USB_PMU_IRQ_ENABLE);
604 if (is_on)
605 val |= 0x01 << 3;
606 else
607 val &= ~(0x01 << 3);
608 USBC_Writel(val, (sunxi_hci->usb_vbase + SUNXI_USB_PMU_IRQ_ENABLE));
609 }
610 #endif
611 /*
612 * Low-power mode USB standby helper functions.
613 */
614 #if IS_ENABLED(SUNXI_USB_STANDBY_LOW_POW_MODE)
sunxi_hci_set_siddq(struct sunxi_hci_hcd * sunxi_hci,int is_on)615 void sunxi_hci_set_siddq(struct sunxi_hci_hcd *sunxi_hci, int is_on)
616 {
617 int reg_value = 0;
618
619 reg_value = USBC_Readl(sunxi_hci->usb_vbase + SUNXI_HCI_PHY_CTRL);
620
621 if (is_on)
622 reg_value |= 0x01 << SUNXI_HCI_PHY_CTRL_SIDDQ;
623 else
624 reg_value &= ~(0x01 << SUNXI_HCI_PHY_CTRL_SIDDQ);
625
626 USBC_Writel(reg_value, (sunxi_hci->usb_vbase + SUNXI_HCI_PHY_CTRL));
627 }
628
sunxi_hci_set_wakeup_ctrl(struct sunxi_hci_hcd * sunxi_hci,int is_on)629 void sunxi_hci_set_wakeup_ctrl(struct sunxi_hci_hcd *sunxi_hci, int is_on)
630 {
631 int reg_value = 0;
632
633 reg_value = USBC_Readl(sunxi_hci->usb_vbase + SUNXI_HCI_CTRL_3);
634
635 if (is_on)
636 reg_value |= 0x01 << SUNXI_HCI_CTRL_3_REMOTE_WAKEUP;
637 else
638 reg_value &= ~(0x01 << SUNXI_HCI_CTRL_3_REMOTE_WAKEUP);
639
640 USBC_Writel(reg_value, (sunxi_hci->usb_vbase + SUNXI_HCI_CTRL_3));
641 }
642
sunxi_hci_set_rc_clk(struct sunxi_hci_hcd * sunxi_hci,int is_on)643 void sunxi_hci_set_rc_clk(struct sunxi_hci_hcd *sunxi_hci, int is_on)
644 {
645 int reg_value = 0;
646
647 reg_value = USBC_Readl(sunxi_hci->usb_vbase + SUNXI_USB_PMU_IRQ_ENABLE);
648
649 if (is_on)
650 reg_value |= 0x01 << SUNXI_HCI_RC16M_CLK_ENBALE;
651 else
652 reg_value &= ~(0x01 << SUNXI_HCI_RC16M_CLK_ENBALE);
653
654 USBC_Writel(reg_value, (sunxi_hci->usb_vbase + SUNXI_USB_PMU_IRQ_ENABLE));
655 }
656
657 #if defined(CONFIG_ARCH_SUN50IW9)
sunxi_hci_set_standby_irq(struct sunxi_hci_hcd * sunxi_hci,int is_on)658 void sunxi_hci_set_standby_irq(struct sunxi_hci_hcd *sunxi_hci, int is_on)
659 {
660 int reg_value = 0;
661
662 reg_value = USBC_Readl(sunxi_hci->usb_vbase + SUNXI_USB_EHCI_TIME_INT);
663
664 if (is_on)
665 reg_value |= 0x01 << SUNXI_USB_EHCI_STANDBY_IRQ;
666 else
667 reg_value &= ~(0x01 << SUNXI_USB_EHCI_STANDBY_IRQ);
668
669 USBC_Writel(reg_value, (sunxi_hci->usb_vbase + SUNXI_USB_EHCI_TIME_INT));
670 }
671 #endif
672
sunxi_hci_clean_standby_irq(struct sunxi_hci_hcd * sunxi_hci)673 void sunxi_hci_clean_standby_irq(struct sunxi_hci_hcd *sunxi_hci)
674 {
675 int reg_value = 0;
676
677 reg_value = USBC_Readl(sunxi_hci->usb_vbase + SUNXI_USB_EHCI_TIME_INT);
678 reg_value |= 0x01 << SUNXI_USB_EHCI_STANDBY_IRQ_STATUS;
679 USBC_Writel(reg_value, (sunxi_hci->usb_vbase + SUNXI_USB_EHCI_TIME_INT));
680 }
681 #endif
682
open_clock(struct sunxi_hci_hcd * sunxi_hci,u32 ohci)683 static int open_clock(struct sunxi_hci_hcd *sunxi_hci, u32 ohci)
684 {
685 int ret;
686
687 mutex_lock(&usb_clock_lock);
688
689 /*
690 * otg and hci share the same phy in fpga,
691 * so need switch phy to hci here.
692 * Notice: not need any more on new platforms.
693 */
694
695 if (sunxi_hci->hci_regulator) {
696 ret = regulator_enable(sunxi_hci->hci_regulator);
697 if (ret)
698 DMSG_PANIC("ERR:%s hci regulator enable failed\n",
699 sunxi_hci->hci_name);
700 }
701 /* otg and hci0 Controller Shared phy in SUN50I */
702 if (sunxi_hci->usbc_no == HCI0_USBC_NO)
703 USBC_SelectPhyToHci(sunxi_hci);
704
705 /* To fix hardware design issue. */
706 #if defined(CONFIG_ARCH_SUN8IW12) || defined(CONFIG_ARCH_SUN50IW3) \
707 || defined(CONFIG_ARCH_SUN50IW6)
708 usb_hci_utmi_phy_tune(sunxi_hci, SUNXI_TX_RES_TUNE, SUNXI_TX_RES_TUNE_OFFSET, 0x3);
709 usb_hci_utmi_phy_tune(sunxi_hci, SUNXI_TX_VREF_TUNE, SUNXI_TX_VREF_TUNE_OFFSET, 0xc);
710 #endif
711
712 #if defined(CONFIG_ARCH_SUN8IW18)
713 usb_hci_utmi_phy_tune(sunxi_hci, SUNXI_TX_PREEMPAMP_TUNE, SUNXI_TX_PREEMPAMP_TUNE_OFFSET, 0x10);
714 usb_hci_utmi_phy_tune(sunxi_hci, SUNXI_TX_VREF_TUNE, SUNXI_TX_VREF_TUNE_OFFSET, 0xc);
715 #endif
716
717 #if defined(CONFIG_ARCH_SUN8IW7) || defined(CONFIG_ARCH_SUN8IW15)
718 usb_hci_utmi_phy_tune(sunxi_hci, SUNXI_TX_VREF_TUNE, SUNXI_TX_VREF_TUNE_OFFSET, 0x4);
719 #endif
720
721 #if defined(CONFIG_ARCH_SUN50IW9)
722 usb_hci_utmi_phy_tune(sunxi_hci, SUNXI_TX_PREEMPAMP_TUNE, SUNXI_TX_PREEMPAMP_TUNE_OFFSET, 0x2);
723 #endif
724
725 if (!sunxi_hci->clk_is_open) {
726 sunxi_hci->clk_is_open = 1;
727
728 if (sunxi_hci->reset_phy) {
729 ret = reset_control_deassert(sunxi_hci->reset_phy);
730 if (ret) {
731 dev_err(&sunxi_hci->pdev->dev, "reset phy err, return %d\n", ret);
732 return ret;
733 }
734 }
735
736 if (sunxi_hci->reset_hci) {
737 ret = reset_control_deassert(sunxi_hci->reset_hci);
738 if (ret) {
739 dev_err(&sunxi_hci->pdev->dev, "reset hci err, return %d\n", ret);
740 return ret;
741 }
742 }
743
744 if (sunxi_hci->clk_bus_hci) {
745 ret = clk_prepare_enable(sunxi_hci->clk_bus_hci);
746 if (ret) {
747 dev_err(&sunxi_hci->pdev->dev, "enable clk_bus_hci err, return %d\n", ret);
748 return ret;
749 }
750 }
751
752 if (sunxi_hci->clk_ohci) {
753 if (strstr(sunxi_hci->hci_name, "ohci")) {
754 ret = clk_prepare_enable(sunxi_hci->clk_ohci);
755 if (ret) {
756 dev_err(&sunxi_hci->pdev->dev,
757 "enable clk_ohci err, return %d\n", ret);
758 return ret;
759 }
760 }
761 }
762
763
764 udelay(10);
765
766 if (sunxi_hci->hsic_flag) {
767 printk("%s()%d yhs\n", __func__, __LINE__);
768 if (sunxi_hci->hsic_ctrl_flag) {
769 if (sunxi_hci->hsic_enable_flag) {
770 if (clk_prepare_enable(sunxi_hci->pll_hsic))
771 DMSG_PANIC("ERR:try to prepare_enable %s pll_hsic failed!\n",
772 sunxi_hci->hci_name);
773
774 if (clk_prepare_enable(sunxi_hci->clk_usbhsic12m))
775 DMSG_PANIC("ERR:try to prepare_enable %s clk_usbhsic12m failed!\n",
776 sunxi_hci->hci_name);
777
778 if (clk_prepare_enable(sunxi_hci->hsic_usbphy))
779 DMSG_PANIC("ERR:try to prepare_enable %s_hsic_usbphy failed!\n",
780 sunxi_hci->hci_name);
781 }
782 } else {
783 if (clk_prepare_enable(sunxi_hci->pll_hsic))
784 DMSG_PANIC("ERR:try to prepare_enable %s pll_hsic failed!\n",
785 sunxi_hci->hci_name);
786
787 if (clk_prepare_enable(sunxi_hci->clk_usbhsic12m))
788 DMSG_PANIC("ERR:try to prepare_enable %s clk_usbhsic12m failed!\n",
789 sunxi_hci->hci_name);
790
791 if (clk_prepare_enable(sunxi_hci->hsic_usbphy))
792 DMSG_PANIC("ERR:try to prepare_enable %s_hsic_usbphy failed!\n",
793 sunxi_hci->hci_name);
794 }
795 } else {
796 if (sunxi_hci->clk_phy) {
797 ret = clk_prepare_enable(sunxi_hci->clk_phy);
798 if (ret) {
799 dev_err(&sunxi_hci->pdev->dev, "enable clk_phy err, return %d\n", ret);
800 return ret;
801 }
802 }
803 }
804
805 udelay(10);
806
807 } else {
808 DMSG_PANIC("[%s]: wrn: open clock failed, (%d, 0x%p)\n",
809 sunxi_hci->hci_name,
810 sunxi_hci->clk_is_open,
811 sunxi_hci->mod_usb);
812 }
813
814 USBC_Clean_SIDDP(sunxi_hci);
815 #if !defined(CONFIG_ARCH_SUN8IW12) && !defined(CONFIG_ARCH_SUN50IW3) \
816 && !defined(CONFIG_ARCH_SUN8IW6) && !defined(CONFIG_ARCH_SUN50IW6) \
817 && !defined(CONFIG_ARCH_SUN8IW15) && !defined(CONFIG_ARCH_SUN50IW8) \
818 && !defined(CONFIG_ARCH_SUN8IW18) && !defined(CONFIG_ARCH_SUN8IW16) \
819 && !defined(CONFIG_ARCH_SUN50IW9) && !defined(CONFIG_ARCH_SUN50IW10) \
820 && !defined(CONFIG_ARCH_SUN8IW19) && !defined(CONFIG_ARCH_SUN50IW11) \
821 && !defined(CONFIG_ARCH_SUN8IW20) && !defined(CONFIG_ARCH_SUN20IW1) \
822 && !defined(CONFIG_ARCH_SUN50IW12)
823 usb_phyx_tp_write(sunxi_hci, 0x2a, 3, 2);
824 #endif
825
826 #if defined(CONFIG_ARCH_SUN8IW20) || defined(CONFIG_ARCH_SUN20IW1)
827 usb_new_phy_init(sunxi_hci);
828 #endif
829
830 mutex_unlock(&usb_clock_lock);
831
832 return 0;
833 }
834
close_clock(struct sunxi_hci_hcd * sunxi_hci,u32 ohci)835 static int close_clock(struct sunxi_hci_hcd *sunxi_hci, u32 ohci)
836 {
837 if (sunxi_hci->clk_is_open) {
838 sunxi_hci->clk_is_open = 0;
839
840 if (sunxi_hci->hsic_flag) {
841 if (sunxi_hci->hsic_ctrl_flag) {
842 if (sunxi_hci->hsic_enable_flag) {
843 clk_disable_unprepare(sunxi_hci->clk_usbhsic12m);
844 clk_disable_unprepare(sunxi_hci->hsic_usbphy);
845 clk_disable_unprepare(sunxi_hci->pll_hsic);
846 }
847 } else {
848 clk_disable_unprepare(sunxi_hci->clk_usbhsic12m);
849 clk_disable_unprepare(sunxi_hci->hsic_usbphy);
850 clk_disable_unprepare(sunxi_hci->pll_hsic);
851 }
852 } else {
853 if (sunxi_hci->clk_phy)
854 clk_disable_unprepare(sunxi_hci->clk_phy);
855 }
856
857 if (strstr(sunxi_hci->hci_name, "ohci"))
858 if (sunxi_hci->clk_ohci)
859 clk_disable_unprepare(sunxi_hci->clk_ohci);
860
861 if (sunxi_hci->clk_bus_hci)
862 clk_disable_unprepare(sunxi_hci->clk_bus_hci);
863
864 if (sunxi_hci->reset_hci)
865 reset_control_assert(sunxi_hci->reset_hci);
866
867 if (sunxi_hci->reset_phy)
868 reset_control_deassert(sunxi_hci->reset_phy);
869
870 udelay(10);
871 } else {
872 DMSG_PANIC("[%s]: wrn: open clock failed, (%d, 0x%p)\n",
873 sunxi_hci->hci_name,
874 sunxi_hci->clk_is_open,
875 sunxi_hci->mod_usb);
876 }
877 return 0;
878 }
879
usb_get_hsic_phy_ctrl(int value,int enable)880 static int usb_get_hsic_phy_ctrl(int value, int enable)
881 {
882 if (enable) {
883 value |= (0x07<<8);
884 value |= (0x01<<1);
885 value |= (0x01<<0);
886 value |= (0x01<<16);
887 value |= (0x01<<20);
888 } else {
889 value &= ~(0x07<<8);
890 value &= ~(0x01<<1);
891 value &= ~(0x01<<0);
892 value &= ~(0x01<<16);
893 value &= ~(0x01<<20);
894 }
895
896 return value;
897 }
898
__usb_passby(struct sunxi_hci_hcd * sunxi_hci,u32 enable,atomic_t * usb_enable_passly_cnt)899 static void __usb_passby(struct sunxi_hci_hcd *sunxi_hci, u32 enable,
900 atomic_t *usb_enable_passly_cnt)
901 {
902 unsigned long reg_value = 0;
903
904 reg_value = USBC_Readl(sunxi_hci->usb_vbase + SUNXI_USB_PMU_IRQ_ENABLE);
905 if (enable && (atomic_read(usb_enable_passly_cnt) == 0)) {
906 if (sunxi_hci->hsic_flag) {
907 reg_value = usb_get_hsic_phy_ctrl(reg_value, enable);
908 } else {
909 /* AHB Master interface INCR8 enable */
910 reg_value |= (1 << 10);
911 /* AHB Master interface burst type INCR4 enable */
912 reg_value |= (1 << 9);
913 /* AHB Master interface INCRX align enable */
914 reg_value |= (1 << 8);
915 if (sunxi_hci->usbc_no == HCI0_USBC_NO)
916 #ifdef SUNXI_USB_FPGA
917 /* enable ULPI, disable UTMI */
918 reg_value |= (0 << 0);
919 #else
920 /* enable UTMI, disable ULPI */
921 reg_value |= (1 << 0);
922 #endif
923 else
924 /* ULPI bypass enable */
925 reg_value |= (1 << 0);
926 }
927 } else if (!enable && (atomic_read(usb_enable_passly_cnt) == 1)) {
928 if (sunxi_hci->hsic_flag) {
929 reg_value = usb_get_hsic_phy_ctrl(reg_value, enable);
930 } else {
931 /* AHB Master interface INCR8 disable */
932 reg_value &= ~(1 << 10);
933 /* AHB Master interface burst type INCR4 disable */
934 reg_value &= ~(1 << 9);
935 /* AHB Master interface INCRX align disable */
936 reg_value &= ~(1 << 8);
937 /* ULPI bypass disable */
938 reg_value &= ~(1 << 0);
939 }
940 }
941 USBC_Writel(reg_value,
942 (sunxi_hci->usb_vbase + SUNXI_USB_PMU_IRQ_ENABLE));
943
944 if (enable)
945 atomic_add(1, usb_enable_passly_cnt);
946 else
947 atomic_sub(1, usb_enable_passly_cnt);
948 }
949
usb_passby(struct sunxi_hci_hcd * sunxi_hci,u32 enable)950 static void usb_passby(struct sunxi_hci_hcd *sunxi_hci, u32 enable)
951 {
952 spinlock_t lock;
953 unsigned long flags = 0;
954
955 mutex_lock(&usb_passby_lock);
956
957 spin_lock_init(&lock);
958 spin_lock_irqsave(&lock, flags);
959 /* enable passby */
960 if (sunxi_hci->usbc_no == HCI0_USBC_NO) {
961 __usb_passby(sunxi_hci, enable, &usb1_enable_passly_cnt);
962 } else if (sunxi_hci->usbc_no == HCI1_USBC_NO) {
963 __usb_passby(sunxi_hci, enable, &usb2_enable_passly_cnt);
964 } else if (sunxi_hci->usbc_no == HCI2_USBC_NO) {
965 __usb_passby(sunxi_hci, enable, &usb3_enable_passly_cnt);
966 } else if (sunxi_hci->usbc_no == HCI3_USBC_NO) {
967 __usb_passby(sunxi_hci, enable, &usb4_enable_passly_cnt);
968 } else {
969 DMSG_PANIC("EER: unknown usbc_no(%d)\n", sunxi_hci->usbc_no);
970 spin_unlock_irqrestore(&lock, flags);
971
972 mutex_unlock(&usb_passby_lock);
973 return;
974 }
975
976 spin_unlock_irqrestore(&lock, flags);
977
978 mutex_unlock(&usb_passby_lock);
979 }
980
alloc_pin(struct sunxi_hci_hcd * sunxi_hci)981 static int alloc_pin(struct sunxi_hci_hcd *sunxi_hci)
982 {
983 u32 ret = 1;
984
985 if (sunxi_hci->hsic_flag) {
986 /* Marvell 4G HSIC ctrl */
987 if (sunxi_hci->usb_host_hsic_rdy_valid) {
988 ret = gpio_request(sunxi_hci->usb_host_hsic_rdy.gpio, NULL);
989 if (ret != 0) {
990 DMSG_PANIC("ERR: gpio_request failed\n");
991 sunxi_hci->usb_host_hsic_rdy_valid = 0;
992 } else {
993 gpio_direction_output(sunxi_hci->usb_host_hsic_rdy.gpio, 0);
994 }
995 }
996
997 /* SMSC usb3503 HSIC HUB ctrl */
998 if (sunxi_hci->usb_hsic_usb3503_flag) {
999 if (sunxi_hci->usb_hsic_hub_connect_valid) {
1000 ret = gpio_request(sunxi_hci->usb_hsic_hub_connect.gpio, NULL);
1001 if (ret != 0) {
1002 DMSG_PANIC("ERR: gpio_request failed\n");
1003 sunxi_hci->usb_hsic_hub_connect_valid = 0;
1004 } else {
1005 gpio_direction_output(sunxi_hci->usb_hsic_hub_connect.gpio, 1);
1006 }
1007 }
1008
1009 if (sunxi_hci->usb_hsic_int_n_valid) {
1010 ret = gpio_request(sunxi_hci->usb_hsic_int_n.gpio, NULL);
1011 if (ret != 0) {
1012 DMSG_PANIC("ERR: gpio_request failed\n");
1013 sunxi_hci->usb_hsic_int_n_valid = 0;
1014 } else {
1015 gpio_direction_output(sunxi_hci->usb_hsic_int_n.gpio, 1);
1016 }
1017 }
1018
1019 msleep(20);
1020
1021 if (sunxi_hci->usb_hsic_reset_n_valid) {
1022 ret = gpio_request(sunxi_hci->usb_hsic_reset_n.gpio, NULL);
1023 if (ret != 0) {
1024 DMSG_PANIC("ERR: gpio_request failed\n");
1025 sunxi_hci->usb_hsic_reset_n_valid = 0;
1026 } else {
1027 gpio_direction_output(sunxi_hci->usb_hsic_reset_n.gpio, 1);
1028 }
1029 }
1030
1031 /**
1032 * usb3503 device goto hub connect status
1033 * is need 100ms after reset
1034 */
1035 msleep(100);
1036 }
1037 }
1038
1039 return 0;
1040 }
1041
free_pin(struct sunxi_hci_hcd * sunxi_hci)1042 static void free_pin(struct sunxi_hci_hcd *sunxi_hci)
1043 {
1044 if (sunxi_hci->hsic_flag) {
1045 /* Marvell 4G HSIC ctrl */
1046 if (sunxi_hci->usb_host_hsic_rdy_valid) {
1047 gpio_free(sunxi_hci->usb_host_hsic_rdy.gpio);
1048 sunxi_hci->usb_host_hsic_rdy_valid = 0;
1049 }
1050
1051 /* SMSC usb3503 HSIC HUB ctrl */
1052 if (sunxi_hci->usb_hsic_usb3503_flag) {
1053 if (sunxi_hci->usb_hsic_hub_connect_valid) {
1054 gpio_free(sunxi_hci->usb_hsic_hub_connect.gpio);
1055 sunxi_hci->usb_hsic_hub_connect_valid = 0;
1056 }
1057
1058 if (sunxi_hci->usb_hsic_int_n_valid) {
1059 gpio_free(sunxi_hci->usb_hsic_int_n.gpio);
1060 sunxi_hci->usb_hsic_int_n_valid = 0;
1061 }
1062
1063 if (sunxi_hci->usb_hsic_reset_n_valid) {
1064 gpio_free(sunxi_hci->usb_hsic_reset_n.gpio);
1065 sunxi_hci->usb_hsic_reset_n_valid = 0;
1066 }
1067 }
1068 }
1069 }
1070
sunxi_set_host_hisc_rdy(struct sunxi_hci_hcd * sunxi_hci,int is_on)1071 void sunxi_set_host_hisc_rdy(struct sunxi_hci_hcd *sunxi_hci, int is_on)
1072 {
1073 if (sunxi_hci->usb_host_hsic_rdy_valid) {
1074 /* set config, output */
1075 gpio_direction_output(sunxi_hci->usb_host_hsic_rdy.gpio, is_on);
1076 }
1077 }
1078 EXPORT_SYMBOL(sunxi_set_host_hisc_rdy);
1079
sunxi_set_host_vbus(struct sunxi_hci_hcd * sunxi_hci,int is_on)1080 void sunxi_set_host_vbus(struct sunxi_hci_hcd *sunxi_hci, int is_on)
1081 {
1082 int ret;
1083
1084 if (sunxi_hci->supply) {
1085 if (is_on) {
1086 ret = regulator_enable(sunxi_hci->supply);
1087 if (ret)
1088 DMSG_PANIC("ERR: %s regulator enable failed\n",
1089 sunxi_hci->hci_name);
1090 } else {
1091 ret = regulator_disable(sunxi_hci->supply);
1092 if (ret)
1093 DMSG_PANIC("ERR: %s regulator force disable failed\n",
1094 sunxi_hci->hci_name);
1095 }
1096 }
1097 }
1098 EXPORT_SYMBOL(sunxi_set_host_vbus);
1099
__sunxi_set_vbus(struct sunxi_hci_hcd * sunxi_hci,int is_on)1100 static void __sunxi_set_vbus(struct sunxi_hci_hcd *sunxi_hci, int is_on)
1101 {
1102 int ret;
1103
1104 /* set power flag */
1105 sunxi_hci->power_flag = is_on;
1106
1107 if (sunxi_hci->hsic_flag) {
1108 if ((sunxi_hci->hsic_regulator_io != NULL) &&
1109 (sunxi_hci->hsic_regulator_io_hdle != NULL)) {
1110 if (is_on) {
1111 if (regulator_enable(sunxi_hci->hsic_regulator_io_hdle) < 0)
1112 DMSG_INFO("%s: hsic_regulator_enable fail\n",
1113 sunxi_hci->hci_name);
1114 } else {
1115 if (regulator_disable(sunxi_hci->hsic_regulator_io_hdle) < 0)
1116 DMSG_INFO("%s: hsic_regulator_disable fail\n",
1117 sunxi_hci->hci_name);
1118 }
1119 }
1120 }
1121
1122 if (sunxi_hci->supply) {
1123 if (is_on) {
1124 ret = regulator_enable(sunxi_hci->supply);
1125 if (ret)
1126 DMSG_PANIC("ERR: %s regulator enable failed\n",
1127 sunxi_hci->hci_name);
1128 } else {
1129 ret = regulator_disable(sunxi_hci->supply);
1130 if (ret)
1131 DMSG_PANIC("ERR: %s regulator force disable failed\n",
1132 sunxi_hci->hci_name);
1133 }
1134 }
1135
1136 if (sunxi_hci->hci_regulator) {
1137 if (!is_on) {
1138 ret = regulator_disable(sunxi_hci->hci_regulator);
1139 if (ret)
1140 DMSG_PANIC("ERR: %s hci regulator force disable failed\n",
1141 sunxi_hci->hci_name);
1142 }
1143 }
1144 }
1145
sunxi_set_vbus(struct sunxi_hci_hcd * sunxi_hci,int is_on)1146 static void sunxi_set_vbus(struct sunxi_hci_hcd *sunxi_hci, int is_on)
1147 {
1148 mutex_lock(&usb_vbus_lock);
1149
1150 if (sunxi_hci->usbc_no == HCI0_USBC_NO) {
1151 if (is_on)
1152 __sunxi_set_vbus(sunxi_hci, is_on); /* power on */
1153 else if (!is_on)
1154 __sunxi_set_vbus(sunxi_hci, is_on); /* power off */
1155 } else if (sunxi_hci->usbc_no == HCI1_USBC_NO) {
1156 if (is_on)
1157 __sunxi_set_vbus(sunxi_hci, is_on); /* power on */
1158 else if (!is_on)
1159 __sunxi_set_vbus(sunxi_hci, is_on); /* power off */
1160 } else if (sunxi_hci->usbc_no == HCI2_USBC_NO) {
1161 if (is_on)
1162 __sunxi_set_vbus(sunxi_hci, is_on); /* power on */
1163 else if (!is_on)
1164 __sunxi_set_vbus(sunxi_hci, is_on); /* power off */
1165 } else if (sunxi_hci->usbc_no == HCI3_USBC_NO) {
1166 if (is_on)
1167 __sunxi_set_vbus(sunxi_hci, is_on); /* power on */
1168 else if (!is_on)
1169 __sunxi_set_vbus(sunxi_hci, is_on); /* power off */
1170 } else {
1171 DMSG_INFO("[%s]: sunxi_set_vbus no: %d\n",
1172 sunxi_hci->hci_name, sunxi_hci->usbc_no);
1173 }
1174
1175 mutex_unlock(&usb_vbus_lock);
1176 }
1177
sunxi_get_hci_base(struct platform_device * pdev,struct sunxi_hci_hcd * sunxi_hci)1178 static int sunxi_get_hci_base(struct platform_device *pdev,
1179 struct sunxi_hci_hcd *sunxi_hci)
1180 {
1181 struct device_node *np = pdev->dev.of_node;
1182 int ret = 0;
1183
1184 sunxi_hci->usb_vbase = of_iomap(np, 0);
1185 if (sunxi_hci->usb_vbase == NULL) {
1186 dev_err(&pdev->dev, "%s, can't get vbase resource\n",
1187 sunxi_hci->hci_name);
1188 return -EINVAL;
1189 }
1190
1191 if (strstr(sunxi_hci->hci_name, "ohci"))
1192 sunxi_hci->usb_vbase -= SUNXI_USB_OHCI_BASE_OFFSET;
1193
1194 sunxi_hci->otg_vbase = of_iomap(np, 2);
1195 if (sunxi_hci->otg_vbase == NULL) {
1196 dev_err(&pdev->dev, "%s, can't get otg_vbase resource\n",
1197 sunxi_hci->hci_name);
1198 return -EINVAL;
1199 }
1200
1201 #if defined(CONFIG_ARCH_SUN50IW10)
1202 sunxi_hci->prcm = of_iomap(np, 3);
1203 if (sunxi_hci->prcm == NULL) {
1204 dev_err(&pdev->dev, "%s, can't get prcm resource\n",
1205 sunxi_hci->hci_name);
1206 return -EINVAL;
1207 }
1208
1209 if (sunxi_hci->usbc_no == HCI0_USBC_NO) {
1210 sunxi_hci->usb_ccmu_config = of_iomap(np, 4);
1211 if (sunxi_hci->usb_ccmu_config == NULL) {
1212 dev_err(&pdev->dev, "%s, can't get ccmu resource\n",
1213 sunxi_hci->hci_name);
1214 return -EINVAL;
1215 }
1216
1217 sunxi_hci->usb_common_phy_config = of_iomap(np, 5);
1218 if (sunxi_hci->usb_common_phy_config == NULL) {
1219 dev_err(&pdev->dev, "%s, can't get common phy resource\n",
1220 sunxi_hci->hci_name);
1221 return -EINVAL;
1222 }
1223 }
1224 #endif
1225
1226 sunxi_hci->usb_base_res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1227 if (sunxi_hci->usb_base_res == NULL) {
1228 dev_err(&pdev->dev, "%s, can't alloc mem\n",
1229 sunxi_hci->hci_name);
1230 return -ENOMEM;
1231 }
1232
1233 ret = of_address_to_resource(np, 0, sunxi_hci->usb_base_res);
1234 if (ret)
1235 dev_err(&pdev->dev, "could not get regs\n");
1236
1237 return 0;
1238 }
1239
sunxi_get_hci_clock(struct platform_device * pdev,struct sunxi_hci_hcd * sunxi_hci)1240 static int sunxi_get_hci_clock(struct platform_device *pdev,
1241 struct sunxi_hci_hcd *sunxi_hci)
1242 {
1243 struct device_node *np = pdev->dev.of_node;
1244
1245 if (strstr(sunxi_hci->hci_name, "ehci")) {
1246 if (sunxi_hci->usbc_no == HCI0_USBC_NO) {
1247 sunxi_hci->reset_phy = devm_reset_control_get_shared(&pdev->dev, "phy");
1248 if (IS_ERR(sunxi_hci->reset_phy))
1249 dev_warn(&pdev->dev, "Could not get phy rst share\n");
1250 } else {
1251 sunxi_hci->reset_phy = devm_reset_control_get_optional_shared(&pdev->dev, "phy");
1252 if (IS_ERR(sunxi_hci->reset_phy))
1253 dev_warn(&pdev->dev, "Could not get phy rst\n");
1254 }
1255 }
1256
1257 if (strstr(sunxi_hci->hci_name, "ohci")) {
1258 sunxi_hci->clk_ohci = devm_clk_get(&pdev->dev, "ohci");
1259 if (IS_ERR(sunxi_hci->clk_ohci)) {
1260 dev_err(&pdev->dev, "Could not get ohci clock\n");
1261 return PTR_ERR(sunxi_hci->clk_ohci);
1262 }
1263
1264 sunxi_hci->reset_phy = devm_reset_control_get_shared(&pdev->dev, "phy");
1265 if (IS_ERR(sunxi_hci->reset_phy))
1266 dev_warn(&pdev->dev, "Could not get phy rst share\n");
1267 }
1268
1269 sunxi_hci->clk_bus_hci = devm_clk_get(&pdev->dev, "bus_hci");
1270 if (IS_ERR(sunxi_hci->clk_bus_hci)) {
1271 dev_err(&pdev->dev, "Could not get bus_hci clock\n");
1272 return PTR_ERR(sunxi_hci->clk_bus_hci);
1273 }
1274
1275 #if !defined(CONFIG_ARCH_SUN8IW20) && !defined(CONFIG_ARCH_SUN20IW1) && !defined(CONFIG_ARCH_SUN50IW12)
1276 sunxi_hci->clk_phy = devm_clk_get(&pdev->dev, "phy");
1277 if (IS_ERR(sunxi_hci->clk_phy)) {
1278 dev_err(&pdev->dev, "Could not get phy clock\n");
1279 return PTR_ERR(sunxi_hci->clk_phy);
1280 }
1281 #endif
1282 sunxi_hci->reset_hci = devm_reset_control_get(&pdev->dev, "hci");
1283 if (IS_ERR(sunxi_hci->reset_hci))
1284 dev_warn(&pdev->dev, "Could not get hci rst\n");
1285
1286
1287 if (sunxi_hci->hsic_flag) {
1288 printk("%s()%d yhs\n", __func__, __LINE__);
1289 sunxi_hci->hsic_usbphy = of_clk_get(np, 2);
1290 if (IS_ERR(sunxi_hci->hsic_usbphy)) {
1291 sunxi_hci->hsic_usbphy = NULL;
1292 DMSG_PANIC("ERR: %s get usb hsic_usbphy failed.\n",
1293 sunxi_hci->hci_name);
1294 }
1295
1296 sunxi_hci->clk_usbhsic12m = of_clk_get(np, 3);
1297 if (IS_ERR(sunxi_hci->clk_usbhsic12m)) {
1298 sunxi_hci->clk_usbhsic12m = NULL;
1299 DMSG_PANIC("ERR: %s get usb clk_usbhsic12m failed.\n",
1300 sunxi_hci->hci_name);
1301 }
1302
1303 sunxi_hci->pll_hsic = of_clk_get(np, 4);
1304 if (IS_ERR(sunxi_hci->pll_hsic)) {
1305 sunxi_hci->pll_hsic = NULL;
1306 DMSG_PANIC("ERR: %s get usb pll_hsic failed.\n",
1307 sunxi_hci->hci_name);
1308 }
1309 }
1310
1311 return 0;
1312 }
1313
get_usb_cfg(struct platform_device * pdev,struct sunxi_hci_hcd * sunxi_hci)1314 static int get_usb_cfg(struct platform_device *pdev,
1315 struct sunxi_hci_hcd *sunxi_hci)
1316 {
1317 struct device_node *usbc_np = NULL;
1318 char np_name[10];
1319 int ret = -1;
1320
1321 sprintf(np_name, "usbc%d", sunxi_get_hci_num(pdev));
1322 usbc_np = of_find_node_by_type(NULL, np_name);
1323
1324 /* usbc enable */
1325 ret = of_property_read_string(usbc_np,
1326 "status", &sunxi_hci->used_status);
1327 if (ret) {
1328 DMSG_PRINT("get %s used is fail, %d\n",
1329 sunxi_hci->hci_name, -ret);
1330 sunxi_hci->used = 0;
1331 } else if (!strcmp(sunxi_hci->used_status, "okay")) {
1332 sunxi_hci->used = 1;
1333 } else {
1334 sunxi_hci->used = 0;
1335 }
1336
1337 /* usbc port type */
1338 if (sunxi_hci->usbc_no == HCI0_USBC_NO) {
1339 ret = of_property_read_u32(usbc_np,
1340 KEY_USB_PORT_TYPE,
1341 &sunxi_hci->port_type);
1342 if (ret)
1343 DMSG_INFO("get usb_port_type is fail, %d\n", -ret);
1344 }
1345
1346 sunxi_hci->hsic_flag = 0;
1347
1348 if (sunxi_hci->usbc_no == HCI1_USBC_NO) {
1349 ret = of_property_read_u32(usbc_np,
1350 KEY_USB_HSIC_USBED, &sunxi_hci->hsic_flag);
1351 if (ret)
1352 sunxi_hci->hsic_flag = 0;
1353
1354 if (sunxi_hci->hsic_flag) {
1355 if (!strncmp(sunxi_hci->hci_name,
1356 "ohci", strlen("ohci"))) {
1357 DMSG_PRINT("HSIC is no susport in %s, and to return\n",
1358 sunxi_hci->hci_name);
1359 sunxi_hci->used = 0;
1360 return 0;
1361 }
1362
1363 /* hsic regulator_io */
1364 ret = of_property_read_string(usbc_np,
1365 KEY_USB_HSIC_REGULATOR_IO,
1366 &sunxi_hci->hsic_regulator_io);
1367 if (ret) {
1368 DMSG_PRINT("get %s, hsic_regulator_io is fail, %d\n",
1369 sunxi_hci->hci_name, -ret);
1370 sunxi_hci->hsic_regulator_io = NULL;
1371 } else {
1372 if (!strcmp(sunxi_hci->hsic_regulator_io, "nocare")) {
1373 DMSG_PRINT("get %s, hsic_regulator_io is no nocare\n",
1374 sunxi_hci->hci_name);
1375 sunxi_hci->hsic_regulator_io = NULL;
1376 }
1377 }
1378
1379 /* Marvell 4G HSIC ctrl */
1380 ret = of_property_read_u32(usbc_np,
1381 KEY_USB_HSIC_CTRL,
1382 &sunxi_hci->hsic_ctrl_flag);
1383 if (ret) {
1384 DMSG_PRINT("get %s usb_hsic_ctrl is fail, %d\n",
1385 sunxi_hci->hci_name, -ret);
1386 sunxi_hci->hsic_ctrl_flag = 0;
1387 }
1388 if (sunxi_hci->hsic_ctrl_flag) {
1389 sunxi_hci->usb_host_hsic_rdy.gpio =
1390 of_get_named_gpio(usbc_np,
1391 KEY_USB_HSIC_RDY_GPIO, 0);
1392 if (gpio_is_valid(sunxi_hci->usb_host_hsic_rdy.gpio)) {
1393 sunxi_hci->usb_host_hsic_rdy_valid = 1;
1394 } else {
1395 sunxi_hci->usb_host_hsic_rdy_valid = 0;
1396 DMSG_PRINT("get %s drv_vbus_gpio is fail\n",
1397 sunxi_hci->hci_name);
1398 }
1399 } else {
1400 sunxi_hci->usb_host_hsic_rdy_valid = 0;
1401 }
1402
1403 /* SMSC usb3503 HSIC HUB ctrl */
1404 ret = of_property_read_u32(usbc_np,
1405 "usb_hsic_usb3503_flag",
1406 &sunxi_hci->usb_hsic_usb3503_flag);
1407 if (ret) {
1408 DMSG_PRINT("get %s usb_hsic_usb3503_flag is fail, %d\n",
1409 sunxi_hci->hci_name, -ret);
1410 sunxi_hci->usb_hsic_usb3503_flag = 0;
1411 }
1412
1413
1414 if (sunxi_hci->usb_hsic_usb3503_flag) {
1415 sunxi_hci->usb_hsic_hub_connect.gpio =
1416 of_get_named_gpio(usbc_np,
1417 "usb_hsic_hub_connect_gpio", 0);
1418 if (gpio_is_valid(sunxi_hci->usb_hsic_hub_connect.gpio)) {
1419 sunxi_hci->usb_hsic_hub_connect_valid = 1;
1420 } else {
1421 sunxi_hci->usb_hsic_hub_connect_valid = 0;
1422 DMSG_PRINT("get %s usb_hsic_hub_connect is fail\n",
1423 sunxi_hci->hci_name);
1424 }
1425
1426
1427 sunxi_hci->usb_hsic_int_n.gpio =
1428 of_get_named_gpio(usbc_np,
1429 "usb_hsic_int_n_gpio", 0);
1430 if (gpio_is_valid(sunxi_hci->usb_hsic_int_n.gpio)) {
1431 sunxi_hci->usb_hsic_int_n_valid = 1;
1432 } else {
1433 sunxi_hci->usb_hsic_int_n_valid = 0;
1434 DMSG_PRINT("get %s usb_hsic_int_n is fail\n",
1435 sunxi_hci->hci_name);
1436 }
1437
1438
1439 sunxi_hci->usb_hsic_reset_n.gpio =
1440 of_get_named_gpio(usbc_np,
1441 "usb_hsic_reset_n_gpio", 0);
1442 if (gpio_is_valid(sunxi_hci->usb_hsic_reset_n.gpio)) {
1443 sunxi_hci->usb_hsic_reset_n_valid = 1;
1444 } else {
1445 sunxi_hci->usb_hsic_reset_n_valid = 0;
1446 DMSG_PRINT("get %s usb_hsic_reset_n is fail\n",
1447 sunxi_hci->hci_name);
1448 }
1449
1450 } else {
1451 sunxi_hci->usb_hsic_hub_connect_valid = 0;
1452 sunxi_hci->usb_hsic_int_n_valid = 0;
1453 sunxi_hci->usb_hsic_reset_n_valid = 0;
1454 }
1455
1456 } else {
1457 sunxi_hci->hsic_ctrl_flag = 0;
1458 sunxi_hci->usb_host_hsic_rdy_valid = 0;
1459 sunxi_hci->usb_hsic_hub_connect_valid = 0;
1460 sunxi_hci->usb_hsic_int_n_valid = 0;
1461 sunxi_hci->usb_hsic_reset_n_valid = 0;
1462 }
1463 }
1464
1465 /* usbc wakeup_suspend */
1466 ret = of_property_read_u32(usbc_np,
1467 KEY_USB_WAKEUP_SUSPEND,
1468 &sunxi_hci->wakeup_suspend);
1469 if (ret) {
1470 DMSG_PRINT("get %s wakeup_suspend is fail, %d\n",
1471 sunxi_hci->hci_name, -ret);
1472 }
1473
1474 /* wakeup-source */
1475 if (of_property_read_bool(usbc_np, KEY_WAKEUP_SOURCE)) {
1476 sunxi_hci->wakeup_source_flag = 1;
1477 } else {
1478 DMSG_PRINT("get %s wakeup-source is fail.\n",
1479 sunxi_hci->hci_name);
1480 sunxi_hci->wakeup_source_flag = 0;
1481 }
1482
1483 return 0;
1484 }
1485
sunxi_get_hci_num(struct platform_device * pdev)1486 int sunxi_get_hci_num(struct platform_device *pdev)
1487 {
1488 struct device_node *np = pdev->dev.of_node;
1489 int ret = 0;
1490 int hci_num = 0;
1491
1492 ret = of_property_read_u32(np, HCI_USBC_NO, &hci_num);
1493 if (ret)
1494 DMSG_PANIC("get hci_ctrl_num is fail, %d\n", -ret);
1495
1496 return hci_num;
1497 }
1498
sunxi_get_hci_name(struct platform_device * pdev,struct sunxi_hci_hcd * sunxi_hci)1499 static int sunxi_get_hci_name(struct platform_device *pdev,
1500 struct sunxi_hci_hcd *sunxi_hci)
1501 {
1502 struct device_node *np = pdev->dev.of_node;
1503
1504 sprintf(sunxi_hci->hci_name, "%s", np->name);
1505
1506 return 0;
1507 }
1508
sunxi_get_hci_irq_no(struct platform_device * pdev,struct sunxi_hci_hcd * sunxi_hci)1509 static int sunxi_get_hci_irq_no(struct platform_device *pdev,
1510 struct sunxi_hci_hcd *sunxi_hci)
1511 {
1512 sunxi_hci->irq_no = platform_get_irq(pdev, 0);
1513
1514 return 0;
1515 }
1516
hci_wakeup_source_init(struct platform_device * pdev,struct sunxi_hci_hcd * sunxi_hci)1517 static int hci_wakeup_source_init(struct platform_device *pdev,
1518 struct sunxi_hci_hcd *sunxi_hci)
1519 {
1520 if (sunxi_hci->wakeup_source_flag) {
1521 device_init_wakeup(&pdev->dev, true);
1522 dev_pm_set_wake_irq(&pdev->dev, sunxi_hci->irq_no);
1523 } else {
1524 DMSG_INFO("sunxi %s don't init wakeup source\n", sunxi_hci->hci_name);
1525 }
1526
1527 return 0;
1528 }
enter_usb_standby(struct sunxi_hci_hcd * sunxi_hci)1529 void enter_usb_standby(struct sunxi_hci_hcd *sunxi_hci)
1530 {
1531 mutex_lock(&usb_standby_lock);
1532 if (!atomic_read(&usb_standby_cnt)) {
1533 atomic_add(1, &usb_standby_cnt);
1534 } else {
1535 /*phy after ehci and ohci suspend.*/
1536 #if IS_ENABLED(CONFIG_ARCH_SUN50IW10)
1537 if (sunxi_hci->usbc_no == HCI0_USBC_NO) {
1538 /*usb1 0x800 bit[2], enable rc16M*/
1539 sunxi_hci_common_set_rc_clk(sunxi_hci, 1);
1540 /*usb1 0x800 bit[31], switch 16M*/
1541 sunxi_hci_common_switch_clk(sunxi_hci, 1);
1542 /*usb1 0x800 bit[3], open 16M gating*/
1543 sunxi_hci_common_set_rcgating(sunxi_hci, 1);
1544 }
1545 #endif
1546 #if IS_ENABLED(SUNXI_USB_STANDBY_LOW_POW_MODE)
1547 #if IS_ENABLED(SUNXI_USB_STANDBY_NEW_MODE)
1548 /*phy reg, offset:0x800 bit2, set 1, enable RC16M CLK*/
1549 sunxi_hci_set_rc_clk(sunxi_hci, 1);
1550 #if IS_ENABLED(CONFIG_ARCH_SUN50IW9)
1551 /*enable standby irq*/
1552 sunxi_hci_set_standby_irq(sunxi_hci, 1);
1553 #endif
1554 /*phy reg, offset:0x808 bit3, set 1, remote enable*/
1555 sunxi_hci_set_wakeup_ctrl(sunxi_hci, 1);
1556 /*phy reg, offset:0x810 bit3 set 1, clean siddq*/
1557 sunxi_hci_set_siddq(sunxi_hci, 1);
1558 #endif
1559 #endif
1560 #if IS_ENABLED(CONFIG_ARCH_SUN50IW10)
1561 /*phy reg, offset:0x0 bit31, set 1*/
1562 sunxi_hci_switch_clk(sunxi_hci, 1);
1563 /*phy reg, offset:0x0 bit3, set 1*/
1564 sunxi_hci_set_rcgating(sunxi_hci, 1);
1565 #endif
1566 atomic_sub(1, &usb_standby_cnt);
1567
1568 }
1569 mutex_unlock(&usb_standby_lock);
1570 }
1571 EXPORT_SYMBOL(enter_usb_standby);
1572
exit_usb_standby(struct sunxi_hci_hcd * sunxi_hci)1573 void exit_usb_standby(struct sunxi_hci_hcd *sunxi_hci)
1574 {
1575 mutex_lock(&usb_standby_lock);
1576 if (atomic_read(&usb_standby_cnt)) {
1577 atomic_sub(1, &usb_standby_cnt);
1578 } else {
1579 /*phy before ehci and ohci*/
1580 #if IS_ENABLED(CONFIG_ARCH_SUN50IW10)
1581 if (sunxi_hci->usbc_no == HCI0_USBC_NO) {
1582 /*usb1 0x800 bit[3]*/
1583 sunxi_hci_common_set_rcgating(sunxi_hci, 0);
1584 /*usb1 0x800 bit[31]*/
1585 sunxi_hci_common_switch_clk(sunxi_hci, 0);
1586 /*usb1 0x800 bit[2]*/
1587 sunxi_hci_common_set_rc_clk(sunxi_hci, 0);
1588 }
1589 /*phy reg, offset:0x0 bit3, set 0*/
1590 sunxi_hci_set_rcgating(sunxi_hci, 0);
1591 /*phy reg, offset:0x0 bit31, set 0*/
1592 sunxi_hci_switch_clk(sunxi_hci, 0);
1593 #endif
1594 #if IS_ENABLED(SUNXI_USB_STANDBY_LOW_POW_MODE)
1595 /*phy reg, offset:0x10 bit3 set 0, enable siddq*/
1596 sunxi_hci_set_siddq(sunxi_hci, 0);
1597 /*phy reg, offset:0x08 bit3, set 0, remote disable*/
1598 sunxi_hci_set_wakeup_ctrl(sunxi_hci, 0);
1599 #if IS_ENABLED(SUNXI_USB_STANDBY_NEW_MODE)
1600 #if IS_ENABLED(CONFIG_ARCH_SUN50IW9)
1601 /*clear standby irq status*/
1602 sunxi_hci_clean_standby_irq(sunxi_hci);
1603 /*disable standby irq */
1604 sunxi_hci_set_standby_irq(sunxi_hci, 0);
1605 #endif
1606 #endif
1607 /*phy reg, offset:0x0 bit2, set 0, disable rc clk*/
1608 sunxi_hci_set_rc_clk(sunxi_hci, 0);
1609 #endif
1610 atomic_add(1, &usb_standby_cnt);
1611 }
1612 mutex_unlock(&usb_standby_lock);
1613 }
1614 EXPORT_SYMBOL(exit_usb_standby);
1615
sunxi_get_hci_resource(struct platform_device * pdev,struct sunxi_hci_hcd * sunxi_hci,int usbc_no)1616 static int sunxi_get_hci_resource(struct platform_device *pdev,
1617 struct sunxi_hci_hcd *sunxi_hci, int usbc_no)
1618 {
1619 if (sunxi_hci == NULL) {
1620 dev_err(&pdev->dev, "sunxi_hci is NULL\n");
1621 return -1;
1622 }
1623
1624 memset(sunxi_hci, 0, sizeof(struct sunxi_hci_hcd));
1625
1626 sunxi_hci->usbc_no = usbc_no;
1627 sunxi_get_hci_name(pdev, sunxi_hci);
1628 get_usb_cfg(pdev, sunxi_hci);
1629
1630 if (sunxi_hci->used == 0) {
1631 DMSG_INFO("sunxi %s is no enable\n", sunxi_hci->hci_name);
1632 return -1;
1633 }
1634
1635 sunxi_get_hci_base(pdev, sunxi_hci);
1636 sunxi_get_hci_clock(pdev, sunxi_hci);
1637 sunxi_get_hci_irq_no(pdev, sunxi_hci);
1638 hci_wakeup_source_init(pdev, sunxi_hci);
1639
1640 request_usb_regulator_io(sunxi_hci);
1641 sunxi_hci->open_clock = open_clock;
1642 sunxi_hci->close_clock = close_clock;
1643 sunxi_hci->set_power = sunxi_set_vbus;
1644 sunxi_hci->usb_passby = usb_passby;
1645
1646 alloc_pin(sunxi_hci);
1647
1648 pdev->dev.platform_data = sunxi_hci;
1649 return 0;
1650 }
1651
sunxi_hci_dump_reg_all(int usbc_type)1652 static int sunxi_hci_dump_reg_all(int usbc_type)
1653 {
1654 struct sunxi_hci_hcd *sunxi_hci, *sunxi_ehci, *sunxi_ohci;
1655 struct resource res, res1;
1656 int i;
1657
1658 switch (usbc_type) {
1659 case SUNXI_USB_EHCI:
1660 for (i = 0; i < 4; i++) {
1661 switch (i) {
1662 case HCI0_USBC_NO:
1663 sunxi_hci = &sunxi_ehci0;
1664 break;
1665 case HCI1_USBC_NO:
1666 sunxi_hci = &sunxi_ehci1;
1667 break;
1668 case HCI2_USBC_NO:
1669 sunxi_hci = &sunxi_ehci2;
1670 break;
1671 case HCI3_USBC_NO:
1672 sunxi_hci = &sunxi_ehci3;
1673 break;
1674 }
1675
1676 if (sunxi_hci->used) {
1677 of_address_to_resource(sunxi_hci->pdev->dev.of_node, 0, &res);
1678 DMSG_INFO("usbc%d, ehci, base[0x%08x]:\n",
1679 i, (unsigned int)res.start);
1680 print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, 4, 4,
1681 sunxi_hci->ehci_base, 0x58, false);
1682 DMSG_INFO("\n");
1683 }
1684 }
1685
1686 return 0;
1687
1688 case SUNXI_USB_OHCI:
1689 for (i = 0; i < 4; i++) {
1690 switch (i) {
1691 case HCI0_USBC_NO:
1692 sunxi_hci = &sunxi_ohci0;
1693 break;
1694 case HCI1_USBC_NO:
1695 sunxi_hci = &sunxi_ohci1;
1696 break;
1697 case HCI2_USBC_NO:
1698 sunxi_hci = &sunxi_ohci2;
1699 break;
1700 case HCI3_USBC_NO:
1701 sunxi_hci = &sunxi_ohci3;
1702 break;
1703 }
1704
1705 if (sunxi_hci->used) {
1706 of_address_to_resource(sunxi_hci->pdev->dev.of_node, 0, &res);
1707 DMSG_INFO("usbc%d, ohci, base[0x%08x]:\n",
1708 i, (unsigned int)(res.start));
1709 print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, 4, 4,
1710 sunxi_hci->ohci_base, 0x58, false);
1711 DMSG_INFO("\n");
1712 }
1713 }
1714
1715 return 0;
1716
1717 case SUNXI_USB_PHY:
1718 for (i = 0; i < 4; i++) {
1719 switch (i) {
1720 case HCI0_USBC_NO:
1721 sunxi_hci = &sunxi_ehci0;
1722 break;
1723 case HCI1_USBC_NO:
1724 sunxi_hci = &sunxi_ehci1;
1725 break;
1726 case HCI2_USBC_NO:
1727 sunxi_hci = &sunxi_ehci2;
1728 break;
1729 case HCI3_USBC_NO:
1730 sunxi_hci = &sunxi_ehci3;
1731 break;
1732 }
1733
1734 if (sunxi_hci->used) {
1735 of_address_to_resource(sunxi_hci->pdev->dev.of_node, 0, &res);
1736 DMSG_INFO("usbc%d, phy, base[0x%08x]:\n",
1737 i, (unsigned int)(res.start + SUNXI_USB_PMU_IRQ_ENABLE));
1738 print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, 4, 4,
1739 sunxi_hci->usb_vbase + SUNXI_USB_PMU_IRQ_ENABLE, 0x34, false);
1740 DMSG_INFO("\n");
1741 }
1742 }
1743
1744 return 0;
1745
1746 case SUNXI_USB_ALL:
1747 for (i = 0; i < 4; i++) {
1748 switch (i) {
1749 case HCI0_USBC_NO:
1750 sunxi_ehci = &sunxi_ehci0;
1751 sunxi_ohci = &sunxi_ohci0;
1752 break;
1753 case HCI1_USBC_NO:
1754 sunxi_ehci = &sunxi_ehci1;
1755 sunxi_ohci = &sunxi_ohci1;
1756 break;
1757 case HCI2_USBC_NO:
1758 sunxi_ehci = &sunxi_ehci2;
1759 sunxi_ohci = &sunxi_ohci2;
1760 break;
1761 case HCI3_USBC_NO:
1762 sunxi_ehci = &sunxi_ehci3;
1763 sunxi_ohci = &sunxi_ohci3;
1764 break;
1765 }
1766
1767 if (sunxi_ehci->used) {
1768 of_address_to_resource(sunxi_ehci->pdev->dev.of_node, 0, &res);
1769 of_address_to_resource(sunxi_ohci->pdev->dev.of_node, 0, &res1);
1770 DMSG_INFO("usbc%d, ehci, base[0x%08x]:\n",
1771 i, (unsigned int)res.start);
1772 print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, 4, 4,
1773 sunxi_ehci->ehci_base, 0x58, false);
1774 DMSG_INFO("usbc%d, ohci, base[0x%08x]:\n",
1775 i, (unsigned int)(res1.start));
1776 print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, 4, 4,
1777 sunxi_ohci->ohci_base, 0x58, false);
1778 DMSG_INFO("usbc%d, phy, base[0x%08x]:\n",
1779 i, (unsigned int)(res.start + SUNXI_USB_PMU_IRQ_ENABLE));
1780 print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, 4, 4,
1781 sunxi_ehci->usb_vbase + SUNXI_USB_PMU_IRQ_ENABLE, 0x34, false);
1782 DMSG_INFO("\n");
1783 }
1784 }
1785
1786 return 0;
1787
1788 default:
1789 DMSG_PANIC("%s()%d invalid argument\n", __func__, __LINE__);
1790 return -EINVAL;
1791 }
1792 }
1793
sunxi_hci_dump_reg(int usbc_no,int usbc_type)1794 static int sunxi_hci_dump_reg(int usbc_no, int usbc_type)
1795 {
1796 struct sunxi_hci_hcd *sunxi_hci, *sunxi_ehci, *sunxi_ohci;
1797 struct resource res, res1;
1798
1799 switch (usbc_type) {
1800 case SUNXI_USB_EHCI:
1801 switch (usbc_no) {
1802 case HCI0_USBC_NO:
1803 sunxi_hci = &sunxi_ehci0;
1804 break;
1805 case HCI1_USBC_NO:
1806 sunxi_hci = &sunxi_ehci1;
1807 break;
1808 case HCI2_USBC_NO:
1809 sunxi_hci = &sunxi_ehci2;
1810 break;
1811 case HCI3_USBC_NO:
1812 sunxi_hci = &sunxi_ehci3;
1813 break;
1814 default:
1815 DMSG_PANIC("%s()%d invalid argument\n", __func__, __LINE__);
1816 return -EINVAL;
1817 }
1818
1819 if (sunxi_hci->used) {
1820 of_address_to_resource(sunxi_hci->pdev->dev.of_node, 0, &res);
1821 DMSG_INFO("usbc%d, ehci, base[0x%08x]:\n",
1822 usbc_no, (unsigned int)res.start);
1823 print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, 4, 4,
1824 sunxi_hci->ehci_base, 0x58, false);
1825 DMSG_INFO("\n");
1826 } else
1827 DMSG_PANIC("%s()%d usbc%d is disable\n", __func__, __LINE__, usbc_no);
1828
1829 return 0;
1830
1831 case SUNXI_USB_OHCI:
1832 switch (usbc_no) {
1833 case HCI0_USBC_NO:
1834 sunxi_hci = &sunxi_ohci0;
1835 break;
1836 case HCI1_USBC_NO:
1837 sunxi_hci = &sunxi_ohci1;
1838 break;
1839 case HCI2_USBC_NO:
1840 sunxi_hci = &sunxi_ohci2;
1841 break;
1842 case HCI3_USBC_NO:
1843 sunxi_hci = &sunxi_ohci3;
1844 break;
1845 default:
1846 DMSG_PANIC("%s()%d invalid argument\n", __func__, __LINE__);
1847 return -EINVAL;
1848 }
1849
1850 if (sunxi_hci->used) {
1851 of_address_to_resource(sunxi_hci->pdev->dev.of_node, 0, &res);
1852 DMSG_INFO("usbc%d, ohci, base[0x%08x]:\n",
1853 usbc_no, (unsigned int)(res.start));
1854 print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, 4, 4,
1855 sunxi_hci->ohci_base, 0x58, false);
1856 DMSG_INFO("\n");
1857 } else
1858 DMSG_PANIC("%s()%d usbc%d is disable\n", __func__, __LINE__, usbc_no);
1859
1860 return 0;
1861
1862 case SUNXI_USB_PHY:
1863 switch (usbc_no) {
1864 case HCI0_USBC_NO:
1865 sunxi_hci = &sunxi_ehci0;
1866 break;
1867 case HCI1_USBC_NO:
1868 sunxi_hci = &sunxi_ehci1;
1869 break;
1870 case HCI2_USBC_NO:
1871 sunxi_hci = &sunxi_ehci2;
1872 break;
1873 case HCI3_USBC_NO:
1874 sunxi_hci = &sunxi_ehci3;
1875 break;
1876 default:
1877 DMSG_PANIC("%s()%d invalid argument\n", __func__, __LINE__);
1878 return -EINVAL;
1879 }
1880
1881 if (sunxi_hci->used) {
1882 of_address_to_resource(sunxi_hci->pdev->dev.of_node, 0, &res);
1883 DMSG_INFO("usbc%d, phy, base[0x%08x]:\n",
1884 usbc_no, (unsigned int)(res.start + SUNXI_USB_PMU_IRQ_ENABLE));
1885 print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, 4, 4,
1886 sunxi_hci->usb_vbase + SUNXI_USB_PMU_IRQ_ENABLE, 0x34, false);
1887 DMSG_INFO("\n");
1888 } else
1889 DMSG_PANIC("%s()%d usbc%d is disable\n", __func__, __LINE__, usbc_no);
1890
1891 return 0;
1892
1893 case SUNXI_USB_ALL:
1894 switch (usbc_no) {
1895 case HCI0_USBC_NO:
1896 sunxi_ehci = &sunxi_ehci0;
1897 sunxi_ohci = &sunxi_ohci0;
1898 break;
1899 case HCI1_USBC_NO:
1900 sunxi_ehci = &sunxi_ehci1;
1901 sunxi_ohci = &sunxi_ohci1;
1902 break;
1903 case HCI2_USBC_NO:
1904 sunxi_ehci = &sunxi_ehci2;
1905 sunxi_ohci = &sunxi_ohci2;
1906 break;
1907 case HCI3_USBC_NO:
1908 sunxi_ehci = &sunxi_ehci3;
1909 sunxi_ohci = &sunxi_ohci3;
1910 break;
1911 default:
1912 DMSG_PANIC("%s()%d invalid argument\n", __func__, __LINE__);
1913 return -EINVAL;
1914 }
1915
1916 if (sunxi_ehci->used) {
1917 of_address_to_resource(sunxi_ehci->pdev->dev.of_node, 0, &res);
1918 of_address_to_resource(sunxi_ohci->pdev->dev.of_node, 0, &res1);
1919 DMSG_INFO("usbc%d, ehci, base[0x%08x]:\n",
1920 usbc_no, (unsigned int)res.start);
1921 print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, 4, 4,
1922 sunxi_ehci->ehci_base, 0x58, false);
1923 DMSG_INFO("usbc%d, ohci, base[0x%08x]:\n",
1924 usbc_no, (unsigned int)(res1.start));
1925 print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, 4, 4,
1926 sunxi_ohci->ohci_base, 0x58, false);
1927 DMSG_INFO("usbc%d, phy, base[0x%08x]:\n",
1928 usbc_no, (unsigned int)(res.start + SUNXI_USB_PMU_IRQ_ENABLE));
1929 print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, 4, 4,
1930 sunxi_ehci->usb_vbase + SUNXI_USB_PMU_IRQ_ENABLE, 0x34, false);
1931 DMSG_INFO("\n");
1932 } else
1933 DMSG_PANIC("%s()%d usbc%d is disable\n", __func__, __LINE__, usbc_no);
1934
1935 return 0;
1936
1937 default:
1938 DMSG_PANIC("%s()%d invalid argument\n", __func__, __LINE__);
1939 return -EINVAL;
1940 }
1941 }
1942
sunxi_hci_standby_completion(int usbc_type)1943 int sunxi_hci_standby_completion(int usbc_type)
1944 {
1945 if (sunxi_ehci0.used) {
1946 if (usbc_type == SUNXI_USB_EHCI) {
1947 complete(&sunxi_ehci0.standby_complete);
1948 } else if (usbc_type == SUNXI_USB_OHCI) {
1949 complete(&sunxi_ohci0.standby_complete);
1950 } else {
1951 pr_err("%s()%d err usb type\n", __func__, __LINE__);
1952 return -1;
1953 }
1954 }
1955
1956 if (sunxi_ehci1.used) {
1957 if (usbc_type == SUNXI_USB_EHCI) {
1958 complete(&sunxi_ehci1.standby_complete);
1959 } else if (usbc_type == SUNXI_USB_OHCI) {
1960 complete(&sunxi_ohci1.standby_complete);
1961 } else {
1962 pr_err("%s()%d err usb type\n", __func__, __LINE__);
1963 return -1;
1964 }
1965 }
1966
1967 if (sunxi_ehci2.used) {
1968 if (usbc_type == SUNXI_USB_EHCI) {
1969 complete(&sunxi_ehci2.standby_complete);
1970 } else if (usbc_type == SUNXI_USB_OHCI) {
1971 complete(&sunxi_ohci2.standby_complete);
1972 } else {
1973 pr_err("%s()%d err usb type\n", __func__, __LINE__);
1974 return -1;
1975 }
1976 }
1977
1978 if (sunxi_ehci3.used) {
1979 if (usbc_type == SUNXI_USB_EHCI) {
1980 complete(&sunxi_ehci3.standby_complete);
1981 } else if (usbc_type == SUNXI_USB_OHCI) {
1982 complete(&sunxi_ohci3.standby_complete);
1983 } else {
1984 pr_err("%s()%d err usb type\n", __func__, __LINE__);
1985 return -1;
1986 }
1987 }
1988
1989 return 0;
1990 }
1991 EXPORT_SYMBOL(sunxi_hci_standby_completion);
1992
exit_sunxi_hci(struct sunxi_hci_hcd * sunxi_hci)1993 int exit_sunxi_hci(struct sunxi_hci_hcd *sunxi_hci)
1994 {
1995 release_usb_regulator_io(sunxi_hci);
1996 free_pin(sunxi_hci);
1997 if (sunxi_hci->usb_base_res)
1998 kfree(sunxi_hci->usb_base_res);
1999 return 0;
2000 }
2001 EXPORT_SYMBOL(exit_sunxi_hci);
2002
init_sunxi_hci(struct platform_device * pdev,int usbc_type)2003 int init_sunxi_hci(struct platform_device *pdev, int usbc_type)
2004 {
2005 struct sunxi_hci_hcd *sunxi_hci = NULL;
2006 int usbc_no = 0;
2007 int hci_num = -1;
2008 int ret = -1;
2009
2010 #if IS_ENABLED(CONFIG_OF)
2011 pdev->dev.dma_mask = &sunxi_hci_dmamask;
2012 pdev->dev.coherent_dma_mask = DMA_BIT_MASK(64);
2013 #endif
2014
2015 hci_num = sunxi_get_hci_num(pdev);
2016
2017 if (usbc_type == SUNXI_USB_XHCI) {
2018 usbc_no = hci_num;
2019 sunxi_hci = &sunxi_xhci;
2020 } else {
2021 switch (hci_num) {
2022 case HCI0_USBC_NO:
2023 usbc_no = HCI0_USBC_NO;
2024 if (usbc_type == SUNXI_USB_EHCI) {
2025 sunxi_hci = &sunxi_ehci0;
2026 } else if (usbc_type == SUNXI_USB_OHCI) {
2027 sunxi_hci = &sunxi_ohci0;
2028 } else {
2029 dev_err(&pdev->dev, "get hci num fail: %d\n", hci_num);
2030 return -1;
2031 }
2032 break;
2033
2034 case HCI1_USBC_NO:
2035 usbc_no = HCI1_USBC_NO;
2036 if (usbc_type == SUNXI_USB_EHCI) {
2037 sunxi_hci = &sunxi_ehci1;
2038 } else if (usbc_type == SUNXI_USB_OHCI) {
2039 sunxi_hci = &sunxi_ohci1;
2040 } else {
2041 dev_err(&pdev->dev, "get hci num fail: %d\n", hci_num);
2042 return -1;
2043 }
2044 break;
2045
2046 case HCI2_USBC_NO:
2047 usbc_no = HCI2_USBC_NO;
2048 if (usbc_type == SUNXI_USB_EHCI) {
2049 sunxi_hci = &sunxi_ehci2;
2050 } else if (usbc_type == SUNXI_USB_OHCI) {
2051 sunxi_hci = &sunxi_ohci2;
2052 } else {
2053 dev_err(&pdev->dev, "get hci num fail: %d\n", hci_num);
2054 return -1;
2055 }
2056 break;
2057
2058 case HCI3_USBC_NO:
2059 usbc_no = HCI3_USBC_NO;
2060 if (usbc_type == SUNXI_USB_EHCI) {
2061 sunxi_hci = &sunxi_ehci3;
2062 } else if (usbc_type == SUNXI_USB_OHCI) {
2063 sunxi_hci = &sunxi_ohci3;
2064 } else {
2065 dev_err(&pdev->dev, "get hci num fail: %d\n", hci_num);
2066 return -1;
2067 }
2068 break;
2069
2070 default:
2071 dev_err(&pdev->dev, "get hci num fail: %d\n", hci_num);
2072 return -1;
2073 }
2074 }
2075
2076 ret = sunxi_get_hci_resource(pdev, sunxi_hci, usbc_no);
2077 if (ret != 0)
2078 return ret;
2079
2080 return ret;
2081 }
2082 EXPORT_SYMBOL(init_sunxi_hci);
2083
__parse_hci_str(const char * buf,size_t size)2084 static int __parse_hci_str(const char *buf, size_t size)
2085 {
2086 int ret = 0;
2087 unsigned long val;
2088
2089 if (!buf) {
2090 pr_err("%s()%d invalid argument\n", __func__, __LINE__);
2091 return -1;
2092 }
2093
2094 ret = kstrtoul(buf, 10, &val);
2095 if (ret) {
2096 pr_err("%s()%d failed to transfer\n", __func__, __LINE__);
2097 return -1;
2098 }
2099
2100 return val;
2101 }
2102
2103 static ssize_t
ehci_reg_show(struct class * class,struct class_attribute * attr,char * buf)2104 ehci_reg_show(struct class *class, struct class_attribute *attr, char *buf)
2105 {
2106 sunxi_hci_dump_reg_all(SUNXI_USB_EHCI);
2107
2108 return 0;
2109 }
2110
2111 static ssize_t
ehci_reg_store(struct class * class,struct class_attribute * attr,const char * buf,size_t count)2112 ehci_reg_store(struct class *class, struct class_attribute *attr,
2113 const char *buf, size_t count)
2114 {
2115 int usbc_no;
2116
2117 usbc_no = __parse_hci_str(buf, count);
2118 if (usbc_no < 0)
2119 return -EINVAL;
2120
2121 sunxi_hci_dump_reg(usbc_no, SUNXI_USB_EHCI);
2122
2123 return count;
2124 }
2125 static CLASS_ATTR_RW(ehci_reg);
2126
2127 static ssize_t
ohci_reg_show(struct class * class,struct class_attribute * attr,char * buf)2128 ohci_reg_show(struct class *class, struct class_attribute *attr, char *buf)
2129 {
2130 sunxi_hci_dump_reg_all(SUNXI_USB_OHCI);
2131
2132 return 0;
2133 }
2134
2135 static ssize_t
ohci_reg_store(struct class * class,struct class_attribute * attr,const char * buf,size_t count)2136 ohci_reg_store(struct class *class, struct class_attribute *attr,
2137 const char *buf, size_t count)
2138 {
2139 int usbc_no;
2140
2141 usbc_no = __parse_hci_str(buf, count);
2142 if (usbc_no < 0)
2143 return -EINVAL;
2144
2145 sunxi_hci_dump_reg(usbc_no, SUNXI_USB_OHCI);
2146
2147 return count;
2148 }
2149 static CLASS_ATTR_RW(ohci_reg);
2150
2151 static ssize_t
phy_reg_show(struct class * class,struct class_attribute * attr,char * buf)2152 phy_reg_show(struct class *class, struct class_attribute *attr, char *buf)
2153 {
2154 sunxi_hci_dump_reg_all(SUNXI_USB_PHY);
2155
2156 return 0;
2157 }
2158
2159 static ssize_t
phy_reg_store(struct class * class,struct class_attribute * attr,const char * buf,size_t count)2160 phy_reg_store(struct class *class, struct class_attribute *attr,
2161 const char *buf, size_t count)
2162 {
2163 int usbc_no;
2164
2165 usbc_no = __parse_hci_str(buf, count);
2166 if (usbc_no < 0)
2167 return -EINVAL;
2168
2169 sunxi_hci_dump_reg(usbc_no, SUNXI_USB_PHY);
2170
2171 return count;
2172 }
2173 static CLASS_ATTR_RW(phy_reg);
2174
2175 static ssize_t
all_reg_show(struct class * class,struct class_attribute * attr,char * buf)2176 all_reg_show(struct class *class, struct class_attribute *attr, char *buf)
2177 {
2178 sunxi_hci_dump_reg_all(SUNXI_USB_ALL);
2179
2180 return 0;
2181 }
2182
2183 static ssize_t
all_reg_store(struct class * class,struct class_attribute * attr,const char * buf,size_t count)2184 all_reg_store(struct class *class, struct class_attribute *attr,
2185 const char *buf, size_t count)
2186 {
2187 int usbc_no;
2188
2189
2190 usbc_no = __parse_hci_str(buf, count);
2191 if (usbc_no < 0)
2192 return -EINVAL;
2193
2194 sunxi_hci_dump_reg(usbc_no, SUNXI_USB_ALL);
2195
2196 return count;
2197 }
2198 static CLASS_ATTR_RW(all_reg);
2199
2200 static struct attribute *hci_class_attrs[] = {
2201 &class_attr_ehci_reg.attr,
2202 &class_attr_ohci_reg.attr,
2203 &class_attr_phy_reg.attr,
2204 &class_attr_all_reg.attr,
2205 NULL,
2206 };
2207 ATTRIBUTE_GROUPS(hci_class);
2208
2209 static struct class hci_class = {
2210 .name = "hci_reg",
2211 .owner = THIS_MODULE,
2212 .class_groups = hci_class_groups,
2213 };
2214
init_sunxi_hci_class(void)2215 static int __init init_sunxi_hci_class(void)
2216 {
2217 int ret = 0;
2218
2219 ret = class_register(&hci_class);
2220 if (ret) {
2221 DMSG_PANIC("%s()%d register class fialed\n", __func__, __LINE__);
2222 return -1;
2223 }
2224
2225 return 0;
2226 }
2227
exit_sunxi_hci_class(void)2228 static void __exit exit_sunxi_hci_class(void)
2229 {
2230 class_unregister(&hci_class);
2231 }
2232
2233 late_initcall(init_sunxi_hci_class);
2234 module_exit(exit_sunxi_hci_class);
2235
2236 MODULE_DESCRIPTION(DRIVER_DESC);
2237 MODULE_LICENSE("GPL v2");
2238 MODULE_ALIAS("platform:" SUNXI_HCI_NAME);
2239 MODULE_AUTHOR("javen");
2240 MODULE_VERSION("1.0.11");
2241