1 /*
2 * linux-5.4/drivers/media/platform/sunxi-vin/top_reg.c
3 *
4 * Copyright (c) 2007-2017 Allwinnertech Co., Ltd.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17 #include <linux/kernel.h>
18 #include "top_reg_i.h"
19 #include "top_reg.h"
20
21 #include "utility/vin_io.h"
22
23 /*isp_id isp_input pasrer_id parser_ch*/
24 static char isp_input[4][4][4][4] = {
25 #if defined(CONFIG_ARCH_SUN50IW3P1) || defined(CONFIG_ARCH_SUN50IW6P1)
26 /*isp0 input0~3*/
27 /*parser0*/ /*parse1*/ /*parser2*/ /*parser3*/
28 {
29 {{0, 0, 0, 0}, {1, 2, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0} },
30 {{0, 0, 0, 0}, {0, 1, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0} },
31 {{0, 0, 0, 0}, {0, 0, 1, 0}, {0, 0, 0, 0}, {0, 0, 0, 0} },
32 {{0, 0, 0, 0}, {0, 0, 0, 1}, {0, 0, 0, 0}, {0, 0, 0, 0} }
33 },
34
35 /*isp1 input0~3*/
36 {
37 {{1, 2, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0} },
38 {{0, 0, 0, 0}, {0, 1, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0} },
39 {{0, 0, 0, 0}, {0, 0, 1, 0}, {0, 0, 0, 0}, {0, 0, 0, 0} },
40 {{0, 0, 0, 0}, {0, 0, 0, 1}, {0, 0, 0, 0}, {0, 0, 0, 0} }
41 },
42 #elif defined (CONFIG_ARCH_SUN8IW15P1) || defined (CONFIG_ARCH_SUN8IW17P1) || defined (CONFIG_ARCH_SUN8IW16P1)
43 /*isp0 input0~3*/
44 {
45 {{0, 4, 0, 0}, {1, 5, 0, 0}, {2, 6, 0, 0}, {3, 7, 0, 0} },
46 {{0, 0, 0, 0}, {0, 1, 0, 0}, {0, 2, 0, 0}, {0, 3, 0, 0} },
47 {{0, 0, 0, 0}, {0, 0, 1, 0}, {0, 0, 2, 0}, {0, 0, 3, 0} },
48 {{0, 0, 0, 0}, {0, 0, 0, 1}, {0, 0, 0, 2}, {0, 0, 0, 3} }
49 },
50
51 /*isp1 input0~3*/
52 {
53 {{0, 4, 0, 0}, {1, 5, 0, 0}, {2, 6, 0, 0}, {3, 7, 0, 0} },
54 {{0, 0, 0, 0}, {0, 1, 0, 0}, {0, 2, 0, 0}, {0, 3, 0, 0} },
55 {{0, 0, 0, 0}, {0, 0, 1, 0}, {0, 0, 2, 0}, {0, 0, 3, 0} },
56 {{0, 0, 0, 0}, {0, 0, 0, 1}, {0, 0, 0, 2}, {0, 0, 0, 3} }
57 },
58
59 /*isp2 input0~3*/
60 {
61 {{0, 4, 0, 0}, {1, 5, 0, 0}, {2, 6, 0, 0}, {3, 7, 0, 0} },
62 {{0, 0, 0, 0}, {0, 1, 0, 0}, {0, 2, 0, 0}, {0, 3, 0, 0} },
63 {{0, 0, 0, 0}, {0, 0, 1, 0}, {0, 0, 2, 0}, {0, 0, 3, 0} },
64 {{0, 0, 0, 0}, {0, 0, 0, 1}, {0, 0, 0, 2}, {0, 0, 0, 3} }
65 },
66
67 /*isp3 input0~3*/
68 {
69 {{0, 4, 0, 0}, {1, 5, 0, 0}, {2, 6, 0, 0}, {3, 7, 0, 0} },
70 {{0, 0, 0, 0}, {0, 1, 0, 0}, {0, 2, 0, 0}, {0, 3, 0, 0} },
71 {{0, 0, 0, 0}, {0, 0, 1, 0}, {0, 0, 2, 0}, {0, 0, 3, 0} },
72 {{0, 0, 0, 0}, {0, 0, 0, 1}, {0, 0, 0, 2}, {0, 0, 0, 3} }
73 }
74 #else
75 /*isp0 input0~3*/
76 {
77 {{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} },
78 {{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} },
79 {{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} },
80 {{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} }
81 },
82
83 /*isp1 input0~3*/
84 {
85 {{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} },
86 {{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} },
87 {{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} },
88 {{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} }
89 },
90
91 /*isp2 input0~3*/
92 {
93 {{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} },
94 {{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} },
95 {{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} },
96 {{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} }
97 },
98
99 /*isp3 input0~3*/
100 {
101 {{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} },
102 {{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} },
103 {{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} },
104 {{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} }
105 },
106 #endif
107 };
108
109 /*vipp_id isp_id isp_ch*/
110 static char vipp_input[8][4][4] = {
111 #if defined(CONFIG_ARCH_SUN50IW3P1) || defined(CONFIG_ARCH_SUN50IW6P1)
112 /*vipp0*/
113 /*isp0*/ /*isp1*/ /*isp2*/ /*isp3*/
114 {{0, 0, 0, 0}, {1, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0} },
115
116 {{0, 2, 0, 0}, {1, 3, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0} },
117
118 {{0, 0, 2, 0}, {1, 0, 3, 0}, {0, 0, 0, 0}, {0, 0, 0, 0} },
119
120 {{0, 0, 0, 2}, {1, 4, 0, 3}, {0, 0, 0, 0}, {0, 0, 0, 0} },
121 #elif defined (CONFIG_ARCH_SUN8IW15P1) || defined (CONFIG_ARCH_SUN8IW17P1) || defined (CONFIG_ARCH_SUN8IW16P1)
122 {{0, 0, 0, 0}, {1, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0} },
123
124 {{0, 2, 0, 0}, {1, 3, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0} },
125
126 {{0, 0, 2, 0}, {1, 0, 3, 0}, {0, 0, 0, 0}, {0, 0, 0, 0} },
127
128 {{0, 0, 0, 2}, {1, 4, 0, 3}, {0, 0, 0, 0}, {0, 0, 0, 0} },
129
130 {{0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 0}, {1, 0, 0, 0} },
131
132 {{0, 0, 0, 0}, {0, 0, 0, 0}, {0, 2, 0, 0}, {1, 3, 0, 0} },
133
134 {{0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 2, 0}, {1, 0, 3, 0} },
135
136 {{0, 0, 0, 0}, {0, 0, 0, 0}, {0, 0, 0, 2}, {1, 4, 0, 3} }
137 #else
138 {{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} },
139
140 {{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} },
141
142 {{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} },
143
144 {{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} },
145
146 {{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} },
147
148 {{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} },
149
150 {{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} },
151
152 {{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} },
153 #endif
154 };
155
156 #if defined (CONFIG_ARCH_SUN50IW9P1)
157 static char dma_input[8][4][4] = {
158 /*parser0*/ /*parser1*/ /*parser2*/ /*parser3*/
159 {{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} }, /*dma0*/
160
161 {{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} }, /*dma1*/
162
163 {{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} }, /*dma2*/
164
165 {{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} }, /*dma3*/
166
167 {{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} }, /*dma4*/
168
169 {{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} }, /*dma5*/
170
171 {{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} }, /*dma6*/
172
173 {{0, 1, 2, 3}, {4, 5, 6, 7}, {8, 9, 10, 11}, {12, 13, 14, 15} } /*dma7*/
174 };
175 #endif
176
177 volatile void __iomem *csic_top_base[MAX_CSIC_TOP_NUM];
178 volatile void __iomem *csic_ccu_base;
179
180 /*
181 * functions about top register
182 */
csic_top_set_base_addr(unsigned int sel,unsigned long addr)183 int csic_top_set_base_addr(unsigned int sel, unsigned long addr)
184 {
185 if (sel > MAX_CSIC_TOP_NUM - 1)
186 return -1;
187 csic_top_base[sel] = (volatile void __iomem *)addr;
188
189 return 0;
190 }
191
csic_top_enable(unsigned int sel)192 void csic_top_enable(unsigned int sel)
193 {
194 vin_reg_clr_set(csic_top_base[sel] + CSIC_TOP_EN_REG_OFF,
195 CSIC_TOP_EN_MASK, 1 << CSIC_TOP_EN);
196 }
197
csic_top_disable(unsigned int sel)198 void csic_top_disable(unsigned int sel)
199 {
200 vin_reg_clr_set(csic_top_base[sel] + CSIC_TOP_EN_REG_OFF,
201 CSIC_TOP_EN_MASK, 0 << CSIC_TOP_EN);
202 }
203
csic_isp_bridge_enable(unsigned int sel)204 void csic_isp_bridge_enable(unsigned int sel)
205 {
206 vin_reg_clr_set(csic_top_base[sel] + CSIC_TOP_EN_REG_OFF,
207 CSIC_ISP_BRIDGE_EN_MASK, 1 << CSIC_ISP_BRIDGE_EN);
208 }
209
csic_isp_bridge_disable(unsigned int sel)210 void csic_isp_bridge_disable(unsigned int sel)
211 {
212 vin_reg_clr_set(csic_top_base[sel] + CSIC_TOP_EN_REG_OFF,
213 CSIC_ISP_BRIDGE_EN_MASK, 0 << CSIC_ISP_BRIDGE_EN);
214 }
215
csic_top_sram_pwdn(unsigned int sel,unsigned int en)216 void csic_top_sram_pwdn(unsigned int sel, unsigned int en)
217 {
218 vin_reg_clr_set(csic_top_base[sel] + CSIC_TOP_EN_REG_OFF,
219 CSIC_SRAM_PWDN_MASK, en << CSIC_SRAM_PWDN);
220 }
221
csic_top_version_read_en(unsigned int sel,unsigned int en)222 void csic_top_version_read_en(unsigned int sel, unsigned int en)
223 {
224 vin_reg_clr_set(csic_top_base[sel] + CSIC_TOP_EN_REG_OFF,
225 CSIC_VER_EN_MASK, en << CSIC_VER_EN);
226 }
227
csic_isp_input_select(unsigned int sel,unsigned int isp,unsigned int in,unsigned int psr,unsigned int ch)228 void csic_isp_input_select(unsigned int sel, unsigned int isp, unsigned int in,
229 unsigned int psr, unsigned int ch)
230 {
231 vin_reg_writel(csic_top_base[sel] + CSIC_ISP0_IN0_REG_OFF + isp * 16 + in * 4,
232 isp_input[isp][in][psr][ch]);
233 }
234
csic_vipp_input_select(unsigned int sel,unsigned int vipp,unsigned int isp,unsigned int ch)235 void csic_vipp_input_select(unsigned int sel, unsigned int vipp,
236 unsigned int isp, unsigned int ch)
237 {
238 vin_reg_writel(csic_top_base[sel] + CSIC_VIPP0_IN_REG_OFF + vipp * 4,
239 vipp_input[vipp][isp][ch]);
240 }
241
csic_dma_input_select(unsigned int sel,unsigned int dma,unsigned int parser,unsigned int ch)242 void csic_dma_input_select(unsigned int sel, unsigned int dma,
243 unsigned int parser, unsigned int ch)
244 {
245 #if defined (CONFIG_ARCH_SUN50IW9P1)
246 vin_reg_writel(csic_top_base[sel] + CSIC_VIPP0_IN_REG_OFF + dma * 4,
247 dma_input[dma][parser][ch]);
248 #endif
249 }
250
csic_feature_list_get(unsigned int sel,struct csic_feature_list * fl)251 void csic_feature_list_get(unsigned int sel, struct csic_feature_list *fl)
252 {
253 unsigned int reg_val = 0;
254
255 reg_val = vin_reg_readl(csic_top_base[sel] + CSIC_FEATURE_REG_OFF);
256 fl->dma_num = (reg_val & CSIC_DMA_NUM_MASK) >> CSIC_DMA_NUM;
257 fl->vipp_num = (reg_val & CSIC_VIPP_NUM_MASK) >> CSIC_VIPP_NUM;
258 fl->isp_num = (reg_val & CSIC_ISP_NUM_MASK) >> CSIC_ISP_NUM;
259 fl->ncsi_num = (reg_val & CSIC_NCSI_NUM_MASK) >> CSIC_NCSI_NUM;
260 fl->mcsi_num = (reg_val & CSIC_MCSI_NUM_MASK) >> CSIC_MCSI_NUM;
261 fl->parser_num = (reg_val & CSIC_PARSER_NUM_MASK) >> CSIC_PARSER_NUM;
262 }
263
csic_version_get(unsigned int sel,struct csic_version * v)264 void csic_version_get(unsigned int sel, struct csic_version *v)
265 {
266 unsigned int reg_val = 0;
267
268 reg_val = vin_reg_readl(csic_top_base[sel] + CSIC_VER_REG_OFF);
269 v->ver_small = (reg_val & CSIC_VER_SMALL_MASK) >> CSIC_VER_SMALL;
270 v->ver_big = (reg_val & CSIC_VER_BIG_MASK) >> CSIC_VER_BIG;
271 }
272
273
csic_mbus_req_mex_set(unsigned int sel,unsigned int data)274 void csic_mbus_req_mex_set(unsigned int sel, unsigned int data)
275 {
276 #if !defined CONFIG_ARCH_SUN8IW15P1 && !defined CONFIG_ARCH_SUN8IW16P1 && !defined CONFIG_ARCH_SUN8IW17P1 && !defined CONFIG_ARCH_SUN50IW9P1 && !defined CONFIG_ARCH_SUN50IW3P1 && !defined CONFIG_ARCH_SUN50IW6P1
277 vin_reg_clr_set(csic_top_base[sel] + CSIC_MBUS_REQ_MAX,
278 MCSI_MEM_REQ_MAX_MASK, data << MCSI_MEM_REQ_MAX);
279 vin_reg_clr_set(csic_top_base[sel] + CSIC_MBUS_REQ_MAX,
280 MCSI_MEM_1_REQ_MAX_MASK, data << MCSI_MEM_1_REQ_MAX);
281 vin_reg_clr_set(csic_top_base[sel] + CSIC_MBUS_REQ_MAX,
282 MISP_MEM_REQ_MAX_MASK, data << MISP_MEM_REQ_MAX);
283 #endif
284 }
285
csic_mulp_mode_en(unsigned int sel,unsigned int en)286 void csic_mulp_mode_en(unsigned int sel, unsigned int en)
287 {
288 vin_reg_clr_set(csic_top_base[sel] + CSIC_MULP_MODE_REG_OFF,
289 CSIC_MULP_EN_MASK, en << CSIC_MULP_EN);
290 }
291
csic_mulp_dma_cs(unsigned int sel,enum csic_mulp_cs cs)292 void csic_mulp_dma_cs(unsigned int sel, enum csic_mulp_cs cs)
293 {
294 vin_reg_clr_set(csic_top_base[sel] + CSIC_MULP_MODE_REG_OFF,
295 CSIC_MULP_CS_MASK, cs << CSIC_MULP_CS);
296 }
297
csic_mulp_int_enable(unsigned int sel,enum csis_mulp_int interrupt)298 void csic_mulp_int_enable(unsigned int sel, enum csis_mulp_int interrupt)
299 {
300 vin_reg_clr_set(csic_top_base[sel] + CSIC_MULP_INT_REG_OFF,
301 CSIC_MULP_INT_EN_MASK, interrupt << CSIC_MULP_INT_EN);
302 }
303
csic_mulp_int_disable(unsigned int sel,enum csis_mulp_int interrupt)304 void csic_mulp_int_disable(unsigned int sel, enum csis_mulp_int interrupt)
305 {
306 vin_reg_clr_set(csic_top_base[sel] + CSIC_MULP_INT_REG_OFF,
307 CSIC_MULP_INT_EN_MASK, ~interrupt << CSIC_MULP_INT_EN);
308 }
309
csic_mulp_int_get_status(unsigned int sel,struct cisc_mulp_int_status * status)310 void csic_mulp_int_get_status(unsigned int sel, struct cisc_mulp_int_status *status)
311 {
312 unsigned int reg_val = vin_reg_readl(csic_top_base[sel] + CSIC_MULP_INT_REG_OFF);
313
314 status->mulf_done = (reg_val & CSIC_MULP_DONE_PD_MASK) >> CSIC_MULP_DONE_PD;
315 status->mulf_err = (reg_val & CSIC_MULP_ERR_PD_MASK) >> CSIC_MULP_ERR_PD;
316 }
317
csic_mulp_int_clear_status(unsigned int sel,enum csis_mulp_int interrupt)318 void csic_mulp_int_clear_status(unsigned int sel, enum csis_mulp_int interrupt)
319 {
320 vin_reg_clr_set(csic_top_base[sel] + CSIC_MULP_INT_REG_OFF,
321 CSIC_MULP_INT_PD_MASK, interrupt << CSIC_MULP_DONE_PD);
322 }
323
csic_ptn_generation_en(unsigned int sel,unsigned int en)324 void csic_ptn_generation_en(unsigned int sel, unsigned int en)
325 {
326 vin_reg_clr_set(csic_top_base[sel] + CSIC_PTN_GEN_EN_REG_OFF,
327 CSIC_PTN_GEN_CYCLE_MASK, 0 << CSIC_PTN_GEN_CYCLE);
328 vin_reg_clr_set(csic_top_base[sel] + CSIC_PTN_GEN_EN_REG_OFF,
329 CSIC_PTN_GEN_EN_MASK, en << CSIC_PTN_GEN_EN);
330 vin_reg_clr_set(csic_top_base[sel] + CSIC_PTN_GEN_EN_REG_OFF,
331 CSIC_PTN_GEN_START_MASK, en << CSIC_PTN_GEN_START);
332 }
333
csic_ptn_control(unsigned int sel,int mode,int dw,int port)334 void csic_ptn_control(unsigned int sel, int mode, int dw, int port)
335 {
336 vin_reg_clr_set(csic_top_base[sel] + CSIC_PTN_CTRL_REG_OFF,
337 CSIC_PTN_CLK_DIV_MASK, 0 << CSIC_PTN_CLK_DIV);
338 vin_reg_clr_set(csic_top_base[sel] + CSIC_PTN_CTRL_REG_OFF,
339 CSIC_PTN_MODE_MASK, mode << CSIC_PTN_MODE);
340 vin_reg_clr_set(csic_top_base[sel] + CSIC_PTN_CTRL_REG_OFF,
341 CSIC_PTN_DATA_WIDTH_MASK, dw << CSIC_PTN_DATA_WIDTH);
342 vin_reg_clr_set(csic_top_base[sel] + CSIC_PTN_CTRL_REG_OFF,
343 CSIC_PTN_PORT_SEL_MASK, port << CSIC_PTN_PORT_SEL);
344 }
345
csic_ptn_length(unsigned int sel,unsigned int len)346 void csic_ptn_length(unsigned int sel, unsigned int len)
347 {
348 vin_reg_writel(csic_top_base[sel] + CSIC_PTN_LEN_REG_OFF, len);
349 }
350
csic_ptn_addr(unsigned int sel,unsigned long dma_addr)351 void csic_ptn_addr(unsigned int sel, unsigned long dma_addr)
352 {
353 vin_reg_writel(csic_top_base[sel] + CSIC_PTN_ADDR_REG_OFF, dma_addr >> 2);
354 }
355
csic_ptn_size(unsigned int sel,unsigned int w,unsigned int h)356 void csic_ptn_size(unsigned int sel, unsigned int w, unsigned int h)
357 {
358 vin_reg_clr_set(csic_top_base[sel] + CSIC_PTN_SIZE_REG_OFF,
359 CSIC_PTN_WIDTH_MASK, w << CSIC_PTN_WIDTH);
360 vin_reg_clr_set(csic_top_base[sel] + CSIC_PTN_SIZE_REG_OFF,
361 CSIC_PTN_HEIGHT_MASK, h << CSIC_PTN_HEIGHT);
362 }
363
364 /*
365 * functions about ccu register
366 */
csic_ccu_set_base_addr(unsigned long addr)367 int csic_ccu_set_base_addr(unsigned long addr)
368 {
369 csic_ccu_base = (volatile void __iomem *)addr;
370
371 return 0;
372 }
373
csic_ccu_clk_gating_enable(void)374 void csic_ccu_clk_gating_enable(void)
375 {
376 vin_reg_clr_set(csic_ccu_base + CSIC_CCU_MODE_REG_OFF,
377 CSIC_CCU_CLK_GATING_DISABLE_MASK, 0 << CSIC_CCU_CLK_GATING_DISABLE);
378 }
379
csic_ccu_clk_gating_disable(void)380 void csic_ccu_clk_gating_disable(void)
381 {
382 vin_reg_clr_set(csic_ccu_base + CSIC_CCU_MODE_REG_OFF,
383 CSIC_CCU_CLK_GATING_DISABLE_MASK, 1 << CSIC_CCU_CLK_GATING_DISABLE);
384 }
385
csic_ccu_mcsi_clk_mode(unsigned int mode)386 void csic_ccu_mcsi_clk_mode(unsigned int mode)
387 {
388 vin_reg_clr_set(csic_ccu_base + CSIC_CCU_MODE_REG_OFF,
389 CSIC_MCSI_CLK_MODE_MASK, mode << CSIC_MCSI_CLK_MODE);
390 vin_reg_clr_set(csic_ccu_base + CSIC_CCU_MODE_REG_OFF,
391 CSIC_MCSI_POST_CLK_MODE_MASK, mode << CSIC_MCSI_POST_CLK_MODE);
392 }
393
csic_ccu_mcsi_combo_clk_en(unsigned int sel,unsigned int en)394 void csic_ccu_mcsi_combo_clk_en(unsigned int sel, unsigned int en)
395 {
396 vin_reg_clr_set(csic_ccu_base + CSIC_CCU_PARSER_CLK_EN_REG_OFF,
397 CSIC_MCSI_COMBO0_CLK_EN_MASK << sel, en << (CSIC_MCSI_COMBO0_CLK_EN + sel));
398 }
399
csic_ccu_mcsi_mipi_clk_en(unsigned int sel,unsigned int en)400 void csic_ccu_mcsi_mipi_clk_en(unsigned int sel, unsigned int en)
401 {
402 vin_reg_clr_set(csic_ccu_base + CSIC_CCU_PARSER_CLK_EN_REG_OFF,
403 CSIC_MCSI_MIPI0_CLK_EN_MASK << sel, en << (CSIC_MCSI_MIPI0_CLK_EN + sel));
404 }
405
csic_ccu_mcsi_parser_clk_en(unsigned int sel,unsigned int en)406 void csic_ccu_mcsi_parser_clk_en(unsigned int sel, unsigned int en)
407 {
408 vin_reg_clr_set(csic_ccu_base + CSIC_CCU_PARSER_CLK_EN_REG_OFF,
409 CSIC_MCSI_PARSER0_CLK_EN_MASK << sel, en << (CSIC_MCSI_PARSER0_CLK_EN + sel));
410 }
411
csic_ccu_misp_isp_clk_en(unsigned int sel,unsigned int en)412 void csic_ccu_misp_isp_clk_en(unsigned int sel, unsigned int en)
413 {
414 vin_reg_clr_set(csic_ccu_base + CSIC_CCU_ISP_CLK_EN_REG_OFF,
415 CSIC_MISP0_CLK_EN_MASK << sel, en << (CSIC_MISP0_CLK_EN + sel));
416 vin_reg_clr_set(csic_ccu_base + CSIC_CCU_ISP_CLK_EN_REG_OFF,
417 CSIC_MISP0_BRIDGE_CLK_EN_MASK << sel, en << (CSIC_MISP0_BRIDGE_CLK_EN + sel));
418 }
419
csic_ccu_mcsi_post_clk_enable(unsigned int sel)420 void csic_ccu_mcsi_post_clk_enable(unsigned int sel)
421 {
422 vin_reg_clr_set(csic_ccu_base + CSIC_CCU_POST0_CLK_EN_REG_OFF + sel*4,
423 CSIC_MCSI_POST0_CLK_EN_MASK, 1 << CSIC_MCSI_POST0_CLK_EN);
424 }
425
csic_ccu_mcsi_post_clk_disable(unsigned int sel)426 void csic_ccu_mcsi_post_clk_disable(unsigned int sel)
427 {
428 vin_reg_clr_set(csic_ccu_base + CSIC_CCU_POST0_CLK_EN_REG_OFF + sel*4,
429 CSIC_MCSI_POST0_CLK_EN_MASK, 0 << CSIC_MCSI_POST0_CLK_EN);
430 }
431
csic_ccu_bk_clk_en(unsigned int sel,unsigned int en)432 void csic_ccu_bk_clk_en(unsigned int sel, unsigned int en)
433 {
434 if (sel < 4)
435 vin_reg_clr_set(csic_ccu_base + CSIC_CCU_POST0_CLK_EN_REG_OFF,
436 CSIC_MCSI_BK0_CLK_EN_MASK << sel, en << (CSIC_MCSI_BK0_CLK_EN + sel));
437 else
438 vin_reg_clr_set(csic_ccu_base + CSIC_CCU_POST0_CLK_EN_REG_OFF + 0x4,
439 CSIC_MCSI_BK0_CLK_EN_MASK << (sel-4), en << (CSIC_MCSI_BK0_CLK_EN + (sel-4)));
440 }
441
csic_ccu_vipp_clk_en(unsigned int sel,unsigned int en)442 void csic_ccu_vipp_clk_en(unsigned int sel, unsigned int en)
443 {
444 if (sel < 4)
445 vin_reg_clr_set(csic_ccu_base + CSIC_CCU_POST0_CLK_EN_REG_OFF,
446 CSIC_MCSI_VIPP0_CLK_EN_MASK << sel, en << (CSIC_MCSI_VIPP0_CLK_EN + sel));
447 else
448 vin_reg_clr_set(csic_ccu_base + CSIC_CCU_POST0_CLK_EN_REG_OFF + 0x4,
449 CSIC_MCSI_VIPP0_CLK_EN_MASK << (sel-4), en << (CSIC_MCSI_VIPP0_CLK_EN + (sel-4)));
450 }
451
452