1 /*
2 * linux-5.4/drivers/media/platform/sunxi-vin/vin-csi/parser_reg.c
3 *
4 * Copyright (c) 2007-2017 Allwinnertech Co., Ltd.
5 *
6 * Authors: Zhao Wei <zhaowei@allwinnertech.com>
7 *
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 */
18
19 #include <linux/kernel.h>
20 #include "parser_reg_i.h"
21 #include "parser_reg.h"
22
23 #include "../utility/vin_io.h"
24 #include "../platform/platform_cfg.h"
25
26 volatile void __iomem *csic_prs_base[VIN_MAX_CSI];
27
csic_prs_set_base_addr(unsigned int sel,unsigned long addr)28 int csic_prs_set_base_addr(unsigned int sel, unsigned long addr)
29 {
30 if (sel > VIN_MAX_CSI - 1)
31 return -1;
32 csic_prs_base[sel] = (volatile void __iomem *)addr;
33
34 return 0;
35 }
36
csic_prs_enable(unsigned int sel)37 void csic_prs_enable(unsigned int sel)
38 {
39 vin_reg_clr_set(csic_prs_base[sel] + PRS_EN_REG_OFF,
40 PRS_EN_REG_PRS_EN_MASK, 1 << PRS_EN_REG_PRS_EN);
41 }
42
csic_prs_disable(unsigned int sel)43 void csic_prs_disable(unsigned int sel)
44 {
45 vin_reg_clr_set(csic_prs_base[sel] + PRS_EN_REG_OFF,
46 PRS_EN_REG_PRS_EN_MASK, 0 << PRS_EN_REG_PRS_EN);
47 }
48
csic_prs_mode(unsigned int sel,enum prs_mode mode)49 void csic_prs_mode(unsigned int sel, enum prs_mode mode)
50 {
51 vin_reg_clr_set(csic_prs_base[sel] + PRS_EN_REG_OFF,
52 PRS_EN_REG_PRS_MODE_MASK, mode << PRS_EN_REG_PRS_MODE);
53 }
54
csic_prs_pclk_en(unsigned int sel,unsigned int en)55 void csic_prs_pclk_en(unsigned int sel, unsigned int en)
56 {
57 vin_reg_clr_set(csic_prs_base[sel] + PRS_EN_REG_OFF,
58 PRS_EN_REG_PCLK_EN_MASK, en << PRS_EN_REG_PCLK_EN);
59 }
60
csic_prs_ncsi_en(unsigned int sel,unsigned int en)61 void csic_prs_ncsi_en(unsigned int sel, unsigned int en)
62 {
63 vin_reg_clr_set(csic_prs_base[sel] + PRS_EN_REG_OFF,
64 PRS_EN_REG_NCSIC_EN_MASK, en << PRS_EN_REG_NCSIC_EN);
65 }
66
csic_prs_mcsi_en(unsigned int sel,unsigned int en)67 void csic_prs_mcsi_en(unsigned int sel, unsigned int en)
68 {
69 vin_reg_clr_set(csic_prs_base[sel] + PRS_EN_REG_OFF,
70 PRS_EN_REG_MCSIC_EN_MASK, en << PRS_EN_REG_MCSIC_EN);
71 }
72
csic_prs_ch_en(unsigned int sel,unsigned int en)73 void csic_prs_ch_en(unsigned int sel, unsigned int en)
74 {
75 vin_reg_clr_set(csic_prs_base[sel] + PRS_EN_REG_OFF,
76 PRS_CH_PRS_MODE_MASK, en << PRS_CH_PRS_MODE);
77 }
78
csic_prs_ncsi_if_cfg(unsigned int sel,struct prs_ncsi_if_cfg * if_cfg)79 void csic_prs_ncsi_if_cfg(unsigned int sel, struct prs_ncsi_if_cfg *if_cfg)
80 {
81 vin_reg_clr_set(csic_prs_base[sel] + PRS_NCSIC_IF_CFG_REG_OFF,
82 PRS_NCSIC_IF_CSI_IF_MASK,
83 if_cfg->intf << PRS_NCSIC_IF_CSI_IF);
84
85 vin_reg_clr_set(csic_prs_base[sel] + PRS_NCSIC_IF_CFG_REG_OFF,
86 PRS_NCSIC_IF_OUTPUT_MODE_MASK,
87 if_cfg->mode << PRS_NCSIC_IF_OUTPUT_MODE);
88
89 vin_reg_clr_set(csic_prs_base[sel] + PRS_NCSIC_IF_CFG_REG_OFF,
90 PRS_NCSIC_IF_INPUT_SEQ_MASK,
91 if_cfg->seq << PRS_NCSIC_IF_INPUT_SEQ);
92
93 vin_reg_clr_set(csic_prs_base[sel] + PRS_NCSIC_IF_CFG_REG_OFF,
94 PRS_NCSIC_IF_DATA_WIDTH_MASK,
95 if_cfg->dw << PRS_NCSIC_IF_DATA_WIDTH);
96
97 vin_reg_clr_set(csic_prs_base[sel] + PRS_NCSIC_IF_CFG_REG_OFF,
98 PRS_NCSIC_IF_CLK_POL_MASK,
99 if_cfg->clk << PRS_NCSIC_IF_CLK_POL);
100
101 vin_reg_clr_set(csic_prs_base[sel] + PRS_NCSIC_IF_CFG_REG_OFF,
102 PRS_NCSIC_IF_HREF_POL_MASK,
103 if_cfg->href << PRS_NCSIC_IF_HREF_POL);
104
105 vin_reg_clr_set(csic_prs_base[sel] + PRS_NCSIC_IF_CFG_REG_OFF,
106 PRS_NCSIC_IF_VREF_POL_MASK,
107 if_cfg->vref << PRS_NCSIC_IF_VREF_POL);
108
109 vin_reg_clr_set(csic_prs_base[sel] + PRS_NCSIC_IF_CFG_REG_OFF,
110 PRS_NCSIC_IF_FIELD_POL_MASK,
111 if_cfg->field << PRS_NCSIC_IF_FIELD_POL);
112
113 #ifndef CONFIG_ARCH_SUN8IW20
114 vin_reg_clr_set(csic_prs_base[sel] + PRS_NCSIC_IF_CFG_REG_OFF,
115 PRS_NCSIC_IF_SRC_TYPE_MASK,
116 if_cfg->type << PRS_NCSIC_IF_SRC_TYPE);
117 #else
118 vin_reg_clr_set(csic_prs_base[sel] + PRS_NCSIC_IF_CFG_REG_OFF,
119 PRS_NCSIC_IF_CH0_SRC_TYPE_MASK,
120 if_cfg->type << PRS_NCSIC_IF_CH0_SRC_TYPE);
121 vin_reg_clr_set(csic_prs_base[sel] + PRS_NCSIC_IF_CFG_REG_OFF,
122 PRS_NCSIC_IF_CH1_SRC_TYPE_MASK,
123 if_cfg->type << PRS_NCSIC_IF_CH1_SRC_TYPE);
124 vin_reg_clr_set(csic_prs_base[sel] + PRS_NCSIC_IF_CFG_REG_OFF,
125 PRS_NCSIC_IF_CH2_SRC_TYPE_MASK,
126 if_cfg->type << PRS_NCSIC_IF_CH2_SRC_TYPE);
127 vin_reg_clr_set(csic_prs_base[sel] + PRS_NCSIC_IF_CFG_REG_OFF,
128 PRS_NCSIC_IF_CH3_SRC_TYPE_MASK,
129 if_cfg->type << PRS_NCSIC_IF_CH3_SRC_TYPE);
130
131 #endif
132 vin_reg_clr_set(csic_prs_base[sel] + PRS_NCSIC_IF_CFG_REG_OFF,
133 PRS_NCSIC_IF_DDR_SAMPLE_MODE_MASK,
134 if_cfg->ddr_sample << PRS_NCSIC_IF_DDR_SAMPLE_MODE);
135 }
136
csic_prs_mcsi_if_cfg(unsigned int sel,struct prs_mcsi_if_cfg * if_cfg)137 void csic_prs_mcsi_if_cfg(unsigned int sel, struct prs_mcsi_if_cfg *if_cfg)
138 {
139 vin_reg_clr_set(csic_prs_base[sel] + PRS_MCSIC_IF_CFG_REG_OFF,
140 PRS_MCSIC_IF_INPUT_SEQ_MASK,
141 if_cfg->seq << PRS_MCSIC_IF_INPUT_SEQ);
142 vin_reg_clr_set(csic_prs_base[sel] + PRS_MCSIC_IF_CFG_REG_OFF,
143 PRS_MCSIC_IF_OUTPUT_MODE_MASK,
144 if_cfg->mode << PRS_MCSIC_IF_OUTPUT_MODE);
145 }
146
csic_prs_capture_start(unsigned int sel,unsigned int ch_total_num,struct prs_cap_mode * mode)147 void csic_prs_capture_start(unsigned int sel, unsigned int ch_total_num,
148 struct prs_cap_mode *mode)
149 {
150 /*u32 reg_val = (((ch_total_num >= 4) ? mode->mode : 0) << 24) +
151 (((ch_total_num >= 3) ? mode->mode : 0) << 16) +
152 (((ch_total_num >= 2) ? mode->mode : 0) << 8) +
153 (((ch_total_num >= 1) ? mode->mode : 0));
154 vin_reg_writel(csic_prs_base[sel] + PRS_CAP_REG_OFF, reg_val);*/
155 if (ch_total_num >= 4)
156 vin_reg_clr_set(csic_prs_base[sel] + PRS_CAP_REG_OFF,
157 CH3_SV_ON_MASK, mode->mode << CH3_SCAP_ON);
158 if (ch_total_num >= 3)
159 vin_reg_clr_set(csic_prs_base[sel] + PRS_CAP_REG_OFF,
160 CH2_SV_ON_MASK, mode->mode << CH2_SCAP_ON);
161 if (ch_total_num >= 2)
162 vin_reg_clr_set(csic_prs_base[sel] + PRS_CAP_REG_OFF,
163 CH1_SV_ON_MASK, mode->mode << CH1_SCAP_ON);
164 if (ch_total_num >= 1)
165 vin_reg_clr_set(csic_prs_base[sel] + PRS_CAP_REG_OFF,
166 CH0_SV_ON_MASK, mode->mode << CH0_SCAP_ON);
167 }
168
csic_prs_capture_stop(unsigned int sel)169 void csic_prs_capture_stop(unsigned int sel)
170 {
171 vin_reg_clr_set(csic_prs_base[sel] + PRS_CAP_REG_OFF,
172 CH3_SV_ON_MASK, 0 << CH3_SCAP_ON);
173 vin_reg_clr_set(csic_prs_base[sel] + PRS_CAP_REG_OFF,
174 CH2_SV_ON_MASK, 0 << CH2_SCAP_ON);
175 vin_reg_clr_set(csic_prs_base[sel] + PRS_CAP_REG_OFF,
176 CH1_SV_ON_MASK, 0 << CH1_SCAP_ON);
177 vin_reg_clr_set(csic_prs_base[sel] + PRS_CAP_REG_OFF,
178 CH0_SV_ON_MASK, 0 << CH0_SCAP_ON);
179 }
180
csic_prs_fps_ds(unsigned int sel,struct prs_fps_ds * prs_fps_ds)181 void csic_prs_fps_ds(unsigned int sel, struct prs_fps_ds *prs_fps_ds)
182 {
183 vin_reg_clr_set(csic_prs_base[sel] + PRS_CAP_REG_OFF,
184 CH0_FPS_DS_MASK, prs_fps_ds->ch0_fps_ds << CH0_FPS_DS);
185 vin_reg_clr_set(csic_prs_base[sel] + PRS_CAP_REG_OFF,
186 CH1_FPS_DS_MASK, prs_fps_ds->ch1_fps_ds << CH1_FPS_DS);
187 vin_reg_clr_set(csic_prs_base[sel] + PRS_CAP_REG_OFF,
188 CH2_FPS_DS_MASK, prs_fps_ds->ch2_fps_ds << CH2_FPS_DS);
189 vin_reg_clr_set(csic_prs_base[sel] + PRS_CAP_REG_OFF,
190 CH3_FPS_DS_MASK, prs_fps_ds->ch3_fps_ds << CH3_FPS_DS);
191 }
192
csic_prs_signal_status(unsigned int sel,struct prs_signal_status * status)193 void csic_prs_signal_status(unsigned int sel, struct prs_signal_status *status)
194 {
195 unsigned int reg_val = vin_reg_readl(csic_prs_base[sel] + PRS_SIGNAL_STA_REG_OFF);
196
197 status->pclk_sta = (reg_val & PCLK_STA_MASK) >> PCLK_STA;
198 status->data_sta = (reg_val & DATA_STA_MASK) >> DATA_STA;
199 }
200
csic_prs_ncsi_bt656_header_cfg(unsigned int sel,struct prs_ncsi_bt656_header * header)201 void csic_prs_ncsi_bt656_header_cfg(unsigned int sel, struct prs_ncsi_bt656_header *header)
202 {
203 unsigned int reg_val = (header->ch0_id << CH0_ID) |
204 (header->ch1_id << CH1_ID) |
205 (header->ch2_id << CH2_ID) |
206 (header->ch3_id << CH3_ID);
207 vin_reg_writel(csic_prs_base[sel] + PRS_NCSIC_BT656_HEAD_CFG_REG_OFF,
208 reg_val);
209 }
210
csic_prs_input_fmt_cfg(unsigned int sel,unsigned int ch,enum prs_input_fmt fmt)211 void csic_prs_input_fmt_cfg(unsigned int sel, unsigned int ch,
212 enum prs_input_fmt fmt)
213 {
214 vin_reg_writel(csic_prs_base[sel] + PRS_CH0_INFMT_REG_OFF +
215 ch * PARSER_CH_OFF, fmt);
216 }
217
csic_prs_output_size_cfg(unsigned int sel,unsigned int ch,struct prs_output_size * size)218 void csic_prs_output_size_cfg(unsigned int sel, unsigned int ch,
219 struct prs_output_size *size)
220 {
221 vin_reg_clr_set(csic_prs_base[sel] + PRS_CH0_OUTPUT_HSIZE_REG_OFF +
222 ch * PARSER_CH_OFF, PRS_CH0_HOR_START_MASK,
223 size->hor_start << PRS_CH0_HOR_START);
224 vin_reg_clr_set(csic_prs_base[sel] + PRS_CH0_OUTPUT_HSIZE_REG_OFF +
225 ch * PARSER_CH_OFF, PRS_CH0_HOR_LEN_MASK,
226 size->hor_len << PRS_CH0_HOR_LEN);
227 vin_reg_clr_set(csic_prs_base[sel] + PRS_CH0_OUTPUT_VSIZE_REG_OFF +
228 ch * PARSER_CH_OFF, PRS_CH0_VER_START_MASK,
229 size->ver_start << PRS_CH0_VER_START);
230 vin_reg_clr_set(csic_prs_base[sel] + PRS_CH0_OUTPUT_VSIZE_REG_OFF +
231 ch * PARSER_CH_OFF, PRS_CH0_VER_LEN_MASK,
232 size->ver_len << PRS_CH0_VER_LEN);
233 }
234
235
236 /* for debug */
csic_prs_input_para_get(unsigned int sel,unsigned int ch,struct prs_input_para * para)237 void csic_prs_input_para_get(unsigned int sel, unsigned int ch,
238 struct prs_input_para *para)
239 {
240 unsigned int reg_val = vin_reg_readl(csic_prs_base[sel] +
241 PRS_CH0_INPUT_PARA1_REG_OFF + ch * PARSER_CH_OFF);
242 para->input_ht = (reg_val >> PRS_CH0_INPUT_HT) & 0X3FFF;
243 para->input_vt = (reg_val >> PRS_CH0_INPUT_VT) & 0X3FFF;
244 reg_val = vin_reg_readl(csic_prs_base[sel] +
245 PRS_CH0_LINE_TIME_REG_OFF + ch * PARSER_CH_OFF);
246 para->input_hs = (reg_val >> PRS_CH0_INPUT_HSYN) & 0XFFFF;
247 para->input_hb = (reg_val >> PRS_CH0_INPUT_HBLK) & 0XFFFF;
248 }
249
csic_prs_int_enable(unsigned int sel,unsigned int ch,enum prs_int_sel interrupt)250 void csic_prs_int_enable(unsigned int sel, unsigned int ch,
251 enum prs_int_sel interrupt)
252 {
253 vin_reg_set(csic_prs_base[sel] + PRS_CH0_INT_EN_REG_OFF +
254 ch * PARSER_CH_OFF, interrupt);
255 }
csic_prs_int_disable(unsigned int sel,unsigned int ch,enum prs_int_sel interrupt)256 void csic_prs_int_disable(unsigned int sel, unsigned int ch,
257 enum prs_int_sel interrupt)
258 {
259 vin_reg_clr(csic_prs_base[sel] + PRS_CH0_INT_EN_REG_OFF +
260 ch * PARSER_CH_OFF, interrupt);
261 }
csic_prs_int_get_status(unsigned int sel,unsigned int ch,struct prs_int_status * status)262 void csic_prs_int_get_status(unsigned int sel, unsigned int ch,
263 struct prs_int_status *status)
264 {
265 unsigned int reg_val = vin_reg_readl(csic_prs_base[sel] +
266 PRS_CH0_INT_STA_REG_OFF + ch * PARSER_CH_OFF);
267 status->input_src_pd0 = (reg_val >> PRS_CH0_INPUT_SRC_PD0) & 0X01;
268 status->input_src_pd1 = (reg_val >> PRS_CH0_INPUT_SRC_PD1) & 0X01;
269 status->mul_err_pd = (reg_val >> PRS_CH0_MUL_ERR_PD) & 0X01;
270 }
csic_prs_int_clear_status(unsigned int sel,unsigned int ch,enum prs_int_sel interrupt)271 void csic_prs_int_clear_status(unsigned int sel, unsigned int ch,
272 enum prs_int_sel interrupt)
273 {
274 vin_reg_writel(csic_prs_base[sel] + PRS_CH0_INT_STA_REG_OFF +
275 ch * PARSER_CH_OFF, interrupt);
276 }
277
csic_prs_set_pclk_dly(unsigned int sel,unsigned int pclk_dly)278 void csic_prs_set_pclk_dly(unsigned int sel, unsigned int pclk_dly)
279 {
280 vin_reg_clr_set(csic_prs_base[sel] + PRS_NCSIC_RX_SIGNAL0_DLY_ADJ_REG_OFF,
281 PRS_PCLK_DLY_MASK, pclk_dly << PRS_PCLK_DLY);
282 }
283
csic_prs_sync_en_cfg(unsigned int sel,struct csi_sync_ctrl * sync)284 void csic_prs_sync_en_cfg(unsigned int sel, struct csi_sync_ctrl *sync)
285 {
286 vin_reg_clr_set(csic_prs_base[sel] + PRS_NCSIC_SYNC_EN_OFF,
287 PRS_NCSIC_SYNC_INPUT_VSYNC_SEL_MASK, sync->prs_sync_scr_sel << PRS_NCSIC_SYNC_INPUT_VSYNC_SEL);
288 vin_reg_clr_set(csic_prs_base[sel] + PRS_NCSIC_SYNC_EN_OFF,
289 PRS_NCSIC_SYNC_BENCH_SEL_MASK, sync->prs_sync_bench_sel << PRS_NCSIC_SYNC_BENCH_SEL);
290 vin_reg_clr_set(csic_prs_base[sel] + PRS_NCSIC_SYNC_EN_OFF,
291 PRS_NCSIC_SYNC_INPUT_VSYNC_EN_MASK, sync->prs_sync_input_vsync_en << PRS_NCSIC_SYNC_INPUT_VSYNC_EN);
292 vin_reg_clr_set(csic_prs_base[sel] + PRS_NCSIC_SYNC_EN_OFF,
293 PRS_NCSIC_SYNC_SINGAL_VIA_BY_MASK, sync->prs_sync_singal_via_by << PRS_NCSIC_SYNC_SINGAL_VIA_BY);
294 vin_reg_clr_set(csic_prs_base[sel] + PRS_NCSIC_SYNC_EN_OFF,
295 PRS_NCSIC_SYNC_SINGAL_SOURCE_SEL_MASK, sync->prs_sync_singal_scr_sel << PRS_NCSIC_SYNC_SINGAL_SOURCE_SEL);
296 }
csic_prs_sync_en(unsigned int sel,struct csi_sync_ctrl * sync)297 void csic_prs_sync_en(unsigned int sel, struct csi_sync_ctrl *sync)
298 {
299 vin_reg_clr_set(csic_prs_base[sel] + PRS_NCSIC_SYNC_EN_OFF,
300 PRS_NCSIC_SYNC_EN_SENT_SYNC_SINGAL_MASK, sync->prs_sync_en << PRS_NCSIC_SYNC_EN_SENT_SYNC_SINGAL);
301 }
302
csic_prs_sync_cfg(unsigned int sel,struct csi_sync_ctrl * sync)303 void csic_prs_sync_cfg(unsigned int sel, struct csi_sync_ctrl *sync)
304 {
305 vin_reg_clr_set(csic_prs_base[sel] + PRS_CSIC_SYNC_CFG_OFF,
306 PRS_CSIC_SYNC_PULSE_CFG_MASK, sync->prs_sync_pulse_cfg << PRS_CSIC_SYNC_PULSE_CFG);
307 vin_reg_clr_set(csic_prs_base[sel] + PRS_CSIC_SYNC_CFG_OFF,
308 PRS_CSIC_SYNC_DISTANCE_MASK, sync->prs_sync_dist << PRS_CSIC_SYNC_DISTANCE);
309 }
csic_prs_sync_wait_N(unsigned int sel,struct csi_sync_ctrl * sync)310 void csic_prs_sync_wait_N(unsigned int sel, struct csi_sync_ctrl *sync)
311 {
312 vin_reg_clr_set(csic_prs_base[sel] + PRS_CSIC_VS_WAIT_N_OFF,
313 PRS_CSIC_SYNC_WAIT_N_MASK, sync->prs_sync_wait_n << PRS_CSIC_SYNC_WAIT_N);
314 }
csic_prs_sync_wait_M(unsigned int sel,struct csi_sync_ctrl * sync)315 void csic_prs_sync_wait_M(unsigned int sel, struct csi_sync_ctrl *sync)
316 {
317 vin_reg_clr_set(csic_prs_base[sel] + PRS_CSIC_VS_WAIT_M_OFF,
318 PRS_CSIC_SYNC_WAIT_M_MASK, sync->prs_sync_wait_m << PRS_CSIC_SYNC_WAIT_M);
319 }
320
csic_prs_xs_en(unsigned int sel,struct csi_sync_ctrl * sync)321 void csic_prs_xs_en(unsigned int sel, struct csi_sync_ctrl *sync)
322 {
323 vin_reg_clr_set(csic_prs_base[sel] + PRS_CSIC_XS_ENABLE_REG_OFF,
324 PRS_CSIC_XS_XVS_OUT_EN_MASK, sync->prs_xvs_out_en << PRS_CSIC_XS_XVS_OUT_EN);
325 vin_reg_clr_set(csic_prs_base[sel] + PRS_CSIC_XS_ENABLE_REG_OFF,
326 PRS_CSIC_XS_XHS_OUT_EN_MASK, sync->prs_xhs_out_en << PRS_CSIC_XS_XHS_OUT_EN);
327 }
328
csic_prs_xs_period_len_register(unsigned int sel,struct csi_sync_ctrl * sync)329 void csic_prs_xs_period_len_register(unsigned int sel, struct csi_sync_ctrl *sync)
330 {
331 vin_reg_clr_set(csic_prs_base[sel] + PRS_CSIC_XVS_PERIOD_REG_OFF,
332 PRS_CSIC_XVS_T_MASK, sync->prs_xvs_t << PRS_CSIC_XVS_T);
333 vin_reg_clr_set(csic_prs_base[sel] + PRS_CSIC_XHS_PERIOD_REG_OFF,
334 PRS_CSIC_XHS_T_MASK, sync->prs_xhs_t << PRS_CSIC_XHS_T);
335 vin_reg_clr_set(csic_prs_base[sel] + PRS_CSIC_XVS_LEN_REG_OFF,
336 PRS_CSIC_XVS_LEN_MASK, sync->prs_xvs_len << PRS_CSIC_XVS_LEN);
337 vin_reg_clr_set(csic_prs_base[sel] + PRS_CSIC_XHS_LEN_REG_OFF,
338 PRS_CSIC_XHS_LEN_MASK, sync->prs_xhs_len << PRS_CSIC_XHS_LEN);
339 }
340