1 2 /* 3 * isp520_reg.h 4 * 5 * Copyright (c) 2007-2017 Allwinnertech Co., Ltd. 6 * 7 * Authors: Zhao Wei <zhaowei@allwinnertech.com> 8 * 9 * This software is licensed under the terms of the GNU General Public 10 * License version 2, as published by the Free Software Foundation, and 11 * may be copied, distributed, and modified under those terms. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 */ 19 20 #ifndef __ISP520__REG__H__ 21 #define __ISP520__REG__H__ 22 23 #define ISP_GLOBAL_CFG0_REG 0x000 24 #define ISP_GLOBAL_CFG1_REG 0x004 25 #define ISP_GLOBAL_CFG2_REG 0x008 26 27 #define ISP_UPDATE_CTRL0_REG 0x020 28 #define ISP_LOAD_ADDR0_REG 0x030 29 #define ISP_LOAD_ADDR1_REG 0x034 30 #define ISP_SAVE_ADDR_REG 0x038 31 #define ISP_INT_BYPASS0_REG 0x040 32 #define ISP_INT_STATUS0_REG 0x048 33 #define ISP_INTER_STATUS0_REG 0x060 34 #define ISP_INTER_STATUS1_REG 0x064 35 #define ISP_VER_CFG_REG 0x080 36 #define ISP_MAX_WIDTH_REG 0x084 37 #define ISP_COMP_FIFO_MAX_LAYER_REG 0x088 38 #define ISP_UNCOMP_FIFO_MAX_LAYER_REG 0x08c 39 40 #define ISP_WDR_CMP_BANDWIDTH_REG 0x090 41 #define ISP_WDR_DECMP_BANDWIDTH_REG 0x094 42 #define ISP_D3D_CMP_BANDWIDTH_REG 0x098 43 #define ISP_D3D_DECMP_BANDWIDTH_REG 0x09c 44 45 #define ISP_S0_FMERR_CNT_REG 0x0a0 46 #define ISP_S1_FMERR_CNT_REG 0x0a4 47 #define ISP_S0_HB_CNT_REG 0x0b0 48 #define ISP_S1_HB_CNT_REG 0x0b4 49 #define ISP_WDR_FIFO_OVERFLOW_LINE_REG 0x0c0 50 #define ISP_D3D_FIFO_OVERFLOW_LINE_REG 0x0c4 51 #define ISP_WDR_EXP_ADDR0_REG 0x0d0 52 #define ISP_WDR_EXP_ADDR1_REG 0x0d4 53 #define ISP_SIM_CTRL_REG 0x0e0 54 #define ISP_D3D_REC_ADDR0_REG 0x0f0 55 #define ISP_D3D_REC_ADDR1_REG 0x0f4 56 #define ISP_TOP_CTRL_REG 0x0fc 57 58 #define ISP_S1_CFG_REG 0x100 59 #define ISP_MODULE_BYPASS0_REG 0x1a0 60 #define ISP_INPUT_SIZE_REG 0x1e0 61 #define ISP_VALID_SIZE_REG 0x1e4 62 #define ISP_VALID_START_REG 0x1e8 63 64 #define ISP_LSC_CFG0_REG 0x390 65 66 #define ISP_PLTM_CFG0_REG 0x3b0 67 68 #define ISP_PLTM_CFG2_REG 0x3b8 69 #define ISP_PLTM_CFG3_REG 0x3bc 70 71 typedef union { 72 unsigned int dwval; 73 struct { 74 unsigned int isp_enable:1; 75 unsigned int cap_en:1; 76 unsigned int isp_ver_rd_en:1; 77 unsigned int int_mode:1; 78 unsigned int input_fmt:3; 79 unsigned int res0:1; 80 unsigned int isp_ch0_en:1; 81 unsigned int isp_ch1_en:1; 82 unsigned int isp_ch2_en:1; 83 unsigned int isp_ch3_en:1; 84 unsigned int wdr_ch_seq:1; 85 unsigned int wdr_exp_seq:1; 86 unsigned int wdr_mode:2; 87 unsigned int res1:16; 88 } bits; 89 } ISP_GLOBAL_CFG0_REG_t; 90 91 typedef union { 92 unsigned int dwval; 93 struct { 94 unsigned int line_int_num:14; 95 unsigned int res0:2; 96 unsigned int speed_mode:3; 97 unsigned int res1:1; 98 unsigned int last_blank_cycle:3; 99 unsigned int res2:1; 100 unsigned int burst_length:3; 101 unsigned int res3:2; 102 unsigned int bandwidth_reg_en:1; 103 unsigned int bandwidth_reg_clr:1; 104 unsigned int fifo_max_layer_clr:1; 105 } bits; 106 } ISP_GLOBAL_CFG1_REG_t; 107 108 typedef union { 109 unsigned int dwval; 110 struct { 111 unsigned int debug_en:1; 112 unsigned int sram_clear:1; 113 unsigned int pltm_sram_clr_en:1; 114 unsigned int module_clr_back_door:1; 115 unsigned int debug_sel:5; 116 unsigned int res0:23; 117 } bits; 118 } ISP_GLOBAL_CFG2_REG_t; 119 120 121 typedef union { 122 unsigned int dwval; 123 struct { 124 unsigned int para_ready:1; 125 unsigned int linear_update:1; 126 unsigned int lens_update:1; 127 unsigned int gamma_update:1; 128 unsigned int drc_update:1; 129 unsigned int satu_update:1; 130 unsigned int wdr_update:1; 131 unsigned int d3d_update:1; 132 unsigned int pltm_update:1; 133 unsigned int cem_update:1; 134 unsigned int res0:1; 135 unsigned int dehaze_update:1; 136 unsigned int s1_para_ready:1; 137 unsigned int s1_linear_update:1; 138 unsigned int res1:18; 139 } bits; 140 } ISP_UPDATE_CTRL0_REG_t; 141 142 typedef union { 143 unsigned int dwval; 144 struct { 145 unsigned int finish_int_en:1; 146 unsigned int s0_start_int_en:1; 147 unsigned int s1_start_int_en:1; 148 unsigned int para_save_int_en:1; 149 unsigned int s0_para_load_int_en:1; 150 unsigned int s1_para_load_int_en:1; 151 unsigned int s0_fifo_int_en:1; 152 unsigned int s1_fifo_int_en:1; 153 unsigned int s0_n_line_start_int_en:1; 154 unsigned int s1_n_line_start_int_en:1; 155 unsigned int s0_frame_error_int_en:1; 156 unsigned int s1_frame_error_int_en:1; 157 unsigned int s0_frame_lost_int_en:1; 158 unsigned int s1_frame_lost_int_en:1; 159 unsigned int s0_hb_short_int_en:1; 160 unsigned int s1_hb_short_int_en:1; 161 unsigned int sram_clr_int_en:1; 162 unsigned int ddr_w_finish_int_en:1; 163 unsigned int res0:14; 164 } bits; 165 } ISP_INT_BYPASS0_REG_t; 166 167 typedef union { 168 unsigned int dwval; 169 struct { 170 unsigned int finish_pd:1; 171 unsigned int s0_start_pd:1; 172 unsigned int s1_start_pd:1; 173 unsigned int para_saved_pd:1; 174 unsigned int s0_para_load_pd:1; 175 unsigned int s1_para_load_pd:1; 176 unsigned int s0_fifo_of_pd:1; 177 unsigned int s1_fifo_of_pd:1; 178 unsigned int s0_n_line_start_pd:1; 179 unsigned int s1_n_line_start_pd:1; 180 unsigned int s0_frame_error_pd:1; 181 unsigned int s1_frame_error_pd:1; 182 unsigned int s0_frame_lost_pd:1; 183 unsigned int s1_frame_lost_pd:1; 184 unsigned int s0_hb_short_pd:1; 185 unsigned int s1_hb_short_pd:1; 186 unsigned int sram_clr_pd:1; 187 unsigned int ddr_w_finish_pd:1; 188 unsigned int res0:13; 189 unsigned int fifo_valid_st:1; 190 } bits; 191 } ISP_INT_STATUS0_REG_t; 192 193 typedef union { 194 unsigned int dwval; 195 struct { 196 unsigned int d3d_w_finish_pd:1; 197 unsigned int wdr_w_finish_pd:1; 198 unsigned int s0_cin_fifo_of_pd:1; 199 unsigned int dpc_fifo_of_pd:1; 200 unsigned int res0:1; 201 unsigned int bis_fifo_of_pd:1; 202 unsigned int cnr_fifo_of_pd:1; 203 unsigned int pltm_fifo_of_pd:1; 204 unsigned int d3d_write_fifo_of_pd:1; 205 unsigned int d3d_read_fifo_of_pd:1; 206 unsigned int res1:1; 207 unsigned int wdr_write_fifo_of_pd:1; 208 unsigned int res2:1; 209 unsigned int wdr_read_fifo_of_pd:1; 210 unsigned int res3:1; 211 unsigned int s1_cin_fifo_of_pd:1; 212 unsigned int res4:16; 213 } bits; 214 } ISP_INTER_STATUS0_REG_t; 215 216 typedef union { 217 unsigned int dwval; 218 struct { 219 unsigned int top_ctrl_st:8; 220 unsigned int wdr_ctrl_st:8; 221 unsigned int mbus_st:1; 222 unsigned int wdr_cmp_mbus_st:1; 223 unsigned int wdr_ucmp_mbus_st:1; 224 unsigned int d3d_cmp_mbus_st:1; 225 unsigned int d3d_ucmp_mbus_st:1; 226 unsigned int mbus_stop:1; 227 unsigned int res1:10; 228 } bits; 229 } ISP_INTER_STATUS1_REG_t; 230 231 typedef union { 232 unsigned int dwval; 233 struct { 234 unsigned int small_ver:12; 235 unsigned int big_ver:12; 236 unsigned int res0:8; 237 } bits; 238 } ISP_VER_CFG_REG_t; 239 240 typedef union { 241 unsigned int dwval; 242 struct { 243 unsigned int max_width:16; 244 unsigned int res0:16; 245 } bits; 246 } ISP_MAX_WIDTH_REG_t; 247 248 typedef union { 249 unsigned int dwval; 250 struct { 251 unsigned int wdr_fifo_max_layer:16; 252 unsigned int d3d_fifo_max_layer:16; 253 } bits; 254 } ISP_COMP_FIFO_MAX_LAYER_REG_t; 255 256 typedef union { 257 unsigned int dwval; 258 struct { 259 unsigned int wdr_fifo_max_layer:16; 260 unsigned int d3d_fifo_max_layer:16; 261 } bits; 262 } ISP_UNCOMP_FIFO_MAX_LAYER_REG_t; 263 264 typedef union { 265 unsigned int dwval; 266 struct { 267 unsigned int wdr_cmp_bandwidth; 268 } bits; 269 } ISP_WDR_CMP_BANDWIDTH_REG_t; 270 271 typedef union { 272 unsigned int dwval; 273 struct { 274 unsigned int wdr_decmp_bandwidth; 275 } bits; 276 } ISP_WDR_DECMP_BANDWIDTH_REG_t; 277 278 typedef union { 279 unsigned int dwval; 280 struct { 281 unsigned int d3d_cmp_bandwidth; 282 } bits; 283 } ISP_D3D_CMP_BANDWIDTH_REG_t; 284 285 typedef union { 286 unsigned int dwval; 287 struct { 288 unsigned int d3d_decmp_bandwidth; 289 } bits; 290 } ISP_D3D_DECMP_BANDWIDTH_REG_t; 291 292 typedef union { 293 unsigned int dwval; 294 struct { 295 unsigned int input_width:14; 296 unsigned int res0:2; 297 unsigned int input_height:14; 298 unsigned int res1:2; 299 } bits; 300 } ISP_S0_FMERR_CNT_REG_t; 301 302 typedef union { 303 unsigned int dwval; 304 struct { 305 unsigned int input_width:14; 306 unsigned int res0:2; 307 unsigned int input_height:14; 308 unsigned int res1:2; 309 } bits; 310 } ISP_S1_FMERR_CNT_REG_t; 311 312 typedef union { 313 unsigned int dwval; 314 struct { 315 unsigned int hb_min:16; 316 unsigned int hb_max:16; 317 } bits; 318 } ISP_S0_HB_CNT_REG_t; 319 320 typedef union { 321 unsigned int dwval; 322 struct { 323 unsigned int hb_min:16; 324 unsigned int hb_max:16; 325 } bits; 326 } ISP_S1_HB_CNT_REG_t; 327 328 typedef union { 329 unsigned int dwval; 330 struct { 331 unsigned int comp_overflow_line:14; 332 unsigned int res0:2; 333 unsigned int decomp_overflow_line:14; 334 unsigned int res1:2; 335 } bits; 336 } ISP_WDR_FIFO_OVERFLOW_LINE_REG_t; 337 338 typedef union { 339 unsigned int dwval; 340 struct { 341 unsigned int comp_overflow_line:14; 342 unsigned int res0:2; 343 unsigned int decomp_overflow_line:14; 344 unsigned int res1:2; 345 } bits; 346 } ISP_D3D_FIFO_OVERFLOW_LINE_REG_t; 347 348 typedef union { 349 unsigned int dwval; 350 struct { 351 unsigned int pltm_mid_test:1; 352 unsigned int pltm_read_finish:1; 353 unsigned int res0:30; 354 } bits; 355 } ISP_SIM_CTRL_REG_t; 356 357 typedef union { 358 unsigned int dwval; 359 struct { 360 unsigned int isp0_max_width:14; 361 unsigned int res0:2; 362 unsigned int isp_mode:1; 363 unsigned int res1:15; 364 } bits; 365 } ISP_TOP_CTRL_REG_t; 366 367 typedef union { 368 unsigned int dwval; 369 struct { 370 unsigned int s1_blc_en:14; 371 unsigned int s1_lc_en:2; 372 unsigned int res0:30; 373 } bits; 374 } ISP_S1_CFG_REG_t; 375 376 typedef union { 377 unsigned int dwval; 378 struct { 379 unsigned int ae_en:1; 380 unsigned int lc_en:1; 381 unsigned int wdr_en:1; 382 unsigned int dpc_en:1; 383 unsigned int d2d_en:1; 384 unsigned int d3d_en:1; 385 unsigned int awb_en:1; 386 unsigned int wb_en:1; 387 unsigned int lsc_en:1; 388 unsigned int bgc_en:1; 389 unsigned int sharp_en:1; 390 unsigned int af_en:1; 391 unsigned int rgb2rgb_en:1; 392 unsigned int rgb_drc_en:1; 393 unsigned int pltm_en:1; 394 unsigned int cem_en:1; 395 unsigned int afs_en:1; 396 unsigned int hist_en:1; 397 unsigned int blc_en:1; 398 unsigned int dg_en:1; 399 unsigned int so_en:1; 400 unsigned int ctc_en:1; 401 unsigned int res0:1; 402 unsigned int cnr_en:1; 403 unsigned int satu_en:1; 404 unsigned int dehaze_en:1; 405 unsigned int res1:6; 406 } bits; 407 } ISP_MODULE_BYPASS0_REG_t; 408 409 typedef union { 410 unsigned int dwval; 411 struct { 412 unsigned int input_width:14; 413 unsigned int res0:2; 414 unsigned int input_height:14; 415 unsigned int res1:2; 416 } bits; 417 } ISP_INPUT_SIZE_REG_t; 418 419 typedef union { 420 unsigned int dwval; 421 struct { 422 unsigned int valid_width:14; 423 unsigned int res0:2; 424 unsigned int valid_height:14; 425 unsigned int res1:2; 426 } bits; 427 } ISP_VALID_SIZE_REG_t; 428 429 typedef union { 430 unsigned int dwval; 431 struct { 432 unsigned int valid_hor_start:13; 433 unsigned int res0:3; 434 unsigned int valid_ver_start:13; 435 unsigned int res1:3; 436 } bits; 437 } ISP_VALID_START_REG_t; 438 439 typedef union { 440 unsigned int dwval; 441 struct { 442 unsigned int lsc_ct_x:13; 443 unsigned int lsc_ct_y:13; 444 unsigned int lsc_rs_value:5; 445 unsigned int res0:1; 446 } bits; 447 } ISP_LSC_CFG0_REG_t; 448 449 typedef union { 450 unsigned int dwval; 451 struct { 452 unsigned int lss_switch:1; 453 unsigned int cal_en:1; 454 unsigned int frm_sm_en:1; 455 unsigned int res0:5; 456 unsigned int last_order_ratio:4; 457 unsigned int res1:4; 458 unsigned int tr_order:4; 459 unsigned int res2:4; 460 unsigned int oripic_ratio:8; 461 } bits; 462 } ISP_PLTM_CFG0_REG_t; 463 464 typedef union { 465 unsigned int dwval; 466 struct { 467 unsigned int block_height:8; 468 unsigned int block_width:8; 469 unsigned int block_v_num:5; 470 unsigned int res0:3; 471 unsigned int block_h_num:5; 472 unsigned int res1:3; 473 } bits; 474 } ISP_PLTM_CFG2_REG_t; 475 476 typedef union { 477 unsigned int dwval; 478 struct { 479 unsigned int statistic_div; 480 } bits; 481 } ISP_PLTM_CFG3_REG_t; 482 483 #endif /*__ISP520__REG__H__*/ 484