1 2 /* 3 * isp521_reg.h 4 * 5 * Copyright (c) 2007-2017 Allwinnertech Co., Ltd. 6 * 7 * Authors: Zhao Wei <zhaowei@allwinnertech.com> 8 * 9 * This software is licensed under the terms of the GNU General Public 10 * License version 2, as published by the Free Software Foundation, and 11 * may be copied, distributed, and modified under those terms. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 */ 19 20 #ifndef _ISP521_REG_H_ 21 #define _ISP521_REG_H_ 22 23 #define ISP_GLOBAL_CFG0_REG 0x000 24 #define ISP_GLOBAL_CFG1_REG 0x004 25 #define ISP_GLOBAL_CFG2_REG 0x008 26 #define ISP_GLOBAL_CFG3_REG 0x00c 27 28 #define ISP_UPDATE_CTRL0_REG 0x020 29 #define ISP_LOAD_ADDR0_REG 0x030 30 #define ISP_LOAD_ADDR1_REG 0x034 31 #define ISP_SAVE_ADDR_REG 0x038 32 #define ISP_INT_BYPASS0_REG 0x040 33 #define ISP_INT_STATUS0_REG 0x048 34 #define ISP_INTER_STATUS0_REG 0x060 35 #define ISP_INTER_STATUS1_REG 0x064 36 #define ISP_INTER_STATUS2_REG 0x068 37 #define ISP_LBC_INTER_STATUS_REG 0x074 38 #define ISP_UNCOMP_FIFO_MAX_LAYER0_REG 0x078 39 #define ISP_UNCOMP_FIFO_MAX_LAYER1_REG 0x07c 40 #define ISP_VER_CFG_REG 0x080 41 #define ISP_MAX_WIDTH_REG 0x084 42 #define ISP_COMP_FIFO_MAX_LAYER0_REG 0x088 43 #define ISP_COMP_FIFO_MAX_LAYER1_REG 0x08c 44 45 #define ISP_WDR_CMP_BANDWIDTH_REG 0x090 46 #define ISP_WDR_DECMP_BANDWIDTH_REG 0x094 47 #define ISP_D3D_CMP_BANDWIDTH_REG 0x098 48 #define ISP_D3D_DECMP_BANDWIDTH_REG 0x09c 49 50 #define ISP_S0_FMERR_CNT_REG 0x0a0 51 #define ISP_S1_FMERR_CNT_REG 0x0a4 52 #define ISP_S0_HB_CNT_REG 0x0b0 53 #define ISP_S1_HB_CNT_REG 0x0b4 54 #define ISP_WDR_FIFO_OVERFLOW_LINE_REG 0x0c0 55 #define ISP_D3D_FIFO_OVERFLOW_LINE_REG 0x0c4 56 #define ISP_WDR_DMA_STRIDE_LEN_REG 0x0c8 57 #define ISP_D3D_DMA_STRIDE_LEN_REG 0x0cc 58 59 #define ISP_WDR_EXP_ADDR0_REG 0x0d0 60 #define ISP_SIM_CTRL_REG 0x0e0 61 62 #define ISP_INPUT_SIZE_REG 0x0e4 63 #define ISP_VALID_SIZE_REG 0x0e8 64 #define ISP_VALID_START_REG 0x0ec 65 66 #define ISP_D3D_REF_K_ADDR_REG 0x0f0 67 #define ISP_D3D_REF_RAW_ADDR_REG 0x0f4 68 #define ISP_D3D_LTF_RAW_ADDR_REG 0x0f8 69 70 #define ISP_TOP_CTRL_REG 0x0fc 71 72 #define ISP_S1_CFG_REG 0x100 73 #define ISP_MODULE_BYPASS0_REG 0x1a0 74 #define ISP_WDR_RAW_LBC_CTRL_REG 0x11c 75 #define ISP_D3D_RAW_LBC_CTRL_REG 0x1d0 76 #define ISP_D3D_K_LBC_CTRL_REG 0x1d4 77 78 typedef union { 79 unsigned int dwval; 80 struct { 81 unsigned int isp_enable:1; 82 unsigned int cap_en:1; 83 unsigned int isp_ver_rd_en:1; 84 unsigned int int_mode:1; 85 unsigned int input_fmt:3; 86 unsigned int res0:1; 87 unsigned int isp_ch0_en:1; 88 unsigned int isp_ch1_en:1; 89 unsigned int isp_ch2_en:1; 90 unsigned int isp_ch3_en:1; 91 unsigned int wdr_ch_seq:1; 92 unsigned int wdr_exp_seq:1; 93 unsigned int wdr_mode:2; 94 unsigned int res1:8; 95 unsigned int wdr_cmp_mode:1; 96 unsigned int res2:7; 97 } bits; 98 } ISP_GLOBAL_CFG0_REG_t; 99 100 typedef union { 101 unsigned int dwval; 102 struct { 103 unsigned int line_int_num:14; 104 unsigned int wdr_en:1; 105 unsigned int res0:1; 106 unsigned int speed_mode:3; 107 unsigned int res1:1; 108 unsigned int last_blank_cycle:3; 109 unsigned int res2:1; 110 unsigned int burst_length:3; 111 unsigned int wdr_fifo_exit:1; 112 unsigned int d3d_ltf_fifo_exit:1; 113 unsigned int d3d_fifo_exit:1; 114 unsigned int bandwidth_reg_en:1; 115 unsigned int fifo_max_layer_en:1; 116 } bits; 117 } ISP_GLOBAL_CFG1_REG_t; 118 119 typedef union { 120 unsigned int dwval; 121 struct { 122 unsigned int debug_en:1; 123 unsigned int sram_clear:1; 124 unsigned int pltm_sram_clr_en:1; 125 unsigned int module_clr_back_door:1; 126 unsigned int debug_sel:5; 127 unsigned int res0:3; 128 unsigned int vgm_en:1; 129 unsigned int vgm_start:1; 130 unsigned int vgm_mode:1; 131 unsigned int res1:1; 132 unsigned int d3d_cmp_ofln_sel:1; 133 unsigned int d3d_uncmp_ofln_sel:2; 134 unsigned int res2:12; 135 unsigned int fsm_back_door_en:1; 136 } bits; 137 } ISP_GLOBAL_CFG2_REG_t; 138 139 typedef union { 140 unsigned int dwval; 141 struct { 142 unsigned int fifo_dep_raw_rd:11; 143 unsigned int res0:1; 144 unsigned int raw_min_ddr_size:2; 145 unsigned int d3d_uncmp_bandwd_sel:2; 146 unsigned int fifo_dep_raw_wr:11; 147 unsigned int res1:1; 148 unsigned int k_min_ddr_size:2; 149 unsigned int d3d_cmp_bandwd_sel:2; 150 } bits; 151 } ISP_GLOBAL_CFG3_REG_t; 152 153 154 typedef union { 155 unsigned int dwval; 156 struct { 157 unsigned int para_ready:1; 158 unsigned int linear_update:1; 159 unsigned int lens_update:1; 160 unsigned int gamma_update:1; 161 unsigned int drc_update:1; 162 unsigned int satu_update:1; 163 unsigned int wdr_update:1; 164 unsigned int d3d_update:1; 165 unsigned int pltm_update:1; 166 unsigned int cem_update:1; 167 unsigned int msc_update:1; 168 unsigned int dehaze_update:1; 169 unsigned int s1_para_ready:1; 170 unsigned int s1_linear_update:1; 171 unsigned int res1:16; 172 unsigned int dbg_tbl_update:1; 173 unsigned int dbg_stat_update:1; 174 } bits; 175 } ISP_UPDATE_CTRL0_REG_t; 176 177 typedef union { 178 unsigned int dwval; 179 struct { 180 unsigned int finish_int_en:1; 181 unsigned int s0_start_int_en:1; 182 unsigned int s1_start_int_en:1; 183 unsigned int para_save_int_en:1; 184 unsigned int s0_para_load_int_en:1; 185 unsigned int s1_para_load_int_en:1; 186 unsigned int s0_fifo_int_en:1; 187 unsigned int s1_fifo_int_en:1; 188 unsigned int s0_n_line_start_int_en:1; 189 unsigned int s1_n_line_start_int_en:1; 190 unsigned int s0_frame_error_int_en:1; 191 unsigned int s1_frame_error_int_en:1; 192 unsigned int s0_frame_lost_int_en:1; 193 unsigned int s1_frame_lost_int_en:1; 194 unsigned int s0_hb_short_int_en:1; 195 unsigned int s1_hb_short_int_en:1; 196 unsigned int sram_clr_int_en:1; 197 unsigned int ddr_w_finish_int_en:1; 198 unsigned int s0_btype_error_int_en:1; 199 unsigned int s1_btype_error_int_en:1; 200 unsigned int addr_error_int_en:1; 201 unsigned int lbc_error_int_en:1; 202 unsigned int fsm_frame_lost_int_en:1; 203 unsigned int res0:9; 204 } bits; 205 } ISP_INT_BYPASS0_REG_t; 206 207 typedef union { 208 unsigned int dwval; 209 struct { 210 unsigned int finish_pd:1; 211 unsigned int s0_start_pd:1; 212 unsigned int s1_start_pd:1; 213 unsigned int para_saved_pd:1; 214 unsigned int s0_para_load_pd:1; 215 unsigned int s1_para_load_pd:1; 216 unsigned int s0_fifo_of_pd:1; 217 unsigned int s1_fifo_of_pd:1; 218 unsigned int s0_n_line_start_pd:1; 219 unsigned int s1_n_line_start_pd:1; 220 unsigned int s0_frame_error_pd:1; 221 unsigned int s1_frame_error_pd:1; 222 unsigned int s0_frame_lost_pd:1; 223 unsigned int s1_frame_lost_pd:1; 224 unsigned int s0_hb_short_pd:1; 225 unsigned int s1_hb_short_pd:1; 226 unsigned int sram_clr_pd:1; 227 unsigned int ddr_w_finish_pd:1; 228 unsigned int s0_btype_error_pd:1; 229 unsigned int s1_btype_error_pd:1; 230 unsigned int addr_error_pd:1; 231 unsigned int lbc_error_pd:1; 232 unsigned int fsm_frame_lost_pd:1; 233 unsigned int res0:8; 234 unsigned int fifo_valid_st:1; 235 } bits; 236 } ISP_INT_STATUS0_REG_t; 237 238 typedef union { 239 unsigned int dwval; 240 struct { 241 unsigned int d3d_w_finish_pd:1; 242 unsigned int wdr_w_finish_pd:1; 243 unsigned int s0_cin_fifo_of_pd:1; 244 unsigned int dpc_fifo_of_pd:1; 245 unsigned int res0:1; 246 unsigned int bis_fifo_of_pd:1; 247 unsigned int cnr_fifo_of_pd:1; 248 unsigned int pltm_fifo_of_pd:1; 249 unsigned int d3d_write_fifo_of_pd:1; 250 unsigned int d3d_read_fifo_of_pd:1; 251 unsigned int res1:1; 252 unsigned int wdr_write_fifo_of_pd:1; 253 unsigned int res2:1; 254 unsigned int wdr_read_fifo_of_pd:1; 255 unsigned int res3:1; 256 unsigned int s1_cin_fifo_of_pd:1; 257 unsigned int lca_rgb_fifo_r_emp_pd:1; 258 unsigned int lca_rgb_fifo_w_full_pd:1; 259 unsigned int lca_by_fifo_r_emp_pd:1; 260 unsigned int lca_by_fifo_w_full_pd:1; 261 unsigned int d3d_k_fifo_w_full_pd:1; 262 unsigned int d3d_raw_fifo_w_full_pd:1; 263 unsigned int d3d_k_fifo_r_emp_pd:1; 264 unsigned int d3d_ref_fifo_r_emp_pd:1; 265 unsigned int d3d_ltf_fifo_r_emp_pd:1; 266 unsigned int res4:7; 267 } bits; 268 } ISP_INTER_STATUS0_REG_t; 269 270 typedef union { 271 unsigned int dwval; 272 struct { 273 unsigned int top_ctrl_st:8; 274 unsigned int wdr_ctrl_st:8; 275 unsigned int mbus_st:1; 276 unsigned int wdr_cmp_mbus_st:1; 277 unsigned int wdr_ucmp_mbus_st:1; 278 unsigned int res0:2; 279 unsigned int mbus_stop:1; 280 unsigned int d3d_k_cmp_mbus_st:1; 281 unsigned int d3d_ref_cmp_mbus_st:1; 282 unsigned int d3d_k_ucmp_mbus_st:1; 283 unsigned int d3d_ref_ucmp_mbus_st:1; 284 unsigned int d3d_ltf_ucmp_mbus_st:1; 285 unsigned int res1:5; 286 } bits; 287 } ISP_INTER_STATUS1_REG_t; 288 289 typedef union { 290 unsigned int dwval; 291 struct { 292 unsigned int wdr_ctrl_st:8; 293 unsigned int res0:24; 294 } bits; 295 } ISP_INTER_STATUS2_REG_t; 296 297 typedef union { 298 unsigned int dwval; 299 struct { 300 unsigned int wdr_lbc_dec_err:5; 301 unsigned int res0:3; 302 unsigned int d3d_k_lbc_dec_err:5; 303 unsigned int res1:3; 304 unsigned int d3d_ref_lbc_dec_err:5; 305 unsigned int res2:3; 306 unsigned int d3d_ltf_lbc_dec_err:5; 307 unsigned int res3:3; 308 } bits; 309 } ISP_LBC_INTER_STATUS_REG_t; 310 311 typedef union { 312 unsigned int dwval; 313 struct { 314 unsigned int small_ver:12; 315 unsigned int big_ver:12; 316 unsigned int res0:8; 317 } bits; 318 } ISP_VER_CFG_REG_t; 319 320 typedef union { 321 unsigned int dwval; 322 struct { 323 unsigned int max_width:16; 324 unsigned int max_height:16; 325 } bits; 326 } ISP_MAX_SIZE_REG_t; 327 328 typedef union { 329 unsigned int dwval; 330 struct { 331 unsigned int d3d_k_fifo_max_layer:16; 332 unsigned int d3d_raw_fifo_max_layer:16; 333 } bits; 334 } ISP_COMP_FIFO_MAX_LAYER0_REG_t; 335 336 typedef union { 337 unsigned int dwval; 338 struct { 339 unsigned int wdr_fifo_max_layer:16; 340 unsigned int res0:16; 341 } bits; 342 } ISP_COMP_FIFO_MAX_LAYER1_REG_t; 343 344 typedef union { 345 unsigned int dwval; 346 struct { 347 unsigned int wdr_fifo_max_layer:16; 348 unsigned int d3d_ltf_fifo_max_layer:16; 349 } bits; 350 } ISP_UNCOMP_FIFO_MAX_LAYER0_REG_t; 351 352 typedef union { 353 unsigned int dwval; 354 struct { 355 unsigned int d3d_k_fifo_max_layer:16; 356 unsigned int d3d_ref_fifo_max_layer:16; 357 } bits; 358 } ISP_UNCOMP_FIFO_MAX_LAYER1_REG_t; 359 360 typedef union { 361 unsigned int dwval; 362 struct { 363 unsigned int wdr_cmp_bandwidth; 364 } bits; 365 } ISP_WDR_CMP_BANDWIDTH_REG_t; 366 367 typedef union { 368 unsigned int dwval; 369 struct { 370 unsigned int wdr_decmp_bandwidth; 371 } bits; 372 } ISP_WDR_DECMP_BANDWIDTH_REG_t; 373 374 typedef union { 375 unsigned int dwval; 376 struct { 377 unsigned int d3d_cmp_bandwidth; 378 } bits; 379 } ISP_D3D_CMP_BANDWIDTH_REG_t; 380 381 typedef union { 382 unsigned int dwval; 383 struct { 384 unsigned int d3d_decmp_bandwidth; 385 } bits; 386 } ISP_D3D_DECMP_BANDWIDTH_REG_t; 387 388 typedef union { 389 unsigned int dwval; 390 struct { 391 unsigned int input_width:14; 392 unsigned int res0:2; 393 unsigned int input_height:14; 394 unsigned int res1:2; 395 } bits; 396 } ISP_S0_FMERR_CNT_REG_t; 397 398 typedef union { 399 unsigned int dwval; 400 struct { 401 unsigned int input_width:14; 402 unsigned int res0:2; 403 unsigned int input_height:14; 404 unsigned int res1:2; 405 } bits; 406 } ISP_S1_FMERR_CNT_REG_t; 407 408 typedef union { 409 unsigned int dwval; 410 struct { 411 unsigned int hb_min:16; 412 unsigned int hb_max:16; 413 } bits; 414 } ISP_S0_HB_CNT_REG_t; 415 416 typedef union { 417 unsigned int dwval; 418 struct { 419 unsigned int hb_min:16; 420 unsigned int hb_max:16; 421 } bits; 422 } ISP_S1_HB_CNT_REG_t; 423 424 typedef union { 425 unsigned int dwval; 426 struct { 427 unsigned int comp_overflow_line:14; 428 unsigned int res0:2; 429 unsigned int decomp_overflow_line:14; 430 unsigned int res1:2; 431 } bits; 432 } ISP_WDR_FIFO_OVERFLOW_LINE_REG_t; 433 434 typedef union { 435 unsigned int dwval; 436 struct { 437 unsigned int comp_overflow_line:14; 438 unsigned int res0:2; 439 unsigned int decomp_overflow_line:14; 440 unsigned int res1:2; 441 } bits; 442 } ISP_D3D_FIFO_OVERFLOW_LINE_REG_t; 443 444 typedef union { 445 unsigned int dwval; 446 struct { 447 unsigned int wdr_dma_len:11; 448 unsigned int res0:21; 449 } bits; 450 } ISP_WDR_DMA_STRIDE_LEN_REG_t; 451 452 typedef union { 453 unsigned int dwval; 454 struct { 455 unsigned int d3d_ref_raw_dma_len:11; 456 unsigned int res0:5; 457 unsigned int d3d_ref_k_dma_len:11; 458 unsigned int res1:5; 459 } bits; 460 } ISP_D3D_DMA_STRIDE_LEN_REG_t; 461 462 typedef union { 463 unsigned int dwval; 464 struct { 465 unsigned int pltm_mid_test:1; 466 unsigned int pltm_read_finish:1; 467 unsigned int res0:30; 468 } bits; 469 } ISP_SIM_CTRL_REG_t; 470 471 typedef union { 472 unsigned int dwval; 473 struct { 474 unsigned int isp0_max_width:14; 475 unsigned int res0:2; 476 unsigned int isp_mode:1; 477 unsigned int res1:15; 478 } bits; 479 } ISP_TOP_CTRL_REG_t; 480 481 typedef union { 482 unsigned int dwval; 483 struct { 484 unsigned int s1_blc_en:1; 485 unsigned int s1_lc_en:1; 486 unsigned int s1_dg_en:1; 487 unsigned int res0:29; 488 } bits; 489 } ISP_S1_CFG_REG_t; 490 491 typedef union { 492 unsigned int dwval; 493 struct { 494 unsigned int ae_en:1; 495 unsigned int lc_en:1; 496 unsigned int wdr_en:1; 497 unsigned int dpc_en:1; 498 unsigned int d2d_en:1; 499 unsigned int d3d_en:1; 500 unsigned int awb_en:1; 501 unsigned int wb_en:1; 502 unsigned int lsc_en:1; 503 unsigned int bgc_en:1; 504 unsigned int sharp_en:1; 505 unsigned int af_en:1; 506 unsigned int rgb2rgb_en:1; 507 unsigned int rgb_drc_en:1; 508 unsigned int pltm_en:1; 509 unsigned int cem_en:1; 510 unsigned int afs_en:1; 511 unsigned int hist_en:1; 512 unsigned int blc_en:1; 513 unsigned int dg_en:1; 514 unsigned int so_en:1; 515 unsigned int ctc_en:1; 516 unsigned int res0:1; 517 unsigned int cnr_en:1; 518 unsigned int satu_en:1; 519 unsigned int dehaze_en:1; 520 unsigned int res1:6; 521 } bits; 522 } ISP_MODULE_BYPASS0_REG_t; 523 524 typedef union { 525 unsigned int dwval; 526 struct { 527 unsigned int input_width:14; 528 unsigned int res0:2; 529 unsigned int input_height:14; 530 unsigned int res1:2; 531 } bits; 532 } ISP_INPUT_SIZE_REG_t; 533 534 typedef union { 535 unsigned int dwval; 536 struct { 537 unsigned int valid_width:14; 538 unsigned int res0:2; 539 unsigned int valid_height:14; 540 unsigned int res1:2; 541 } bits; 542 } ISP_VALID_SIZE_REG_t; 543 544 typedef union { 545 unsigned int dwval; 546 struct { 547 unsigned int valid_hor_start:13; 548 unsigned int res0:3; 549 unsigned int valid_ver_start:13; 550 unsigned int res1:3; 551 } bits; 552 } ISP_VALID_START_REG_t; 553 554 typedef union { 555 unsigned int dwval; 556 struct { 557 unsigned int line_tar_bits:16; 558 unsigned int lmtqp_min:4; 559 unsigned int mb_min_bit:9; 560 unsigned int res0:1; 561 unsigned int lmtqp_en:1; 562 unsigned int is_lossy:1; 563 } bits; 564 } ISP_WDR_RAW_LBC_CTRL_REG_t; 565 566 typedef union { 567 unsigned int dwval; 568 struct { 569 unsigned int line_tar_bits:16; 570 unsigned int lmtqp_min:4; 571 unsigned int mb_min_bit:9; 572 unsigned int res0:1; 573 unsigned int lmtqp_en:1; 574 unsigned int is_lossy:1; 575 } bits; 576 } ISP_D3D_RAW_LBC_CTRL_REG_t; 577 578 typedef union { 579 unsigned int dwval; 580 struct { 581 unsigned int line_tar_bits:16; 582 unsigned int res0:1; 583 unsigned int lmtqp_min:3; 584 unsigned int mb_min_bit:7; 585 unsigned int res1:3; 586 unsigned int lmtqp_en:1; 587 unsigned int is_lossy:1; 588 } bits; 589 } ISP_D3D_K_LBC_CTRL_REG_t; 590 591 #endif /*_ISP521_REG_H_*/ 592