1 2 /* 3 * isp522_reg.h 4 * 5 * Copyright (c) 2007-2019 Allwinnertech Co., Ltd. 6 * 7 * Authors: zheng jiangwei <zhengjiangwei@allwinnertech.com> 8 * 9 * This software is licensed under the terms of the GNU General Public 10 * License version 2, as published by the Free Software Foundation, and 11 * may be copied, distributed, and modified under those terms. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 */ 19 20 #ifndef _ISP522_REG_H_ 21 #define _ISP522_REG_H_ 22 23 #define ISP0_BASE_ADDR_OFFSET 0x0000 24 #define ISP1_BASE_ADDR_OFFSET 0x2000 25 26 #define ISP_GLOBAL_CFG0_REG 0x000 27 #define ISP_GLOBAL_CFG1_REG 0x004 28 #define ISP_GLOBAL_CFG2_REG 0x008 29 #define ISP_UPDATE_CTRL0_REG 0x020 30 #define ISP_LOAD_ADDR0_REG 0x030 31 #define ISP_LOAD_ADDR1_REG 0x034 32 #define ISP_SAVE_ADDR_REG 0x038 33 #define ISP_INT_BYPASS0_REG 0x040 34 #define ISP_INT_STATUS0_REG 0x048 35 #define ISP_INTER_STATUS0_REG 0x060 36 #define ISP_INTER_STATUS1_REG 0x064 37 #define ISP_WR_ADDR_RET_REG 0x070 38 #define ISP_VER_CFG_REG 0x080 39 #define ISP_MAX_WIDTH_REG 0x084 40 #define ISP_S0_FMERR_CNT_REG 0x0a0 41 #define ISP_S0_HB_CNT_REG 0x0b0 42 #define ISP_INPUT_SIZE_REG 0x0e4 43 #define ISP_VALID_SIZE_REG 0x0e8 44 #define ISP_VALID_START_REG 0x0ec 45 #define ISP_MODULE_STATUS_REG 0x180 46 #define ISP_MODULE_BYPASS0_REG 0x1a0 47 #define ISP_MODULE_MODE0_REG 0x1b0 48 49 50 typedef union { 51 unsigned int dwval; 52 struct { 53 unsigned int isp_enable:1; 54 unsigned int cap_en:1; 55 unsigned int isp_ver_rd_en:1; 56 unsigned int int_mode:1; 57 unsigned int input_fmt:3; 58 unsigned int res0:1; 59 unsigned int isp_ch0_en:1; 60 unsigned int isp_ch1_en:1; 61 unsigned int isp_ch2_en:1; 62 unsigned int isp_ch3_en:1; 63 unsigned int res1:4; 64 unsigned int res2:16; 65 } bits; 66 } ISP_GLOBAL_CFG0_REG_t; 67 68 typedef union { 69 unsigned int dwval; 70 struct { 71 unsigned int line_int_num:14; 72 unsigned int res0:2; 73 unsigned int speed_mode:3; 74 unsigned int res1:1; 75 unsigned int last_blank_cycle:3; 76 unsigned int res2:1; 77 unsigned int res4:8; 78 } bits; 79 } ISP_GLOBAL_CFG1_REG_t; 80 81 typedef union { 82 unsigned int dwval; 83 struct { 84 unsigned int debug_en:1; 85 unsigned int sram_clear:1; 86 unsigned int pltm_sram_clr_en:1; 87 unsigned int module_clr_back_door:1; 88 unsigned int debug_sel:5; 89 unsigned int res0:3; 90 unsigned int vgm_en:1; 91 unsigned int vgm_start:1; 92 unsigned int vgm_mode:1; 93 unsigned int res1:1; 94 unsigned int d3d_cmp_ofln_sel:1; 95 unsigned int d3d_uncmp_ofln_sel:2; 96 unsigned int res2:9; 97 unsigned int af_stat_sum_mode:1; 98 unsigned int para_ready_mode:1; 99 unsigned int hw_sram_clear_en:1; 100 unsigned int fsm_back_door_en:1; 101 } bits; 102 } ISP_GLOBAL_CFG2_REG_t; 103 104 typedef union { 105 unsigned int dwval; 106 struct { 107 unsigned int fifo_dep_raw_rd:11; 108 unsigned int res0:1; 109 unsigned int raw_min_ddr_size:2; 110 unsigned int d3d_uncmp_bandwd_sel:2; 111 unsigned int fifo_dep_raw_wr:11; 112 unsigned int res1:1; 113 unsigned int k_min_ddr_size:2; 114 unsigned int d3d_cmp_bandwd_sel:2; 115 } bits; 116 } ISP_GLOBAL_CFG3_REG_t; 117 118 119 typedef union { 120 unsigned int dwval; 121 struct { 122 unsigned int para_ready:1; 123 unsigned int linear_update:1; 124 unsigned int lens_update:1; 125 unsigned int gamma_update:1; 126 unsigned int drc_update:1; 127 unsigned int satu_update:1; 128 unsigned int wdr_update:1; 129 unsigned int d3d_update:1; 130 unsigned int pltm_update:1; 131 unsigned int cem_update:1; 132 unsigned int msc_update:1; 133 unsigned int dehaze_update:1; 134 unsigned int s1_para_ready:1; 135 unsigned int s1_linear_update:1; 136 unsigned int res1:16; 137 unsigned int dbg_tbl_update:1; 138 unsigned int dbg_stat_update:1; 139 } bits; 140 } ISP_UPDATE_CTRL0_REG_t; 141 142 typedef union { 143 unsigned int dwval; 144 struct { 145 unsigned int finish_int_en:1; 146 unsigned int s0_start_int_en:1; 147 unsigned int s1_start_int_en:1; 148 unsigned int para_save_int_en:1; 149 unsigned int s0_para_load_int_en:1; 150 unsigned int s1_para_load_int_en:1; 151 unsigned int s0_fifo_int_en:1; 152 unsigned int s1_fifo_int_en:1; 153 unsigned int s0_n_line_start_int_en:1; 154 unsigned int s1_n_line_start_int_en:1; 155 unsigned int s0_frame_error_int_en:1; 156 unsigned int s1_frame_error_int_en:1; 157 unsigned int s0_frame_lost_int_en:1; 158 unsigned int s1_frame_lost_int_en:1; 159 unsigned int s0_hb_short_int_en:1; 160 unsigned int s1_hb_short_int_en:1; 161 unsigned int sram_clr_int_en:1; 162 unsigned int ddr_w_finish_int_en:1; 163 unsigned int s0_btype_error_int_en:1; 164 unsigned int s1_btype_error_int_en:1; 165 unsigned int addr_error_int_en:1; 166 unsigned int lbc_error_int_en:1; 167 unsigned int fsm_frame_lost_int_en:1; 168 unsigned int res0:9; 169 } bits; 170 } ISP_INT_BYPASS0_REG_t; 171 172 typedef union { 173 unsigned int dwval; 174 struct { 175 unsigned int finish_pd:1; 176 unsigned int s0_start_pd:1; 177 unsigned int s1_start_pd:1; 178 unsigned int para_saved_pd:1; 179 unsigned int s0_para_load_pd:1; 180 unsigned int s1_para_load_pd:1; 181 unsigned int s0_fifo_of_pd:1; 182 unsigned int s1_fifo_of_pd:1; 183 unsigned int s0_n_line_start_pd:1; 184 unsigned int s1_n_line_start_pd:1; 185 unsigned int s0_frame_error_pd:1; 186 unsigned int s1_frame_error_pd:1; 187 unsigned int s0_frame_lost_pd:1; 188 unsigned int s1_frame_lost_pd:1; 189 unsigned int s0_hb_short_pd:1; 190 unsigned int s1_hb_short_pd:1; 191 unsigned int sram_clr_pd:1; 192 unsigned int ddr_w_finish_pd:1; 193 unsigned int s0_btype_error_pd:1; 194 unsigned int s1_btype_error_pd:1; 195 unsigned int addr_error_pd:1; 196 unsigned int lbc_error_pd:1; 197 unsigned int fsm_frame_lost_pd:1; 198 unsigned int res0:8; 199 unsigned int fifo_valid_st:1; 200 } bits; 201 } ISP_INT_STATUS0_REG_t; 202 203 typedef union { 204 unsigned int dwval; 205 struct { 206 unsigned int d3d_w_finish_pd:1; 207 unsigned int wdr_w_finish_pd:1; 208 unsigned int s0_cin_fifo_of_pd:1; 209 unsigned int dpc_fifo_of_pd:1; 210 unsigned int res0:1; 211 unsigned int bis_fifo_of_pd:1; 212 unsigned int cnr_fifo_of_pd:1; 213 unsigned int pltm_fifo_of_pd:1; 214 unsigned int d3d_write_fifo_of_pd:1; 215 unsigned int d3d_read_fifo_of_pd:1; 216 unsigned int res1:1; 217 unsigned int wdr_write_fifo_of_pd:1; 218 unsigned int res2:1; 219 unsigned int wdr_read_fifo_of_pd:1; 220 unsigned int res3:1; 221 unsigned int s1_cin_fifo_of_pd:1; 222 unsigned int lca_rgb_fifo_r_emp_pd:1; 223 unsigned int lca_rgb_fifo_w_full_pd:1; 224 unsigned int lca_by_fifo_r_emp_pd:1; 225 unsigned int lca_by_fifo_w_full_pd:1; 226 unsigned int d3d_k_fifo_w_full_pd:1; 227 unsigned int d3d_raw_fifo_w_full_pd:1; 228 unsigned int d3d_k_fifo_r_emp_pd:1; 229 unsigned int d3d_ref_fifo_r_emp_pd:1; 230 unsigned int d3d_ltf_fifo_r_emp_pd:1; 231 unsigned int res4:7; 232 } bits; 233 } ISP_INTER_STATUS0_REG_t; 234 235 typedef union { 236 unsigned int dwval; 237 struct { 238 unsigned int top_ctrl_st:11; 239 unsigned int res0:5; 240 unsigned int res1:16; 241 } bits; 242 } ISP_INTER_STATUS1_REG_t; 243 244 typedef union { 245 unsigned int dwval; 246 struct { 247 unsigned int ahb_ddr_w_addr:12; 248 unsigned int res0:20; 249 } bits; 250 } ISP_WR_ADDR_RET_REG_t; 251 252 typedef union { 253 unsigned int dwval; 254 struct { 255 unsigned int wdr_ctrl_st:8; 256 unsigned int res0:24; 257 } bits; 258 } ISP_INTER_STATUS2_REG_t; 259 260 typedef union { 261 unsigned int dwval; 262 struct { 263 unsigned int wdr_lbc_dec_err:5; 264 unsigned int res0:3; 265 unsigned int d3d_k_lbc_dec_err:5; 266 unsigned int res1:3; 267 unsigned int d3d_ref_lbc_dec_err:5; 268 unsigned int res2:3; 269 unsigned int d3d_ltf_lbc_dec_err:5; 270 unsigned int res3:3; 271 } bits; 272 } ISP_LBC_INTER_STATUS_REG_t; 273 274 typedef union { 275 unsigned int dwval; 276 struct { 277 unsigned int small_ver:12; 278 unsigned int big_ver:12; 279 unsigned int res0:8; 280 } bits; 281 } ISP_VER_CFG_REG_t; 282 283 typedef union { 284 unsigned int dwval; 285 struct { 286 unsigned int max_width:16; 287 unsigned int max_height:16; 288 } bits; 289 } ISP_MAX_SIZE_REG_t; 290 291 typedef union { 292 unsigned int dwval; 293 struct { 294 unsigned int d3d_k_fifo_max_layer:16; 295 unsigned int d3d_raw_fifo_max_layer:16; 296 } bits; 297 } ISP_COMP_FIFO_MAX_LAYER0_REG_t; 298 299 typedef union { 300 unsigned int dwval; 301 struct { 302 unsigned int wdr_fifo_max_layer:16; 303 unsigned int res0:16; 304 } bits; 305 } ISP_COMP_FIFO_MAX_LAYER1_REG_t; 306 307 typedef union { 308 unsigned int dwval; 309 struct { 310 unsigned int wdr_fifo_max_layer:16; 311 unsigned int d3d_ltf_fifo_max_layer:16; 312 } bits; 313 } ISP_UNCOMP_FIFO_MAX_LAYER0_REG_t; 314 315 typedef union { 316 unsigned int dwval; 317 struct { 318 unsigned int d3d_k_fifo_max_layer:16; 319 unsigned int d3d_ref_fifo_max_layer:16; 320 } bits; 321 } ISP_UNCOMP_FIFO_MAX_LAYER1_REG_t; 322 323 typedef union { 324 unsigned int dwval; 325 struct { 326 unsigned int wdr_cmp_bandwidth; 327 } bits; 328 } ISP_WDR_CMP_BANDWIDTH_REG_t; 329 330 typedef union { 331 unsigned int dwval; 332 struct { 333 unsigned int wdr_decmp_bandwidth; 334 } bits; 335 } ISP_WDR_DECMP_BANDWIDTH_REG_t; 336 337 typedef union { 338 unsigned int dwval; 339 struct { 340 unsigned int d3d_cmp_bandwidth; 341 } bits; 342 } ISP_D3D_CMP_BANDWIDTH_REG_t; 343 344 typedef union { 345 unsigned int dwval; 346 struct { 347 unsigned int d3d_decmp_bandwidth; 348 } bits; 349 } ISP_D3D_DECMP_BANDWIDTH_REG_t; 350 351 typedef union { 352 unsigned int dwval; 353 struct { 354 unsigned int input_width:14; 355 unsigned int res0:2; 356 unsigned int input_height:14; 357 unsigned int res1:2; 358 } bits; 359 } ISP_S0_FMERR_CNT_REG_t; 360 361 typedef union { 362 unsigned int dwval; 363 struct { 364 unsigned int input_width:14; 365 unsigned int res0:2; 366 unsigned int input_height:14; 367 unsigned int res1:2; 368 } bits; 369 } ISP_S1_FMERR_CNT_REG_t; 370 371 typedef union { 372 unsigned int dwval; 373 struct { 374 unsigned int hb_min:16; 375 unsigned int hb_max:16; 376 } bits; 377 } ISP_S0_HB_CNT_REG_t; 378 379 typedef union { 380 unsigned int dwval; 381 struct { 382 unsigned int hb_min:16; 383 unsigned int hb_max:16; 384 } bits; 385 } ISP_S1_HB_CNT_REG_t; 386 387 typedef union { 388 unsigned int dwval; 389 struct { 390 unsigned int comp_overflow_line:14; 391 unsigned int res0:2; 392 unsigned int decomp_overflow_line:14; 393 unsigned int res1:2; 394 } bits; 395 } ISP_WDR_FIFO_OVERFLOW_LINE_REG_t; 396 397 typedef union { 398 unsigned int dwval; 399 struct { 400 unsigned int comp_overflow_line:14; 401 unsigned int res0:2; 402 unsigned int decomp_overflow_line:14; 403 unsigned int res1:2; 404 } bits; 405 } ISP_D3D_FIFO_OVERFLOW_LINE_REG_t; 406 407 typedef union { 408 unsigned int dwval; 409 struct { 410 unsigned int wdr_dma_len:11; 411 unsigned int res0:21; 412 } bits; 413 } ISP_WDR_DMA_STRIDE_LEN_REG_t; 414 415 typedef union { 416 unsigned int dwval; 417 struct { 418 unsigned int d3d_ref_raw_dma_len:11; 419 unsigned int res0:5; 420 unsigned int d3d_ref_k_dma_len:11; 421 unsigned int res1:5; 422 } bits; 423 } ISP_D3D_DMA_STRIDE_LEN_REG_t; 424 425 typedef union { 426 unsigned int dwval; 427 struct { 428 unsigned int pltm_mid_test:1; 429 unsigned int pltm_read_finish:1; 430 unsigned int res0:30; 431 } bits; 432 } ISP_SIM_CTRL_REG_t; 433 434 typedef union { 435 unsigned int dwval; 436 struct { 437 unsigned int isp0_max_width:14; 438 unsigned int res0:2; 439 unsigned int isp_mode:1; 440 unsigned int res1:15; 441 } bits; 442 } ISP_TOP_CTRL_REG_t; 443 444 typedef union { 445 unsigned int dwval; 446 struct { 447 unsigned int s1_blc_en:1; 448 unsigned int s1_lc_en:1; 449 unsigned int s1_dg_en:1; 450 unsigned int res0:29; 451 } bits; 452 } ISP_S1_CFG_REG_t; 453 454 typedef union { 455 unsigned int dwval; 456 struct { 457 unsigned int ae_en:1; 458 unsigned int lc_en:1; 459 unsigned int wdr_en:1; 460 unsigned int dpc_en:1; 461 unsigned int d2d_en:1; 462 unsigned int d3d_en:1; 463 unsigned int awb_en:1; 464 unsigned int wb_en:1; 465 unsigned int lsc_en:1; 466 unsigned int bgc_en:1; 467 unsigned int sharp_en:1; 468 unsigned int af_en:1; 469 unsigned int rgb2rgb_en:1; 470 unsigned int rgb_drc_en:1; 471 unsigned int pltm_en:1; 472 unsigned int cem_en:1; 473 unsigned int afs_en:1; 474 unsigned int hist_en:1; 475 unsigned int blc_en:1; 476 unsigned int dg_en:1; 477 unsigned int so_en:1; 478 unsigned int ctc_en:1; 479 unsigned int res0:1; 480 unsigned int cnr_en:1; 481 unsigned int satu_en:1; 482 unsigned int dehaze_en:1; 483 unsigned int res1:6; 484 } bits; 485 } ISP_MODULE_BYPASS0_REG_t; 486 487 typedef union { 488 unsigned int dwval; 489 struct { 490 unsigned int res0:1; 491 unsigned int satu_mode:1; 492 unsigned int demosaic_mode:1; 493 unsigned int res1:5; 494 unsigned int hist_mode:2; 495 unsigned int res2:6; 496 unsigned int rsc_mode:2; 497 unsigned int msc_mode:3; 498 unsigned int res3:11; 499 } bits; 500 } ISP_MODULE_MODE0_REG_t; 501 502 typedef union { 503 unsigned int dwval; 504 struct { 505 unsigned int input_width:14; 506 unsigned int res0:2; 507 unsigned int input_height:14; 508 unsigned int res1:2; 509 } bits; 510 } ISP_INPUT_SIZE_REG_t; 511 512 typedef union { 513 unsigned int dwval; 514 struct { 515 unsigned int valid_width:14; 516 unsigned int res0:2; 517 unsigned int valid_height:14; 518 unsigned int res1:2; 519 } bits; 520 } ISP_VALID_SIZE_REG_t; 521 522 typedef union { 523 unsigned int dwval; 524 struct { 525 unsigned int valid_hor_start:13; 526 unsigned int res0:3; 527 unsigned int valid_ver_start:13; 528 unsigned int res1:3; 529 } bits; 530 } ISP_VALID_START_REG_t; 531 532 typedef union { 533 unsigned int dwval; 534 struct { 535 unsigned int isp_index:1; 536 unsigned int res0:31; 537 } bits; 538 } ISP_MODULE_STATUS_REG_t; 539 540 typedef union { 541 unsigned int dwval; 542 struct { 543 unsigned int line_tar_bits:16; 544 unsigned int lmtqp_min:4; 545 unsigned int mb_min_bit:9; 546 unsigned int res0:1; 547 unsigned int lmtqp_en:1; 548 unsigned int is_lossy:1; 549 } bits; 550 } ISP_WDR_RAW_LBC_CTRL_REG_t; 551 552 typedef union { 553 unsigned int dwval; 554 struct { 555 unsigned int line_tar_bits:16; 556 unsigned int lmtqp_min:4; 557 unsigned int mb_min_bit:9; 558 unsigned int res0:1; 559 unsigned int lmtqp_en:1; 560 unsigned int is_lossy:1; 561 } bits; 562 } ISP_D3D_RAW_LBC_CTRL_REG_t; 563 564 typedef union { 565 unsigned int dwval; 566 struct { 567 unsigned int line_tar_bits:16; 568 unsigned int res0:1; 569 unsigned int lmtqp_min:3; 570 unsigned int mb_min_bit:7; 571 unsigned int res1:3; 572 unsigned int lmtqp_en:1; 573 unsigned int is_lossy:1; 574 } bits; 575 } ISP_D3D_K_LBC_CTRL_REG_t; 576 577 #endif /*_ISP522_REG_H_*/ 578