1 /* 2 * linux-5.4/drivers/media/platform/sunxi-vin/vin-tdm/parser_reg_i.h 3 * 4 * Copyright (c) 2007-2019 Allwinnertech Co., Ltd. 5 * 6 * Authors: Zheng Zequn <zequnzheng@allwinnertech.com> 7 * 8 * This software is licensed under the terms of the GNU General Public 9 * License version 2, as published by the Free Software Foundation, and 10 * may be copied, distributed, and modified under those terms. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 */ 18 19 #ifndef __CSIC__TDM__REG__I__H__ 20 #define __CSIC__TDM__REG__I__H__ 21 22 /* 23 * Detail information of registers 24 */ 25 /* 26 * tdm top registers 27 */ 28 #define TMD_BASE_ADDR 0x02108000 29 30 #define TDM_GOLBAL_CFG0_REG_OFF 0X000 31 #define TDM_TOP_EN 0 32 #define TDM_TOP_EN_MASK (0X1 << TDM_TOP_EN) 33 #define TDM_EN 1 34 #define TDM_EN_MASK (0X1 << TDM_EN) 35 #define VGM_EN 3 36 #define VGM_EN_MASK (0X1 << VGM_EN) 37 #define TDM_RX_FIFO_MAX_LAYER_EN 4 38 #define TDM_RX_FIFO_MAX_LAYER_EN_MASK (0X1 << TDM_RX_FIFO_MAX_LAYER_EN) 39 #define MODULE_CLK_BACK_DOOR 27 40 #define MODULE_CLK_BACK_DOOR_MASK (0X1 << MODULE_CLK_BACK_DOOR) 41 42 #define TDM_INT_BYPASS0_REG_OFF 0X010 43 44 #define TDM_INT_STATUS0_REG_OFF 0X018 45 #define RX_FRM_LOST_PD 0 46 #define RX_FRM_LOST_PD_MASK (0X1 << RX_FRM_LOST_PD) 47 #define RX_FRM_ERR_PD 1 48 #define RX_FRM_ERR_PD_MASK (0X1 << RX_FRM_ERR_PD) 49 #define RX_BTYPE_ERR_PD 2 50 #define RX_BTYPE_ERR_PD_MASK (0X1 << RX_BTYPE_ERR_PD) 51 #define RX_BUF_FULL_PD 3 52 #define RX_BUF_FULL_PD_MASK (0X1 << RX_BUF_FULL_PD) 53 #define RX_COMP_ERR_PD 4 54 #define RX_COMP_ERR_PD_MASK (0X1 << RX_COMP_ERR_PD) 55 #define RX_HB_SHORT_PD 5 56 #define RX_HB_SHORT_PD_MASK (0X1 << RX_HB_SHORT_PD) 57 #define RX_FIFO_FULL_PD 6 58 #define RX_FIFO_FULL_PD_MASK (0X1 << RX_FIFO_FULL_PD) 59 #define RX0_FRM_DONE_PD 16 60 #define RX0_FRM_DONE_PD_MASK (0X1 << RX0_FRM_DONE_PD) 61 #define RX1_FRM_DONE_PD 17 62 #define RX1_FRM_DONE_PD_MASK (0X1 << RX1_FRM_DONE_PD) 63 64 #define TDM_INTERNAL_STATUS0_REG_OFF 0X020 65 #define RX0_FRM_LOST_PD (1 << 0) 66 #define RX1_FRM_LOST_PD (1 << 1) 67 #define RX0_FRM_ERR_PD (1 << 8) 68 #define RX1_FRM_ERR_PD (1 << 9) 69 #define RX0_BTYPE_ERR_PD (1 << 16) 70 #define RX1_BTYPE_ERR_PD (1 << 17) 71 #define RX0_BUF_FULL_PD (1 << 24) 72 #define RX1_BUF_FULL_PD (1 << 25) 73 74 #define TDM_INTERNAL_STATUS1_REG_OFF 0X024 75 #define RX0_COMP_ERR_PD (1 << 0) 76 #define RX1_COMP_ERR_PD (1 << 1) 77 #define RX0_HB_SHORT_PD (1 << 8) 78 #define RX1_HB_SHORT_PD (1 << 9) 79 #define RX0_FIFO_FULL_PD (1 << 16) 80 #define RX1_FIFO_FULL_PD (1 << 17) 81 82 /* 83 * tdm tx registers 84 */ 85 #define TMD_TX_OFFSET 0x0a0 86 87 #define TDM_TX_CFG0_REG_OFF 0X000 88 #define TDM_TX_CAP_EN 0 89 #define TDM_TX_CAP_EN_MASK (0X1 << TDM_TX_CAP_EN) 90 #define TDM_TX_OMODE 1 91 #define TDM_TX_OMODE_MASK (0X1 << TDM_TX_OMODE) 92 93 #define TDM_TX_CFG1_REG_OFF 0X004 94 #define TDM_TX_H_BLANK 0 95 #define TDM_TX_H_BLANK_MASK (0X3FFF << TDM_TX_H_BLANK) 96 97 #define TDM_TX_CFG2_REG_OFF 0X008 98 #define TDM_TX_V_BLANK_FE 0 99 #define TDM_TX_V_BLANK_FE_MASK (0X3FFF << TDM_TX_V_BLANK_FE) 100 #define TDM_TX_V_BLANK_BE 16 101 #define TDM_TX_V_BLANK_BE_MASK (0X3FFF << TDM_TX_V_BLANK_BE) 102 103 /* 104 * tdm rx registers 105 */ 106 #define TMD_RX0_OFFSET 0x100 107 #define TMD_RX1_OFFSET 0x140 108 #define AMONG_RX_OFFSET 0x40 109 110 #define TDM_RX_CFG0_REG_OFF 0X000 111 #define TDM_RX_EN 0 112 #define TDM_RX_EN_MASK (0X1 << TDM_RX_EN) 113 #define TDM_RX_CAP_EN 1 114 #define TDM_RX_CAP_EN_MASK (0X1 << TDM_RX_CAP_EN) 115 #define TDM_RX_ABD_EN 2 116 #define TDM_RX_ABD_EN_MASK (0X1 << TDM_RX_ABD_EN) 117 #define TDM_RX_BUF_NUM 8 118 #define TDM_RX_BUF_NUM_MASK (0XF << TDM_RX_BUF_NUM) 119 #define TDM_RX_CH0_EN 16 120 #define TDM_RX_CH0_EN_MASK (0X1 << TDM_RX_CH0_EN) 121 #define TDM_RX_MIN_DDR_SIZE 24 122 #define TDM_RX_MIN_DDR_SIZE_MASK (0X3 << TDM_RX_MIN_DDR_SIZE) 123 #define TDM_INPUT_BIT 28 124 #define TDM_INPUT_BIT_MASK (0X3 << TDM_INPUT_BIT) 125 126 #define TDM_RX_CFG1_REG_OFF 0X004 127 #define TDM_RX_WIDTH 0 128 #define TDM_RX_WIDTH_MASK (0X3FFF << TDM_RX_WIDTH) 129 #define TDM_RX_HEIGHT 16 130 #define TDM_RX_HEIGHT_MASK (0X3FFF << TDM_RX_HEIGHT) 131 132 #define TDM_RX_CFG2_REG_OFF 0X010 133 #define TDM_RX_ADDR 0 134 #define TDM_RX_ADDR_MASK (0XFFFFFFFF << TDM_RX_ADDR) 135 136 #define TDM_RX_FRAME_ERR_REG_OFF 0X020 137 #define TDM_RX_HB_SHORT_REG_OFF 0X024 138 139 #endif /* __CSIC__TDM__REG__I__H__ */ 140