1 /* 2 * linux-5.4/drivers/media/platform/sunxi-vin/vin-vipp/vipp_reg_i.h 3 * 4 * Copyright (c) 2007-2017 Allwinnertech Co., Ltd. 5 * 6 * Authors: Zhao Wei <zhaowei@allwinnertech.com> 7 * 8 * This software is licensed under the terms of the GNU General Public 9 * License version 2, as published by the Free Software Foundation, and 10 * may be copied, distributed, and modified under those terms. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 */ 18 19 #ifndef __VIPP__REG__I__H__ 20 #define __VIPP__REG__I__H__ 21 22 /* 23 * Detail information of registers 24 */ 25 26 #define VIPP_TOP_EN_REG_OFF 0X000 27 #define VIPP_CLK_GATING_EN 0 28 #define VIPP_CLK_GATING_EN_MASK (0X1 << VIPP_CLK_GATING_EN) 29 30 #define VIPP_EN_REG_OFF 0X004 31 #define VIPP_EN 0 32 #define VIPP_EN_MASK (0X1 << VIPP_EN) 33 #define VIPP_VER_EN 3 34 #define VIPP_VER_EN_MASK (0X1 << VIPP_VER_EN) 35 36 #define VIPP_VER_REG_OFF 0X008 37 #define VIPP_SMALL_VER 0 38 #define VIPP_SMALL_VER_MASK (0XFFF << VIPP_SMALL_VER) 39 #define VIPP_BIG_VER 12 40 #define VIPP_BIG_VER_MASK (0XFFF << VIPP_BIG_VER) 41 42 #define VIPP_FEATURE_REG_OFF 0X00C 43 #define VIPP_OSD_EXIST 0 44 #define VIPP_OSD_EXIST_MASK (0X1 << VIPP_OSD_EXIST) 45 #define VIPP_YUV422TO420 1 46 #define VIPP_YUV422TO420_MASK (0X1 << VIPP_YUV422TO420) 47 48 #define VIPP_CTRL_REG_OFF 0X014 49 #define VIPP_OSD_OV_UPDATE 0 50 #define VIPP_OSD_OV_UPDATE_MASK (0X1 << VIPP_OSD_OV_UPDATE) 51 #define VIPP_OSD_CV_UPDATE 1 52 #define VIPP_OSD_CV_UPDATE_MASK (0X1 << VIPP_OSD_CV_UPDATE) 53 #define VIPP_PARA_READY 2 54 #define VIPP_PARA_READY_MASK (0X1 << VIPP_PARA_READY) 55 56 #define VIPP_OSD_LOAD_ADDR_REG_OFF 0X018 57 #define VIPP_OSD_STAT_ADDR_REG_OFF 0X01C 58 #define VIPP_OSD_BM_ADDR_REG_OFF 0X020 59 #define VIPP_REG_LOAD_ADDR_REG_OFF 0X024 60 61 #define VIPP_STA_REG_OFF 0X030 62 #define VIPP_REG_LOAD_PD 0 63 #define VIPP_REG_LOAD_PD_MASK (0X01 << VIPP_REG_LOAD_PD) 64 #define VIPP_MBUS_IDLE_PD 1 65 #define VIPP_MBUS_IDLE_PD_MASK (0X01 << VIPP_MBUS_IDLE_PD) 66 #define VIPP_BM_ERROR_PD 2 67 #define VIPP_BM_ERROR_PD_MASK (0X01 << VIPP_BM_ERROR_PD) 68 #define VIPP_FRAME_LOST_PD 3 69 #define VIPP_FRAME_LOST_PD_MASK (0X01 << VIPP_FRAME_LOST_PD) 70 #define VIPP_HBLANK_SHORT_PD 4 71 #define VIPP_HBLANK_SHORT_PD_MASK (0X01 << VIPP_HBLANK_SHORT_PD) 72 #define VIPP_BM_RDADDR_ERR_PD 5 73 #define VIPP_BM_RDADDR_ERR_PD_MASK (0X01 << VIPP_BM_RDADDR_ERR_PD) 74 #define VIPP_FRMEND_BM_NOTIDLE_PD 6 75 #define VIPP_FRMEND_BM_NOTIDLE_PD_MASK (0X01 << VIPP_FRMEND_BM_NOTIDLE_PD) 76 77 #define VIPP_INTER_STATUS_REG_OFF 0X034 78 #define VIPP_TOP_CTL_ST 0 79 #define VIPP_TOP_CTL_ST_MASK (0X3FF << VIPP_TOP_CTL_ST) 80 #define VIPP_BM_CORE_CTL_ST 10 81 #define VIPP_BM_CORE_CTL_ST_MASK (0XFF << VIPP_BM_CORE_CTL_ST) 82 83 #define VIPP_FIFO_RW_POINTER_REG_OFF 0X038 84 #define VIPP_FIFO_RPT 0 85 #define VIPP_FIFO_RPT_MASK (0X7FF << VIPP_FIFO_RPT) 86 #define VIPP_FIFO_WPT 16 87 #define VIPP_FIFO_WPT_MASK (0X7FF << VIPP_FIFO_WPT) 88 89 #define VIPP_BMAP_STATUS_REG_OFF 0X03C 90 #define VIPP_BMAP_CNT_Y 0 91 #define VIPP_BMAP_CNT_Y_MASK (0XFFF << VIPP_BMAP_CNT_Y) 92 #define VIPP_BMAP_CNT_X 12 93 #define VIPP_BMAP_CNT_X_MASK (0X1FF << VIPP_BMAP_CNT_X) 94 #define VIPP_RXO_CMD_WPT 21 95 #define VIPP_RXO_CMD_WPT_MASK (0X7FF << VIPP_RXO_CMD_WPT) 96 97 #define VIPP_MODULE_EN_REG_OFF 0X040 98 #define VIPP_SC_CFG_REG_OFF 0X044 99 #define VIPP_SC_SIZE_REG_OFF 0X048 100 #define VIPP_MODE_REG_OFF 0X04C 101 102 #define VIPP_OSD_CFG_REG_OFF 0X050 103 104 #if defined CONFIG_ARCH_SUN8IW12P1 || defined CONFIG_ARCH_SUN8IW15P1 || defined CONFIG_ARCH_SUN8IW17P1 105 #define VIPP_OSD_GAIN0_REG_OFF 0X054 106 #define VIPP_OSD_GAIN1_REG_OFF 0X058 107 #define VIPP_OSD_GAIN2_REG_OFF 0X05C 108 #define VIPP_OSD_GAIN3_REG_OFF 0X060 109 #define VIPP_OSD_GAIN4_REG_OFF 0X064 110 #define VIPP_OSD_OFFSET_REG_OFF 0X068 111 #define VIPP_CROP_START_REG_OFF 0X070 112 #define VIPP_CROP_SIZE_REG_OFF 0X074 113 114 #else 115 116 #define VIPP_OSD_OV0_ST_REG_OFF 0X054 117 #define VIPP_OSD_OV0_ED_REG_OFF 0X058 118 #define VIPP_OSD_OV1_ST_REG_OFF 0X05C 119 #define VIPP_OSD_OV1_ED_REG_OFF 0X060 120 #define VIPP_OSD_OV2_ST_REG_OFF 0X064 121 #define VIPP_OSD_OV2_ED_REG_OFF 0X068 122 #define VIPP_OSD_OV3_ST_REG_OFF 0X06C 123 #define VIPP_OSD_OV3_ED_REG_OFF 0X070 124 #define VIPP_OSD_OV4_ST_REG_OFF 0X074 125 #define VIPP_OSD_OV4_ED_REG_OFF 0X078 126 #define VIPP_OSD_OV5_ST_REG_OFF 0X07C 127 #define VIPP_OSD_OV5_ED_REG_OFF 0X080 128 #define VIPP_OSD_OV6_ST_REG_OFF 0X084 129 #define VIPP_OSD_OV6_ED_REG_OFF 0X088 130 #define VIPP_OSD_OV7_ST_REG_OFF 0X08C 131 #define VIPP_OSD_OV7_ED_REG_OFF 0X090 132 133 #define VIPP_OSD_OV_ALPHA_CFG0_REG_OFF 0X094 134 #define VIPP_OSD_OV_ALPHA_CFG1_REG_OFF 0X098 135 136 #define VIPP_OSD_CV0_ST_REG_OFF 0X09C 137 #define VIPP_OSD_CV0_ED_REG_OFF 0X0A0 138 #define VIPP_OSD_CV1_ST_REG_OFF 0X0A4 139 #define VIPP_OSD_CV1_ED_REG_OFF 0X0A8 140 #define VIPP_OSD_CV2_ST_REG_OFF 0X0AC 141 #define VIPP_OSD_CV2_ED_REG_OFF 0X0B0 142 #define VIPP_OSD_CV3_ST_REG_OFF 0X0B4 143 #define VIPP_OSD_CV3_ED_REG_OFF 0X0B8 144 #define VIPP_OSD_CV4_ST_REG_OFF 0X0BC 145 #define VIPP_OSD_CV4_ED_REG_OFF 0X0C0 146 #define VIPP_OSD_CV5_ST_REG_OFF 0X0C4 147 #define VIPP_OSD_CV5_ED_REG_OFF 0X0C8 148 #define VIPP_OSD_CV6_ST_REG_OFF 0X0CC 149 #define VIPP_OSD_CV6_ED_REG_OFF 0X0D0 150 #define VIPP_OSD_CV7_ST_REG_OFF 0X0D4 151 #define VIPP_OSD_CV7_ED_REG_OFF 0X0D8 152 153 #define VIPP_OSD_CV0_YUV_REG_OFF 0X0DC 154 #define VIPP_OSD_CV1_YUV_REG_OFF 0X0E0 155 #define VIPP_OSD_CV2_YUV_REG_OFF 0X0E4 156 #define VIPP_OSD_CV3_YUV_REG_OFF 0X0E8 157 #define VIPP_OSD_CV4_YUV_REG_OFF 0X0EC 158 #define VIPP_OSD_CV5_YUV_REG_OFF 0X0F0 159 #define VIPP_OSD_CV6_YUV_REG_OFF 0X0F4 160 #define VIPP_OSD_CV7_YUV_REG_OFF 0X0F8 161 162 #define VIPP_OSD_INV_WIDTH_REG_OFF 0X0FC 163 #define VIPP_OSD_INV_HEIGHT_REG_OFF 0X100 164 165 #define VIPP_OSD_GAIN0_REG_OFF 0X104 166 #define VIPP_OSD_GAIN1_REG_OFF 0X108 167 #define VIPP_OSD_GAIN2_REG_OFF 0X10C 168 #define VIPP_OSD_GAIN3_REG_OFF 0X110 169 #define VIPP_OSD_GAIN4_REG_OFF 0X114 170 #define VIPP_OSD_OFFSET_REG_OFF 0X118 171 #define VIPP_CROP_START_REG_OFF 0X11C 172 #define VIPP_CROP_SIZE_REG_OFF 0X120 173 #define VIPP_ORL_CONTROL_REG_OFF 0X130 174 #define VIPP_ORL_START0_REG_OFF 0X140 175 #define VIPP_ORL_END0_REG_OFF 0X180 176 #define VIPP_ORL_YUV0_REG_OFF 0X1C0 177 178 #endif 179 180 typedef union { 181 unsigned int dwval; 182 struct { 183 unsigned int sc_en:1; 184 unsigned int osd_en:1; 185 unsigned int chroma_ds_en:1; 186 unsigned int res0:29; 187 } bits; 188 } VIPP_MODULE_EN_REG_t; 189 190 typedef union { 191 unsigned int dwval; 192 struct { 193 #if !defined CONFIG_ARCH_SUN8IW19P1 && !defined CONFIG_ARCH_SUN50IW10 194 unsigned int sc_out_fmt:1; 195 unsigned int res0:3; 196 unsigned int sc_xratio:12; 197 unsigned int sc_yratio:12; 198 unsigned int sc_weight_shift:4; 199 #else 200 unsigned int sc_xratio:13; 201 unsigned int res0:1; 202 unsigned int sc_yratio:13; 203 unsigned int sc_weight_shift:5; 204 #endif 205 } bits; 206 } VIPP_SCALER_CFG_REG_t; 207 208 typedef union { 209 unsigned int dwval; 210 struct { 211 unsigned int sc_width:13; 212 unsigned int res0:3; 213 unsigned int sc_height:13; 214 unsigned int res1:3; 215 } bits; 216 } VIPP_SCALER_OUTPUT_SIZE_REG_t; 217 218 typedef union { 219 unsigned int dwval; 220 struct { 221 unsigned int vipp_out_fmt:1; 222 unsigned int vipp_in_fmt:1; 223 unsigned int sc_out_fmt:1; 224 unsigned int res0:29; 225 } bits; 226 } VIPP_OUTPUT_FMT_REG_t; 227 228 #if defined CONFIG_ARCH_SUN8IW12P1 229 typedef union { 230 unsigned int dwval; 231 struct { 232 unsigned int osd_ov_en:1; 233 unsigned int osd_cv_en:1; 234 unsigned int osd_argb_mode:2; 235 unsigned int osd_stat_en:1; 236 unsigned int res0:3; 237 unsigned int osd_ov_num:6; 238 unsigned int res1:2; 239 unsigned int osd_cv_num:3; 240 unsigned int res2:13; 241 } bits; 242 } VIPP_OSD_CFG_REG_t; 243 244 #else 245 246 typedef union { 247 unsigned int dwval; 248 struct { 249 unsigned int inv_en0:1; 250 unsigned int inv_en1:1; 251 unsigned int inv_en2:1; 252 unsigned int inv_en3:1; 253 unsigned int inv_en4:1; 254 unsigned int inv_en5:1; 255 unsigned int inv_en6:1; 256 unsigned int inv_en7:1; 257 unsigned int inv_th:8; 258 unsigned int stat_en:1; 259 unsigned int hflip:1; 260 unsigned int vflip:1; 261 unsigned int argb_mode:2; 262 unsigned int ov_num:4; 263 unsigned int cv_num:4; 264 unsigned int res0:3; 265 } bits; 266 } VIPP_OSD_CFG_REG_t; 267 268 typedef union { 269 unsigned long long ddwval; 270 struct { 271 unsigned int h_start:12; 272 unsigned int res0:4; 273 unsigned int v_start:12; 274 unsigned int res1:4; 275 unsigned int h_end:12; 276 unsigned int res2:4; 277 unsigned int v_end:12; 278 unsigned int res3:4; 279 } bits; 280 } VIPP_OSD_REGION_REG_t; 281 282 typedef union { 283 unsigned int dwval; 284 struct { 285 unsigned int ov_alpha_rgn0:5; 286 unsigned int ov_alpha_rgn1:5; 287 unsigned int ov_alpha_rgn2:5; 288 unsigned int ov_alpha_rgn3:5; 289 unsigned int res0:12; 290 } bits; 291 } VIPP_OSD_OV_ALPHA_CFG0_REG_t; 292 293 typedef union { 294 unsigned int dwval; 295 struct { 296 unsigned int ov_alpha_rgn4:5; 297 unsigned int ov_alpha_rgn5:5; 298 unsigned int ov_alpha_rgn6:5; 299 unsigned int ov_alpha_rgn7:5; 300 unsigned int res0:12; 301 } bits; 302 } VIPP_OSD_OV_ALPHA_CFG1_REG_t; 303 304 typedef union { 305 unsigned int dwval; 306 struct { 307 unsigned int cv_y:8; 308 unsigned int cv_u:8; 309 unsigned int cv_v:8; 310 unsigned int res0:8; 311 } bits; 312 } VIPP_OSD_CV_REGION_YUV_REG_t; 313 314 typedef union { 315 unsigned int dwval; 316 struct { 317 unsigned int inv_w_rgn0:4; 318 unsigned int inv_w_rgn1:4; 319 unsigned int inv_w_rgn2:4; 320 unsigned int inv_w_rgn3:4; 321 unsigned int inv_w_rgn4:4; 322 unsigned int inv_w_rgn5:4; 323 unsigned int inv_w_rgn6:4; 324 unsigned int inv_w_rgn7:4; 325 } bits; 326 } VIPP_OSD_INV_W_REG_t; 327 328 typedef union { 329 unsigned int dwval; 330 struct { 331 unsigned int inv_h_rgn0:4; 332 unsigned int inv_h_rgn1:4; 333 unsigned int inv_h_rgn2:4; 334 unsigned int inv_h_rgn3:4; 335 unsigned int inv_h_rgn4:4; 336 unsigned int inv_h_rgn5:4; 337 unsigned int inv_h_rgn6:4; 338 unsigned int inv_h_rgn7:4; 339 } bits; 340 } VIPP_OSD_INV_H_REG_t; 341 342 typedef union { 343 unsigned int dwval; 344 struct { 345 unsigned int orl_num:5; 346 unsigned int res0:3; 347 unsigned int orl_width:3; 348 unsigned int res1:5; 349 } bits; 350 } VIPP_ORL_CONTROL_REG_t; 351 352 typedef union { 353 unsigned int dwval; 354 struct { 355 unsigned int orl_xs:13; 356 unsigned int res0:3; 357 unsigned int orl_ys:13; 358 unsigned int res1:3; 359 } bits; 360 } VIPP_ORL_START_REG_t; 361 362 typedef union { 363 unsigned int dwval; 364 struct { 365 unsigned int orl_xe:13; 366 unsigned int res0:3; 367 unsigned int orl_ye:13; 368 unsigned int res1:3; 369 } bits; 370 } VIPP_ORL_END_REG_t; 371 372 typedef union { 373 unsigned int dwval; 374 struct { 375 unsigned int orl_y:8; 376 unsigned int orl_u:8; 377 unsigned int orl_v:8; 378 unsigned int res0:8; 379 } bits; 380 } VIPP_ORL_YUV_REG_t; 381 382 #endif 383 384 typedef union { 385 unsigned int dwval; 386 struct { 387 unsigned int jc0:11; 388 unsigned int res0:5; 389 unsigned int jc1:11; 390 unsigned int res1:5; 391 } bits; 392 } VIPP_OSD_RGB2YUV_GAIN0_REG_t; 393 394 typedef union { 395 unsigned int dwval; 396 struct { 397 unsigned int jc2:11; 398 unsigned int res0:5; 399 unsigned int jc3:11; 400 unsigned int res1:5; 401 } bits; 402 } VIPP_OSD_RGB2YUV_GAIN1_REG_t; 403 404 typedef union { 405 unsigned int dwval; 406 struct { 407 unsigned int jc4:11; 408 unsigned int res0:5; 409 unsigned int jc5:11; 410 unsigned int res1:5; 411 } bits; 412 } VIPP_OSD_RGB2YUV_GAIN2_REG_t; 413 414 typedef union { 415 unsigned int dwval; 416 struct { 417 unsigned int jc6:11; 418 unsigned int res0:5; 419 unsigned int jc7:11; 420 unsigned int res1:5; 421 } bits; 422 } VIPP_OSD_RGB2YUV_GAIN3_REG_t; 423 424 typedef union { 425 unsigned int dwval; 426 struct { 427 unsigned int jc8:11; 428 unsigned int res0:21; 429 } bits; 430 } VIPP_OSD_RGB2YUV_GAIN4_REG_t; 431 432 typedef union { 433 unsigned int dwval; 434 struct { 435 unsigned int jc9:9; 436 unsigned int jc10:9; 437 unsigned int jc11:9; 438 unsigned int res0:5; 439 } bits; 440 } VIPP_OSD_RGB2YUV_OFFSET_REG_t; 441 442 typedef union { 443 unsigned int dwval; 444 struct { 445 unsigned int crop_hor_st:13; 446 unsigned int res0:3; 447 unsigned int crop_ver_st:13; 448 unsigned int res1:5; 449 } bits; 450 } VIPP_CROP_START_POSITION_REG_t; 451 452 typedef union { 453 unsigned int dwval; 454 struct { 455 unsigned int crop_width:13; 456 unsigned int res0:3; 457 unsigned int crop_height:13; 458 unsigned int res1:5; 459 } bits; 460 } VIPP_CROP_SIZE_REG_t; 461 462 typedef union { 463 unsigned long long ddwval; 464 struct { 465 unsigned long long h_start:13; 466 unsigned long long h_end:13; 467 unsigned long long res0:6; 468 unsigned long long v_start:13; 469 unsigned long long v_end:13; 470 unsigned long long alpha:5; 471 unsigned long long inverse_en:1; 472 } bits; 473 } VIPP_OSD_OVERLAY_CFG_REG_t; 474 475 typedef union { 476 unsigned long long ddwval; 477 struct { 478 unsigned long long h_start:13; 479 unsigned long long h_end:13; 480 unsigned long long res0:6; 481 unsigned long long v_start:13; 482 unsigned long long v_end:13; 483 unsigned long long res1:6; 484 } bits; 485 } VIPP_OSD_COVER_CFG_REG_t; 486 487 typedef union { 488 unsigned long long ddwval; 489 struct { 490 unsigned long long y:8; 491 unsigned long long u:8; 492 unsigned long long v:8; 493 unsigned long long res0:40; 494 } bits; 495 } VIPP_OSD_COVER_DATA_REG_t; 496 497 #endif /*__VIPP__REG__I__H__*/ 498