1 /* 2 * Copyright (C) 2019 Allwinnertech Co.Ltd 3 * Authors: zhengwanyu 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2 of the License, or (at your 8 * option) any later version. 9 * 10 */ 11 12 #ifndef _UAPI_SUNXI_DRM_H_ 13 #define _UAPI_SUNXI_DRM_H_ 14 15 #include <video/sunxi_display2.h> 16 #include <uapi/drm/drm.h> 17 18 #if defined(__cplusplus) 19 extern "C" { 20 #endif 21 22 /** 23 * User-desired buffer creation information structure. 24 * 25 * @size: user-desired memory allocation size. 26 * - this size value would be page-aligned internally. 27 * @flags: user request for setting memory type or cache attributes. 28 * @handle: returned a handle to created gem object. 29 * - this handle will be set by gem module of kernel side. 30 */ 31 struct drm_sunxi_gem_create { 32 __u64 size; 33 __u32 flags; 34 __u32 handle; 35 }; 36 37 struct sunxi_drm_crtc_enhance { 38 unsigned int crtc_obj_id; 39 unsigned int mode; 40 bool enable; 41 }; 42 43 struct sunxi_drm_crtc_smbl { 44 unsigned int crtc_obj_id; 45 struct disp_rect window; 46 bool enable; 47 }; 48 49 struct sunxi_drm_phyaddr { 50 /* return the physical address */ 51 __u64 phyaddr; 52 /* dmabuf file descriptor */ 53 __s32 fd; 54 }; 55 56 #define SUNXI_SET_ENHANCE 0x01 57 #define SUNXI_GET_ENHANCE 0x02 58 #define SUNXI_SET_SMBL 0x03 59 #define SUNXI_GET_SMBL 0x04 60 #define SUNXI_GEM_FD_TO_PHYADDR 0X05 61 #define SUNXI_GEM_CREATE 0X06 62 63 /* enhance */ 64 #define DRM_IOCTL_SUNXI_SET_ENHANCE \ 65 DRM_IOWR(DRM_COMMAND_BASE + SUNXI_SET_ENHANCE, \ 66 struct sunxi_drm_crtc_enhance) 67 68 #define DRM_IOCTL_SUNXI_GET_ENHANCE \ 69 DRM_IOWR(DRM_COMMAND_BASE + SUNXI_GET_ENHANCE, \ 70 struct sunxi_drm_crtc_enhance) 71 72 /* smbl */ 73 #define DRM_IOCTL_SUNXI_SET_SMBL \ 74 DRM_IOWR(DRM_COMMAND_BASE + SUNXI_SET_SMBL, \ 75 struct sunxi_drm_crtc_smbl) 76 77 #define DRM_IOCTL_SUNXI_GET_SMBL \ 78 DRM_IOWR(DRM_COMMAND_BASE + SUNXI_GET_SMBL, \ 79 struct sunxi_drm_crtc_smbl) 80 81 /* L2 */ 82 #define DRM_IOCTL_SUNXI_GEM_FD_TO_PHYADDR \ 83 DRM_IOWR(DRM_COMMAND_BASE + SUNXI_GEM_FD_TO_PHYADDR, \ 84 struct sunxi_drm_phyaddr) 85 86 #define DRM_IOCTL_SUNXI_GEM_CREATE \ 87 DRM_IOWR(DRM_COMMAND_BASE + SUNXI_GEM_CREATE, \ 88 struct drm_sunxi_gem_create) 89 90 /* memory type definitions. */ 91 enum e_drm_sunxi_gem_mem_type { 92 /* Physically Continuous memory and used as default. */ 93 SUNXI_BO_CONTIG = 0 << 0, 94 /* Physically Non-Continuous memory. */ 95 SUNXI_BO_NONCONTIG = 1 << 0, 96 /* non-cachable mapping and used as default. */ 97 SUNXI_BO_NONCACHABLE = 0 << 1, 98 /* cachable mapping. */ 99 SUNXI_BO_CACHABLE = 1 << 1, 100 /* write-combine mapping. */ 101 SUNXI_BO_WC = 1 << 2, 102 SUNXI_BO_MASK = SUNXI_BO_NONCONTIG | SUNXI_BO_CACHABLE | 103 SUNXI_BO_WC 104 }; 105 106 #if defined(__cplusplus) 107 } 108 #endif 109 110 #endif 111