1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * allwinner socs boot information. 4 * 5 * copyright (c) 2019 allwinner. 6 * 7 * this file is licensed under the terms of the gnu general public 8 * license version 2. this program is licensed "as is" without any 9 * warranty of any kind, whether express or implied. 10 */ 11 12 #ifndef __SUNXI_BOOT_H__ 13 #define __SUNXI_BOOT_H__ 14 15 #include <linux/types.h> 16 17 enum size_type { 18 BYTE, 19 SECTOR, 20 PAGE, 21 BLOCK 22 }; 23 24 25 #define SBROM_TOC0_HEAD_SPACE (0x80) 26 #define NDFC_PAGE_TAB_MAGIC "BT0.NTAB" 27 #define NDFC_PAGE_TAB_HEAD_SIZE (64) 28 #define STAMP_VALUE 0x5F0A6C39 29 #define NDFC_RR_TAB_MAGIC "BT0.RRTB" 30 #define NDFC_DMY_TAB_MAGIC "BT0.DMTB" //dummy table 31 32 33 typedef struct { 34 __u8 ChipCnt; /* the count of the total nand flash chips are currently connecting on the CE pin */ 35 __u8 ConnectMode; /* the rb connect mode */ 36 __u8 BankCntPerChip; /* the count of the banks in one nand chip, multiple banks can support Inter-Leave */ 37 __u8 DieCntPerChip; /* the count of the dies in one nand chip, block management is based on Die */ 38 __u8 PlaneCntPerDie; /* the count of planes in one die, multiple planes can support multi-plane operation */ 39 __u8 SectorCntPerPage; /* the count of sectors in one single physic page, one sector is 0.5k */ 40 __u16 ChipConnectInfo; /* chip connect information, bit == 1 means there is a chip connecting on the CE pin */ 41 __u32 PageCntPerPhyBlk; /* the count of physic pages in one physic block */ 42 __u32 BlkCntPerDie; /* the count of the physic blocks in one die, include valid block and invalid block */ 43 __u32 OperationOpt; /* the mask of the operation types which current nand flash can support support */ 44 __u32 FrequencePar; /* the parameter of the hardware access clock, based on 'MHz' */ 45 __u32 SpiMode; /* spi nand mode, 0:mode 0, 3:mode 3 */ 46 __u8 NandChipId[8]; /* the nand chip id of current connecting nand chip */ 47 __u32 pagewithbadflag; /* bad block flag was written at the first byte of spare area of this page */ 48 __u32 MultiPlaneBlockOffset; /* the value of the block number offset between the two plane block */ 49 __u32 MaxEraseTimes; /* the max erase times of a physic block */ 50 __u32 MaxEccBits; /* the max ecc bits that nand support */ 51 __u32 EccLimitBits; /* the ecc limit flag for tne nand */ 52 __u32 uboot_start_block; 53 __u32 uboot_next_block; 54 __u32 logic_start_block; 55 __u32 nand_specialinfo_page; 56 __u32 nand_specialinfo_offset; 57 __u32 physic_block_reserved; 58 __u32 Reserved[4]; 59 } boot_spinand_para_t; 60 61 typedef struct { 62 unsigned int ChannelCnt; 63 /*count of total nand chips are currently connecting on the CE pin*/ 64 unsigned int ChipCnt; 65 /*chip connect info, bit=1 means one chip connecting on the CE pin*/ 66 unsigned int ChipConnectInfo; 67 unsigned int RbCnt; 68 /*connect info of all rb chips are connected*/ 69 unsigned int RbConnectInfo; 70 unsigned int RbConnectMode; /*rb connect mode*/ 71 /*count of banks in one nand chip, multi banks can support Inter-Leave*/ 72 unsigned int BankCntPerChip; 73 /*count of dies in one nand chip, block management is based on Die*/ 74 unsigned int DieCntPerChip; 75 /*count of planes in one die, >1 can support multi-plane operation*/ 76 unsigned int PlaneCntPerDie; 77 /*count of sectors in one single physic page, one sector is 0.5k*/ 78 unsigned int SectorCntPerPage; 79 /*count of physic pages in one physic block*/ 80 unsigned int PageCntPerPhyBlk; 81 /*count of physic blocks in one die, include valid and invalid blocks*/ 82 unsigned int BlkCntPerDie; 83 /*mask of operation types which current nand flash can support support*/ 84 unsigned int OperationOpt; 85 /*parameter of hardware access clock, based on 'MHz'*/ 86 unsigned int FrequencePar; 87 /*Ecc Mode for nand chip, 0: bch-16, 1:bch-28, 2:bch_32*/ 88 unsigned int EccMode; 89 /*nand chip id of current connecting nand chip*/ 90 unsigned char NandChipId[8]; 91 /*ratio of valid physical blocks, based on 1024*/ 92 unsigned int ValidBlkRatio; 93 unsigned int good_block_ratio; /*good block ratio get from hwscan*/ 94 unsigned int ReadRetryType; /*read retry type*/ 95 unsigned int DDRType; 96 unsigned int uboot_start_block; 97 unsigned int uboot_next_block; 98 unsigned int logic_start_block; 99 unsigned int nand_specialinfo_page; 100 unsigned int nand_specialinfo_offset; 101 unsigned int physic_block_reserved; 102 /*special nand cmd for some nand in batch cmd, only for write*/ 103 unsigned int random_cmd2_send_flag; 104 /*random col addr num in batch cmd*/ 105 unsigned int random_addr_num; 106 /*real physic page size*/ 107 unsigned int nand_real_page_size; 108 unsigned int Reserved[23]; 109 } boot_nand_para_t; 110 111 typedef struct _normal_gpio_cfg { 112 unsigned char port; 113 unsigned char port_num; 114 char mul_sel; 115 char pull; 116 char drv_level; 117 char data; 118 unsigned char reserved[2]; 119 } normal_gpio_cfg; 120 121 /******************************************************************************/ 122 /* head of Boot0 */ 123 /******************************************************************************/ 124 typedef struct _boot0_private_head_t { 125 unsigned int prvt_head_size; 126 char prvt_head_vsn[4]; /* the version of boot0_private_head_t */ 127 unsigned int dram_para[32]; /* Original values is arbitrary */ 128 int uart_port; 129 normal_gpio_cfg uart_ctrl[2]; 130 int enable_jtag; /* 1 : enable, 0 : disable */ 131 normal_gpio_cfg jtag_gpio[5]; 132 normal_gpio_cfg storage_gpio[32]; 133 char storage_data[512 - sizeof(normal_gpio_cfg) * 32]; 134 } 135 boot0_private_head_t; 136 137 typedef struct standard_Boot_file_head { 138 unsigned int jump_instruction; /* one intruction jumping to real code */ 139 unsigned char magic[8]; /* ="eGON.BT0" or "eGON.BT1", not C-style string */ 140 unsigned int check_sum; /* generated by PC */ 141 unsigned int length; /* generated by PC */ 142 unsigned int pub_head_size; /* size of boot_file_head_t */ 143 unsigned char pub_head_vsn[4]; /* version of boot_file_head_t */ 144 unsigned char file_head_vsn[4]; /* version of boot0_file_head_t or boot1_file_head_t */ 145 unsigned char Boot_vsn[4]; /* Boot version */ 146 unsigned char eGON_vsn[4]; /* eGON version */ 147 unsigned char platform[8]; /* platform information */ 148 } standard_boot_file_head_t; 149 150 typedef struct _boot0_file_head_t { 151 standard_boot_file_head_t boot_head; 152 boot0_private_head_t prvt_head; 153 } boot0_file_head_t; 154 155 typedef struct _boot_core_para_t { 156 unsigned int user_set_clock; 157 unsigned int user_set_core_vol; 158 unsigned int vol_threshold; 159 } boot_core_para_t; 160 161 typedef struct { 162 u8 name[8]; 163 u32 magic; 164 u32 check_sum; 165 166 u32 serial_num; 167 u32 status; 168 169 u32 items_nr; 170 u32 length; 171 u8 platform[4]; 172 u32 reserved[2]; 173 u32 end; 174 175 } toc0_private_head_t; 176 177 typedef struct sbrom_toc0_config { 178 unsigned char config_vsn[4]; 179 unsigned int dram_para[32]; 180 int uart_port; 181 normal_gpio_cfg uart_ctrl[2]; 182 int enable_jtag; 183 normal_gpio_cfg jtag_gpio[5]; 184 normal_gpio_cfg storage_gpio[50]; 185 char storage_data[384]; 186 unsigned int secure_dram_mbytes; 187 unsigned int drm_start_mbytes; 188 unsigned int drm_size_mbytes; 189 unsigned int res[8]; 190 } sbrom_toc0_config_t; 191 192 /******************************************************************************/ 193 /* head of Boot1 */ 194 /******************************************************************************/ 195 typedef struct _boot1_private_head_t { 196 unsigned int dram_para[32]; 197 int run_clock; /* Mhz*/ 198 int run_core_vol; /* mV*/ 199 int uart_port; 200 normal_gpio_cfg uart_gpio[2]; 201 int twi_port; 202 normal_gpio_cfg twi_gpio[2]; 203 int work_mode; 204 int storage_type; /* 0nand 1sdcard 2: spinor*/ 205 normal_gpio_cfg nand_gpio[32]; 206 char nand_spare_data[256]; 207 normal_gpio_cfg sdcard_gpio[32]; 208 char sdcard_spare_data[256]; 209 int reserved[6]; 210 } boot1_private_head_t; 211 #if 0 212 typedef struct _Boot_file_head { 213 unsigned int jump_instruction; /* one intruction jumping to real code */ 214 unsigned char magic[8]; /* ="u-boot" */ 215 unsigned int check_sum; /* generated by PC */ 216 unsigned int align_size; /* align size in byte */ 217 unsigned int length; /* the size of all file */ 218 unsigned int uboot_length; /* the size of uboot */ 219 unsigned char version[8]; /* uboot version */ 220 unsigned char platform[8]; /* platform information */ 221 int reserved[1]; /* stamp space, 16bytes align */ 222 } boot_file_head_t; 223 224 typedef struct _boot1_file_head_t { 225 boot_file_head_t boot_head; 226 boot1_private_head_t prvt_head; 227 } boot1_file_head_t; 228 #endif 229 230 typedef struct _Boot_file_head { 231 __u32 jump_instruction; /* one intruction jumping to real code */ 232 __u8 magic[8]; /* ="eGON.BT0" */ 233 __u32 check_sum; /* generated by PC */ 234 __u32 length; /* generated by PC */ 235 __u32 pub_head_size; /* the size of boot_file_head_t */ 236 __u8 pub_head_vsn[4]; /* the version of boot_file_head_t */ 237 __u32 ret_addr; /* the return value */ 238 __u32 run_addr; /* run addr */ 239 __u32 boot_cpu; /* eGON version */ 240 __u8 platform[8]; /* platform information */ 241 } boot_file_head_t; 242 243 244 245 struct boot_ndfc_cfg { 246 u8 page_size_kb; 247 u8 ecc_mode; 248 u8 sequence_mode; 249 u8 res[5]; 250 }; 251 #endif /*SUNXI_BOOT_H*/ 252