1 /* 2 * Allwinner SoCs display driver. 3 * 4 * Copyright (C) 2016 Allwinner. 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 */ 10 11 #ifndef __SUNXI_DISPLAY2_H__ 12 #define __SUNXI_DISPLAY2_H__ 13 14 struct disp_manager; 15 struct disp_device; 16 struct disp_smbl; 17 struct disp_enhance; 18 struct disp_capture; 19 20 struct disp_color { 21 unsigned char alpha; 22 unsigned char red; 23 unsigned char green; 24 unsigned char blue; 25 }; 26 27 struct disp_rect { 28 int x; 29 int y; 30 unsigned int width; 31 unsigned int height; 32 }; 33 34 struct disp_rectsz { 35 unsigned int width; 36 unsigned int height; 37 }; 38 39 struct disp_position { 40 int x; 41 int y; 42 }; 43 44 enum disp_pixel_format { 45 DISP_FORMAT_ARGB_8888 = 0x00, /* MSB A-R-G-B LSB */ 46 DISP_FORMAT_ABGR_8888 = 0x01, 47 DISP_FORMAT_RGBA_8888 = 0x02, 48 DISP_FORMAT_BGRA_8888 = 0x03, 49 DISP_FORMAT_XRGB_8888 = 0x04, 50 DISP_FORMAT_XBGR_8888 = 0x05, 51 DISP_FORMAT_RGBX_8888 = 0x06, 52 DISP_FORMAT_BGRX_8888 = 0x07, 53 DISP_FORMAT_RGB_888 = 0x08, 54 DISP_FORMAT_BGR_888 = 0x09, 55 DISP_FORMAT_RGB_565 = 0x0a, 56 DISP_FORMAT_BGR_565 = 0x0b, 57 DISP_FORMAT_ARGB_4444 = 0x0c, 58 DISP_FORMAT_ABGR_4444 = 0x0d, 59 DISP_FORMAT_RGBA_4444 = 0x0e, 60 DISP_FORMAT_BGRA_4444 = 0x0f, 61 DISP_FORMAT_ARGB_1555 = 0x10, 62 DISP_FORMAT_ABGR_1555 = 0x11, 63 DISP_FORMAT_RGBA_5551 = 0x12, 64 DISP_FORMAT_BGRA_5551 = 0x13, 65 DISP_FORMAT_A2R10G10B10 = 0x14, 66 DISP_FORMAT_A2B10G10R10 = 0x15, 67 DISP_FORMAT_R10G10B10A2 = 0x16, 68 DISP_FORMAT_B10G10R10A2 = 0x17, 69 DISP_FORMAT_1bpp_palette_LE = 0x18, 70 DISP_FORMAT_2bpp_palette_LE = 0x19, 71 DISP_FORMAT_4bpp_palette_LE = 0x1a, 72 DISP_FORMAT_8bpp_palette_LE = 0x1b, 73 /* 74 * SP: semi-planar 75 * P:planar 76 * I:interleaved 77 * UVUV: U in the LSBs; 78 * VUVU: V in the LSBs 79 */ 80 DISP_FORMAT_YUV444_I_AYUV = 0x40, /* MSB A-Y-U-V LSB */ 81 DISP_FORMAT_YUV444_I_VUYA = 0x41, /* MSB V-U-Y-A LSB */ 82 DISP_FORMAT_YUV422_I_YVYU = 0x42, /* MSB Y-V-Y-U LSB */ 83 DISP_FORMAT_YUV422_I_YUYV = 0x43, /* MSB Y-U-Y-V LSB */ 84 DISP_FORMAT_YUV422_I_UYVY = 0x44, /* MSB U-Y-V-Y LSB */ 85 DISP_FORMAT_YUV422_I_VYUY = 0x45, /* MSB V-Y-U-Y LSB */ 86 DISP_FORMAT_YUV444_P = 0x46, /* MSB P3-2-1-0 LSB, YYYY UUUU VVVV */ 87 DISP_FORMAT_YUV422_P = 0x47, /* MSB P3-2-1-0 LSB YYYY UU VV */ 88 DISP_FORMAT_YUV420_P = 0x48, /* MSB P3-2-1-0 LSB YYYY U V */ 89 DISP_FORMAT_YUV411_P = 0x49, /* MSB P3-2-1-0 LSB YYYY U V */ 90 DISP_FORMAT_YUV422_SP_UVUV = 0x4a, /* MSB V-U-V-U LSB */ 91 DISP_FORMAT_YUV422_SP_VUVU = 0x4b, /* MSB U-V-U-V LSB */ 92 DISP_FORMAT_YUV420_SP_UVUV = 0x4c, 93 DISP_FORMAT_YUV420_SP_VUVU = 0x4d, 94 DISP_FORMAT_YUV411_SP_UVUV = 0x4e, 95 DISP_FORMAT_YUV411_SP_VUVU = 0x4f, 96 DISP_FORMAT_8BIT_GRAY = 0x50, 97 DISP_FORMAT_YUV444_I_AYUV_10BIT = 0x51, 98 DISP_FORMAT_YUV444_I_VUYA_10BIT = 0x52, 99 DISP_FORMAT_YUV422_I_YVYU_10BIT = 0x53, 100 DISP_FORMAT_YUV422_I_YUYV_10BIT = 0x54, 101 DISP_FORMAT_YUV422_I_UYVY_10BIT = 0x55, 102 DISP_FORMAT_YUV422_I_VYUY_10BIT = 0x56, 103 DISP_FORMAT_YUV444_P_10BIT = 0x57, 104 DISP_FORMAT_YUV422_P_10BIT = 0x58, 105 DISP_FORMAT_YUV420_P_10BIT = 0x59, 106 DISP_FORMAT_YUV411_P_10BIT = 0x5a, 107 DISP_FORMAT_YUV422_SP_UVUV_10BIT = 0x5b, 108 DISP_FORMAT_YUV422_SP_VUVU_10BIT = 0x5c, 109 DISP_FORMAT_YUV420_SP_UVUV_10BIT = 0x5d, 110 DISP_FORMAT_YUV420_SP_VUVU_10BIT = 0x5e, 111 DISP_FORMAT_YUV411_SP_UVUV_10BIT = 0x5f, 112 DISP_FORMAT_YUV411_SP_VUVU_10BIT = 0x60, 113 DISP_FORMAT_MAX, 114 }; 115 116 enum disp_3d_out_mode { 117 DISP_3D_OUT_MODE_CI_1 = 0x5, /* column interlaved 1 */ 118 DISP_3D_OUT_MODE_CI_2 = 0x6, /* column interlaved 2 */ 119 DISP_3D_OUT_MODE_CI_3 = 0x7, /* column interlaved 3 */ 120 DISP_3D_OUT_MODE_CI_4 = 0x8, /* column interlaved 4 */ 121 DISP_3D_OUT_MODE_LIRGB = 0x9, /* line interleaved rgb */ 122 123 DISP_3D_OUT_MODE_TB = 0x0, /* top bottom */ 124 DISP_3D_OUT_MODE_FP = 0x1, /* frame packing */ 125 DISP_3D_OUT_MODE_SSF = 0x2, /* side by side full */ 126 DISP_3D_OUT_MODE_SSH = 0x3, /* side by side half */ 127 DISP_3D_OUT_MODE_LI = 0x4, /* line interleaved */ 128 DISP_3D_OUT_MODE_FA = 0xa, /* field alternative */ 129 }; 130 131 enum disp_color_space { 132 DISP_UNDEF = 0x00, 133 DISP_UNDEF_F = 0x01, 134 DISP_GBR = 0x100, 135 DISP_BT709 = 0x101, 136 DISP_FCC = 0x102, 137 DISP_BT470BG = 0x103, 138 DISP_BT601 = 0x104, 139 DISP_SMPTE240M = 0x105, 140 DISP_YCGCO = 0x106, 141 DISP_BT2020NC = 0x107, 142 DISP_BT2020C = 0x108, 143 DISP_GBR_F = 0x200, 144 DISP_BT709_F = 0x201, 145 DISP_FCC_F = 0x202, 146 DISP_BT470BG_F = 0x203, 147 DISP_BT601_F = 0x204, 148 DISP_SMPTE240M_F = 0x205, 149 DISP_YCGCO_F = 0x206, 150 DISP_BT2020NC_F = 0x207, 151 DISP_BT2020C_F = 0x208, 152 DISP_RESERVED = 0x300, 153 DISP_RESERVED_F = 0x301, 154 }; 155 156 enum disp_csc_type { 157 DISP_CSC_TYPE_RGB = 0, 158 DISP_CSC_TYPE_YUV444 = 1, 159 DISP_CSC_TYPE_YUV422 = 2, 160 DISP_CSC_TYPE_YUV420 = 3, 161 }; 162 163 enum disp_data_bits { 164 DISP_DATA_8BITS = 0, 165 DISP_DATA_10BITS = 1, 166 DISP_DATA_12BITS = 2, 167 DISP_DATA_16BITS = 3, 168 }; 169 enum disp_dvi_hdmi { 170 DISP_DVI_HDMI_UNDEFINED = 0, 171 DISP_DVI = 1, 172 DISP_HDMI = 2, 173 }; 174 enum disp_scan_info { 175 DISP_SCANINFO_NO_DATA = 0, 176 OVERSCAN = 1, 177 UNDERSCAN = 2, 178 }; 179 enum disp_color_range { 180 DISP_COLOR_RANGE_DEFAULT = 0, /*default*/ 181 DISP_COLOR_RANGE_0_255 = 1, 182 DISP_COLOR_RANGE_16_235 = 2, 183 }; 184 185 enum disp_output_type { 186 DISP_OUTPUT_TYPE_NONE = 0, 187 DISP_OUTPUT_TYPE_LCD = 1, 188 DISP_OUTPUT_TYPE_TV = 2, 189 DISP_OUTPUT_TYPE_HDMI = 4, 190 DISP_OUTPUT_TYPE_VGA = 8, 191 DISP_OUTPUT_TYPE_VDPO = 16, 192 DISP_OUTPUT_TYPE_EDP = 32, /*16 for vdpo*/ 193 DISP_OUTPUT_TYPE_RTWB = 64, 194 }; 195 196 enum disp_tv_mode { 197 DISP_TV_MOD_480I = 0, 198 DISP_TV_MOD_576I = 1, 199 DISP_TV_MOD_480P = 2, 200 DISP_TV_MOD_576P = 3, 201 DISP_TV_MOD_720P_50HZ = 4, 202 DISP_TV_MOD_720P_60HZ = 5, 203 DISP_TV_MOD_1080I_50HZ = 6, 204 DISP_TV_MOD_1080I_60HZ = 7, 205 DISP_TV_MOD_1080P_24HZ = 8, 206 DISP_TV_MOD_1080P_50HZ = 9, 207 DISP_TV_MOD_1080P_60HZ = 0xa, 208 DISP_TV_MOD_1080P_24HZ_3D_FP = 0x17, 209 DISP_TV_MOD_720P_50HZ_3D_FP = 0x18, 210 DISP_TV_MOD_720P_60HZ_3D_FP = 0x19, 211 DISP_TV_MOD_1080P_25HZ = 0x1a, 212 DISP_TV_MOD_1080P_30HZ = 0x1b, 213 DISP_TV_MOD_PAL = 0xb, 214 DISP_TV_MOD_PAL_SVIDEO = 0xc, 215 DISP_TV_MOD_NTSC = 0xe, 216 DISP_TV_MOD_NTSC_SVIDEO = 0xf, 217 DISP_TV_MOD_PAL_M = 0x11, 218 DISP_TV_MOD_PAL_M_SVIDEO = 0x12, 219 DISP_TV_MOD_PAL_NC = 0x14, 220 DISP_TV_MOD_PAL_NC_SVIDEO = 0x15, 221 DISP_TV_MOD_3840_2160P_30HZ = 0x1c, 222 DISP_TV_MOD_3840_2160P_25HZ = 0x1d, 223 DISP_TV_MOD_3840_2160P_24HZ = 0x1e, 224 DISP_TV_MOD_4096_2160P_24HZ = 0x1f, 225 DISP_TV_MOD_4096_2160P_25HZ = 0x20, 226 DISP_TV_MOD_4096_2160P_30HZ = 0x21, 227 DISP_TV_MOD_3840_2160P_60HZ = 0x22, 228 DISP_TV_MOD_4096_2160P_60HZ = 0x23, 229 DISP_TV_MOD_3840_2160P_50HZ = 0x24, 230 DISP_TV_MOD_4096_2160P_50HZ = 0x25, 231 DISP_TV_MOD_2560_1440P_60HZ = 0x26, 232 DISP_TV_MOD_1440_2560P_70HZ = 0x27, 233 DISP_TV_MOD_1080_1920P_60HZ = 0x28, 234 DISP_TV_MOD_1280_1024P_60HZ = 0x41, 235 DISP_TV_MOD_1024_768P_60HZ = 0x42, 236 DISP_TV_MOD_900_540P_60HZ = 0x43, 237 DISP_TV_MOD_1920_720P_60HZ = 0x44, 238 /* vga */ 239 DISP_VGA_MOD_640_480P_60 = 0x50, 240 DISP_VGA_MOD_800_600P_60 = 0x51, 241 DISP_VGA_MOD_1024_768P_60 = 0x52, 242 DISP_VGA_MOD_1280_768P_60 = 0x53, 243 DISP_VGA_MOD_1280_800P_60 = 0x54, 244 DISP_VGA_MOD_1366_768P_60 = 0x55, 245 DISP_VGA_MOD_1440_900P_60 = 0x56, 246 DISP_VGA_MOD_1920_1080P_60 = 0x57, 247 DISP_VGA_MOD_1920_1200P_60 = 0x58, 248 DISP_TV_MOD_3840_1080P_30 = 0x59, 249 DISP_VGA_MOD_1280_720P_60 = 0x5a, 250 DISP_VGA_MOD_1600_900P_60 = 0x5b, 251 DISP_VGA_MOD_MAX_NUM = 0x5c, 252 DISP_TV_MODE_NUM, 253 }; 254 255 enum disp_exit_mode { 256 DISP_EXIT_MODE_CLEAN_ALL = 0, 257 DISP_EXIT_MODE_CLEAN_PARTLY = 1, /* only clean interrupt temply */ 258 }; 259 260 enum disp_buffer_flags { 261 DISP_BF_NORMAL = 0, /* non-stereo */ 262 DISP_BF_STEREO_TB = 1 << 0, /* stereo top-bottom */ 263 DISP_BF_STEREO_FP = 1 << 1, /* stereo frame packing */ 264 DISP_BF_STEREO_SSH = 1 << 2, /* stereo side by side half */ 265 DISP_BF_STEREO_SSF = 1 << 3, /* stereo side by side full */ 266 DISP_BF_STEREO_LI = 1 << 4, /* stereo line interlace */ 267 /* 268 * 2d plus depth to convert into 3d, 269 * left and right image using the same frame buffer 270 */ 271 DISP_BF_STEREO_2D_DEPTH = 1 << 5, 272 }; 273 274 enum disp_layer_mode { 275 LAYER_MODE_BUFFER = 0, 276 LAYER_MODE_COLOR = 1, 277 }; 278 279 enum disp_scan_flags { 280 DISP_SCAN_PROGRESSIVE = 0, 281 DISP_SCAN_INTERLACED_ODD_FLD_FIRST = 1 << 0, 282 DISP_SCAN_INTERLACED_EVEN_FLD_FIRST = 1 << 1, 283 }; 284 285 enum disp_eotf { 286 DISP_EOTF_RESERVED = 0x000, 287 DISP_EOTF_BT709 = 0x001, 288 DISP_EOTF_UNDEF = 0x002, 289 DISP_EOTF_GAMMA22 = 0x004, /* SDR */ 290 DISP_EOTF_GAMMA28 = 0x005, 291 DISP_EOTF_BT601 = 0x006, 292 DISP_EOTF_SMPTE240M = 0x007, 293 DISP_EOTF_LINEAR = 0x008, 294 DISP_EOTF_LOG100 = 0x009, 295 DISP_EOTF_LOG100S10 = 0x00a, 296 DISP_EOTF_IEC61966_2_4 = 0x00b, 297 DISP_EOTF_BT1361 = 0x00c, 298 DISP_EOTF_IEC61966_2_1 = 0X00d, 299 DISP_EOTF_BT2020_0 = 0x00e, 300 DISP_EOTF_BT2020_1 = 0x00f, 301 DISP_EOTF_SMPTE2084 = 0x010, /* HDR10 */ 302 DISP_EOTF_SMPTE428_1 = 0x011, 303 DISP_EOTF_ARIB_STD_B67 = 0x012, /* HLG */ 304 }; 305 /* disp_atw_mode - mode for asynchronous time warp 306 * 307 * @NORMAL_MODE: dual buffer, left eye and right eye buffer is individual 308 * @LEFT_RIGHT_MODE: single buffer, the left half of each line buffer 309 * is for left eye, the right half is for the right eye 310 * @UP_DOWN_MODE: single buffer, the first half of the total buffer 311 * is for the left eye, the second half is for the right eye 312 */ 313 enum disp_atw_mode { 314 NORMAL_MODE, 315 LEFT_RIGHT_MODE, 316 UP_DOWN_MODE, 317 }; 318 struct disp_output { 319 unsigned int type; 320 unsigned int mode; 321 }; 322 323 enum disp_transform { 324 DISP_TRANSFORM_ROT_0 = 0x00, 325 DISP_TRANSFORM_ROT_90 = 0x01, 326 DISP_TRANSFORM_ROT_180 = 0x02, 327 DISP_TRANSFORM_ROT_270 = 0x03, 328 DISP_TRANSFORM_FLIP_H = 0x04, 329 DISP_TRANSFORM_ROT_90_FLIP_H = 0x05, 330 DISP_TRANSFORM_FLIP_V = 0x06, 331 DISP_TRANSFORM_ROT_90_FLIP_V = 0x07, 332 }; 333 334 struct disp_rect64 { 335 long long x; 336 long long y; 337 long long width; 338 long long height; 339 }; 340 341 struct disp_lbc_info { 342 unsigned int is_lossy; 343 unsigned int rc_en; 344 unsigned int pitch; 345 unsigned int seg_bit; 346 }; 347 348 struct disp_fb_info { 349 /* address of frame buffer, 350 * single addr for interleaved fomart, 351 * double addr for semi-planar fomart 352 * triple addr for planar format 353 */ 354 unsigned long long addr[3]; 355 struct disp_rectsz size[3]; 356 /* align for 3 comonent,unit: bytes */ 357 unsigned int align[3]; 358 enum disp_pixel_format format; 359 enum disp_color_space color_space; /* color space */ 360 unsigned int trd_right_addr[3]; /* right address of 3d fb */ 361 bool pre_multiply; /* true: pre-multiply fb */ 362 struct disp_rect64 crop; /* crop rectangle boundaries */ 363 enum disp_buffer_flags flags; 364 enum disp_scan_flags scan; 365 unsigned int lbc_en; 366 struct disp_lbc_info lbc_info; 367 }; 368 369 struct disp_layer_info { 370 enum disp_layer_mode mode; 371 unsigned char zorder; 372 /* 0: pixel alpha; 1: global alpha; 2: global pixel alpha */ 373 unsigned char alpha_mode; 374 unsigned char alpha_value; /* global alpha value */ 375 struct disp_rect screen_win; /* display window on the screen */ 376 bool b_trd_out; /* 3d display */ 377 enum disp_3d_out_mode out_trd_mode; /* 3d display mode */ 378 union { 379 unsigned int color; /* valid when LAYER_MODE_COLOR */ 380 struct disp_fb_info fb; /* valid when LAYER_MODE_BUFFER */ 381 }; 382 383 unsigned int id; /* frame id, the id of frame display currently */ 384 }; 385 386 struct disp_layer_config { 387 struct disp_layer_info info; 388 bool enable; 389 unsigned int channel; 390 unsigned int layer_id; 391 }; 392 393 /* disp_atw_info - asynchronous time wrap infomation 394 * 395 * @used: indicate if the atw funtion is used 396 * @mode: atw mode 397 * @b_row: the row number of the micro block 398 * @b_col: the column number of the micro block 399 * @cof_fd: dma_buf fd for the buffer contaied coefficient for atw 400 */ 401 struct disp_atw_info { 402 bool used; 403 enum disp_atw_mode mode; 404 unsigned int b_row; 405 unsigned int b_col; 406 int cof_fd; 407 }; 408 /** 409 * disp_vdpo_config 410 */ 411 struct disp_vdpo_config { 412 unsigned int data_seq_sel; 413 unsigned int dclk_invt; 414 unsigned int dclk_dly_num; 415 unsigned int spl_type_u; 416 unsigned int spl_type_v; 417 }; 418 419 /* disp_fb_info2 - image buffer info v2 420 * 421 * @fd: dma_buf fd for frame buffer 422 * @size: size<width,height> for each buffer, unit:pixels 423 * @align: align for each buffer, unit:bytes 424 * @format: pixel format 425 * @color_space: color space 426 * @trd_right_fd: dma_buf fd for the right-eye frame buffer, 427 * valid when frame-packing 3d buffer input 428 * @pre_multiply: indicate the pixel use premultiplied alpha 429 * @crop: crop rectangle for buffer to be display 430 * @flag: indicate stereo/non-stereo buffer 431 * @scan: indicate interleave/progressive scan type, and the scan order 432 * @depth: depth perception for stereo image, only valid when stereo image input 433 * unit: pixel 434 * @fbd_en: indicate if enable fbd function 435 * @lbc_en: indicate if enable lbc function 436 * @metadata_fd: dma_buf fd for the buffer contained metadata for fbc/hdr 437 * @metadata_size: the size of metadata buffer, unit:bytes 438 * @metadata_flag: the flag to indicate the type of metadata buffer 439 * 0 : no metadata 440 * 1 << 0: hdr static metadata 441 * 1 << 1: hdr dynamic metadata 442 * 1 << 4: frame buffer compress(fbc) metadata 443 * x : all type could be "or" together 444 */ 445 struct disp_fb_info2 { 446 int fd; 447 struct disp_rectsz size[3]; 448 unsigned int align[3]; 449 enum disp_pixel_format format; 450 enum disp_color_space color_space; 451 int trd_right_fd; 452 bool pre_multiply; 453 struct disp_rect64 crop; 454 enum disp_buffer_flags flags; 455 enum disp_scan_flags scan; 456 enum disp_eotf eotf; 457 int depth; 458 unsigned int fbd_en; 459 unsigned int lbc_en; 460 struct disp_lbc_info lbc_info; 461 int metadata_fd; 462 unsigned int metadata_size; 463 unsigned int metadata_flag; 464 }; 465 466 /** 467 * disp_snr_info 468 */ 469 struct disp_snr_info { 470 unsigned char en; 471 unsigned char demo_en; 472 struct disp_rect demo_win; 473 unsigned char y_strength; 474 unsigned char u_strength; 475 unsigned char v_strength; 476 unsigned char th_ver_line; 477 unsigned char th_hor_line; 478 }; 479 480 /* disp_layer_info2 - layer info v2 481 * 482 * @mode: buffer/clolor mode, when in color mode, the layer is widthout buffer 483 * @zorder: the zorder of layer, 0~max-layer-number 484 * @alpha_mode: 485 * 0: pixel alpha; 486 * 1: global alpha 487 * 2: mixed alpha, compositing width pixel alpha before global alpha 488 * @alpha_value: global alpha value, valid when alpha_mode is not pixel alpha 489 * @screen_win: the rectangle on the screen for fb to be display 490 * @b_trd_out: indicate if 3d display output 491 * @out_trd_mode: 3d output mode, valid when b_trd_out is true 492 * @color: the color value to be display, valid when layer is in color mode 493 * @fb: the framebuffer info related width the layer, valid when in buffer mode 494 * @id: frame id, the user could get the frame-id display currently by 495 * DISP_LAYER_GET_FRAME_ID ioctl 496 * @atw: asynchronous time wrap information 497 */ 498 struct disp_layer_info2 { 499 enum disp_layer_mode mode; 500 unsigned char zorder; 501 unsigned char alpha_mode; 502 unsigned char alpha_value; 503 struct disp_rect screen_win; 504 bool b_trd_out; 505 enum disp_3d_out_mode out_trd_mode; 506 union { 507 unsigned int color; 508 struct disp_fb_info2 fb; 509 }; 510 511 unsigned int id; 512 struct disp_atw_info atw; 513 enum disp_transform transform; 514 struct disp_snr_info snr; 515 }; 516 517 /* disp_layer_config2 - layer config v2 518 * 519 * @info: layer info 520 * @enable: indicate to enable/disable the layer 521 * @channel: the channel index of the layer, 0~max-channel-number 522 * @layer_id: the layer index of the layer widthin it's channel 523 */ 524 struct disp_layer_config2 { 525 struct disp_layer_info2 info; 526 bool enable; 527 unsigned int channel; 528 unsigned int layer_id; 529 }; 530 531 532 /* disp_palette_config - palette config 533 * 534 * @num: the num of palette 535 * @data: the palette data, each palette data takes 4 bytes,show as below 536 * bits description 537 * 31:24 alpha value 538 * 23:16 red value 539 * 15:8 green value 540 * 7:0 blue value 541 * @channel: the channel index of the layer, 0~max-channel-number 542 */ 543 struct disp_palette_config { 544 unsigned int num; 545 void *data; 546 unsigned int channel; 547 }; 548 549 /** 550 * match rule: 0/1:always match; 551 * 2:match if min<=color<=max; 552 * 3:match if color>max or color<min 553 */ 554 struct disp_colorkey { 555 struct disp_color ck_max; 556 struct disp_color ck_min; 557 unsigned int red_match_rule; 558 unsigned int green_match_rule; 559 unsigned int blue_match_rule; 560 }; 561 562 struct disp_s_frame { 563 enum disp_pixel_format format; 564 struct disp_rectsz size[3]; 565 struct disp_rect crop; 566 unsigned long long addr[3]; 567 }; 568 569 struct disp_capture_info { 570 /* capture the whole screen if window eq ZERO */ 571 struct disp_rect window; 572 struct disp_s_frame out_frame; 573 }; 574 575 /* disp_s_frame2 - display simple frame buffer 576 * 577 * @format: pixel format of fb 578 * @size: size for each plane 579 * @crop: crop zone to be fill image data 580 * @fd: dma_buf fd 581 */ 582 struct disp_s_frame2 { 583 enum disp_pixel_format format; 584 struct disp_rectsz size[3]; 585 struct disp_rect crop; 586 int fd; 587 }; 588 589 /* disp_capture_info2 - display capture information 590 * 591 * @window: the rectange on the screen to be capture 592 * @out_frame: the framebuffer to be restore capture image data 593 */ 594 struct disp_capture_info2 { 595 struct disp_rect window; 596 struct disp_s_frame2 out_frame; 597 }; 598 599 struct disp_capture_fmt { 600 enum disp_pixel_format format; /* write-back ouput format, doson't support YUV ouput yet */ 601 struct disp_rect window; /* source crop */ 602 struct disp_rect crop; /* output crop */ 603 }; 604 605 struct disp_capture_buffer { 606 int handle; /* Unique integer id represent this buffer */ 607 enum disp_pixel_format format; /* write-back ouput format */ 608 struct disp_rect window; /* source crop */ 609 struct disp_rect crop; /* output crop */ 610 struct disp_rectsz size[3]; 611 612 int fd; 613 int width; /* buffer width in pixels */ 614 int height; /* buffer height in pixels */ 615 }; 616 617 struct disp_capture_handle { 618 int handle; /* unique integer id represent a capture buffer */ 619 int fencefd; /* fence fd for this buffer */ 620 }; 621 622 enum disp_capture_extend_cmd { 623 DISP_CAPTURE_E_SET_FMT, 624 DISP_CAPTURE_E_BUFFER_LIST_INIT, 625 DISP_CAPTURE_E_BUFFER_LIST_CLEAR, 626 DISP_CAPTURE_E_ACQUIRE_BUFFER, 627 DISP_CAPTURE_E_RELEASE_BUFFER, 628 DISP_CAPTURE_E_CTRL, 629 }; 630 631 /* disp_device_config - display deivce config 632 * 633 * @type: output type 634 * @mode: output mode 635 * @format: data format 636 * @bits: data bits 637 * @eotf: electro-optical transfer function 638 * SDR : DISP_EOTF_GAMMA22 639 * HDR10: DISP_EOTF_SMPTE2084 640 * HLG : DISP_EOTF_ARIB_STD_B67 641 * @cs: color space type 642 * DISP_BT601: SDR for SD resolution(< 720P) 643 * DISP_BT709: SDR for HD resolution(>= 720P) 644 * DISP_BT2020NC: HDR10 or HLG or wide-color-gamut 645 * @dvi_hdmi: output mode 646 * DVI: DISP_DVI 647 * HDMI: DISP_HDMI 648 * @range: RGB/YUV quantization range 649 * DEFUALT: limited range when sending a CE video format 650 * full range when sending an IT video format 651 * LIMITED: color limited range from 16 to 235 652 * FULL: color full range from 0 to 255 653 * @scan info: 654 * DISP_SCANINFO_NO_DATA: overscan if it is a CE format, 655 * underscan if it is an IT format 656 * OVERSCAN: composed for overscan display 657 * UNDERSCAN: composed for underscan display 658 * @aspect_ratio: active format aspect ratio 659 */ 660 struct disp_device_config { 661 enum disp_output_type type; 662 enum disp_tv_mode mode; 663 enum disp_csc_type format; 664 enum disp_data_bits bits; 665 enum disp_eotf eotf; 666 enum disp_color_space cs; 667 enum disp_dvi_hdmi dvi_hdmi; 668 enum disp_color_range range; 669 enum disp_scan_info scan; 670 unsigned int aspect_ratio; 671 unsigned int reserve1; 672 }; 673 674 /* disp_device_dynamic_config - display deivce dynamic config 675 * 676 * @metadata_fd: dma_buf fd for the buffer contained metadata for fbc/hdr 677 * @metadata_size: the size of metadata buffer, unit:bytes 678 * @metadata_flag: the flag to indicate the type of metadata buffer 679 * 0 : no metadata 680 * 1 << 0: hdr static metadata 681 * 1 << 1: hdr dynamic metadata 682 * 1 << 4: frame buffer compress(fbc) metadata 683 * x : all type could be "or" together 684 * @vmap:vmap a block contigous phys memory into virtual space 685 * @vunmap: release virtual mapping obtained by vmap() 686 */ 687 struct disp_device_dynamic_config { 688 int metadata_fd; 689 unsigned int metadata_size; 690 unsigned int metadata_flag; 691 void *(*vmap)(unsigned long phys_addr, unsigned long size); 692 void (*vunmap)(const void *vaddr); 693 }; 694 struct disp_video_timings { 695 unsigned int vic; /* video information code */ 696 unsigned int tv_mode; 697 unsigned int pixel_clk; 698 unsigned int pixel_repeat; /* pixel repeat (pixel_repeat+1) times */ 699 unsigned int x_res; 700 unsigned int y_res; 701 unsigned int hor_total_time; 702 unsigned int hor_back_porch; 703 unsigned int hor_front_porch; 704 unsigned int hor_sync_time; 705 unsigned int ver_total_time; 706 unsigned int ver_back_porch; 707 unsigned int ver_front_porch; 708 unsigned int ver_sync_time; 709 unsigned int hor_sync_polarity; /* 0: negative, 1: positive */ 710 unsigned int ver_sync_polarity; /* 0: negative, 1: positive */ 711 bool b_interlace; 712 unsigned int vactive_space; 713 unsigned int trd_mode; 714 unsigned long dclk_rate_set; /*unit: hz */ 715 unsigned long long frame_period; /* unit: ns */ 716 int start_delay; /* unit: line */ 717 }; 718 719 enum disp_fb_mode { 720 FB_MODE_SCREEN0 = 0, 721 FB_MODE_SCREEN1 = 1, 722 FB_MODE_SCREEN2 = 2, 723 FB_MODE_DUAL_SAME_SCREEN_TB = 3,/* two screen, top buffer for screen0, bottom buffer for screen1 */ 724 FB_MODE_DUAL_DIFF_SCREEN_SAME_CONTENTS = 4,/* two screen, they have same contents; */ 725 }; 726 727 struct disp_fb_create_info { 728 enum disp_fb_mode fb_mode; 729 enum disp_layer_mode mode; 730 unsigned int buffer_num; 731 unsigned int width; 732 unsigned int height; 733 734 unsigned int output_width; /* used when scaler mode */ 735 unsigned int output_height; /* used when scaler mode */ 736 }; 737 738 enum disp_init_mode { 739 DISP_INIT_MODE_SCREEN0 = 0, /* fb0 for screen0 */ 740 DISP_INIT_MODE_SCREEN1 = 1, /* fb0 for screen1 */ 741 DISP_INIT_MODE_SCREEN2 = 2, /* fb0 for screen1 */ 742 DISP_INIT_MODE_TWO_DIFF_SCREEN = 3,/* fb0 for screen0 and fb1 for screen1 */ 743 DISP_INIT_MODE_TWO_SAME_SCREEN = 4,/* fb0(up buffer for screen0, down buffer for screen1) */ 744 DISP_INIT_MODE_TWO_DIFF_SCREEN_SAME_CONTENTS = 5,/* fb0 for two different screen(screen0 layer is normal layer, screen1 layer is scaler layer); */ 745 }; 746 747 struct disp_tv_func { 748 int (*tv_enable)(u32 sel); 749 int (*tv_disable)(u32 sel); 750 int (*tv_suspend)(u32 sel); 751 int (*tv_resume)(u32 sel); 752 int (*tv_get_mode)(u32 sel); 753 int (*tv_set_mode)(u32 sel, enum disp_tv_mode tv_mod); 754 int (*tv_get_input_csc)(u32 sel); 755 int (*tv_get_video_timing_info)(u32 sel, 756 struct disp_video_timings ** 757 video_info); 758 int (*tv_mode_support)(u32 sel, enum disp_tv_mode mode); 759 int (*tv_hot_plugging_detect)(u32 state); 760 int (*tv_set_enhance_mode)(u32 sel, u32 mode); 761 int (*tv_irq_enable)(u32 sel, u32 irq_id, u32 en); 762 int (*tv_irq_query)(u32 sel); 763 unsigned int (*tv_get_cur_line)(u32 sel); 764 int (*vdpo_set_config)(u32 sel, struct disp_vdpo_config *p_cfg); 765 int (*tv_get_startdelay)(u32 sel); 766 void (*tv_show_builtin_patten)(u32 sel, u32 patten); 767 }; 768 769 /* disp_vdevice_interface_para - vdevice interaface parameter 770 * 771 * @intf:interface 772 * 0:hv, 1:cpu, 3:lvds, 4:dsi 773 * @sub_intf: sub interface 774 * rgb interface: 0:parallel hv, 8:serial hv, 10:dummy rgb 775 * 11: rgb dummy, 12: ccir656 776 * cpu interface: 0:18 pin, 10:9pin, 12:6pin, 8:16pin, 14:8pin 777 * lvds interface:0:single link, 1:dual link 778 * dsi inerafce: 0:video mode, 1:command mode, 2: video burst mode 779 * @sequence:output sequence 780 * rgb output: 0:rgb rgb, 1:rgb brg, 2:rgb gbr, 4:brg rgb 781 * 5:brg brg, 6:brg gbr 782 * 8:grb rgb, 9:grb brg, 10:grb gbr 783 * yuv output:0:yuyv, 1: yvyu, 2:uyvy, 3:vyuy 784 * @fdelay:yuv eav/sav F line delay 785 * 0: F toggle right after active video line 786 * 1: delay 2 line(CCIR NTSC) 787 * 2: delay 3 line(CCIR PAL) 788 * @clk_phase:clk phase 789 * 0: 0 degree, 1:90 degree, 2: 180 degree, 3:270 degree 790 * @sync_polarity:sync signals polarity 791 * 0: vsync active low,hsync active low 792 * 1: vsync active high,hsync active low 793 * 2: vsync active low,hsync active high 794 * 3: vsync active high,hsync active high 795 */ 796 struct disp_vdevice_interface_para { 797 unsigned int intf; 798 unsigned int sub_intf; 799 unsigned int sequence; 800 unsigned int fdelay; 801 unsigned int clk_phase; 802 unsigned int sync_polarity; 803 unsigned int ccir_clk_div; 804 unsigned int input_csc;/*not need to config for user*/ 805 }; 806 807 struct disp_vdevice_source_ops { 808 int (*tcon_enable)(struct disp_device *dispdev); 809 int (*tcon_disable)(struct disp_device *dispdev); 810 int (*tcon_simple_enable)(struct disp_device *dispdev); 811 int (*tcon_simple_disable)(struct disp_device *dispdev); 812 }; 813 814 struct disp_device_func { 815 int (*enable)(void); 816 int (*smooth_enable)(void); 817 int (*disable)(void); 818 int (*set_mode)(u32 mode); 819 int (*mode_support)(u32 mode); 820 int (*get_HPD_status)(void); 821 int (*get_input_csc)(void); 822 int (*get_input_color_range)(void); 823 int (*get_video_timing_info)(struct disp_video_timings **video_info); 824 int (*suspend)(void); 825 int (*resume)(void); 826 int (*early_suspend)(void); 827 int (*late_resume)(void); 828 int (*get_interface_para)(void *para); 829 int (*set_static_config)(struct disp_device_config *config); 830 int (*get_static_config)(struct disp_device_config *config); 831 int (*set_dynamic_config)(struct disp_device_dynamic_config *config); 832 int (*get_dynamic_config)(struct disp_device_dynamic_config *config); 833 834 /*for hdmi cec*/ 835 s32 (*cec_standby_request)(void); 836 s32 (*cec_send_one_touch_play)(void); 837 }; 838 839 struct disp_vdevice_init_data { 840 char name[32]; 841 u32 disp; 842 u32 fix_timing; 843 enum disp_output_type type; 844 struct disp_device_func func; 845 }; 846 847 enum disp_tv_dac_source { 848 DISP_TV_DAC_SRC_COMPOSITE = 0, 849 DISP_TV_DAC_SRC_LUMA = 1, 850 DISP_TV_DAC_SRC_CHROMA = 2, 851 DISP_TV_DAC_SRC_Y = 4, 852 DISP_TV_DAC_SRC_PB = 5, 853 DISP_TV_DAC_SRC_PR = 6, 854 DISP_TV_DAC_SRC_NONE = 7, 855 }; 856 857 enum disp_tv_output { 858 DISP_TV_NONE = 0, 859 DISP_TV_CVBS = 1, 860 DISP_TV_YPBPR = 2, 861 DISP_TV_SVIDEO = 4, 862 DISP_VGA = 5, 863 }; 864 865 enum tag_DISP_CMD { 866 /* ----disp global---- */ 867 DISP_RESERVE0 = 0x00, 868 DISP_RESERVE1 = 0x01, 869 DISP_SET_BKCOLOR = 0x03, 870 DISP_GET_BKCOLOR = 0x04, 871 DISP_SET_COLORKEY = 0x05, 872 DISP_GET_COLORKEY = 0x06, 873 DISP_GET_SCN_WIDTH = 0x07, 874 DISP_GET_SCN_HEIGHT = 0x08, 875 DISP_GET_OUTPUT_TYPE = 0x09, 876 DISP_SET_EXIT_MODE = 0x0A, 877 DISP_VSYNC_EVENT_EN = 0x0B, 878 DISP_BLANK = 0x0C, 879 DISP_SHADOW_PROTECT = 0x0D, 880 DISP_HWC_COMMIT = 0x0E, 881 DISP_DEVICE_SWITCH = 0x0F, 882 DISP_GET_OUTPUT = 0x10, 883 DISP_SET_COLOR_RANGE = 0x11, 884 DISP_GET_COLOR_RANGE = 0x12, 885 DISP_HWC_CUSTOM = 0x13, 886 DISP_DEVICE_SET_CONFIG = 0x14, 887 DISP_DEVICE_GET_CONFIG = 0x15, 888 DISP_SET_KSC_PARA = 0x16, 889 DISP_RTWB_COMMIT = 0x17, 890 DISP_GET_VSYNC_TIMESTAMP = 0x18, 891 DISP_NODE_LCD_MESSAGE_REQUEST = 0x19, 892 DISP_RELOAD_LCD = 0x20, 893 894 /* ----layer---- */ 895 DISP_LAYER_ENABLE = 0x40, 896 DISP_LAYER_DISABLE = 0x41, 897 DISP_LAYER_SET_INFO = 0x42, 898 DISP_LAYER_GET_INFO = 0x43, 899 DISP_LAYER_TOP = 0x44, 900 DISP_LAYER_BOTTOM = 0x45, 901 DISP_LAYER_GET_FRAME_ID = 0x46, 902 DISP_LAYER_SET_CONFIG = 0x47, 903 DISP_LAYER_GET_CONFIG = 0x48, 904 /* 905 * LAYER_S(G)ET_CONFIG2 takes disp_layer_config2, 906 * it will support more featuras 907 */ 908 DISP_LAYER_SET_CONFIG2 = 0x49, 909 DISP_LAYER_GET_CONFIG2 = 0x4a, 910 DISP_CHN_SET_PALETTE = 0x4b, 911 912 /* ----hdmi---- */ 913 DISP_HDMI_SUPPORT_MODE = 0xc4, 914 DISP_SET_TV_HPD = 0xc5, 915 DISP_HDMI_GET_EDID = 0xc6, 916 DISP_CEC_ONE_TOUCH_PLAY = 0xc7, 917 918 /* ----lcd---- */ 919 DISP_LCD_ENABLE = 0x100, 920 DISP_LCD_DISABLE = 0x101, 921 DISP_LCD_SET_BRIGHTNESS = 0x102, 922 DISP_LCD_GET_BRIGHTNESS = 0x103, 923 DISP_LCD_BACKLIGHT_ENABLE = 0x104, 924 DISP_LCD_BACKLIGHT_DISABLE = 0x105, 925 DISP_LCD_SET_SRC = 0x106, 926 DISP_LCD_SET_FPS = 0x107, 927 DISP_LCD_GET_FPS = 0x108, 928 DISP_LCD_GET_SIZE = 0x109, 929 DISP_LCD_GET_MODEL_NAME = 0x10a, 930 DISP_LCD_SET_GAMMA_TABLE = 0x10b, 931 DISP_LCD_GAMMA_CORRECTION_ENABLE = 0x10c, 932 DISP_LCD_GAMMA_CORRECTION_DISABLE = 0x10d, 933 DISP_LCD_USER_DEFINED_FUNC = 0x10e, 934 DISP_LCD_CHECK_OPEN_FINISH = 0x10f, 935 DISP_LCD_CHECK_CLOSE_FINISH = 0x110, 936 937 /*tv*/ 938 DISP_TV_SET_GAMMA_TABLE = 0x111, 939 /* ---- capture --- */ 940 DISP_CAPTURE_START = 0x140,/* caputre screen and scaler to dram */ 941 DISP_CAPTURE_STOP = 0x141, 942 DISP_CAPTURE_COMMIT = 0x142, 943 DISP_CAPTURE_COMMIT2 = 0x143, 944 DISP_CAPTURE_QUERY = 0x144, 945 DISP_CAPTURE_EXTEND = 0x145, 946 947 /* ---enhance --- */ 948 DISP_ENHANCE_ENABLE = 0x180, 949 DISP_ENHANCE_DISABLE = 0x181, 950 DISP_ENHANCE_GET_EN = 0x182, 951 DISP_ENHANCE_SET_WINDOW = 0x183, 952 DISP_ENHANCE_GET_WINDOW = 0x184, 953 DISP_ENHANCE_SET_MODE = 0x185, 954 DISP_ENHANCE_GET_MODE = 0x186, 955 DISP_ENHANCE_DEMO_ENABLE = 0x187, 956 DISP_ENHANCE_DEMO_DISABLE = 0x188, 957 958 /* ---smart backlight --- */ 959 DISP_SMBL_ENABLE = 0x200, 960 DISP_SMBL_DISABLE = 0x201, 961 DISP_SMBL_GET_EN = 0x202, 962 DISP_SMBL_SET_WINDOW = 0x203, 963 DISP_SMBL_GET_WINDOW = 0x204, 964 965 /* ---- for test */ 966 DISP_FB_REQUEST = 0x280, 967 DISP_FB_RELEASE = 0x281, 968 969 DISP_MEM_REQUEST = 0x2c0, 970 DISP_MEM_RELEASE = 0x2c1, 971 DISP_MEM_GETADR = 0x2c2, 972 DISP_VDPO_SET_CONFIG = 0x2c3, 973 974 DISP_EINK_UPDATE = 0x402, 975 DISP_EINK_SET_TEMP = 0x403, 976 DISP_EINK_GET_TEMP = 0x404, 977 DISP_EINK_OVERLAP_SKIP = 0x405, 978 DISP_EINK_UPDATE2 = 0x406, 979 }; 980 981 enum { 982 ROTATION_SW_0 = 0, 983 ROTATION_SW_90 = 1, 984 ROTATION_SW_180 = 2, 985 ROTATION_SW_270 = 3, 986 }; 987 988 /* struct disp_ksc_info - keystone correction struct 989 * 990 * @enable: 1:enable; 0:disable 991 * @first_line_width: the width in pixel of first line you want 992 * @ration: ration is 12-bit Fixed point decimal with 5-bit interger (<= 256) 993 * direction = 0: 994 * last_line_width = first_line_width + (lcd_y-1)*ration_double 995 * ration_double = (last_line_width - first_line_width) / (lcd_y -1) 996 * direction = 1: 997 * last_line_width = first_line_width - (lcd_y-1)*ration_double 998 * ration_double = (first_line_width - last_line_width) / (lcd_y -1) 999 * ration = int(ration_double * pow(2, 12)) 1000 * @direction: see above 1001 * 1002 */ 1003 struct disp_ksc_info { 1004 unsigned int enable; 1005 unsigned int first_line_width; 1006 unsigned int ration; 1007 unsigned int direction; 1008 }; 1009 1010 struct disp_vsync_timestame { 1011 int disp; 1012 int64_t timestamp; 1013 }; 1014 1015 #define FBIOGET_LAYER_HDL_0 0x4700 1016 #define FBIOGET_LAYER_HDL_1 0x4701 1017 1018 #endif 1019