1 /*
2 * Linux DHD Bus Module for PCIE
3 *
4 * Copyright (C) 1999-2019, Broadcom.
5 *
6 * Unless you and Broadcom execute a separate written software license
7 * agreement governing use of this software, this software is licensed to you
8 * under the terms of the GNU General Public License version 2 (the "GPL"),
9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the
10 * following added to such license:
11 *
12 * As a special exception, the copyright holders of this software give you
13 * permission to link this software with independent modules, and to copy and
14 * distribute the resulting executable under terms of your choice, provided that
15 * you also meet, for each linked independent module, the terms and conditions
16 * of the license of that module. An independent module is a module which is
17 * not derived from this software. The special exception does not apply to any
18 * modifications of the software.
19 *
20 * Notwithstanding the above, under no circumstances may you combine this
21 * software in any way with any other Broadcom software provided under a license
22 * other than the GPL, without Broadcom's express prior written consent.
23 *
24 *
25 * <<Broadcom-WL-IPTag/Open:>>
26 *
27 * $Id: dhd_pcie.h 816392 2019-04-24 14:39:02Z $
28 */
29
30 #ifndef dhd_pcie_h
31 #define dhd_pcie_h
32
33 #include <bcmpcie.h>
34 #include <hnd_cons.h>
35 #include <dhd_linux.h>
36
37 /* defines */
38 #define PCIE_SHARED_VERSION PCIE_SHARED_VERSION_7
39
40 #define PCMSGBUF_HDRLEN 0
41 #define DONGLE_REG_MAP_SIZE (32 * 1024)
42 #define DONGLE_TCM_MAP_SIZE (4096 * 1024)
43 #define DONGLE_MIN_MEMSIZE (128 * 1024)
44 #ifdef DHD_DEBUG
45 #define DHD_PCIE_SUCCESS 0
46 #define DHD_PCIE_FAILURE 1
47 #endif /* DHD_DEBUG */
48 #define REMAP_ENAB(bus) ((bus)->remap)
49 #define REMAP_ISADDR(bus, a) \
50 (((a) >= ((bus)->orig_ramsize)) && ((a) < ((bus)->ramsize)))
51
52 #define MAX_DHD_TX_FLOWS 320
53
54 /* user defined data structures */
55 /* Device console log buffer state */
56 #define CONSOLE_LINE_MAX 192u
57 #define CONSOLE_BUFFER_MAX (8 * 1024)
58
59 #ifdef IDLE_TX_FLOW_MGMT
60 #define IDLE_FLOW_LIST_TIMEOUT 5000
61 #define IDLE_FLOW_RING_TIMEOUT 5000
62 #endif /* IDLE_TX_FLOW_MGMT */
63
64 /* HWA enabled and inited */
65 #define HWA_ACTIVE(dhd) (((dhd)->hwa_enable) && ((dhd)->hwa_inited))
66
67 /* implicit DMA for h2d wr and d2h rd indice from Host memory to TCM */
68 #define IDMA_ENAB(dhd) ((dhd)->idma_enable)
69 #define IDMA_ACTIVE(dhd) (((dhd)->idma_enable) && ((dhd)->idma_inited))
70
71 #define IDMA_CAPABLE(bus) \
72 (((bus)->sih->buscorerev == 19) || ((bus)->sih->buscorerev >= 23))
73
74 /* IFRM (Implicit Flow Ring Manager enable and inited */
75 #define IFRM_ENAB(dhd) ((dhd)->ifrm_enable)
76 #define IFRM_ACTIVE(dhd) (((dhd)->ifrm_enable) && ((dhd)->ifrm_inited))
77
78 /* DAR registers use for h2d doorbell */
79 #define DAR_ENAB(dhd) ((dhd)->dar_enable)
80 #define DAR_ACTIVE(dhd) (((dhd)->dar_enable) && ((dhd)->dar_inited))
81
82 /* DAR WAR for revs < 64 */
83 #define DAR_PWRREQ(bus) (((bus)->_dar_war) && DAR_ACTIVE((bus)->dhd))
84
85 /* PCIE CTO Prevention and Recovery */
86 #define PCIECTO_ENAB(bus) ((bus)->cto_enable)
87
88 /* Implicit DMA index usage :
89 * Index 0 for h2d write index transfer
90 * Index 1 for d2h read index transfer
91 */
92 #define IDMA_IDX0 0
93 #define IDMA_IDX1 1
94 #define IDMA_IDX2 2
95 #define IDMA_IDX3 3
96 #define DMA_TYPE_SHIFT 4
97 #define DMA_TYPE_IDMA 1
98
99 #define DHDPCIE_CONFIG_HDR_SIZE 16
100 #define DHDPCIE_CONFIG_CHECK_DELAY_MS 10 /* 10ms */
101 #define DHDPCIE_CONFIG_CHECK_RETRY_COUNT 20
102 #define DHDPCIE_DONGLE_PWR_TOGGLE_DELAY 1000 /* 1ms in units of us */
103 #define DHDPCIE_PM_D3_DELAY 200000 /* 200ms in units of us */
104 #define DHDPCIE_PM_D2_DELAY 200 /* 200us */
105
106 typedef struct dhd_console {
107 uint count; /* Poll interval msec counter */
108 uint log_addr; /* Log struct address (fixed) */
109 hnd_log_t log; /* Log struct (host copy) */
110 uint bufsize; /* Size of log buffer */
111 uint8 *buf; /* Log buffer (host copy) */
112 uint last; /* Last buffer read index */
113 } dhd_console_t;
114
115 typedef struct ring_sh_info {
116 uint32 ring_mem_addr;
117 uint32 ring_state_w;
118 uint32 ring_state_r;
119 } ring_sh_info_t;
120
121 #define DEVICE_WAKE_NONE 0
122 #define DEVICE_WAKE_OOB 1
123 #define DEVICE_WAKE_INB 2
124
125 #define INBAND_DW_ENAB(bus) ((bus)->dw_option == DEVICE_WAKE_INB)
126 #define OOB_DW_ENAB(bus) ((bus)->dw_option == DEVICE_WAKE_OOB)
127 #define NO_DW_ENAB(bus) ((bus)->dw_option == DEVICE_WAKE_NONE)
128
129 #define PCIE_RELOAD_WAR_ENAB(buscorerev) \
130 ((buscorerev == 66) || (buscorerev == 67) || (buscorerev == 68) || \
131 (buscorerev == 70))
132
133 /*
134 * HW JIRA - CRWLPCIEGEN2-672
135 * Producer Index Feature which is used by F1 gets reset on F0 FLR
136 * fixed in REV68
137 */
138 #define PCIE_ENUM_RESET_WAR_ENAB(buscorerev) \
139 ((buscorerev == 66) || (buscorerev == 67))
140
141 struct dhd_bus;
142
143 struct dhd_pcie_rev {
144 uint8 fw_rev;
145 void (*handle_mb_data)(struct dhd_bus *);
146 };
147
148 typedef struct dhdpcie_config_save {
149 uint32 header[DHDPCIE_CONFIG_HDR_SIZE];
150 /* pmcsr save */
151 uint32 pmcsr;
152 /* express save */
153 uint32 exp_dev_ctrl_stat;
154 uint32 exp_link_ctrl_stat;
155 uint32 exp_dev_ctrl_stat2;
156 uint32 exp_link_ctrl_stat2;
157 /* msi save */
158 uint32 msi_cap;
159 uint32 msi_addr0;
160 uint32 msi_addr1;
161 uint32 msi_data;
162 /* l1pm save */
163 uint32 l1pm0;
164 uint32 l1pm1;
165 /* ltr save */
166 uint32 ltr;
167 /* aer save */
168 uint32 aer_caps_ctrl; /* 0x18 */
169 uint32 aer_severity; /* 0x0C */
170 uint32 aer_umask; /* 0x08 */
171 uint32 aer_cmask; /* 0x14 */
172 uint32 aer_root_cmd; /* 0x2c */
173 /* BAR0 and BAR1 windows */
174 uint32 bar0_win;
175 uint32 bar1_win;
176 } dhdpcie_config_save_t;
177
178 /* The level of bus communication with the dongle */
179 enum dhd_bus_low_power_state {
180 DHD_BUS_NO_LOW_POWER_STATE, /* Not in low power state */
181 DHD_BUS_D3_INFORM_SENT, /* D3 INFORM sent */
182 DHD_BUS_D3_ACK_RECIEVED, /* D3 ACK recieved */
183 };
184
185 /** Instantiated once for each hardware (dongle) instance that this DHD manages
186 */
187 typedef struct dhd_bus {
188 dhd_pub_t *dhd; /**< pointer to per hardware (dongle) unique instance */
189 struct pci_dev *rc_dev; /* pci RC device handle */
190 struct pci_dev *dev; /* pci device handle */
191
192 dll_t flowring_active_list; /* constructed list of tx flowring queues */
193 #ifdef IDLE_TX_FLOW_MGMT
194 uint64 active_list_last_process_ts;
195 /* stores the timestamp of active list processing */
196 #endif /* IDLE_TX_FLOW_MGMT */
197
198 si_t *sih; /* Handle for SI calls */
199 char *vars; /* Variables (from CIS and/or other) */
200 uint varsz; /* Size of variables buffer */
201 uint32 sbaddr; /* Current SB window pointer (-1, invalid) */
202 sbpcieregs_t *reg; /* Registers for PCIE core */
203
204 uint armrev; /* CPU core revision */
205 uint coreid; /* CPU core id */
206 uint ramrev; /* SOCRAM core revision */
207 uint32 ramsize; /* Size of RAM in SOCRAM (bytes) */
208 uint32 orig_ramsize; /* Size of RAM in SOCRAM (bytes) */
209 bool ramsize_adjusted; /* flag to note adjustment, so that
210 * adjustment routine and file io
211 * are avoided on D3 cold -> D0
212 */
213 uint32 srmemsize; /* Size of SRMEM */
214
215 uint32 bus; /* gSPI or SDIO bus */
216 uint32 bus_num; /* bus number */
217 uint32 slot_num; /* slot ID */
218 uint32 intstatus; /* Intstatus bits (events) pending */
219 bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */
220 bool fcstate; /* State of dongle flow-control */
221
222 uint16 cl_devid; /* cached devid for dhdsdio_probe_attach() */
223 char *fw_path; /* module_param: path to firmware image */
224 char *nv_path; /* module_param: path to nvram vars file */
225
226 struct pktq txq; /* Queue length used for flow-control */
227
228 bool intr; /* Use interrupts */
229 bool poll; /* Use polling */
230 bool ipend; /* Device interrupt is pending */
231 bool intdis; /* Interrupts disabled by isr */
232 uint intrcount; /* Count of device interrupt callbacks */
233 uint lastintrs; /* Count as of last watchdog timer */
234
235 dhd_console_t console; /* Console output polling support */
236 uint console_addr; /* Console address from shared struct */
237
238 bool alp_only; /* Don't use HT clock (ALP only) */
239
240 bool remap; /* Contiguous 1MB RAM: 512K socram + 512K devram
241 * Available with socram rev 16
242 * Remap region not DMA-able
243 */
244 uint32 resetinstr;
245 uint32 dongle_ram_base;
246
247 ulong shared_addr;
248 pciedev_shared_t *pcie_sh;
249 uint32 dma_rxoffset;
250 volatile char *regs; /* pci device memory va */
251 volatile char *tcm; /* pci device memory va */
252 osl_t *osh;
253 uint32 nvram_csm; /* Nvram checksum */
254 uint16 pollrate;
255 uint16 polltick;
256
257 volatile uint32 *pcie_mb_intr_addr;
258 volatile uint32 *pcie_mb_intr_2_addr;
259 void *pcie_mb_intr_osh;
260 bool sleep_allowed;
261
262 wake_counts_t wake_counts;
263
264 /* version 3 shared struct related info start */
265 ring_sh_info_t ring_sh[BCMPCIE_COMMON_MSGRINGS + MAX_DHD_TX_FLOWS];
266
267 uint8 h2d_ring_count;
268 uint8 d2h_ring_count;
269 uint32 ringmem_ptr;
270 uint32 ring_state_ptr;
271
272 uint32 d2h_dma_scratch_buffer_mem_addr;
273
274 uint32 h2d_mb_data_ptr_addr;
275 uint32 d2h_mb_data_ptr_addr;
276 /* version 3 shared struct related info end */
277
278 uint32 def_intmask;
279 uint32 d2h_mb_mask;
280 uint32 pcie_mailbox_mask;
281 uint32 pcie_mailbox_int;
282 bool ltrsleep_on_unload;
283 uint wait_for_d3_ack;
284 uint16 max_tx_flowrings;
285 uint16 max_submission_rings;
286 uint16 max_completion_rings;
287 uint16 max_cmn_rings;
288 uint32 rw_index_sz;
289 bool db1_for_mb;
290
291 dhd_timeout_t doorbell_timer;
292 bool device_wake_state;
293 bool irq_registered;
294 bool d2h_intr_method;
295 int32 idletime; /* Control for activity timeout */
296 uint32 d3_inform_cnt;
297 uint32 d0_inform_cnt;
298 uint32 d0_inform_in_use_cnt;
299 uint8 force_suspend;
300 uint8 is_linkdown;
301 uint8 no_bus_init;
302 #ifdef IDLE_TX_FLOW_MGMT
303 bool enable_idle_flowring_mgmt;
304 #endif /* IDLE_TX_FLOW_MGMT */
305 struct dhd_pcie_rev api;
306 bool use_mailbox;
307 bool use_d0_inform;
308 void *bus_lock;
309 void *backplane_access_lock;
310 enum dhd_bus_low_power_state bus_low_power_state;
311 uint32 hostready_count; /* Number of hostready issued */
312 #if defined(BCMPCIE_OOB_HOST_WAKE)
313 bool oob_presuspend;
314 #endif // endif
315 dhdpcie_config_save_t saved_config;
316 ulong resume_intr_enable_count;
317 ulong dpc_intr_enable_count;
318 ulong isr_intr_disable_count;
319 ulong suspend_intr_disable_count;
320 ulong dpc_return_busdown_count;
321 ulong non_ours_irq_count;
322 #ifdef BCMPCIE_OOB_HOST_WAKE
323 ulong oob_intr_count;
324 ulong oob_intr_enable_count;
325 ulong oob_intr_disable_count;
326 uint64 last_oob_irq_time;
327 uint64 last_oob_irq_enable_time;
328 uint64 last_oob_irq_disable_time;
329 #endif /* BCMPCIE_OOB_HOST_WAKE */
330 uint64 isr_entry_time;
331 uint64 isr_exit_time;
332 uint64 dpc_sched_time;
333 uint64 dpc_entry_time;
334 uint64 dpc_exit_time;
335 uint64 resched_dpc_time;
336 uint64 last_d3_inform_time;
337 uint64 last_process_ctrlbuf_time;
338 uint64 last_process_flowring_time;
339 uint64 last_process_txcpl_time;
340 uint64 last_process_rxcpl_time;
341 uint64 last_process_infocpl_time;
342 uint64 last_process_edl_time;
343 uint64 last_suspend_start_time;
344 uint64 last_suspend_end_time;
345 uint64 last_resume_start_time;
346 uint64 last_resume_end_time;
347 uint64 last_non_ours_irq_time;
348 uint8 hwa_enab_bmap;
349 bool idma_enabled;
350 bool ifrm_enabled;
351 bool dar_enabled;
352 uint32 dmaxfer_complete;
353 uint8 dw_option;
354 bool _dar_war;
355 uint8 dma_chan;
356 bool cto_enable; /* enable PCIE CTO Prevention and recovery */
357 uint32 cto_threshold; /* PCIE CTO timeout threshold */
358 bool cto_triggered; /* CTO is triggered */
359 int pwr_req_ref;
360 bool flr_force_fail; /* user intends to simulate flr force fail */
361 bool intr_enabled; /* ready to receive interrupts from dongle */
362 bool force_bt_quiesce; /* send bt_quiesce command to BT driver. */
363 #if defined(DHD_H2D_LOG_TIME_SYNC)
364 ulong dhd_rte_time_sync_count; /* OSL_SYSUPTIME_US() */
365 #endif /* DHD_H2D_LOG_TIME_SYNC */
366 bool rc_ep_aspm_cap; /* RC and EP ASPM capable */
367 bool rc_ep_l1ss_cap; /* EC and EP L1SS capable */
368 uint16 hp2p_txcpl_max_items;
369 uint16 hp2p_rxcpl_max_items;
370 /* PCIE coherent status */
371 uint32 coherent_state;
372 } dhd_bus_t;
373
374 #ifdef DHD_MSI_SUPPORT
375 extern uint enable_msi;
376 #endif /* DHD_MSI_SUPPORT */
377
378 enum { PCIE_INTX = 0, PCIE_MSI = 1 };
379
380 /* function declarations */
381
382 extern uint32 *dhdpcie_bus_reg_map(osl_t *osh, ulong addr, int size);
383 extern int dhdpcie_bus_register(void);
384 extern void dhdpcie_bus_unregister(void);
385 extern bool dhdpcie_chipmatch(uint16 vendor, uint16 device);
386
387 extern int dhdpcie_bus_attach(osl_t *osh, dhd_bus_t **bus_ptr,
388 volatile char *regs, volatile char *tcm,
389 void *pci_dev, wifi_adapter_info_t *adapter);
390 extern uint32 dhdpcie_bus_cfg_read_dword(struct dhd_bus *bus, uint32 addr,
391 uint32 size);
392 extern void dhdpcie_bus_cfg_write_dword(struct dhd_bus *bus, uint32 addr,
393 uint32 size, uint32 data);
394 extern void dhdpcie_bus_intr_enable(struct dhd_bus *bus);
395 extern void dhdpcie_bus_intr_disable(struct dhd_bus *bus);
396 extern int dhpcie_bus_mask_interrupt(dhd_bus_t *bus);
397 extern void dhdpcie_bus_release(struct dhd_bus *bus);
398 extern int32 dhdpcie_bus_isr(struct dhd_bus *bus);
399 extern void dhdpcie_free_irq(dhd_bus_t *bus);
400 extern void dhdpcie_bus_ringbell_fast(struct dhd_bus *bus, uint32 value);
401 extern void dhdpcie_bus_ringbell_2_fast(struct dhd_bus *bus, uint32 value,
402 bool devwake);
403 extern void dhdpcie_dongle_reset(dhd_bus_t *bus);
404 #ifdef DHD_PCIE_NATIVE_RUNTIMEPM
405 extern int dhdpcie_bus_suspend(struct dhd_bus *bus, bool state, bool byint);
406 #else
407 extern int dhdpcie_bus_suspend(struct dhd_bus *bus, bool state);
408 #endif /* DHD_PCIE_NATIVE_RUNTIMEPM */
409 extern int dhdpcie_pci_suspend_resume(struct dhd_bus *bus, bool state);
410 extern uint32 dhdpcie_force_alp(struct dhd_bus *bus, bool enable);
411 extern uint32 dhdpcie_set_l1_entry_time(struct dhd_bus *bus,
412 int force_l1_entry_time);
413 extern bool dhdpcie_tcm_valid(dhd_bus_t *bus);
414 extern void dhdpcie_pme_active(osl_t *osh, bool enable);
415 extern bool dhdpcie_pme_cap(osl_t *osh);
416 extern uint32 dhdpcie_lcreg(osl_t *osh, uint32 mask, uint32 val);
417 extern void dhdpcie_set_pmu_min_res_mask(struct dhd_bus *bus,
418 uint min_res_mask);
419 extern uint8 dhdpcie_clkreq(osl_t *osh, uint32 mask, uint32 val);
420 extern int dhdpcie_disable_irq(dhd_bus_t *bus);
421 extern int dhdpcie_disable_irq_nosync(dhd_bus_t *bus);
422 extern int dhdpcie_enable_irq(dhd_bus_t *bus);
423
424 extern void dhd_bus_dump_dar_registers(struct dhd_bus *bus);
425
426 extern uint32 dhdpcie_rc_config_read(dhd_bus_t *bus, uint offset);
427 extern uint32 dhdpcie_rc_access_cap(dhd_bus_t *bus, int cap, uint offset,
428 bool is_ext, bool is_write,
429 uint32 writeval);
430 extern uint32 dhdpcie_ep_access_cap(dhd_bus_t *bus, int cap, uint offset,
431 bool is_ext, bool is_write,
432 uint32 writeval);
433 extern uint32 dhd_debug_get_rc_linkcap(dhd_bus_t *bus);
434 extern int dhdpcie_start_host_pcieclock(dhd_bus_t *bus);
435 extern int dhdpcie_stop_host_pcieclock(dhd_bus_t *bus);
436 extern int dhdpcie_disable_device(dhd_bus_t *bus);
437 extern int dhdpcie_alloc_resource(dhd_bus_t *bus);
438 extern void dhdpcie_free_resource(dhd_bus_t *bus);
439 extern void dhdpcie_dump_resource(dhd_bus_t *bus);
440 extern int dhdpcie_bus_request_irq(struct dhd_bus *bus);
441 void dhdpcie_os_setbar1win(dhd_bus_t *bus, uint32 addr);
442 void dhdpcie_os_wtcm8(dhd_bus_t *bus, ulong offset, uint8 data);
443 uint8 dhdpcie_os_rtcm8(dhd_bus_t *bus, ulong offset);
444 void dhdpcie_os_wtcm16(dhd_bus_t *bus, ulong offset, uint16 data);
445 uint16 dhdpcie_os_rtcm16(dhd_bus_t *bus, ulong offset);
446 void dhdpcie_os_wtcm32(dhd_bus_t *bus, ulong offset, uint32 data);
447 uint32 dhdpcie_os_rtcm32(dhd_bus_t *bus, ulong offset);
448 #ifdef DHD_SUPPORT_64BIT
449 void dhdpcie_os_wtcm64(dhd_bus_t *bus, ulong offset, uint64 data);
450 uint64 dhdpcie_os_rtcm64(dhd_bus_t *bus, ulong offset);
451 #endif // endif
452
453 extern int dhdpcie_enable_device(dhd_bus_t *bus);
454
455 #ifdef BCMPCIE_OOB_HOST_WAKE
456 extern int dhdpcie_oob_intr_register(dhd_bus_t *bus);
457 extern void dhdpcie_oob_intr_unregister(dhd_bus_t *bus);
458 extern void dhdpcie_oob_intr_set(dhd_bus_t *bus, bool enable);
459 extern int dhdpcie_get_oob_irq_num(struct dhd_bus *bus);
460 extern int dhdpcie_get_oob_irq_status(struct dhd_bus *bus);
461 extern int dhdpcie_get_oob_irq_level(void);
462 #endif /* BCMPCIE_OOB_HOST_WAKE */
463
464 #if defined(CONFIG_ARCH_EXYNOS)
465 #define SAMSUNG_PCIE_VENDOR_ID 0x144d
466 #if defined(CONFIG_MACH_UNIVERSAL7420) || defined(CONFIG_SOC_EXYNOS7420)
467 #define SAMSUNG_PCIE_DEVICE_ID 0xa575
468 #define SAMSUNG_PCIE_CH_NUM 1
469 #elif defined(CONFIG_SOC_EXYNOS8890)
470 #define SAMSUNG_PCIE_DEVICE_ID 0xa544
471 #define SAMSUNG_PCIE_CH_NUM 0
472 #elif defined(CONFIG_SOC_EXYNOS8895) || defined(CONFIG_SOC_EXYNOS9810) || \
473 defined(CONFIG_SOC_EXYNOS9820)
474 #define SAMSUNG_PCIE_DEVICE_ID 0xecec
475 #define SAMSUNG_PCIE_CH_NUM 0
476 #else
477 #error "Not supported platform"
478 #endif /* CONFIG_SOC_EXYNOSXXXX & CONFIG_MACH_UNIVERSALXXXX */
479 #endif /* CONFIG_ARCH_EXYNOS */
480
481 #if defined(CONFIG_ARCH_MSM)
482 #define MSM_PCIE_VENDOR_ID 0x17cb
483 #if defined(CONFIG_ARCH_APQ8084)
484 #define MSM_PCIE_DEVICE_ID 0x0101
485 #elif defined(CONFIG_ARCH_MSM8994)
486 #define MSM_PCIE_DEVICE_ID 0x0300
487 #elif defined(CONFIG_ARCH_MSM8996)
488 #define MSM_PCIE_DEVICE_ID 0x0104
489 #elif defined(CONFIG_ARCH_MSM8998)
490 #define MSM_PCIE_DEVICE_ID 0x0105
491 #elif defined(CONFIG_ARCH_SDM845) || defined(CONFIG_ARCH_SM8150)
492 #define MSM_PCIE_DEVICE_ID 0x0106
493 #else
494 #error "Not supported platform"
495 #endif // endif
496 #endif /* CONFIG_ARCH_MSM */
497
498 #if defined(CONFIG_X86)
499 #define X86_PCIE_VENDOR_ID 0x8086
500 #define X86_PCIE_DEVICE_ID 0x9c1a
501 #endif /* CONFIG_X86 */
502
503 #if defined(CONFIG_ARCH_TEGRA)
504 #define TEGRA_PCIE_VENDOR_ID 0x14e4
505 #define TEGRA_PCIE_DEVICE_ID 0x4347
506 #endif /* CONFIG_ARCH_TEGRA */
507
508 #define HIKEY_PCIE_VENDOR_ID 0x19e5
509 #define HIKEY_PCIE_DEVICE_ID 0x3660
510
511 #define DUMMY_PCIE_VENDOR_ID 0xffff
512 #define DUMMY_PCIE_DEVICE_ID 0xffff
513
514 #if defined(CONFIG_ARCH_EXYNOS)
515 #define PCIE_RC_VENDOR_ID SAMSUNG_PCIE_VENDOR_ID
516 #define PCIE_RC_DEVICE_ID SAMSUNG_PCIE_DEVICE_ID
517 #elif defined(CONFIG_ARCH_MSM)
518 #define PCIE_RC_VENDOR_ID MSM_PCIE_VENDOR_ID
519 #define PCIE_RC_DEVICE_ID MSM_PCIE_DEVICE_ID
520 #elif defined(CONFIG_X86)
521 #define PCIE_RC_VENDOR_ID X86_PCIE_VENDOR_ID
522 #define PCIE_RC_DEVICE_ID X86_PCIE_DEVICE_ID
523 #elif defined(CONFIG_ARCH_TEGRA)
524 #define PCIE_RC_VENDOR_ID TEGRA_PCIE_VENDOR_ID
525 #define PCIE_RC_DEVICE_ID TEGRA_PCIE_DEVICE_ID
526 #else
527 #define PCIE_RC_VENDOR_ID HIKEY_PCIE_VENDOR_ID
528 #define PCIE_RC_DEVICE_ID HIKEY_PCIE_DEVICE_ID
529 #endif /* CONFIG_ARCH_EXYNOS */
530
531 #define DHD_REGULAR_RING 0
532 #define DHD_HP2P_RING 1
533
534 #ifdef USE_EXYNOS_PCIE_RC_PMPATCH
535 extern int exynos_pcie_pm_suspend(int ch_num);
536 extern int exynos_pcie_pm_resume(int ch_num);
537 #endif /* USE_EXYNOS_PCIE_RC_PMPATCH */
538
539 #ifdef CONFIG_ARCH_TEGRA
540 extern int tegra_pcie_pm_suspend(void);
541 extern int tegra_pcie_pm_resume(void);
542 #endif /* CONFIG_ARCH_TEGRA */
543
544 extern int dhd_buzzz_dump_dngl(dhd_bus_t *bus);
545 #ifdef IDLE_TX_FLOW_MGMT
546 extern int dhd_bus_flow_ring_resume_request(struct dhd_bus *bus, void *arg);
547 extern void dhd_bus_flow_ring_resume_response(struct dhd_bus *bus,
548 uint16 flowid, int32 status);
549 extern int dhd_bus_flow_ring_suspend_request(struct dhd_bus *bus, void *arg);
550 extern void dhd_bus_flow_ring_suspend_response(struct dhd_bus *bus,
551 uint16 flowid, uint32 status);
552 extern void
553 dhd_flow_ring_move_to_active_list_head(struct dhd_bus *bus,
554 flow_ring_node_t *flow_ring_node);
555 extern void dhd_flow_ring_add_to_active_list(struct dhd_bus *bus,
556 flow_ring_node_t *flow_ring_node);
557 extern void
558 dhd_flow_ring_delete_from_active_list(struct dhd_bus *bus,
559 flow_ring_node_t *flow_ring_node);
560 extern void
561 __dhd_flow_ring_delete_from_active_list(struct dhd_bus *bus,
562 flow_ring_node_t *flow_ring_node);
563 #endif /* IDLE_TX_FLOW_MGMT */
564
565 extern int dhdpcie_send_mb_data(dhd_bus_t *bus, uint32 h2d_mb_data);
566
567 #ifdef DHD_WAKE_STATUS
568 int bcmpcie_get_total_wake(struct dhd_bus *bus);
569 int bcmpcie_set_get_wake(struct dhd_bus *bus, int flag);
570 #endif /* DHD_WAKE_STATUS */
571 extern bool dhdpcie_bus_get_pcie_hostready_supported(dhd_bus_t *bus);
572 extern void dhd_bus_hostready(struct dhd_bus *bus);
573 extern void dhdpcie_bus_enab_pcie_dw(dhd_bus_t *bus, uint8 dw_option);
574 extern int dhdpcie_irq_disabled(struct dhd_bus *bus);
575
dhdpcie_is_arm_halted(struct dhd_bus * bus)576 static INLINE bool dhdpcie_is_arm_halted(struct dhd_bus *bus)
577 {
578 return TRUE;
579 }
dhd_os_wifi_platform_set_power(uint32 value)580 static INLINE int dhd_os_wifi_platform_set_power(uint32 value)
581 {
582 return BCME_OK;
583 }
dhdpcie_dongle_flr_or_pwr_toggle(dhd_bus_t * bus)584 static INLINE void dhdpcie_dongle_flr_or_pwr_toggle(dhd_bus_t *bus)
585 {
586 return;
587 }
588
589 int dhdpcie_config_check(dhd_bus_t *bus);
590 int dhdpcie_config_restore(dhd_bus_t *bus, bool restore_pmcsr);
591 int dhdpcie_config_save(dhd_bus_t *bus);
592 int dhdpcie_set_pwr_state(dhd_bus_t *bus, uint state);
593
594 extern bool dhdpcie_bus_get_pcie_hwa_supported(dhd_bus_t *bus);
595 extern bool dhdpcie_bus_get_pcie_idma_supported(dhd_bus_t *bus);
596 extern bool dhdpcie_bus_get_pcie_ifrm_supported(dhd_bus_t *bus);
597 extern bool dhdpcie_bus_get_pcie_dar_supported(dhd_bus_t *bus);
598
dhd_pcie_config_read(osl_t * osh,uint offset,uint size)599 static INLINE uint32 dhd_pcie_config_read(osl_t *osh, uint offset, uint size)
600 {
601 OSL_DELAY(100);
602 return OSL_PCI_READ_CONFIG(osh, offset, size);
603 }
604
dhd_pcie_corereg_read(si_t * sih,uint val)605 static INLINE uint32 dhd_pcie_corereg_read(si_t *sih, uint val)
606 {
607 OSL_DELAY(100);
608 si_corereg(sih, sih->buscoreidx, OFFSETOF(sbpcieregs_t, configaddr), ~0,
609 val);
610 return si_corereg(sih, sih->buscoreidx, OFFSETOF(sbpcieregs_t, configdata),
611 0, 0);
612 }
613
614 extern int dhdpcie_get_fwpath_otp(dhd_bus_t *bus, char *fw_path, char *nv_path,
615 char *clm_path, char *txcap_path);
616
617 extern int dhd_pcie_debug_info_dump(dhd_pub_t *dhd);
618 extern void dhd_pcie_intr_count_dump(dhd_pub_t *dhd);
619 extern void dhdpcie_bus_clear_intstatus(dhd_bus_t *bus);
620 #ifdef DHD_HP2P
621 extern uint16 dhd_bus_get_hp2p_ring_max_size(dhd_bus_t *bus, bool tx);
622 #endif // endif
623
624 #endif /* dhd_pcie_h */
625