1 /* 2 * MSGBUF network driver ioctl/indication encoding 3 * Broadcom 802.11abg Networking Device Driver 4 * 5 * Definitions subject to change without notice. 6 * 7 * Copyright (C) 1999-2019, Broadcom. 8 * 9 * Unless you and Broadcom execute a separate written software license 10 * agreement governing use of this software, this software is licensed to you 11 * under the terms of the GNU General Public License version 2 (the "GPL"), 12 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 13 * following added to such license: 14 * 15 * As a special exception, the copyright holders of this software give you 16 * permission to link this software with independent modules, and to copy and 17 * distribute the resulting executable under terms of your choice, provided that 18 * you also meet, for each linked independent module, the terms and conditions 19 * of the license of that module. An independent module is a module which is 20 * not derived from this software. The special exception does not apply to any 21 * modifications of the software. 22 * 23 * Notwithstanding the above, under no circumstances may you combine this 24 * software in any way with any other Broadcom software provided under a license 25 * other than the GPL, without Broadcom's express prior written consent. 26 * 27 * 28 * <<Broadcom-WL-IPTag/Open:>> 29 * 30 * $Id: bcmmsgbuf.h 814986 2019-04-15 21:18:21Z $ 31 */ 32 #ifndef _bcmmsgbuf_h_ 33 #define _bcmmsgbuf_h_ 34 35 #include <ethernet.h> 36 #include <wlioctl.h> 37 #include <bcmpcie.h> 38 39 #define MSGBUF_MAX_MSG_SIZE ETHER_MAX_LEN 40 41 #define D2H_EPOCH_MODULO 253 /* sequence number wrap */ 42 #define D2H_EPOCH_INIT_VAL (D2H_EPOCH_MODULO + 1) 43 44 #define H2D_EPOCH_MODULO 253 /* sequence number wrap */ 45 #define H2D_EPOCH_INIT_VAL (H2D_EPOCH_MODULO + 1) 46 47 #define H2DRING_TXPOST_ITEMSIZE 48 48 #define H2DRING_RXPOST_ITEMSIZE 32 49 #define H2DRING_CTRL_SUB_ITEMSIZE 40 50 51 #define D2HRING_TXCMPLT_ITEMSIZE 24 52 #define D2HRING_RXCMPLT_ITEMSIZE 40 53 54 #define D2HRING_TXCMPLT_ITEMSIZE_PREREV7 16 55 #define D2HRING_RXCMPLT_ITEMSIZE_PREREV7 32 56 57 #define D2HRING_CTRL_CMPLT_ITEMSIZE 24 58 #define H2DRING_INFO_BUFPOST_ITEMSIZE H2DRING_CTRL_SUB_ITEMSIZE 59 #define D2HRING_INFO_BUFCMPLT_ITEMSIZE D2HRING_CTRL_CMPLT_ITEMSIZE 60 61 #define D2HRING_SNAPSHOT_CMPLT_ITEMSIZE 20 62 63 #define H2DRING_TXPOST_MAX_ITEM 512 64 #define H2DRING_RXPOST_MAX_ITEM 512 65 #define H2DRING_CTRL_SUB_MAX_ITEM 64 66 #define D2HRING_TXCMPLT_MAX_ITEM 1024 67 #define D2HRING_RXCMPLT_MAX_ITEM 512 68 69 #define H2DRING_DYNAMIC_INFO_MAX_ITEM 32 70 #define D2HRING_DYNAMIC_INFO_MAX_ITEM 32 71 72 #define D2HRING_EDL_HDR_SIZE 48u 73 #define D2HRING_EDL_ITEMSIZE 2048u 74 #define D2HRING_EDL_MAX_ITEM 256u 75 #define D2HRING_EDL_WATERMARK (D2HRING_EDL_MAX_ITEM >> 5u) 76 77 #define D2HRING_CTRL_CMPLT_MAX_ITEM 64 78 79 enum { DNGL_TO_HOST_MSGBUF, HOST_TO_DNGL_MSGBUF }; 80 81 enum { 82 HOST_TO_DNGL_TXP_DATA, 83 HOST_TO_DNGL_RXP_DATA, 84 HOST_TO_DNGL_CTRL, 85 DNGL_TO_HOST_DATA, 86 DNGL_TO_HOST_CTRL 87 }; 88 89 #define MESSAGE_PAYLOAD(a) (a & MSG_TYPE_INTERNAL_USE_START) ? TRUE : FALSE 90 #define PCIEDEV_FIRMWARE_TSINFO 0x1 91 #define PCIEDEV_FIRMWARE_TSINFO_FIRST 0x1 92 #define PCIEDEV_FIRMWARE_TSINFO_MIDDLE 0x2 93 #define PCIEDEV_BTLOG_POST 0x3 94 #define PCIEDEV_BT_SNAPSHOT_POST 0x4 95 96 #ifdef PCIE_API_REV1 97 98 #define BCMMSGBUF_DUMMY_REF(a, b) \ 99 do { \ 100 BCM_REFERENCE((a)); \ 101 BCM_REFERENCE((b)); \ 102 } while (0) 103 104 #define BCMMSGBUF_API_IFIDX(a) 0 105 #define BCMMSGBUF_API_SEQNUM(a) 0 106 #define BCMMSGBUF_IOCTL_XTID(a) 0 107 #define BCMMSGBUF_IOCTL_PKTID(a) ((a)->cmd_id) 108 109 #define BCMMSGBUF_SET_API_IFIDX(a, b) BCMMSGBUF_DUMMY_REF(a, b) 110 #define BCMMSGBUF_SET_API_SEQNUM(a, b) BCMMSGBUF_DUMMY_REF(a, b) 111 #define BCMMSGBUF_IOCTL_SET_PKTID(a, b) (BCMMSGBUF_IOCTL_PKTID(a) = (b)) 112 #define BCMMSGBUF_IOCTL_SET_XTID(a, b) BCMMSGBUF_DUMMY_REF(a, b) 113 114 #else /* PCIE_API_REV1 */ 115 116 #define BCMMSGBUF_API_IFIDX(a) ((a)->if_id) 117 #define BCMMSGBUF_IOCTL_PKTID(a) ((a)->pkt_id) 118 #define BCMMSGBUF_API_SEQNUM(a) ((a)->u.seq.seq_no) 119 #define BCMMSGBUF_IOCTL_XTID(a) ((a)->xt_id) 120 121 #define BCMMSGBUF_SET_API_IFIDX(a, b) (BCMMSGBUF_API_IFIDX((a)) = (b)) 122 #define BCMMSGBUF_SET_API_SEQNUM(a, b) (BCMMSGBUF_API_SEQNUM((a)) = (b)) 123 #define BCMMSGBUF_IOCTL_SET_PKTID(a, b) (BCMMSGBUF_IOCTL_PKTID((a)) = (b)) 124 #define BCMMSGBUF_IOCTL_SET_XTID(a, b) (BCMMSGBUF_IOCTL_XTID((a)) = (b)) 125 126 #endif /* PCIE_API_REV1 */ 127 128 /* utility data structures */ 129 130 union addr64 { 131 struct { 132 uint32 low; 133 uint32 high; 134 }; 135 struct { 136 uint32 low_addr; 137 uint32 high_addr; 138 }; 139 uint64 u64; 140 } DECLSPEC_ALIGN(0x8); 141 142 typedef union addr64 bcm_addr64_t; 143 144 /* IOCTL req Hdr */ 145 /* cmn Msg Hdr */ 146 typedef struct cmn_msg_hdr { 147 /** message type */ 148 uint8 msg_type; 149 /** interface index this is valid for */ 150 uint8 if_id; 151 /* flags */ 152 uint8 flags; 153 /** sequence number */ 154 uint8 epoch; 155 /** packet Identifier for the associated host buffer */ 156 uint32 request_id; 157 } cmn_msg_hdr_t; 158 159 /** message type */ 160 typedef enum bcmpcie_msgtype { 161 MSG_TYPE_GEN_STATUS = 0x1, 162 MSG_TYPE_RING_STATUS = 0x2, 163 MSG_TYPE_FLOW_RING_CREATE = 0x3, 164 MSG_TYPE_FLOW_RING_CREATE_CMPLT = 0x4, 165 /* Enum value as copied from BISON 7.15: new generic message */ 166 MSG_TYPE_RING_CREATE_CMPLT = 0x4, 167 MSG_TYPE_FLOW_RING_DELETE = 0x5, 168 MSG_TYPE_FLOW_RING_DELETE_CMPLT = 0x6, 169 /* Enum value as copied from BISON 7.15: new generic message */ 170 MSG_TYPE_RING_DELETE_CMPLT = 0x6, 171 MSG_TYPE_FLOW_RING_FLUSH = 0x7, 172 MSG_TYPE_FLOW_RING_FLUSH_CMPLT = 0x8, 173 MSG_TYPE_IOCTLPTR_REQ = 0x9, 174 MSG_TYPE_IOCTLPTR_REQ_ACK = 0xA, 175 MSG_TYPE_IOCTLRESP_BUF_POST = 0xB, 176 MSG_TYPE_IOCTL_CMPLT = 0xC, 177 MSG_TYPE_EVENT_BUF_POST = 0xD, 178 MSG_TYPE_WL_EVENT = 0xE, 179 MSG_TYPE_TX_POST = 0xF, 180 MSG_TYPE_TX_STATUS = 0x10, 181 MSG_TYPE_RXBUF_POST = 0x11, 182 MSG_TYPE_RX_CMPLT = 0x12, 183 MSG_TYPE_LPBK_DMAXFER = 0x13, 184 MSG_TYPE_LPBK_DMAXFER_CMPLT = 0x14, 185 MSG_TYPE_FLOW_RING_RESUME = 0x15, 186 MSG_TYPE_FLOW_RING_RESUME_CMPLT = 0x16, 187 MSG_TYPE_FLOW_RING_SUSPEND = 0x17, 188 MSG_TYPE_FLOW_RING_SUSPEND_CMPLT = 0x18, 189 MSG_TYPE_INFO_BUF_POST = 0x19, 190 MSG_TYPE_INFO_BUF_CMPLT = 0x1A, 191 MSG_TYPE_H2D_RING_CREATE = 0x1B, 192 MSG_TYPE_D2H_RING_CREATE = 0x1C, 193 MSG_TYPE_H2D_RING_CREATE_CMPLT = 0x1D, 194 MSG_TYPE_D2H_RING_CREATE_CMPLT = 0x1E, 195 MSG_TYPE_H2D_RING_CONFIG = 0x1F, 196 MSG_TYPE_D2H_RING_CONFIG = 0x20, 197 MSG_TYPE_H2D_RING_CONFIG_CMPLT = 0x21, 198 MSG_TYPE_D2H_RING_CONFIG_CMPLT = 0x22, 199 MSG_TYPE_H2D_MAILBOX_DATA = 0x23, 200 MSG_TYPE_D2H_MAILBOX_DATA = 0x24, 201 MSG_TYPE_TIMSTAMP_BUFPOST = 0x25, 202 MSG_TYPE_HOSTTIMSTAMP = 0x26, 203 MSG_TYPE_HOSTTIMSTAMP_CMPLT = 0x27, 204 MSG_TYPE_FIRMWARE_TIMESTAMP = 0x28, 205 MSG_TYPE_SNAPSHOT_UPLOAD = 0x29, 206 MSG_TYPE_SNAPSHOT_CMPLT = 0x2A, 207 MSG_TYPE_H2D_RING_DELETE = 0x2B, 208 MSG_TYPE_D2H_RING_DELETE = 0x2C, 209 MSG_TYPE_H2D_RING_DELETE_CMPLT = 0x2D, 210 MSG_TYPE_D2H_RING_DELETE_CMPLT = 0x2E, 211 MSG_TYPE_API_MAX_RSVD = 0x3F 212 } bcmpcie_msg_type_t; 213 214 typedef enum bcmpcie_msgtype_int { 215 MSG_TYPE_INTERNAL_USE_START = 0x40, 216 MSG_TYPE_EVENT_PYLD = 0x41, 217 MSG_TYPE_IOCT_PYLD = 0x42, 218 MSG_TYPE_RX_PYLD = 0x43, 219 MSG_TYPE_HOST_FETCH = 0x44, 220 MSG_TYPE_LPBK_DMAXFER_PYLD = 0x45, 221 MSG_TYPE_TXMETADATA_PYLD = 0x46, 222 MSG_TYPE_INDX_UPDATE = 0x47, 223 MSG_TYPE_INFO_PYLD = 0x48, 224 MSG_TYPE_TS_EVENT_PYLD = 0x49, 225 MSG_TYPE_PVT_BTLOG_CMPLT = 0x4A, 226 MSG_TYPE_BTLOG_PYLD = 0x4B, 227 MSG_TYPE_HMAPTEST_PYLD = 0x4C, 228 MSG_TYPE_PVT_BT_SNAPSHOT_CMPLT = 0x4D, 229 MSG_TYPE_BT_SNAPSHOT_PYLD = 0x4E 230 } bcmpcie_msgtype_int_t; 231 232 typedef enum bcmpcie_msgtype_u { 233 MSG_TYPE_TX_BATCH_POST = 0x80, 234 MSG_TYPE_IOCTL_REQ = 0x81, 235 MSG_TYPE_HOST_EVNT = 0x82, /* console related */ 236 MSG_TYPE_LOOPBACK = 0x83 237 } bcmpcie_msgtype_u_t; 238 239 /** 240 * D2H ring host wakeup soft doorbell, override the PCIE doorbell. 241 * Host configures an <32bit address,value> tuple, and dongle uses SBTOPCIE 242 * Transl0 to write specified value to host address. 243 * 244 * Use case: 32bit Address mapped to HW Accelerator Core/Thread Wakeup Register 245 * and value is Core/Thread context. Host will ensure routing the 32bit address 246 * offerred to PCIE to the mapped register. 247 * 248 * D2H_RING_CONFIG_SUBTYPE_SOFT_DOORBELL 249 */ 250 typedef struct bcmpcie_soft_doorbell { 251 uint32 value; /* host defined value to be written, eg HW threadid */ 252 bcm_addr64_t haddr; /* host address, eg thread wakeup register address */ 253 uint16 items; /* interrupt coalescing: item count before wakeup */ 254 uint16 msecs; /* interrupt coalescing: timeout in millisecs */ 255 } bcmpcie_soft_doorbell_t; 256 257 /** 258 * D2H interrupt using MSI instead of INTX 259 * Host configures MSI vector offset for each D2H interrupt 260 * 261 * D2H_RING_CONFIG_SUBTYPE_MSI_DOORBELL 262 */ 263 typedef enum bcmpcie_msi_intr_idx { 264 MSI_INTR_IDX_CTRL_CMPL_RING = 0, 265 MSI_INTR_IDX_TXP_CMPL_RING = 1, 266 MSI_INTR_IDX_RXP_CMPL_RING = 2, 267 MSI_INTR_IDX_INFO_CMPL_RING = 3, 268 MSI_INTR_IDX_MAILBOX = 4, 269 MSI_INTR_IDX_MAX = 5 270 } bcmpcie_msi_intr_idx_t; 271 272 #define BCMPCIE_D2H_MSI_OFFSET_SINGLE 0 273 typedef enum bcmpcie_msi_offset_type { 274 BCMPCIE_D2H_MSI_OFFSET_MB0 = 2, 275 BCMPCIE_D2H_MSI_OFFSET_MB1 = 3, 276 BCMPCIE_D2H_MSI_OFFSET_DB0 = 4, 277 BCMPCIE_D2H_MSI_OFFSET_DB1 = 5, 278 BCMPCIE_D2H_MSI_OFFSET_H1_DB0 = 6, 279 BCMPCIE_D2H_MSI_OFFSET_MAX = 7 280 } bcmpcie_msi_offset_type_t; 281 282 typedef struct bcmpcie_msi_offset { 283 uint16 intr_idx; /* interrupt index */ 284 uint16 msi_offset; /* msi vector offset */ 285 } bcmpcie_msi_offset_t; 286 287 typedef struct bcmpcie_msi_offset_config { 288 uint32 len; 289 bcmpcie_msi_offset_t bcmpcie_msi_offset[MSI_INTR_IDX_MAX]; 290 } bcmpcie_msi_offset_config_t; 291 292 #define BCMPCIE_D2H_MSI_OFFSET_DEFAULT BCMPCIE_D2H_MSI_OFFSET_DB1 293 294 #define BCMPCIE_D2H_MSI_SINGLE 0xFFFE 295 296 /* if_id */ 297 #define BCMPCIE_CMNHDR_IFIDX_PHYINTF_SHFT 5 298 #define BCMPCIE_CMNHDR_IFIDX_PHYINTF_MAX 0x7 299 #define BCMPCIE_CMNHDR_IFIDX_PHYINTF_MASK \ 300 (BCMPCIE_CMNHDR_IFIDX_PHYINTF_MAX << BCMPCIE_CMNHDR_IFIDX_PHYINTF_SHFT) 301 #define BCMPCIE_CMNHDR_IFIDX_VIRTINTF_SHFT 0 302 #define BCMPCIE_CMNHDR_IFIDX_VIRTINTF_MAX 0x1F 303 #define BCMPCIE_CMNHDR_IFIDX_VIRTINTF_MASK \ 304 (BCMPCIE_CMNHDR_IFIDX_PHYINTF_MAX << BCMPCIE_CMNHDR_IFIDX_PHYINTF_SHFT) 305 306 /* flags */ 307 #define BCMPCIE_CMNHDR_FLAGS_DMA_R_IDX 0x1 308 #define BCMPCIE_CMNHDR_FLAGS_DMA_R_IDX_INTR 0x2 309 #define BCMPCIE_CMNHDR_FLAGS_TS_SEQNUM_INIT 0x4 310 #define BCMPCIE_CMNHDR_FLAGS_PHASE_BIT 0x80 311 #define BCMPCIE_CMNHDR_PHASE_BIT_INIT 0x80 312 313 /* IOCTL request message */ 314 typedef struct ioctl_req_msg { 315 /** common message header */ 316 cmn_msg_hdr_t cmn_hdr; 317 /** ioctl command type */ 318 uint32 cmd; 319 /** ioctl transaction ID, to pair with a ioctl response */ 320 uint16 trans_id; 321 /** input arguments buffer len */ 322 uint16 input_buf_len; 323 /** expected output len */ 324 uint16 output_buf_len; 325 /** to align the host address on 8 byte boundary */ 326 uint16 rsvd[3]; 327 /** always align on 8 byte boundary */ 328 bcm_addr64_t host_input_buf_addr; 329 /* rsvd */ 330 uint32 rsvd1[2]; 331 } ioctl_req_msg_t; 332 333 /** buffer post messages for device to use to return IOCTL responses, Events */ 334 typedef struct ioctl_resp_evt_buf_post_msg { 335 /** common message header */ 336 cmn_msg_hdr_t cmn_hdr; 337 /** length of the host buffer supplied */ 338 uint16 host_buf_len; 339 /** to align the host address on 8 byte boundary */ 340 uint16 reserved[3]; 341 /** always align on 8 byte boundary */ 342 bcm_addr64_t host_buf_addr; 343 uint32 rsvd[4]; 344 } ioctl_resp_evt_buf_post_msg_t; 345 346 /* buffer post messages for device to use to return dbg buffers */ 347 typedef ioctl_resp_evt_buf_post_msg_t info_buf_post_msg_t; 348 349 #define DHD_INFOBUF_RX_BUFPOST_PKTSZ (2 * 1024) 350 351 #define DHD_BTLOG_RX_BUFPOST_PKTSZ (2 * 1024) 352 353 /* An infobuf host buffer starts with a 32 bit (LE) version. */ 354 #define PCIE_INFOBUF_V1 1 355 /* Infobuf v1 type MSGTRACE's data is exactly the same as the MSGTRACE data that 356 * is wrapped previously/also in a WLC_E_TRACE event. See structure 357 * msgrace_hdr_t in msgtrace.h. 358 */ 359 #define PCIE_INFOBUF_V1_TYPE_MSGTRACE 1 360 361 /* Infobuf v1 type LOGTRACE data is exactly the same as the LOGTRACE data that 362 * is wrapped previously/also in a WLC_E_TRACE event. See structure 363 * msgrace_hdr_t in msgtrace.h. (The only difference between a MSGTRACE 364 * and a LOGTRACE is the "trace type" field.) 365 */ 366 #define PCIE_INFOBUF_V1_TYPE_LOGTRACE 2 367 368 /* An infobuf version 1 host buffer has a single TLV. The information on the 369 * version 1 types follow this structure definition. (int's LE) 370 */ 371 typedef struct info_buf_payload_hdr_s { 372 uint16 type; 373 uint16 length; 374 } info_buf_payload_hdr_t; 375 376 /* BT logs/memory to DMA directly from BT memory to host */ 377 typedef struct info_buf_btlog_s { 378 void (*status_cb)(void *ctx, void *p, 379 int error); /* obsolete - to be removed */ 380 void *ctx; 381 dma64addr_t src_addr; 382 uint32 length; 383 bool (*pcie_status_cb)(osl_t *osh, void *p, int error); 384 uint32 bt_intstatus; 385 int error; 386 } info_buf_btlog_t; 387 388 /** snapshot upload request message */ 389 typedef struct snapshot_upload_request_msg { 390 /** common message header */ 391 cmn_msg_hdr_t cmn_hdr; 392 /** length of the snaphost buffer supplied */ 393 uint32 snapshot_buf_len; 394 /** type of snapshot */ 395 uint8 snapshot_type; 396 /** snapshot param */ 397 uint8 snapshot_param; 398 /** to align the host address on 8 byte boundary */ 399 uint8 reserved[2]; 400 /** always align on 8 byte boundary */ 401 bcm_addr64_t host_buf_addr; 402 uint32 rsvd[4]; 403 } snapshot_upload_request_msg_t; 404 405 /** snapshot types */ 406 typedef enum bcmpcie_snapshot_type { 407 SNAPSHOT_TYPE_BT = 0, /* Bluetooth SRAM and patch RAM */ 408 SNAPSHOT_TYPE_WLAN_SOCRAM = 1, /* WLAN SOCRAM */ 409 SNAPSHOT_TYPE_WLAN_HEAP = 2, /* WLAN HEAP */ 410 SNAPSHOT_TYPE_WLAN_REGISTER = 3 /* WLAN registers */ 411 } bcmpcie_snapshot_type_t; 412 413 #define PCIE_DMA_XFER_FLG_D11_LPBK_MASK 0xF 414 #define PCIE_DMA_XFER_FLG_D11_LPBK_SHIFT 2 415 #define PCIE_DMA_XFER_FLG_CORE_NUMBER_MASK 3 416 #define PCIE_DMA_XFER_FLG_CORE_NUMBER_SHIFT 0 417 418 typedef struct pcie_dma_xfer_params { 419 /** common message header */ 420 cmn_msg_hdr_t cmn_hdr; 421 422 /** always align on 8 byte boundary */ 423 bcm_addr64_t host_input_buf_addr; 424 425 /** always align on 8 byte boundary */ 426 bcm_addr64_t host_ouput_buf_addr; 427 428 /** length of transfer */ 429 uint32 xfer_len; 430 /** delay before doing the src txfer */ 431 uint32 srcdelay; 432 /** delay before doing the dest txfer */ 433 uint32 destdelay; 434 uint8 rsvd[3]; 435 /* bit0: D11 DMA loopback flag */ 436 uint8 flags; 437 } pcie_dma_xfer_params_t; 438 439 #define BCMPCIE_FLOW_RING_INTF_HP2P 0x1 440 /** Complete msgbuf hdr for flow ring update from host to dongle */ 441 typedef struct tx_flowring_create_request { 442 cmn_msg_hdr_t msg; 443 uint8 da[ETHER_ADDR_LEN]; 444 uint8 sa[ETHER_ADDR_LEN]; 445 uint8 tid; 446 uint8 if_flags; 447 uint16 flow_ring_id; 448 uint8 tc; 449 /* priority_ifrmmask is to define core mask in ifrm mode. 450 * currently it is not used for priority. so uses solely for ifrm mask 451 */ 452 uint8 priority_ifrmmask; 453 uint16 int_vector; 454 uint16 max_items; 455 uint16 len_item; 456 bcm_addr64_t flow_ring_ptr; 457 } tx_flowring_create_request_t; 458 459 typedef struct tx_flowring_delete_request { 460 cmn_msg_hdr_t msg; 461 uint16 flow_ring_id; 462 uint16 reason; 463 uint32 rsvd[7]; 464 } tx_flowring_delete_request_t; 465 466 typedef tx_flowring_delete_request_t d2h_ring_delete_req_t; 467 typedef tx_flowring_delete_request_t h2d_ring_delete_req_t; 468 469 typedef struct tx_flowring_flush_request { 470 cmn_msg_hdr_t msg; 471 uint16 flow_ring_id; 472 uint16 reason; 473 uint32 rsvd[7]; 474 } tx_flowring_flush_request_t; 475 476 /** Subtypes for ring_config_req control message */ 477 typedef enum ring_config_subtype { 478 /** Default D2H PCIE doorbell override using ring_config_req msg */ 479 D2H_RING_CONFIG_SUBTYPE_SOFT_DOORBELL = 1, /* Software doorbell */ 480 D2H_RING_CONFIG_SUBTYPE_MSI_DOORBELL = 2 /* MSI configuration */ 481 } ring_config_subtype_t; 482 483 typedef struct ring_config_req { 484 cmn_msg_hdr_t msg; 485 uint16 subtype; 486 uint16 ring_id; 487 uint32 rsvd; 488 union { 489 uint32 data[6]; 490 /** D2H_RING_CONFIG_SUBTYPE_SOFT_DOORBELL */ 491 bcmpcie_soft_doorbell_t soft_doorbell; 492 /** D2H_RING_CONFIG_SUBTYPE_MSI_DOORBELL */ 493 bcmpcie_msi_offset_config_t msi_offset; 494 }; 495 } ring_config_req_t; 496 497 /* data structure to use to create on the fly d2h rings */ 498 typedef struct d2h_ring_create_req { 499 cmn_msg_hdr_t msg; 500 uint16 ring_id; 501 uint16 ring_type; 502 uint32 flags; 503 bcm_addr64_t ring_ptr; 504 uint16 max_items; 505 uint16 len_item; 506 uint32 rsvd[3]; 507 } d2h_ring_create_req_t; 508 509 /* data structure to use to create on the fly h2d rings */ 510 #define MAX_COMPLETION_RING_IDS_ASSOCIATED 4 511 typedef struct h2d_ring_create_req { 512 cmn_msg_hdr_t msg; 513 uint16 ring_id; 514 uint8 ring_type; 515 uint8 n_completion_ids; 516 uint32 flags; 517 bcm_addr64_t ring_ptr; 518 uint16 max_items; 519 uint16 len_item; 520 uint16 completion_ring_ids[MAX_COMPLETION_RING_IDS_ASSOCIATED]; 521 uint32 rsvd; 522 } h2d_ring_create_req_t; 523 524 typedef struct d2h_ring_config_req { 525 cmn_msg_hdr_t msg; 526 uint16 d2h_ring_config_subtype; 527 uint16 d2h_ring_id; 528 uint32 d2h_ring_config_data[4]; 529 uint32 rsvd[3]; 530 } d2h_ring_config_req_t; 531 532 typedef struct h2d_ring_config_req { 533 cmn_msg_hdr_t msg; 534 uint16 h2d_ring_config_subtype; 535 uint16 h2d_ring_id; 536 uint32 h2d_ring_config_data; 537 uint32 rsvd[6]; 538 } h2d_ring_config_req_t; 539 540 typedef struct h2d_mailbox_data { 541 cmn_msg_hdr_t msg; 542 uint32 mail_box_data; 543 uint32 rsvd[7]; 544 } h2d_mailbox_data_t; 545 typedef struct host_timestamp_msg { 546 cmn_msg_hdr_t msg; 547 uint16 xt_id; /* transaction ID */ 548 uint16 input_data_len; /* data len at the host_buf_addr, data in TLVs */ 549 uint16 seqnum; /* number of times host captured the timestamp */ 550 uint16 rsvd; 551 /* always align on 8 byte boundary */ 552 bcm_addr64_t host_buf_addr; 553 /* rsvd */ 554 uint32 rsvd1[4]; 555 } host_timestamp_msg_t; 556 557 /* buffer post message for timestamp events MSG_TYPE_TIMSTAMP_BUFPOST */ 558 typedef ioctl_resp_evt_buf_post_msg_t ts_buf_post_msg_t; 559 560 typedef union ctrl_submit_item { 561 ioctl_req_msg_t ioctl_req; 562 ioctl_resp_evt_buf_post_msg_t resp_buf_post; 563 pcie_dma_xfer_params_t dma_xfer; 564 tx_flowring_create_request_t flow_create; 565 tx_flowring_delete_request_t flow_delete; 566 tx_flowring_flush_request_t flow_flush; 567 ring_config_req_t ring_config_req; 568 d2h_ring_create_req_t d2h_create; 569 h2d_ring_create_req_t h2d_create; 570 d2h_ring_config_req_t d2h_config; 571 h2d_ring_config_req_t h2d_config; 572 h2d_mailbox_data_t h2d_mailbox_data; 573 host_timestamp_msg_t host_ts; 574 ts_buf_post_msg_t ts_buf_post; 575 d2h_ring_delete_req_t d2h_delete; 576 h2d_ring_delete_req_t h2d_delete; 577 unsigned char check[H2DRING_CTRL_SUB_ITEMSIZE]; 578 } ctrl_submit_item_t; 579 580 typedef struct info_ring_submit_item { 581 info_buf_post_msg_t info_buf_post; 582 unsigned char check[H2DRING_INFO_BUFPOST_ITEMSIZE]; 583 } info_sumbit_item_t; 584 585 /** Control Completion messages (20 bytes) */ 586 typedef struct compl_msg_hdr { 587 union { 588 /** status for the completion */ 589 int16 status; 590 591 /* mutually exclusive with pkt fate debug feature */ 592 struct pktts_compl_hdr { 593 uint16 d_t4; /* Delta TimeStamp 3: T4-tref */ 594 } tx_pktts; 595 }; 596 /** submisison flow ring id which generated this status */ 597 union { 598 uint16 ring_id; 599 uint16 flow_ring_id; 600 }; 601 } compl_msg_hdr_t; 602 603 /** XOR checksum or a magic number to audit DMA done */ 604 typedef uint32 dma_done_t; 605 606 #define MAX_CLKSRC_ID 0xF 607 #define TX_PKT_RETRY_CNT_0_MASK 0x000000FF 608 #define TX_PKT_RETRY_CNT_0_SHIFT 0 609 #define TX_PKT_RETRY_CNT_1_MASK 0x0000FF00 610 #define TX_PKT_RETRY_CNT_1_SHIFT 8 611 #define TX_PKT_RETRY_CNT_2_MASK 0x00FF0000 612 #define TX_PKT_RETRY_CNT_2_SHIFT 16 613 #define TX_PKT_BAND_INFO 0x0F000000 614 #define TX_PKT_BAND_INFO_SHIFT 24 615 #define TX_PKT_VALID_INFO 0xF0000000 616 #define TX_PKT_VALID_INFO_SHIFT 28 617 618 typedef struct ts_timestamp_srcid { 619 union { 620 uint32 ts_low; /* time stamp low 32 bits */ 621 uint32 rate_spec; /* use ratespec */ 622 }; 623 union { 624 uint32 ts_high; /* time stamp high 28 bits */ 625 union { 626 uint32 ts_high_ext : 28; /* time stamp high 28 bits */ 627 uint32 clk_id_ext : 3; /* clock ID source */ 628 uint32 phase : 1; /* Phase bit */ 629 dma_done_t marker_ext; 630 }; 631 uint32 tx_pkt_band_retry_info; 632 }; 633 } ts_timestamp_srcid_t; 634 635 typedef ts_timestamp_srcid_t ipc_timestamp_t; 636 637 typedef struct ts_timestamp { 638 uint32 low; 639 uint32 high; 640 } ts_timestamp_t; 641 642 typedef ts_timestamp_t tick_count_64_t; 643 typedef ts_timestamp_t ts_timestamp_ns_64_t; 644 typedef ts_timestamp_t ts_correction_m_t; 645 typedef ts_timestamp_t ts_correction_b_t; 646 647 typedef struct _pktts { 648 uint32 tref; /* Ref Clk in uSec (currently, tsf) */ 649 uint16 d_t2; /* Delta TimeStamp 1: T2-tref */ 650 uint16 d_t3; /* Delta TimeStamp 2: T3-tref */ 651 } pktts_t; 652 653 /* completion header status codes */ 654 #define BCMPCIE_SUCCESS 0 655 #define BCMPCIE_NOTFOUND 1 656 #define BCMPCIE_NOMEM 2 657 #define BCMPCIE_BADOPTION 3 658 #define BCMPCIE_RING_IN_USE 4 659 #define BCMPCIE_RING_ID_INVALID 5 660 #define BCMPCIE_PKT_FLUSH 6 661 #define BCMPCIE_NO_EVENT_BUF 7 662 #define BCMPCIE_NO_RX_BUF 8 663 #define BCMPCIE_NO_IOCTLRESP_BUF 9 664 #define BCMPCIE_MAX_IOCTLRESP_BUF 10 665 #define BCMPCIE_MAX_EVENT_BUF 11 666 #define BCMPCIE_BAD_PHASE 12 667 #define BCMPCIE_INVALID_CPL_RINGID 13 668 #define BCMPCIE_RING_TYPE_INVALID 14 669 #define BCMPCIE_NO_TS_EVENT_BUF 15 670 #define BCMPCIE_MAX_TS_EVENT_BUF 16 671 #define BCMPCIE_PCIE_NO_BTLOG_BUF 17 672 #define BCMPCIE_BT_DMA_ERR 18 673 #define BCMPCIE_BT_DMA_DESCR_FETCH_ERR 19 674 #define BCMPCIE_SNAPSHOT_ERR 20 675 #define BCMPCIE_NOT_READY 21 676 #define BCMPCIE_INVALID_DATA 22 677 #define BCMPCIE_NO_RESPONSE 23 678 #define BCMPCIE_NO_CLOCK 24 679 680 /** IOCTL completion response */ 681 typedef struct ioctl_compl_resp_msg { 682 /** common message header */ 683 cmn_msg_hdr_t cmn_hdr; 684 /** completion message header */ 685 compl_msg_hdr_t compl_hdr; 686 /** response buffer len where a host buffer is involved */ 687 uint16 resp_len; 688 /** transaction id to pair with a request */ 689 uint16 trans_id; 690 /** cmd id */ 691 uint32 cmd; 692 /** XOR checksum or a magic number to audit DMA done */ 693 dma_done_t marker; 694 } ioctl_comp_resp_msg_t; 695 696 /** IOCTL request acknowledgement */ 697 typedef struct ioctl_req_ack_msg { 698 /** common message header */ 699 cmn_msg_hdr_t cmn_hdr; 700 /** completion message header */ 701 compl_msg_hdr_t compl_hdr; 702 /** cmd id */ 703 uint32 cmd; 704 uint32 rsvd; 705 /** XOR checksum or a magic number to audit DMA done */ 706 dma_done_t marker; 707 } ioctl_req_ack_msg_t; 708 709 /** WL event message: send from device to host */ 710 typedef struct wlevent_req_msg { 711 /** common message header */ 712 cmn_msg_hdr_t cmn_hdr; 713 /** completion message header */ 714 compl_msg_hdr_t compl_hdr; 715 /** event data len valid with the event buffer */ 716 uint16 event_data_len; 717 /** sequence number */ 718 uint16 seqnum; 719 /** rsvd */ 720 uint32 rsvd; 721 /** XOR checksum or a magic number to audit DMA done */ 722 dma_done_t marker; 723 } wlevent_req_msg_t; 724 725 /** dma xfer complete message */ 726 typedef struct pcie_dmaxfer_cmplt { 727 /** common message header */ 728 cmn_msg_hdr_t cmn_hdr; 729 /** completion message header */ 730 compl_msg_hdr_t compl_hdr; 731 uint32 rsvd[2]; 732 /** XOR checksum or a magic number to audit DMA done */ 733 dma_done_t marker; 734 } pcie_dmaxfer_cmplt_t; 735 736 /** general status message */ 737 typedef struct pcie_gen_status { 738 /** common message header */ 739 cmn_msg_hdr_t cmn_hdr; 740 /** completion message header */ 741 compl_msg_hdr_t compl_hdr; 742 uint32 rsvd[2]; 743 /** XOR checksum or a magic number to audit DMA done */ 744 dma_done_t marker; 745 } pcie_gen_status_t; 746 747 /** ring status message */ 748 typedef struct pcie_ring_status { 749 /** common message header */ 750 cmn_msg_hdr_t cmn_hdr; 751 /** completion message header */ 752 compl_msg_hdr_t compl_hdr; 753 /** message which firmware couldn't decode */ 754 uint16 write_idx; 755 uint16 rsvd[3]; 756 /** XOR checksum or a magic number to audit DMA done */ 757 dma_done_t marker; 758 } pcie_ring_status_t; 759 760 typedef struct ring_create_response { 761 cmn_msg_hdr_t cmn_hdr; 762 compl_msg_hdr_t cmplt; 763 uint32 rsvd[2]; 764 /** XOR checksum or a magic number to audit DMA done */ 765 dma_done_t marker; 766 } ring_create_response_t; 767 768 typedef ring_create_response_t tx_flowring_create_response_t; 769 typedef ring_create_response_t h2d_ring_create_response_t; 770 typedef ring_create_response_t d2h_ring_create_response_t; 771 772 typedef struct tx_flowring_delete_response { 773 cmn_msg_hdr_t msg; 774 compl_msg_hdr_t cmplt; 775 uint16 read_idx; 776 uint16 rsvd[3]; 777 /** XOR checksum or a magic number to audit DMA done */ 778 dma_done_t marker; 779 } tx_flowring_delete_response_t; 780 781 typedef tx_flowring_delete_response_t h2d_ring_delete_response_t; 782 typedef tx_flowring_delete_response_t d2h_ring_delete_response_t; 783 784 typedef struct tx_flowring_flush_response { 785 cmn_msg_hdr_t msg; 786 compl_msg_hdr_t cmplt; 787 uint32 rsvd[2]; 788 /** XOR checksum or a magic number to audit DMA done */ 789 dma_done_t marker; 790 } tx_flowring_flush_response_t; 791 792 /** Common layout of all d2h control messages */ 793 typedef struct ctrl_compl_msg { 794 /** common message header */ 795 cmn_msg_hdr_t cmn_hdr; 796 /** completion message header */ 797 compl_msg_hdr_t compl_hdr; 798 uint32 rsvd[2]; 799 /** XOR checksum or a magic number to audit DMA done */ 800 dma_done_t marker; 801 } ctrl_compl_msg_t; 802 803 typedef struct ring_config_resp { 804 /** common message header */ 805 cmn_msg_hdr_t cmn_hdr; 806 /** completion message header */ 807 compl_msg_hdr_t compl_hdr; 808 uint16 subtype; 809 uint16 rsvd[3]; 810 /** XOR checksum or a magic number to audit DMA done */ 811 dma_done_t marker; 812 } ring_config_resp_t; 813 814 typedef struct d2h_mailbox_data { 815 cmn_msg_hdr_t msg; 816 compl_msg_hdr_t cmplt; 817 uint32 d2h_mailbox_data; 818 uint32 rsvd[1]; 819 /* XOR checksum or a magic number to audit DMA done */ 820 dma_done_t marker; 821 } d2h_mailbox_data_t; 822 823 /* dbg buf completion msg: send from device to host */ 824 typedef struct info_buf_resp { 825 /* common message header */ 826 cmn_msg_hdr_t cmn_hdr; 827 /* completion message header */ 828 compl_msg_hdr_t compl_hdr; 829 /* event data len valid with the event buffer */ 830 uint16 info_data_len; 831 /* sequence number */ 832 uint16 seqnum; 833 /* destination */ 834 uint8 dest; 835 /* rsvd */ 836 uint8 rsvd[3]; 837 /* XOR checksum or a magic number to audit DMA done */ 838 dma_done_t marker; 839 } info_buf_resp_t; 840 841 /* snapshot completion msg: send from device to host */ 842 typedef struct snapshot_resp { 843 /* common message header */ 844 cmn_msg_hdr_t cmn_hdr; 845 /* completion message header */ 846 compl_msg_hdr_t compl_hdr; 847 /* snapshot length uploaded */ 848 uint32 resp_len; 849 /* snapshot type */ 850 uint8 type; 851 /* rsvd */ 852 uint8 rsvd[3]; 853 /* XOR checksum or a magic number to audit DMA done */ 854 dma_done_t marker; 855 } snapshot_resp_t; 856 857 typedef struct info_ring_cpl_item { 858 info_buf_resp_t info_buf_post; 859 unsigned char check[D2HRING_INFO_BUFCMPLT_ITEMSIZE]; 860 } info_cpl_item_t; 861 862 typedef struct host_timestamp_msg_cpl { 863 cmn_msg_hdr_t msg; 864 compl_msg_hdr_t cmplt; 865 uint16 xt_id; /* transaction ID */ 866 uint16 rsvd; 867 uint32 rsvd1; 868 /* XOR checksum or a magic number to audit DMA done */ 869 dma_done_t marker; 870 } host_timestamp_msg_cpl_t; 871 872 typedef struct fw_timestamp_event_msg { 873 cmn_msg_hdr_t msg; 874 compl_msg_hdr_t cmplt; 875 /* fw captures time stamp info and passed that to host in TLVs */ 876 uint16 buf_len; /* length of the time stamp data copied in host buf */ 877 uint16 seqnum; /* number of times fw captured time stamp */ 878 uint32 rsvd; 879 /* XOR checksum or a magic number to audit DMA done */ 880 dma_done_t marker; 881 } fw_timestamp_event_msg_t; 882 883 typedef union ctrl_completion_item { 884 ioctl_comp_resp_msg_t ioctl_resp; 885 wlevent_req_msg_t event; 886 ioctl_req_ack_msg_t ioct_ack; 887 pcie_dmaxfer_cmplt_t pcie_xfer_cmplt; 888 pcie_gen_status_t pcie_gen_status; 889 pcie_ring_status_t pcie_ring_status; 890 tx_flowring_create_response_t txfl_create_resp; 891 tx_flowring_delete_response_t txfl_delete_resp; 892 tx_flowring_flush_response_t txfl_flush_resp; 893 ctrl_compl_msg_t ctrl_compl; 894 ring_config_resp_t ring_config_resp; 895 d2h_mailbox_data_t d2h_mailbox_data; 896 info_buf_resp_t dbg_resp; 897 h2d_ring_create_response_t h2d_ring_create_resp; 898 d2h_ring_create_response_t d2h_ring_create_resp; 899 host_timestamp_msg_cpl_t host_ts_cpl; 900 fw_timestamp_event_msg_t fw_ts_event; 901 h2d_ring_delete_response_t h2d_ring_delete_resp; 902 d2h_ring_delete_response_t d2h_ring_delete_resp; 903 unsigned char ctrl_response[D2HRING_CTRL_CMPLT_ITEMSIZE]; 904 } ctrl_completion_item_t; 905 906 /** H2D Rxpost ring work items */ 907 typedef struct host_rxbuf_post { 908 /** common message header */ 909 cmn_msg_hdr_t cmn_hdr; 910 /** provided meta data buffer len */ 911 uint16 metadata_buf_len; 912 /** provided data buffer len to receive data */ 913 uint16 data_buf_len; 914 /** alignment to make the host buffers start on 8 byte boundary */ 915 uint32 rsvd; 916 /** provided meta data buffer */ 917 bcm_addr64_t metadata_buf_addr; 918 /** provided data buffer to receive data */ 919 bcm_addr64_t data_buf_addr; 920 } host_rxbuf_post_t; 921 922 typedef union rxbuf_submit_item { 923 host_rxbuf_post_t rxpost; 924 unsigned char check[H2DRING_RXPOST_ITEMSIZE]; 925 } rxbuf_submit_item_t; 926 927 /* D2H Rxcompletion ring work items for IPC rev7 */ 928 typedef struct host_rxbuf_cmpl { 929 /** common message header */ 930 cmn_msg_hdr_t cmn_hdr; 931 /** completion message header */ 932 compl_msg_hdr_t compl_hdr; 933 /** filled up meta data len */ 934 uint16 metadata_len; 935 /** filled up buffer len to receive data */ 936 uint16 data_len; 937 /** offset in the host rx buffer where the data starts */ 938 uint16 data_offset; 939 /** offset in the host rx buffer where the data starts */ 940 uint16 flags; 941 /** rx status */ 942 uint32 rx_status_0; 943 uint32 rx_status_1; 944 945 union { /* size per IPC = (3 x uint32) bytes */ 946 struct { 947 /* used by Monitor mode */ 948 uint32 marker; 949 /* timestamp */ 950 ipc_timestamp_t ts; 951 }; 952 953 /* LatTS_With_XORCSUM */ 954 struct { 955 /* latency timestamp */ 956 pktts_t rx_pktts; 957 /* XOR checksum or a magic number to audit DMA done */ 958 dma_done_t marker_ext; 959 }; 960 }; 961 } host_rxbuf_cmpl_t; 962 963 typedef union rxbuf_complete_item { 964 host_rxbuf_cmpl_t rxcmpl; 965 unsigned char check[D2HRING_RXCMPLT_ITEMSIZE]; 966 } rxbuf_complete_item_t; 967 968 typedef struct host_txbuf_post { 969 /** common message header */ 970 cmn_msg_hdr_t cmn_hdr; 971 /** eth header */ 972 uint8 txhdr[ETHER_HDR_LEN]; 973 /** flags */ 974 uint8 flags; 975 /** number of segments */ 976 uint8 seg_cnt; 977 978 /** provided meta data buffer for txstatus */ 979 bcm_addr64_t metadata_buf_addr; 980 /** provided data buffer to receive data */ 981 bcm_addr64_t data_buf_addr; 982 /** provided meta data buffer len */ 983 uint16 metadata_buf_len; 984 /** provided data buffer len to receive data */ 985 uint16 data_len; 986 union { 987 struct { 988 /** extended transmit flags */ 989 uint8 ext_flags; 990 uint8 scale_factor; 991 992 /** user defined rate */ 993 uint8 rate; 994 uint8 exp_time; 995 }; 996 /** XOR checksum or a magic number to audit DMA done */ 997 dma_done_t marker; 998 }; 999 } host_txbuf_post_t; 1000 1001 #define BCMPCIE_PKT_FLAGS_FRAME_802_3 0x01 1002 #define BCMPCIE_PKT_FLAGS_FRAME_802_11 0x02 1003 1004 #define BCMPCIE_PKT_FLAGS_FRAME_NORETRY 0x01 /* Disable retry on this frame */ 1005 #define BCMPCIE_PKT_FLAGS_FRAME_NOAGGR \ 1006 0x02 /* Disable aggregation for this frame */ 1007 #define BCMPCIE_PKT_FLAGS_FRAME_UDR 0x04 /* User defined rate for this frame \ 1008 */ 1009 #define BCMPCIE_PKT_FLAGS_FRAME_ATTR_MASK 0x07 /* Attribute mask */ 1010 1011 #define BCMPCIE_PKT_FLAGS_FRAME_EXEMPT_MASK 0x03 /* Exempt uses 2 bits */ 1012 #define BCMPCIE_PKT_FLAGS_FRAME_EXEMPT_SHIFT \ 1013 0x02 /* needs to be shifted past other bits */ 1014 1015 #define BCMPCIE_PKT_FLAGS_EPOCH_SHIFT 3u 1016 #define BCMPCIE_PKT_FLAGS_EPOCH_MASK (1u << BCMPCIE_PKT_FLAGS_EPOCH_SHIFT) 1017 1018 #define BCMPCIE_PKT_FLAGS_PRIO_SHIFT 5 1019 #define BCMPCIE_PKT_FLAGS_PRIO_MASK (7 << BCMPCIE_PKT_FLAGS_PRIO_SHIFT) 1020 #define BCMPCIE_PKT_FLAGS_MONITOR_NO_AMSDU 0x00 1021 #define BCMPCIE_PKT_FLAGS_MONITOR_FIRST_PKT 0x01 1022 #define BCMPCIE_PKT_FLAGS_MONITOR_INTER_PKT 0x02 1023 #define BCMPCIE_PKT_FLAGS_MONITOR_LAST_PKT 0x03 1024 #define BCMPCIE_PKT_FLAGS_MONITOR_SHIFT 8 1025 #define BCMPCIE_PKT_FLAGS_MONITOR_MASK (3 << BCMPCIE_PKT_FLAGS_MONITOR_SHIFT) 1026 1027 /* These are added to fix up compile issues */ 1028 #define BCMPCIE_TXPOST_FLAGS_FRAME_802_3 BCMPCIE_PKT_FLAGS_FRAME_802_3 1029 #define BCMPCIE_TXPOST_FLAGS_FRAME_802_11 BCMPCIE_PKT_FLAGS_FRAME_802_11 1030 #define BCMPCIE_TXPOST_FLAGS_PRIO_SHIFT BCMPCIE_PKT_FLAGS_PRIO_SHIFT 1031 #define BCMPCIE_TXPOST_FLAGS_PRIO_MASK BCMPCIE_PKT_FLAGS_PRIO_MASK 1032 1033 /* H2D Txpost ring work items */ 1034 typedef union txbuf_submit_item { 1035 host_txbuf_post_t txpost; 1036 unsigned char check[H2DRING_TXPOST_ITEMSIZE]; 1037 } txbuf_submit_item_t; 1038 1039 /* D2H Txcompletion ring work items - extended for IOC rev7 */ 1040 typedef struct host_txbuf_cmpl { 1041 /** common message header */ 1042 cmn_msg_hdr_t cmn_hdr; 1043 /** completion message header */ 1044 compl_msg_hdr_t compl_hdr; 1045 1046 union { /* size per IPC = (3 x uint32) bytes */ 1047 /* Usage 1: TxS_With_TimeSync */ 1048 struct { 1049 struct { 1050 union { 1051 /** provided meta data len */ 1052 uint16 metadata_len; 1053 /** provided extended TX status */ 1054 uint16 tx_status_ext; 1055 }; /* Ext_TxStatus */ 1056 1057 /** WLAN side txstatus */ 1058 uint16 tx_status; 1059 }; /* TxS */ 1060 /* timestamp */ 1061 ipc_timestamp_t ts; 1062 }; /* TxS_with_TS */ 1063 1064 /* Usage 2: LatTS_With_XORCSUM */ 1065 struct { 1066 /* latency timestamp */ 1067 pktts_t tx_pktts; 1068 /* XOR checksum or a magic number to audit DMA done */ 1069 dma_done_t marker_ext; 1070 }; 1071 }; 1072 } host_txbuf_cmpl_t; 1073 1074 typedef union txbuf_complete_item { 1075 host_txbuf_cmpl_t txcmpl; 1076 unsigned char check[D2HRING_TXCMPLT_ITEMSIZE]; 1077 } txbuf_complete_item_t; 1078 1079 #define PCIE_METADATA_VER 1u 1080 1081 /* version and length are not part of this structure. 1082 * dhd queries version and length through bus iovar "bus:metadata_info". 1083 */ 1084 struct metadata_txcmpl_v1 { 1085 uint32 tref; /* TSF or Ref Clock in uSecs */ 1086 uint16 d_t2; /* T2-fwt1 delta */ 1087 uint16 d_t3; /* T3-fwt1 delta */ 1088 uint16 d_t4; /* T4-fwt1 delta */ 1089 uint16 rsvd; /* reserved */ 1090 }; 1091 typedef struct metadata_txcmpl_v1 metadata_txcmpl_t; 1092 1093 #define BCMPCIE_D2H_METADATA_HDRLEN 4 1094 #define BCMPCIE_D2H_METADATA_MINLEN (BCMPCIE_D2H_METADATA_HDRLEN + 4) 1095 1096 /** ret buf struct */ 1097 typedef struct ret_buf_ptr { 1098 uint32 low_addr; 1099 uint32 high_addr; 1100 } ret_buf_t; 1101 1102 #ifdef PCIE_API_REV1 1103 1104 /* ioctl specific hdr */ 1105 typedef struct ioctl_hdr { 1106 uint16 cmd; 1107 uint16 retbuf_len; 1108 uint32 cmd_id; 1109 } ioctl_hdr_t; 1110 1111 typedef struct ioctlptr_hdr { 1112 uint16 cmd; 1113 uint16 retbuf_len; 1114 uint16 buflen; 1115 uint16 rsvd; 1116 uint32 cmd_id; 1117 } ioctlptr_hdr_t; 1118 1119 #else /* PCIE_API_REV1 */ 1120 1121 typedef struct ioctl_req_hdr { 1122 uint32 pkt_id; /**< Packet ID */ 1123 uint32 cmd; /**< IOCTL ID */ 1124 uint16 retbuf_len; 1125 uint16 buflen; 1126 uint16 xt_id; /**< transaction ID */ 1127 uint16 rsvd[1]; 1128 } ioctl_req_hdr_t; 1129 1130 #endif /* PCIE_API_REV1 */ 1131 1132 /** Complete msgbuf hdr for ioctl from host to dongle */ 1133 typedef struct ioct_reqst_hdr { 1134 cmn_msg_hdr_t msg; 1135 #ifdef PCIE_API_REV1 1136 ioctl_hdr_t ioct_hdr; 1137 #else 1138 ioctl_req_hdr_t ioct_hdr; 1139 #endif // endif 1140 ret_buf_t ret_buf; 1141 } ioct_reqst_hdr_t; 1142 1143 typedef struct ioctptr_reqst_hdr { 1144 cmn_msg_hdr_t msg; 1145 #ifdef PCIE_API_REV1 1146 ioctlptr_hdr_t ioct_hdr; 1147 #else 1148 ioctl_req_hdr_t ioct_hdr; 1149 #endif // endif 1150 ret_buf_t ret_buf; 1151 ret_buf_t ioct_buf; 1152 } ioctptr_reqst_hdr_t; 1153 1154 /** ioctl response header */ 1155 typedef struct ioct_resp_hdr { 1156 cmn_msg_hdr_t msg; 1157 #ifdef PCIE_API_REV1 1158 uint32 cmd_id; 1159 #else 1160 uint32 pkt_id; 1161 #endif // endif 1162 uint32 status; 1163 uint32 ret_len; 1164 uint32 inline_data; 1165 #ifdef PCIE_API_REV1 1166 #else 1167 uint16 xt_id; /**< transaction ID */ 1168 uint16 rsvd[1]; 1169 #endif // endif 1170 } ioct_resp_hdr_t; 1171 1172 /* ioct resp header used in dongle */ 1173 /* ret buf hdr will be stripped off inside dongle itself */ 1174 typedef struct msgbuf_ioctl_resp { 1175 ioct_resp_hdr_t ioct_hdr; 1176 ret_buf_t ret_buf; /**< ret buf pointers */ 1177 } msgbuf_ioct_resp_t; 1178 1179 /** WL event hdr info */ 1180 typedef struct wl_event_hdr { 1181 cmn_msg_hdr_t msg; 1182 uint16 event; 1183 uint8 flags; 1184 uint8 rsvd; 1185 uint16 retbuf_len; 1186 uint16 rsvd1; 1187 uint32 rxbufid; 1188 } wl_event_hdr_t; 1189 1190 #define TXDESCR_FLOWID_PCIELPBK_1 0xFF 1191 #define TXDESCR_FLOWID_PCIELPBK_2 0xFE 1192 1193 typedef struct txbatch_lenptr_tup { 1194 uint32 pktid; 1195 uint16 pktlen; 1196 uint16 rsvd; 1197 ret_buf_t ret_buf; /**< ret buf pointers */ 1198 } txbatch_lenptr_tup_t; 1199 1200 typedef struct txbatch_cmn_msghdr { 1201 cmn_msg_hdr_t msg; 1202 uint8 priority; 1203 uint8 hdrlen; 1204 uint8 pktcnt; 1205 uint8 flowid; 1206 uint8 txhdr[ETHER_HDR_LEN]; 1207 uint16 rsvd; 1208 } txbatch_cmn_msghdr_t; 1209 1210 typedef struct txbatch_msghdr { 1211 txbatch_cmn_msghdr_t txcmn; 1212 txbatch_lenptr_tup_t tx_tup[0]; /**< Based on packet count */ 1213 } txbatch_msghdr_t; 1214 1215 /* TX desc posting header */ 1216 typedef struct tx_lenptr_tup { 1217 uint16 pktlen; 1218 uint16 rsvd; 1219 ret_buf_t ret_buf; /**< ret buf pointers */ 1220 } tx_lenptr_tup_t; 1221 1222 typedef struct txdescr_cmn_msghdr { 1223 cmn_msg_hdr_t msg; 1224 uint8 priority; 1225 uint8 hdrlen; 1226 uint8 descrcnt; 1227 uint8 flowid; 1228 uint32 pktid; 1229 } txdescr_cmn_msghdr_t; 1230 1231 typedef struct txdescr_msghdr { 1232 txdescr_cmn_msghdr_t txcmn; 1233 uint8 txhdr[ETHER_HDR_LEN]; 1234 uint16 rsvd; 1235 tx_lenptr_tup_t tx_tup[0]; /**< Based on descriptor count */ 1236 } txdescr_msghdr_t; 1237 1238 /** Tx status header info */ 1239 typedef struct txstatus_hdr { 1240 cmn_msg_hdr_t msg; 1241 uint32 pktid; 1242 } txstatus_hdr_t; 1243 1244 /** RX bufid-len-ptr tuple */ 1245 typedef struct rx_lenptr_tup { 1246 uint32 rxbufid; 1247 uint16 len; 1248 uint16 rsvd2; 1249 ret_buf_t ret_buf; /**< ret buf pointers */ 1250 } rx_lenptr_tup_t; 1251 1252 /** Rx descr Post hdr info */ 1253 typedef struct rxdesc_msghdr { 1254 cmn_msg_hdr_t msg; 1255 uint16 rsvd0; 1256 uint8 rsvd1; 1257 uint8 descnt; 1258 rx_lenptr_tup_t rx_tup[0]; 1259 } rxdesc_msghdr_t; 1260 1261 /** RX complete tuples */ 1262 typedef struct rxcmplt_tup { 1263 uint16 retbuf_len; 1264 uint16 data_offset; 1265 uint32 rxstatus0; 1266 uint32 rxstatus1; 1267 uint32 rxbufid; 1268 } rxcmplt_tup_t; 1269 1270 /** RX complete messge hdr */ 1271 typedef struct rxcmplt_hdr { 1272 cmn_msg_hdr_t msg; 1273 uint16 rsvd0; 1274 uint16 rxcmpltcnt; 1275 rxcmplt_tup_t rx_tup[0]; 1276 } rxcmplt_hdr_t; 1277 1278 typedef struct hostevent_hdr { 1279 cmn_msg_hdr_t msg; 1280 uint32 evnt_pyld; 1281 } hostevent_hdr_t; 1282 1283 typedef struct dma_xfer_params { 1284 uint32 src_physaddr_hi; 1285 uint32 src_physaddr_lo; 1286 uint32 dest_physaddr_hi; 1287 uint32 dest_physaddr_lo; 1288 uint32 len; 1289 uint32 srcdelay; 1290 uint32 destdelay; 1291 } dma_xfer_params_t; 1292 1293 enum { HOST_EVENT_CONS_CMD = 1 }; 1294 1295 /* defines for flags */ 1296 #define MSGBUF_IOC_ACTION_MASK 0x1 1297 1298 #define MAX_SUSPEND_REQ 15 1299 1300 typedef struct tx_idle_flowring_suspend_request { 1301 cmn_msg_hdr_t msg; 1302 uint16 ring_id[MAX_SUSPEND_REQ]; /* ring Id's */ 1303 uint16 num; /* number of flowid's to suspend */ 1304 } tx_idle_flowring_suspend_request_t; 1305 1306 typedef struct tx_idle_flowring_suspend_response { 1307 cmn_msg_hdr_t msg; 1308 compl_msg_hdr_t cmplt; 1309 uint32 rsvd[2]; 1310 dma_done_t marker; 1311 } tx_idle_flowring_suspend_response_t; 1312 1313 typedef struct tx_idle_flowring_resume_request { 1314 cmn_msg_hdr_t msg; 1315 uint16 flow_ring_id; 1316 uint16 reason; 1317 uint32 rsvd[7]; 1318 } tx_idle_flowring_resume_request_t; 1319 1320 typedef struct tx_idle_flowring_resume_response { 1321 cmn_msg_hdr_t msg; 1322 compl_msg_hdr_t cmplt; 1323 uint32 rsvd[2]; 1324 dma_done_t marker; 1325 } tx_idle_flowring_resume_response_t; 1326 1327 /* timesync related additions */ 1328 1329 typedef struct _bcm_xtlv { 1330 uint16 id; /* TLV idenitifier */ 1331 uint16 len; /* TLV length in bytes */ 1332 } _bcm_xtlv_t; 1333 1334 #define BCMMSGBUF_FW_CLOCK_INFO_TAG 0 1335 #define BCMMSGBUF_HOST_CLOCK_INFO_TAG 1 1336 #define BCMMSGBUF_HOST_CLOCK_SELECT_TAG 2 1337 #define BCMMSGBUF_D2H_CLOCK_CORRECTION_TAG 3 1338 #define BCMMSGBUF_HOST_TIMESTAMPING_CONFIG_TAG 4 1339 #define BCMMSGBUF_MAX_TSYNC_TAG 5 1340 1341 /* Flags in fw clock info TLV */ 1342 #define CAP_DEVICE_TS (1 << 0) 1343 #define CAP_CORRECTED_TS (1 << 1) 1344 #define TS_CLK_ACTIVE (1 << 2) 1345 1346 typedef struct ts_fw_clock_info { 1347 _bcm_xtlv_t xtlv; /* BCMMSGBUF_FW_CLOCK_INFO_TAG */ 1348 ts_timestamp_srcid_t ts; /* tick count */ 1349 uchar clk_src[4]; /* clock source acronym ILP/AVB/TSF */ 1350 uint32 nominal_clock_freq; 1351 uint32 reset_cnt; 1352 uint8 flags; 1353 uint8 rsvd[3]; 1354 } ts_fw_clock_info_t; 1355 1356 typedef struct ts_host_clock_info { 1357 _bcm_xtlv_t xtlv; /* BCMMSGBUF_HOST_CLOCK_INFO_TAG */ 1358 tick_count_64_t ticks; /* 64 bit host tick counter */ 1359 ts_timestamp_ns_64_t ns; /* 64 bit host time in nano seconds */ 1360 } ts_host_clock_info_t; 1361 1362 typedef struct ts_host_clock_sel { 1363 _bcm_xtlv_t xtlv; /* BCMMSGBUF_HOST_CLOCK_SELECT_TAG */ 1364 uint32 seqnum; /* number of times GPIO time sync toggled */ 1365 uint8 1366 min_clk_idx; /* clock idenitifer configured for packet tiem stamping */ 1367 uint8 1368 max_clk_idx; /* clock idenitifer configured for packet tiem stamping */ 1369 uint16 rsvd[1]; 1370 } ts_host_clock_sel_t; 1371 1372 typedef struct ts_d2h_clock_correction { 1373 _bcm_xtlv_t xtlv; /* BCMMSGBUF_HOST_CLOCK_INFO_TAG */ 1374 uint8 clk_id; /* clock source in the device */ 1375 uint8 rsvd[3]; 1376 ts_correction_m_t m; /* y = 'm' x + b */ 1377 ts_correction_b_t b; /* y = 'm' x + 'c' */ 1378 } ts_d2h_clock_correction_t; 1379 1380 typedef struct ts_host_timestamping_config { 1381 _bcm_xtlv_t xtlv; /* BCMMSGBUF_HOST_TIMESTAMPING_CONFIG_TAG */ 1382 /* time period to capture the device time stamp and toggle 1383 * WLAN_TIME_SYNC_GPIO */ 1384 uint16 period_ms; 1385 uint8 flags; 1386 uint8 post_delay; 1387 uint32 reset_cnt; 1388 } ts_host_timestamping_config_t; 1389 1390 /* Flags in host timestamping config TLV */ 1391 #define FLAG_HOST_RESET (1 << 0) 1392 #define IS_HOST_RESET(x) ((x)&FLAG_HOST_RESET) 1393 #define CLEAR_HOST_RESET(x) ((x) & ~FLAG_HOST_RESET) 1394 1395 #define FLAG_CONFIG_NODROP (1 << 1) 1396 #define IS_CONFIG_NODROP(x) ((x)&FLAG_CONFIG_NODROP) 1397 #define CLEAR_CONFIG_NODROP(x) ((x) & ~FLAG_CONFIG_NODROP) 1398 1399 #endif /* _bcmmsgbuf_h_ */ 1400