1 /* 2 * Broadcom PCIE 3 * Software-specific definitions shared between device and host side 4 * Explains the shared area between host and dongle 5 * 6 * Copyright (C) 1999-2019, Broadcom. 7 * 8 * Unless you and Broadcom execute a separate written software license 9 * agreement governing use of this software, this software is licensed to you 10 * under the terms of the GNU General Public License version 2 (the "GPL"), 11 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 12 * following added to such license: 13 * 14 * As a special exception, the copyright holders of this software give you 15 * permission to link this software with independent modules, and to copy and 16 * distribute the resulting executable under terms of your choice, provided that 17 * you also meet, for each linked independent module, the terms and conditions 18 * of the license of that module. An independent module is a module which is 19 * not derived from this software. The special exception does not apply to any 20 * modifications of the software. 21 * 22 * Notwithstanding the above, under no circumstances may you combine this 23 * software in any way with any other Broadcom software provided under a license 24 * other than the GPL, without Broadcom's express prior written consent. 25 * 26 * 27 * <<Broadcom-WL-IPTag/Open:>> 28 * 29 * $Id: bcmpcie.h 821465 2019-05-23 19:50:00Z $ 30 */ 31 32 #ifndef _bcmpcie_h_ 33 #define _bcmpcie_h_ 34 35 #include <typedefs.h> 36 37 #define ADDR_64(x) (x.addr) 38 #define HIGH_ADDR_32(x) ((uint32)(((sh_addr_t)x).high_addr)) 39 #define LOW_ADDR_32(x) ((uint32)(((sh_addr_t)x).low_addr)) 40 41 typedef struct { 42 uint32 low_addr; 43 uint32 high_addr; 44 } sh_addr_t; 45 46 /* May be overridden by 43xxxxx-roml.mk */ 47 #if !defined(BCMPCIE_MAX_TX_FLOWS) 48 #define BCMPCIE_MAX_TX_FLOWS 40 49 #endif /* ! BCMPCIE_MAX_TX_FLOWS */ 50 51 #define PCIE_SHARED_VERSION_7 0x00007 52 #define PCIE_SHARED_VERSION_6 0x00006 /* rev6 is compatible with rev 5 */ 53 #define PCIE_SHARED_VERSION_5 0x00005 /* rev6 is compatible with rev 5 */ 54 /** 55 * Feature flags enabled in dongle. Advertised by dongle to DHD via the PCIe 56 * Shared structure that is located in device memory. 57 */ 58 #define PCIE_SHARED_VERSION_MASK 0x000FF 59 #define PCIE_SHARED_ASSERT_BUILT 0x00100 60 #define PCIE_SHARED_ASSERT 0x00200 61 #define PCIE_SHARED_TRAP 0x00400 62 #define PCIE_SHARED_IN_BRPT 0x00800 63 #define PCIE_SHARED_SET_BRPT 0x01000 64 #define PCIE_SHARED_PENDING_BRPT 0x02000 65 /* BCMPCIE_SUPPORT_TX_PUSH_RING 0x04000 obsolete */ 66 #define PCIE_SHARED_EVT_SEQNUM 0x08000 67 #define PCIE_SHARED_DMA_INDEX 0x10000 68 69 /** 70 * There are host types where a device interrupt can 'race ahead' of data 71 * written by the device into host memory. The dongle can avoid this condition 72 * using a variety of techniques (read barrier, using PCIe Message Signalled 73 * Interrupts, or by using the PCIE_DMA_INDEX feature). Unfortunately these 74 * techniques have drawbacks on router platforms. For these platforms, it was 75 * decided to not avoid the condition, but to detect the condition instead and 76 * act on it. D2H M2M DMA Complete Sync mechanism: Modulo-253-SeqNum or XORCSUM 77 */ 78 #define PCIE_SHARED_D2H_SYNC_SEQNUM 0x20000 79 #define PCIE_SHARED_D2H_SYNC_XORCSUM 0x40000 80 #define PCIE_SHARED_D2H_SYNC_MODE_MASK \ 81 (PCIE_SHARED_D2H_SYNC_SEQNUM | PCIE_SHARED_D2H_SYNC_XORCSUM) 82 #define PCIE_SHARED_IDLE_FLOW_RING 0x80000 83 #define PCIE_SHARED_2BYTE_INDICES 0x100000 84 85 #define PCIE_SHARED_FAST_DELETE_RING 0x00000020 /* Fast Delete Ring */ 86 #define PCIE_SHARED_EVENT_BUF_POOL_MAX \ 87 0x000000c0 /* event buffer pool max bits */ 88 #define PCIE_SHARED_EVENT_BUF_POOL_MAX_POS \ 89 6 /* event buffer pool max bit position */ 90 91 /* dongle supports fatal buf log collection */ 92 #define PCIE_SHARED_FATAL_LOGBUG_VALID 0x200000 93 94 /* Implicit DMA with corerev 19 and after */ 95 #define PCIE_SHARED_IDMA 0x400000 96 97 /* MSI support */ 98 #define PCIE_SHARED_D2H_MSI_MULTI_MSG 0x800000 99 100 /* IFRM with corerev 19 and after */ 101 #define PCIE_SHARED_IFRM 0x1000000 102 103 /** 104 * From Rev6 and above, suspend/resume can be done using two handshake methods. 105 * 1. Using ctrl post/ctrl cmpl messages (Default rev6) 106 * 2. Using Mailbox data (old method as used in rev5) 107 * This shared flag indicates whether to overide rev6 default method and use 108 * mailbox for suspend/resume. 109 */ 110 #define PCIE_SHARED_USE_MAILBOX 0x2000000 111 112 /* Firmware compiled for mfgbuild purposes */ 113 #define PCIE_SHARED_MFGBUILD_FW 0x4000000 114 115 /* Firmware could use DB0 value as host timestamp */ 116 #define PCIE_SHARED_TIMESTAMP_DB0 0x8000000 117 /* Firmware could use Hostready (IPC rev7) */ 118 #define PCIE_SHARED_HOSTRDY_SUPPORT 0x10000000 119 120 /* When set, Firmwar does not support OOB Device Wake based DS protocol */ 121 #define PCIE_SHARED_NO_OOB_DW 0x20000000 122 123 /* When set, Firmwar supports Inband DS protocol */ 124 #define PCIE_SHARED_INBAND_DS 0x40000000 125 126 /* use DAR registers */ 127 #define PCIE_SHARED_DAR 0x80000000 128 129 /** 130 * Following are the shared2 flags. All bits in flags have been used. A flags2 131 * field got added and the definition for these flags come here: 132 */ 133 /* WAR: D11 txstatus through unused status field of PCIe completion header */ 134 #define PCIE_SHARED2_EXTENDED_TRAP_DATA \ 135 0x00000001 /* using flags2 in shared area */ 136 #define PCIE_SHARED2_TXSTATUS_METADATA 0x00000002 137 #define PCIE_SHARED2_BT_LOGGING 0x00000004 /* BT logging support */ 138 #define PCIE_SHARED2_SNAPSHOT_UPLOAD \ 139 0x00000008 /* BT/WLAN snapshot upload support */ 140 #define PCIE_SHARED2_SUBMIT_COUNT_WAR 0x00000010 /* submission count WAR */ 141 #define PCIE_SHARED2_FAST_DELETE_RING 0x00000020 /* Fast Delete ring support \ 142 */ 143 #define PCIE_SHARED2_EVTBUF_MAX_MASK 0x000000C0 /* 0:32, 1:64, 2:128, 3: 256 \ 144 */ 145 146 /* using flags2 to indicate firmware support added to reuse timesync to update 147 * PKT txstatus */ 148 #define PCIE_SHARED2_PKT_TX_STATUS 0x00000100 149 #define PCIE_SHARED2_FW_SMALL_MEMDUMP 0x00000200 /* FW small memdump */ 150 #define PCIE_SHARED2_FW_HC_ON_TRAP 0x00000400 151 #define PCIE_SHARED2_HSCB 0x00000800 /* Host SCB support */ 152 153 #define PCIE_SHARED2_EDL_RING 0x00001000 /* Support Enhanced Debug Lane */ 154 #define PCIE_SHARED2_DEBUG_BUF_DEST 0x00002000 /* debug buf dest support */ 155 #define PCIE_SHARED2_PCIE_ENUM_RESET_FLR \ 156 0x00004000 /* BT producer index reset WAR */ 157 #define PCIE_SHARED2_PKT_TIMESTAMP 0x00008000 /* Timestamp in packet */ 158 159 #define PCIE_SHARED2_HP2P 0x00010000u /* HP2P feature */ 160 #define PCIE_SHARED2_HWA 0x00020000u /* HWA feature */ 161 #define PCIE_SHARED2_TRAP_ON_HOST_DB7 \ 162 0x00040000u /* can take a trap on DB7 from host */ 163 164 #define PCIE_SHARED2_DURATION_SCALE 0x00100000u 165 166 #define PCIE_SHARED2_D2H_D11_TX_STATUS 0x40000000 167 #define PCIE_SHARED2_H2D_D11_TX_STATUS 0x80000000 168 169 #define PCIE_SHARED_D2H_MAGIC 0xFEDCBA09 170 #define PCIE_SHARED_H2D_MAGIC 0x12345678 171 172 typedef uint16 pcie_hwa_db_index_t; /* 16 bit HWA index (IPC Rev 7) */ 173 #define PCIE_HWA_DB_INDEX_SZ (2u) /* 2 bytes sizeof(pcie_hwa_db_index_t) */ 174 175 /** 176 * Message rings convey messages between host and device. They are 177 * unidirectional, and are located in host memory. 178 * 179 * This is the minimal set of message rings, known as 'common message rings': 180 */ 181 #define BCMPCIE_H2D_MSGRING_CONTROL_SUBMIT 0 182 #define BCMPCIE_H2D_MSGRING_RXPOST_SUBMIT 1 183 #define BCMPCIE_D2H_MSGRING_CONTROL_COMPLETE 2 184 #define BCMPCIE_D2H_MSGRING_TX_COMPLETE 3 185 #define BCMPCIE_D2H_MSGRING_RX_COMPLETE 4 186 #define BCMPCIE_COMMON_MSGRING_MAX_ID 4 187 188 #define BCMPCIE_H2D_COMMON_MSGRINGS 2 189 #define BCMPCIE_D2H_COMMON_MSGRINGS 3 190 #define BCMPCIE_COMMON_MSGRINGS 5 191 192 #define BCMPCIE_H2D_MSGRINGS(max_tx_flows) \ 193 (BCMPCIE_H2D_COMMON_MSGRINGS + (max_tx_flows)) 194 195 /* different ring types */ 196 #define BCMPCIE_H2D_RING_TYPE_CTRL_SUBMIT 0x1 197 #define BCMPCIE_H2D_RING_TYPE_TXFLOW_RING 0x2 198 #define BCMPCIE_H2D_RING_TYPE_RXBUFPOST 0x3 199 #define BCMPCIE_H2D_RING_TYPE_TXSUBMIT 0x4 200 #define BCMPCIE_H2D_RING_TYPE_DBGBUF_SUBMIT 0x5 201 #define BCMPCIE_H2D_RING_TYPE_BTLOG_SUBMIT 0x6 202 203 #define BCMPCIE_D2H_RING_TYPE_CTRL_CPL 0x1 204 #define BCMPCIE_D2H_RING_TYPE_TX_CPL 0x2 205 #define BCMPCIE_D2H_RING_TYPE_RX_CPL 0x3 206 #define BCMPCIE_D2H_RING_TYPE_DBGBUF_CPL 0x4 207 #define BCMPCIE_D2H_RING_TYPE_AC_RX_COMPLETE 0x5 208 #define BCMPCIE_D2H_RING_TYPE_BTLOG_CPL 0x6 209 #define BCMPCIE_D2H_RING_TYPE_EDL 0x7 210 #define BCMPCIE_D2H_RING_TYPE_HPP_TX_CPL 0x8 211 #define BCMPCIE_D2H_RING_TYPE_HPP_RX_CPL 0x9 212 213 /** 214 * H2D and D2H, WR and RD index, are maintained in the following arrays: 215 * - Array of all H2D WR Indices 216 * - Array of all H2D RD Indices 217 * - Array of all D2H WR Indices 218 * - Array of all D2H RD Indices 219 * 220 * The offset of the WR or RD indexes (for common rings) in these arrays are 221 * listed below. Arrays ARE NOT indexed by a ring's id. 222 * 223 * D2H common rings WR and RD index start from 0, even though their ringids 224 * start from BCMPCIE_H2D_COMMON_MSGRINGS 225 */ 226 227 #define BCMPCIE_H2D_RING_IDX(h2d_ring_id) (h2d_ring_id) 228 229 enum h2dring_idx { 230 /* H2D common rings */ 231 BCMPCIE_H2D_MSGRING_CONTROL_SUBMIT_IDX = 232 BCMPCIE_H2D_RING_IDX(BCMPCIE_H2D_MSGRING_CONTROL_SUBMIT), 233 BCMPCIE_H2D_MSGRING_RXPOST_SUBMIT_IDX = 234 BCMPCIE_H2D_RING_IDX(BCMPCIE_H2D_MSGRING_RXPOST_SUBMIT), 235 236 /* First TxPost's WR or RD index starts after all H2D common rings */ 237 BCMPCIE_H2D_MSGRING_TXFLOW_IDX_START = 238 BCMPCIE_H2D_RING_IDX(BCMPCIE_H2D_COMMON_MSGRINGS) 239 }; 240 241 #define BCMPCIE_D2H_RING_IDX(d2h_ring_id) \ 242 ((d2h_ring_id) - BCMPCIE_H2D_COMMON_MSGRINGS) 243 244 enum d2hring_idx { 245 /* D2H Common Rings */ 246 BCMPCIE_D2H_MSGRING_CONTROL_COMPLETE_IDX = 247 BCMPCIE_D2H_RING_IDX(BCMPCIE_D2H_MSGRING_CONTROL_COMPLETE), 248 BCMPCIE_D2H_MSGRING_TX_COMPLETE_IDX = 249 BCMPCIE_D2H_RING_IDX(BCMPCIE_D2H_MSGRING_TX_COMPLETE), 250 BCMPCIE_D2H_MSGRING_RX_COMPLETE_IDX = 251 BCMPCIE_D2H_RING_IDX(BCMPCIE_D2H_MSGRING_RX_COMPLETE) 252 }; 253 254 /** 255 * Macros for managing arrays of RD WR indices: 256 * rw_index_sz: 257 * - in dongle, rw_index_sz is known at compile time 258 * - in host/DHD, rw_index_sz is derived from advertized pci_shared flags 259 * 260 * ring_idx: See h2dring_idx and d2hring_idx 261 */ 262 263 /** Offset of a RD or WR index in H2D or D2H indices array */ 264 #define BCMPCIE_RW_INDEX_OFFSET(rw_index_sz, ring_idx) \ 265 ((rw_index_sz) * (ring_idx)) 266 267 /** Fetch the address of RD or WR index in H2D or D2H indices array */ 268 #define BCMPCIE_RW_INDEX_ADDR(indices_array_base, rw_index_sz, ring_idx) \ 269 (void *)((uint32)(indices_array_base) + \ 270 BCMPCIE_RW_INDEX_OFFSET((rw_index_sz), (ring_idx))) 271 272 /** H2D DMA Indices array size: given max flow rings */ 273 #define BCMPCIE_H2D_RW_INDEX_ARRAY_SZ(rw_index_sz, max_tx_flows) \ 274 ((rw_index_sz)*BCMPCIE_H2D_MSGRINGS(max_tx_flows)) 275 276 /** D2H DMA Indices array size */ 277 #define BCMPCIE_D2H_RW_INDEX_ARRAY_SZ(rw_index_sz) \ 278 ((rw_index_sz)*BCMPCIE_D2H_COMMON_MSGRINGS) 279 280 /** 281 * This type is used by a 'message buffer' (which is a FIFO for messages). 282 * Message buffers are used for host<->device communication and are instantiated 283 * on both sides. ring_mem_t is instantiated both in host as well as device 284 * memory. 285 */ 286 typedef struct ring_mem { 287 uint16 idx; /* ring id */ 288 uint8 type; 289 uint8 rsvd; 290 uint16 max_item; /* Max number of items in flow ring */ 291 uint16 len_items; /* Items are fixed size. Length in bytes of one item */ 292 sh_addr_t base_addr; /* 64 bits address, either in host or device memory */ 293 } ring_mem_t; 294 295 /** 296 * Per flow ring, information is maintained in device memory, eg at what address 297 * the ringmem and ringstate are located. The flow ring itself can be 298 * instantiated in either host or device memory. 299 * 300 * Perhaps this type should be renamed to make clear that it resides in device 301 * memory only. 302 */ 303 typedef struct ring_info { 304 uint32 ringmem_ptr; /* ring mem location in dongle memory */ 305 306 /* Following arrays are indexed using h2dring_idx and d2hring_idx, and not 307 * by a ringid. 308 */ 309 310 /* 32bit ptr to arrays of WR or RD indices for all rings in dongle memory */ 311 uint32 h2d_w_idx_ptr; /* Array of all H2D ring's WR indices */ 312 uint32 h2d_r_idx_ptr; /* Array of all H2D ring's RD indices */ 313 uint32 d2h_w_idx_ptr; /* Array of all D2H ring's WR indices */ 314 uint32 d2h_r_idx_ptr; /* Array of all D2H ring's RD indices */ 315 316 /* PCIE_DMA_INDEX feature: Dongle uses mem2mem DMA to sync arrays in host. 317 * Host may directly fetch WR and RD indices from these host-side arrays. 318 * 319 * 64bit ptr to arrays of WR or RD indices for all rings in host memory. 320 */ 321 sh_addr_t h2d_w_idx_hostaddr; /* Array of all H2D ring's WR indices */ 322 sh_addr_t h2d_r_idx_hostaddr; /* Array of all H2D ring's RD indices */ 323 sh_addr_t d2h_w_idx_hostaddr; /* Array of all D2H ring's WR indices */ 324 sh_addr_t d2h_r_idx_hostaddr; /* Array of all D2H ring's RD indices */ 325 326 uint16 max_tx_flowrings; /* maximum number of H2D rings: common + flow */ 327 uint16 328 max_submission_queues; /* maximum number of H2D rings: common + flow */ 329 uint16 330 max_completion_rings; /* maximum number of H2D rings: common + flow */ 331 uint16 max_vdevs; /* max number of virtual interfaces supported */ 332 333 sh_addr_t 334 ifrm_w_idx_hostaddr; /* Array of all H2D ring's WR indices for IFRM */ 335 336 /* 32bit ptr to arrays of HWA DB indices for all rings in dongle memory */ 337 uint32 h2d_hwa_db_idx_ptr; /* Array of all H2D ring's HWA DB indices */ 338 uint32 d2h_hwa_db_idx_ptr; /* Array of all D2H ring's HWA DB indices */ 339 } ring_info_t; 340 341 /** 342 * A structure located in TCM that is shared between host and device, primarily 343 * used during initialization. 344 */ 345 typedef struct { 346 /** shared area version captured at flags 7:0 */ 347 uint32 flags; 348 349 uint32 trap_addr; 350 uint32 assert_exp_addr; 351 uint32 assert_file_addr; 352 uint32 assert_line; 353 uint32 console_addr; /**< Address of hnd_cons_t */ 354 355 uint32 msgtrace_addr; 356 357 uint32 fwid; 358 359 /* Used for debug/flow control */ 360 uint16 total_lfrag_pkt_cnt; 361 uint16 max_host_rxbufs; /* rsvd in spec */ 362 363 uint32 dma_rxoffset; /* rsvd in spec */ 364 365 /** these will be used for sleep request/ack, d3 req/ack */ 366 uint32 h2d_mb_data_ptr; 367 uint32 d2h_mb_data_ptr; 368 369 /* information pertinent to host IPC/msgbuf channels */ 370 /** location in the TCM memory which has the ring_info */ 371 uint32 rings_info_ptr; 372 373 /** block of host memory for the scratch buffer */ 374 uint32 host_dma_scratch_buffer_len; 375 sh_addr_t host_dma_scratch_buffer; 376 377 /* location in host memory for scb host offload structures */ 378 sh_addr_t host_scb_addr; 379 uint32 host_scb_size; 380 381 /* anonymous union for overloading fields in structure */ 382 union { 383 uint32 buzz_dbg_ptr; /* BUZZZ state format strings and trace buffer */ 384 struct { 385 /* Host provided trap buffer length in words */ 386 uint16 device_trap_debug_buffer_len; 387 uint16 rsvd2; 388 }; 389 }; 390 391 /* rev6 compatible changes */ 392 uint32 flags2; 393 uint32 host_cap; 394 395 /* location in the host address space to write trap indication. 396 * At this point for the current rev of the spec, firmware will 397 * support only indications to 32 bit host addresses. 398 * This essentially is device_trap_debug_buffer_addr 399 */ 400 sh_addr_t host_trap_addr; 401 402 /* location for host fatal error log buffer start address */ 403 uint32 device_fatal_logbuf_start; 404 405 /* location in host memory for offloaded modules */ 406 sh_addr_t hoffload_addr; 407 uint32 flags3; 408 uint32 host_cap2; 409 uint32 host_cap3; 410 } pciedev_shared_t; 411 412 /* Device F/W provides the following access function: 413 * pciedev_shared_t *hnd_get_pciedev_shared(void); 414 */ 415 416 /* host capabilities */ 417 #define HOSTCAP_PCIEAPI_VERSION_MASK 0x000000FF 418 #define HOSTCAP_H2D_VALID_PHASE 0x00000100 419 #define HOSTCAP_H2D_ENABLE_TRAP_ON_BADPHASE 0x00000200 420 #define HOSTCAP_H2D_ENABLE_HOSTRDY 0x00000400 421 #define HOSTCAP_DB0_TIMESTAMP 0x00000800 422 #define HOSTCAP_DS_NO_OOB_DW 0x00001000 423 #define HOSTCAP_DS_INBAND_DW 0x00002000 424 #define HOSTCAP_H2D_IDMA 0x00004000 425 #define HOSTCAP_H2D_IFRM 0x00008000 426 #define HOSTCAP_H2D_DAR 0x00010000 427 #define HOSTCAP_EXTENDED_TRAP_DATA 0x00020000 428 #define HOSTCAP_TXSTATUS_METADATA 0x00040000 429 #define HOSTCAP_BT_LOGGING 0x00080000 430 #define HOSTCAP_SNAPSHOT_UPLOAD 0x00100000 431 #define HOSTCAP_FAST_DELETE_RING 0x00200000 432 #define HOSTCAP_PKT_TXSTATUS 0x00400000 433 #define HOSTCAP_UR_FW_NO_TRAP 0x00800000 /* Don't trap on UR */ 434 #define HOSTCAP_HSCB 0x02000000 435 /* Host support for extended device trap debug buffer */ 436 #define HOSTCAP_EXT_TRAP_DBGBUF 0x04000000 437 /* Host support for enhanced debug lane */ 438 #define HOSTCAP_EDL_RING 0x10000000 439 #define HOSTCAP_PKT_TIMESTAMP 0x20000000 440 #define HOSTCAP_PKT_HP2P 0x40000000 441 #define HOSTCAP_HWA 0x80000000 442 #define HOSTCAP2_DURATION_SCALE_MASK 0x0000003Fu 443 444 /* extended trap debug buffer allocation sizes. Note that this buffer can be 445 * used for other trap related purposes also. 446 */ 447 #define BCMPCIE_HOST_EXT_TRAP_DBGBUF_LEN_MIN (64u * 1024u) 448 #define BCMPCIE_HOST_EXT_TRAP_DBGBUF_LEN_MAX (256u * 1024u) 449 450 /** 451 * Mailboxes notify a remote party that an event took place, using interrupts. 452 * They use hardware support. 453 */ 454 455 /* H2D mail box Data */ 456 #define H2D_HOST_D3_INFORM 0x00000001 457 #define H2D_HOST_DS_ACK 0x00000002 458 #define H2D_HOST_DS_NAK 0x00000004 459 #define H2D_HOST_D0_INFORM_IN_USE 0x00000008 460 #define H2D_HOST_D0_INFORM 0x00000010 461 #define H2DMB_DS_ACTIVE 0x00000020 462 #define H2DMB_DS_DEVICE_WAKE 0x00000040 463 #define H2D_HOST_IDMA_INITED 0x00000080 464 #define H2D_HOST_ACK_NOINT 0x00010000 /* d2h_ack interrupt ignore */ 465 #define H2D_HOST_CONS_INT 0x80000000 /**< h2d int for console cmds */ 466 #define H2D_FW_TRAP 0x20000000 /**< h2d force TRAP */ 467 #define H2DMB_DS_HOST_SLEEP_INFORM H2D_HOST_D3_INFORM 468 #define H2DMB_DS_DEVICE_SLEEP_ACK H2D_HOST_DS_ACK 469 #define H2DMB_DS_DEVICE_SLEEP_NAK H2D_HOST_DS_NAK 470 #define H2DMB_D0_INFORM_IN_USE H2D_HOST_D0_INFORM_IN_USE 471 #define H2DMB_D0_INFORM H2D_HOST_D0_INFORM 472 #define H2DMB_FW_TRAP H2D_FW_TRAP 473 #define H2DMB_HOST_CONS_INT H2D_HOST_CONS_INT 474 #define H2DMB_DS_DEVICE_WAKE_ASSERT H2DMB_DS_DEVICE_WAKE 475 #define H2DMB_DS_DEVICE_WAKE_DEASSERT H2DMB_DS_ACTIVE 476 477 /* D2H mail box Data */ 478 #define D2H_DEV_D3_ACK 0x00000001 479 #define D2H_DEV_DS_ENTER_REQ 0x00000002 480 #define D2H_DEV_DS_EXIT_NOTE 0x00000004 481 #define D2HMB_DS_HOST_SLEEP_EXIT_ACK 0x00000008 482 #define D2H_DEV_IDMA_INITED 0x00000010 483 #define D2HMB_DS_HOST_SLEEP_ACK D2H_DEV_D3_ACK 484 #define D2HMB_DS_DEVICE_SLEEP_ENTER_REQ D2H_DEV_DS_ENTER_REQ 485 #define D2HMB_DS_DEVICE_SLEEP_EXIT D2H_DEV_DS_EXIT_NOTE 486 487 #define D2H_DEV_MB_MASK \ 488 (D2H_DEV_D3_ACK | D2H_DEV_DS_ENTER_REQ | D2H_DEV_DS_EXIT_NOTE | \ 489 D2H_DEV_IDMA_INITED) 490 #define D2H_DEV_MB_INVALIDATED(x) ((!x) || (x & ~D2H_DEV_MB_MASK)) 491 492 /* trap data codes */ 493 #define D2H_DEV_FWHALT 0x10000000 494 #define D2H_DEV_EXT_TRAP_DATA 0x20000000 495 #define D2H_DEV_TRAP_IN_TRAP 0x40000000 496 #define D2H_DEV_TRAP_HOSTDB 0x80000000 /* trap as set by host DB */ 497 #define D2H_DEV_TRAP_DUE_TO_BT 0x01000000 498 /* Indicates trap due to HMAP violation */ 499 #define D2H_DEV_TRAP_DUE_TO_HMAP 0x02000000 500 /* Indicates whether HMAP violation was Write */ 501 #define D2H_DEV_TRAP_HMAP_WRITE 0x04000000 502 #define D2H_DEV_TRAP_PING_HOST_FAILURE 0x08000000 503 #define D2H_FWTRAP_MASK 0x0000001F /* Adding maskbits for TRAP information */ 504 505 #define D2HMB_FWHALT D2H_DEV_FWHALT 506 #define D2HMB_TRAP_IN_TRAP D2H_DEV_TRAP_IN_TRAP 507 #define D2HMB_EXT_TRAP_DATA D2H_DEV_EXT_TRAP_DATA 508 509 /* Size of Extended Trap data Buffer */ 510 #define BCMPCIE_EXT_TRAP_DATA_MAXLEN 4096 511 512 /** These macro's operate on type 'inuse_lclbuf_pool_t' and are used by firmware 513 * only */ 514 #define PREVTXP(i, d) (((i) == 0) ? ((d)-1) : ((i)-1)) 515 #define NEXTTXP(i, d) ((((i) + 1) >= (d)) ? 0 : ((i) + 1)) 516 #define NEXTNTXP(i, n, d) ((((i) + (n)) >= (d)) ? 0 : ((i) + (n))) 517 #define NTXPACTIVE(r, w, d) (((r) <= (w)) ? ((w) - (r)) : ((d) - (r) + (w))) 518 #define NTXPAVAIL(r, w, d) (((d)-NTXPACTIVE((r), (w), (d))) > 1) 519 520 /* Function can be used to notify host of FW halt */ 521 #define READ_AVAIL_SPACE(w, r, d) ((w >= r) ? (uint32)(w - r) : (uint32)(d - r)) 522 #define WRITE_SPACE_AVAIL_CONTINUOUS(r, w, d) ((w >= r) ? (d - w) : (r - w)) 523 #define WRITE_SPACE_AVAIL(r, w, d) (d - (NTXPACTIVE(r, w, d)) - 1) 524 #define CHECK_WRITE_SPACE(r, w, d) \ 525 ((r) > (w)) ? (uint32)((r) - (w)-1) \ 526 : ((r) == 0 || (w) == 0) ? (uint32)((d) - (w)-1) \ 527 : (uint32)((d) - (w)) 528 529 #define CHECK_NOWRITE_SPACE(r, w, d) \ 530 (((uint32)(r) == (uint32)((w) + 1)) || (((r) == 0) && ((w) == ((d)-1)))) 531 532 #define WRT_PEND(x) ((x)->wr_pending) 533 #define DNGL_RING_WPTR(msgbuf) \ 534 (*((msgbuf)->tcm_rs_w_ptr)) /**< advanced by producer */ 535 #define BCMMSGBUF_RING_SET_W_PTR(msgbuf, a) (DNGL_RING_WPTR(msgbuf) = (a)) 536 537 #define DNGL_RING_RPTR(msgbuf) \ 538 (*((msgbuf)->tcm_rs_r_ptr)) /**< advanced by consumer */ 539 #define BCMMSGBUF_RING_SET_R_PTR(msgbuf, a) (DNGL_RING_RPTR(msgbuf) = (a)) 540 541 #define MODULO_RING_IDX(x, y) ((x) % (y)->bitmap_size) 542 543 #define RING_READ_PTR(x) ((x)->ringstate->r_offset) 544 #define RING_WRITE_PTR(x) ((x)->ringstate->w_offset) 545 #define RING_START_PTR(x) ((x)->ringmem->base_addr.low_addr) 546 #define RING_MAX_ITEM(x) ((x)->ringmem->max_item) 547 #define RING_LEN_ITEMS(x) ((x)->ringmem->len_items) 548 #define HOST_RING_BASE(x) ((x)->dma_buf.va) 549 #define HOST_RING_END(x) \ 550 ((uint8 *)HOST_RING_BASE((x)) + \ 551 ((RING_MAX_ITEM((x)) - 1) * RING_LEN_ITEMS((x)))) 552 553 /* Trap types copied in the pciedev_shared.trap_addr */ 554 #define FW_INITIATED_TRAP_TYPE (0x1 << 7) 555 #define HEALTHCHECK_NODS_TRAP_TYPE (0x1 << 6) 556 557 #endif /* _bcmpcie_h_ */ 558