1 /* 2 * Broadcom SDIO/PCMCIA 3 * Software-specific definitions shared between device and host side 4 * 5 * Copyright (C) 1999-2019, Broadcom. 6 * 7 * Unless you and Broadcom execute a separate written software license 8 * agreement governing use of this software, this software is licensed to you 9 * under the terms of the GNU General Public License version 2 (the "GPL"), 10 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 11 * following added to such license: 12 * 13 * As a special exception, the copyright holders of this software give you 14 * permission to link this software with independent modules, and to copy and 15 * distribute the resulting executable under terms of your choice, provided that 16 * you also meet, for each linked independent module, the terms and conditions 17 * of the license of that module. An independent module is a module which is 18 * not derived from this software. The special exception does not apply to any 19 * modifications of the software. 20 * 21 * Notwithstanding the above, under no circumstances may you combine this 22 * software in any way with any other Broadcom software provided under a license 23 * other than the GPL, without Broadcom's express prior written consent. 24 * 25 * 26 * <<Broadcom-WL-IPTag/Open:>> 27 * 28 * $Id: bcmsdpcm.h 700076 2017-05-17 14:42:22Z $ 29 */ 30 31 #ifndef _bcmsdpcm_h_ 32 #define _bcmsdpcm_h_ 33 34 /* 35 * Software allocation of To SB Mailbox resources 36 */ 37 38 /* intstatus bits */ 39 #define I_SMB_NAK I_SMB_SW0 /* To SB Mailbox Frame NAK */ 40 #define I_SMB_INT_ACK I_SMB_SW1 /* To SB Mailbox Host Interrupt ACK */ 41 #define I_SMB_USE_OOB I_SMB_SW2 /* To SB Mailbox Use OOB Wakeup */ 42 #define I_SMB_DEV_INT I_SMB_SW3 /* To SB Mailbox Miscellaneous Interrupt */ 43 44 #define I_TOSBMAIL (I_SMB_NAK | I_SMB_INT_ACK | I_SMB_USE_OOB | I_SMB_DEV_INT) 45 46 /* tosbmailbox bits corresponding to intstatus bits */ 47 #define SMB_NAK (1 << 0) /* To SB Mailbox Frame NAK */ 48 #define SMB_INT_ACK (1 << 1) /* To SB Mailbox Host Interrupt ACK */ 49 #define SMB_USE_OOB (1 << 2) /* To SB Mailbox Use OOB Wakeup */ 50 #define SMB_DEV_INT (1 << 3) /* To SB Mailbox Miscellaneous Interrupt */ 51 #define SMB_MASK 0x0000000f /* To SB Mailbox Mask */ 52 53 /* tosbmailboxdata */ 54 55 #ifdef DS_PROT 56 /* Bit msgs for custom deep sleep protocol */ 57 #define SMB_DATA_D3INFORM 0x100 /* host announcing D3 entry */ 58 #define SMB_DATA_DSACK 0x200 /* host acking a deepsleep request */ 59 #define SMB_DATA_DSNACK 0x400 /* host nacking a deepsleep request */ 60 #endif /* DS_PROT */ 61 /* force a trap */ 62 #define SMB_DATA_TRAP 0x800 /* host forcing trap */ 63 64 #define SMB_DATA_VERSION_MASK \ 65 0x00ff0000 /* host protocol version (sent with F2 enable) */ 66 #define SMB_DATA_VERSION_SHIFT \ 67 16 /* host protocol version (sent with F2 enable) */ 68 69 /* 70 * Software allocation of To Host Mailbox resources 71 */ 72 73 /* intstatus bits */ 74 #define I_HMB_INT_ACK I_HMB_SW0 /* To Host Mailbox Dev Interrupt ACK */ 75 #define I_HMB_FC_STATE I_HMB_SW0 /* To Host Mailbox Flow Control State */ 76 #define I_HMB_FC_CHANGE \ 77 I_HMB_SW1 /* To Host Mailbox Flow Control State Changed */ 78 #define I_HMB_FRAME_IND I_HMB_SW2 /* To Host Mailbox Frame Indication */ 79 #define I_HMB_HOST_INT I_HMB_SW3 /* To Host Mailbox Miscellaneous Interrupt */ 80 81 #define I_TOHOSTMAIL (I_HMB_INT_ACK | I_HMB_FRAME_IND | I_HMB_HOST_INT) 82 83 /* tohostmailbox bits corresponding to intstatus bits */ 84 #define HMB_INT_ACK (1 << 0) /* To Host Mailbox Dev Interrupt ACK */ 85 #define HMB_FRAME_IND (1 << 2) /* To Host Mailbox Frame Indication */ 86 #define HMB_HOST_INT (1 << 3) /* To Host Mailbox Miscellaneous Interrupt */ 87 #define HMB_MASK 0x0000000f /* To Host Mailbox Mask */ 88 89 /* tohostmailboxdata */ 90 #define HMB_DATA_NAKHANDLED \ 91 0x01 /* we're ready to retransmit NAK'd frame to host */ 92 #define HMB_DATA_DEVREADY 0x02 /* we're ready to to talk to host after enable \ 93 */ 94 #define HMB_DATA_FC 0x04 /* per prio flowcontrol update flag to host */ 95 #define HMB_DATA_FWREADY 0x08 /* firmware is ready for protocol activity */ 96 #define HMB_DATA_FWHALT 0x10 /* firmware has halted operation */ 97 98 #ifdef DS_PROT 99 /* Bit msgs for custom deep sleep protocol */ 100 #define HMB_DATA_DSREQ 0x100 /* firmware requesting deepsleep entry */ 101 #define HMB_DATA_DSEXIT 0x200 /* firmware announcing deepsleep exit */ 102 #define HMB_DATA_D3ACK 0x400 /* firmware acking a D3 notice from host */ 103 #define HMB_DATA_D3EXIT 0x800 /* firmware announcing D3 exit */ 104 #define HMB_DATA_DSPROT_MASK 0xf00 105 #endif /* DS_PROT */ 106 107 #define HMB_DATA_FCDATA_MASK 0xff000000 /* per prio flowcontrol data */ 108 #define HMB_DATA_FCDATA_SHIFT 24 /* per prio flowcontrol data */ 109 110 #define HMB_DATA_VERSION_MASK \ 111 0x00ff0000 /* device protocol version (with devready) */ 112 #define HMB_DATA_VERSION_SHIFT 16 /* device protocol version (with devready) \ 113 */ 114 115 /* 116 * Software-defined protocol header 117 */ 118 119 /* Current protocol version */ 120 #define SDPCM_PROT_VERSION 4 121 122 /* SW frame header */ 123 #define SDPCM_SEQUENCE_MASK 0x000000ff /* Sequence Number Mask */ 124 #define SDPCM_PACKET_SEQUENCE(p) \ 125 (((uint8 *)p)[0] & 0xff) /* p starts w/SW Header */ 126 127 #define SDPCM_CHANNEL_MASK 0x00000f00 /* Channel Number Mask */ 128 #define SDPCM_CHANNEL_SHIFT 8 /* Channel Number Shift */ 129 #define SDPCM_PACKET_CHANNEL(p) \ 130 (((uint8 *)p)[1] & 0x0f) /* p starts w/SW Header */ 131 132 #define SDPCM_FLAGS_MASK 0x0000f000 /* Mask of flag bits */ 133 #define SDPCM_FLAGS_SHIFT 12 /* Flag bits shift */ 134 #define SDPCM_PACKET_FLAGS(p) \ 135 ((((uint8 *)p)[1] & 0xf0) >> 4) /* p starts w/SW Header */ 136 137 /* Next Read Len: lookahead length of next frame, in 16-byte units (rounded up) 138 */ 139 #define SDPCM_NEXTLEN_MASK 0x00ff0000 /* Next Read Len Mask */ 140 #define SDPCM_NEXTLEN_SHIFT 16 /* Next Read Len Shift */ 141 #define SDPCM_NEXTLEN_VALUE(p) \ 142 ((((uint8 *)p)[2] & 0xff) << 4) /* p starts w/SW Header */ 143 #define SDPCM_NEXTLEN_OFFSET 2 144 145 /* Data Offset from SOF (HW Tag, SW Tag, Pad) */ 146 #define SDPCM_DOFFSET_OFFSET 3 /* Data Offset */ 147 #define SDPCM_DOFFSET_VALUE(p) (((uint8 *)p)[SDPCM_DOFFSET_OFFSET] & 0xff) 148 #define SDPCM_DOFFSET_MASK 0xff000000 149 #define SDPCM_DOFFSET_SHIFT 24 150 151 #define SDPCM_FCMASK_OFFSET 4 /* Flow control */ 152 #define SDPCM_FCMASK_VALUE(p) (((uint8 *)p)[SDPCM_FCMASK_OFFSET] & 0xff) 153 #define SDPCM_WINDOW_OFFSET 5 /* Credit based fc */ 154 #define SDPCM_WINDOW_VALUE(p) (((uint8 *)p)[SDPCM_WINDOW_OFFSET] & 0xff) 155 #define SDPCM_VERSION_OFFSET 6 /* Version # */ 156 #define SDPCM_VERSION_VALUE(p) (((uint8 *)p)[SDPCM_VERSION_OFFSET] & 0xff) 157 #define SDPCM_UNUSED_OFFSET 7 /* Spare */ 158 #define SDPCM_UNUSED_VALUE(p) (((uint8 *)p)[SDPCM_UNUSED_OFFSET] & 0xff) 159 160 #define SDPCM_SWHEADER_LEN 8 /* SW header is 64 bits */ 161 162 /* logical channel numbers */ 163 #define SDPCM_CONTROL_CHANNEL 0 /* Control Request/Response Channel Id */ 164 #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication Channel Id */ 165 #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv Channel Id */ 166 #define SDPCM_GLOM_CHANNEL 3 /* For coalesced packets (superframes) */ 167 #define SDPCM_TEST_CHANNEL 15 /* Reserved for test/debug packets */ 168 #define SDPCM_MAX_CHANNEL 15 169 170 #define SDPCM_SEQUENCE_WRAP \ 171 256 /* wrap-around val for eight-bit frame seq number */ 172 173 #define SDPCM_FLAG_RESVD0 0x01 174 #define SDPCM_FLAG_RESVD1 0x02 175 #define SDPCM_FLAG_GSPI_TXENAB 0x04 176 #define SDPCM_FLAG_GLOMDESC 0x08 /* Superframe descriptor mask */ 177 178 /* For GLOM_CHANNEL frames, use a flag to indicate descriptor frame */ 179 #define SDPCM_GLOMDESC_FLAG (SDPCM_FLAG_GLOMDESC << SDPCM_FLAGS_SHIFT) 180 181 #define SDPCM_GLOMDESC(p) (((uint8 *)p)[1] & 0x80) 182 183 /* For TEST_CHANNEL packets, define another 4-byte header */ 184 #define SDPCM_TEST_HDRLEN \ 185 4 /* Generally: Cmd(1), Ext(1), Len(2); \ 186 * Semantics of Ext byte depend on command. \ 187 * Len is current or requested frame length, not \ 188 * including test header; sent little-endian. \ 189 */ 190 #define SDPCM_TEST_PKT_CNT_FLD_LEN 4 /* Packet count filed legth */ 191 #define SDPCM_TEST_DISCARD 0x01 /* Receiver discards. Ext is a pattern id. */ 192 #define SDPCM_TEST_ECHOREQ 0x02 /* Echo request. Ext is a pattern id. */ 193 #define SDPCM_TEST_ECHORSP 0x03 /* Echo response. Ext is a pattern id. */ 194 #define SDPCM_TEST_BURST \ 195 0x04 /* Receiver to send a burst. Ext is a frame count \ 196 * (Backward compatabilty) Set frame count in a \ 197 * 4 byte filed adjacent to the HDR \ 198 */ 199 #define SDPCM_TEST_SEND \ 200 0x05 /* Receiver sets send mode. Ext is boolean on/off \ 201 * Set frame count in a 4 byte filed adjacent to \ 202 * the HDR \ 203 */ 204 205 /* Handy macro for filling in datagen packets with a pattern */ 206 #define SDPCM_TEST_FILL(byteno, id) ((uint8)(id + byteno)) 207 208 /* 209 * Software counters (first part matches hardware counters) 210 */ 211 212 typedef volatile struct { 213 uint32 cmd52rd; /* Cmd52RdCount, SDIO: cmd52 reads */ 214 uint32 cmd52wr; /* Cmd52WrCount, SDIO: cmd52 writes */ 215 uint32 cmd53rd; /* Cmd53RdCount, SDIO: cmd53 reads */ 216 uint32 cmd53wr; /* Cmd53WrCount, SDIO: cmd53 writes */ 217 uint32 abort; /* AbortCount, SDIO: aborts */ 218 uint32 datacrcerror; /* DataCrcErrorCount, SDIO: frames w/CRC error */ 219 uint32 rdoutofsync; /* RdOutOfSyncCount, SDIO/PCMCIA: Rd Frm out of sync */ 220 uint32 wroutofsync; /* RdOutOfSyncCount, SDIO/PCMCIA: Wr Frm out of sync */ 221 uint32 writebusy; /* WriteBusyCount, SDIO: device asserted "busy" */ 222 uint32 readwait; /* ReadWaitCount, SDIO: no data ready for a read cmd */ 223 uint32 readterm; /* ReadTermCount, SDIO: read frame termination cmds */ 224 uint32 writeterm; /* WriteTermCount, SDIO: write frames termination cmds */ 225 uint32 rxdescuflo; /* receive descriptor underflows */ 226 uint32 rxfifooflo; /* receive fifo overflows */ 227 uint32 txfifouflo; /* transmit fifo underflows */ 228 uint32 runt; /* runt (too short) frames recv'd from bus */ 229 uint32 badlen; /* frame's rxh len does not match its hw tag len */ 230 uint32 badcksum; /* frame's hw tag chksum doesn't agree with len value */ 231 uint32 232 seqbreak; /* break in sequence # space from one rx frame to the next */ 233 uint32 rxfcrc; /* frame rx header indicates crc error */ 234 uint32 rxfwoos; /* frame rx header indicates write out of sync */ 235 uint32 rxfwft; /* frame rx header indicates write frame termination */ 236 uint32 rxfabort; /* frame rx header indicates frame aborted */ 237 uint32 woosint; /* write out of sync interrupt */ 238 uint32 roosint; /* read out of sync interrupt */ 239 uint32 rftermint; /* read frame terminate interrupt */ 240 uint32 wftermint; /* write frame terminate interrupt */ 241 } sdpcmd_cnt_t; 242 243 /* 244 * Register Access Macros 245 */ 246 247 #define SDIODREV_IS(var, val) ((var) == (val)) 248 #define SDIODREV_GE(var, val) ((var) >= (val)) 249 #define SDIODREV_GT(var, val) ((var) > (val)) 250 #define SDIODREV_LT(var, val) ((var) < (val)) 251 #define SDIODREV_LE(var, val) ((var) <= (val)) 252 253 #define SDIODDMAREG32(h, dir, chnl) \ 254 ((dir) == DMA_TX \ 255 ? (void *)(uintptr) & ((h)->regs->dma.sdiod32.dma32regs[chnl].xmt) \ 256 : (void *)(uintptr) & ((h)->regs->dma.sdiod32.dma32regs[chnl].rcv)) 257 258 #define SDIODDMAREG64(h, dir, chnl) \ 259 ((dir) == DMA_TX \ 260 ? (void *)(uintptr) & ((h)->regs->dma.sdiod64.dma64regs[chnl].xmt) \ 261 : (void *)(uintptr) & ((h)->regs->dma.sdiod64.dma64regs[chnl].rcv)) 262 263 #define SDIODDMAREG(h, dir, chnl) \ 264 (SDIODREV_LT((h)->corerev, 1) ? SDIODDMAREG32((h), (dir), (chnl)) \ 265 : SDIODDMAREG64((h), (dir), (chnl))) 266 267 #define PCMDDMAREG(h, dir, chnl) \ 268 ((dir) == DMA_TX ? (void *)(uintptr) & ((h)->regs->dma.pcm32.dmaregs.xmt) \ 269 : (void *)(uintptr) & ((h)->regs->dma.pcm32.dmaregs.rcv)) 270 271 #define SDPCMDMAREG(h, dir, chnl, coreid) \ 272 ((coreid) == SDIOD_CORE_ID ? SDIODDMAREG(h, dir, chnl) \ 273 : PCMDDMAREG(h, dir, chnl)) 274 275 #define SDIODFIFOREG(h, corerev) \ 276 (SDIODREV_LT((corerev), 1) \ 277 ? ((dma32diag_t *)(uintptr) & ((h)->regs->dma.sdiod32.dmafifo)) \ 278 : ((dma32diag_t *)(uintptr) & ((h)->regs->dma.sdiod64.dmafifo))) 279 280 #define PCMDFIFOREG(h) \ 281 ((dma32diag_t *)(uintptr) & ((h)->regs->dma.pcm32.dmafifo)) 282 283 #define SDPCMFIFOREG(h, coreid, corerev) \ 284 ((coreid) == SDIOD_CORE_ID ? SDIODFIFOREG(h, corerev) : PCMDFIFOREG(h)) 285 286 /* 287 * Shared structure between dongle and the host. 288 * The structure contains pointers to trap or assert information. 289 */ 290 #define SDPCM_SHARED_VERSION 0x0001 291 #define SDPCM_SHARED_VERSION_MASK 0x00FF 292 #define SDPCM_SHARED_ASSERT_BUILT 0x0100 293 #define SDPCM_SHARED_ASSERT 0x0200 294 #define SDPCM_SHARED_TRAP 0x0400 295 #define SDPCM_SHARED_IN_BRPT 0x0800 296 #define SDPCM_SHARED_SET_BRPT 0x1000 297 #define SDPCM_SHARED_PENDING_BRPT 0x2000 298 #define SDPCM_SHARED_FATAL_LOGBUF_VALID 0x100000 299 #define SDPCM_SHARED_RXLIM_POST 0x4000 300 #define SDPCM_SHARED_TXSEQ_SYNC 0x4000 301 302 typedef struct { 303 uint32 flags; 304 uint32 trap_addr; 305 uint32 assert_exp_addr; 306 uint32 assert_file_addr; 307 uint32 assert_line; 308 uint32 console_addr; /* Address of hnd_cons_t */ 309 uint32 msgtrace_addr; 310 uint32 fwid; 311 uint32 device_fatal_logbuf_start; 312 #ifdef BCMSDIO_TXSEQ_SYNC 313 uint32 txseq_sync_addr; 314 #endif /* BCMSDIO_TXSEQ_SYNC */ 315 } sdpcm_shared_t; 316 317 /* Device F/W provides the following access function: 318 * sdpcm_shared_t *hnd_get_sdpcm_shared(void); 319 */ 320 321 #endif /* _bcmsdpcm_h_ */ 322