1 /* 2 * Table that encodes the srom formats for PCI/PCIe NICs. 3 * 4 * Copyright (C) 1999-2019, Broadcom. 5 * 6 * Unless you and Broadcom execute a separate written software license 7 * agreement governing use of this software, this software is licensed to you 8 * under the terms of the GNU General Public License version 2 (the "GPL"), 9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 10 * following added to such license: 11 * 12 * As a special exception, the copyright holders of this software give you 13 * permission to link this software with independent modules, and to copy and 14 * distribute the resulting executable under terms of your choice, provided that 15 * you also meet, for each linked independent module, the terms and conditions 16 * of the license of that module. An independent module is a module which is 17 * not derived from this software. The special exception does not apply to any 18 * modifications of the software. 19 * 20 * Notwithstanding the above, under no circumstances may you combine this 21 * software in any way with any other Broadcom software provided under a license 22 * other than the GPL, without Broadcom's express prior written consent. 23 * 24 * 25 * <<Broadcom-WL-IPTag/Open:>> 26 * 27 * $Id: bcmsrom_tbl.h 700323 2017-05-18 16:12:11Z $ 28 */ 29 30 #ifndef _bcmsrom_tbl_h_ 31 #define _bcmsrom_tbl_h_ 32 33 #include "sbpcmcia.h" 34 #include "wlioctl.h" 35 #include <bcmsrom_fmt.h> 36 37 typedef struct { 38 const char *name; 39 uint32 revmask; 40 uint32 flags; 41 uint16 off; 42 uint16 mask; 43 } sromvar_t; 44 45 #define SRFL_MORE 1 /* value continues as described by the next entry */ 46 #define SRFL_NOFFS 2 /* value bits can't be all one's */ 47 #define SRFL_PRHEX 4 /* value is in hexdecimal format */ 48 #define SRFL_PRSIGN 8 /* value is in signed decimal format */ 49 #define SRFL_CCODE 0x10 /* value is in country code format */ 50 #define SRFL_ETHADDR 0x20 /* value is an Ethernet address */ 51 #define SRFL_LEDDC 0x40 /* value is an LED duty cycle */ 52 #define SRFL_NOVAR 0x80 /* do not generate a nvram param, entry is for mfgc */ 53 #define SRFL_ARRAY \ 54 0x100 /* value is in an array. All elements EXCEPT FOR THE LAST \ 55 * ONE in the array should have this flag set. \ 56 */ 57 #define PRHEX_N_MORE (SRFL_PRHEX | SRFL_MORE) 58 59 #define SROM_DEVID_PCIE 48 60 61 /** 62 * Assumptions: 63 * - Ethernet address spans across 3 consecutive words 64 * 65 * Table rules: 66 * - Add multiple entries next to each other if a value spans across multiple 67 * words (even multiple fields in the same word) with each entry except the last 68 * having it's SRFL_MORE bit set. 69 * - Ethernet address entry does not follow above rule and must not have 70 * SRFL_MORE bit set. Its SRFL_ETHADDR bit implies it takes multiple words. 71 * - The last entry's name field must be NULL to indicate the end of the table. 72 * Other entries must have non-NULL name. 73 */ 74 #if !defined(SROM15_MEMOPT) 75 static const sromvar_t pci_sromvars[] = { 76 /* name revmask flags off mask */ 77 #if defined(CABLECPE) 78 {"devid", 0xffffff00, SRFL_PRHEX, PCI_F0DEVID, 0xffff}, 79 #elif defined(BCMPCIEDEV) && defined(BCMPCIEDEV_ENABLED) 80 {"devid", 0xffffff00, SRFL_PRHEX, SROM_DEVID_PCIE, 0xffff}, 81 #else 82 {"devid", 0xffffff00, SRFL_PRHEX | SRFL_NOVAR, PCI_F0DEVID, 0xffff}, 83 #endif // endif 84 {"boardrev", 0x0000000e, SRFL_PRHEX, SROM_AABREV, SROM_BR_MASK}, 85 {"boardrev", 0x000000f0, SRFL_PRHEX, SROM4_BREV, 0xffff}, 86 {"boardrev", 0xffffff00, SRFL_PRHEX, SROM8_BREV, 0xffff}, 87 {"boardflags", 0x00000002, SRFL_PRHEX, SROM_BFL, 0xffff}, 88 {"boardflags", 0x00000004, SRFL_PRHEX | SRFL_MORE, SROM_BFL, 0xffff}, 89 {"", 0, 0, SROM_BFL2, 0xffff}, 90 {"boardflags", 0x00000008, SRFL_PRHEX | SRFL_MORE, SROM_BFL, 0xffff}, 91 {"", 0, 0, SROM3_BFL2, 0xffff}, 92 {"boardflags", 0x00000010, SRFL_PRHEX | SRFL_MORE, SROM4_BFL0, 0xffff}, 93 {"", 0, 0, SROM4_BFL1, 0xffff}, 94 {"boardflags", 0x000000e0, SRFL_PRHEX | SRFL_MORE, SROM5_BFL0, 0xffff}, 95 {"", 0, 0, SROM5_BFL1, 0xffff}, 96 {"boardflags", 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL0, 0xffff}, 97 {"", 0, 0, SROM8_BFL1, 0xffff}, 98 {"boardflags2", 0x00000010, SRFL_PRHEX | SRFL_MORE, SROM4_BFL2, 0xffff}, 99 {"", 0, 0, SROM4_BFL3, 0xffff}, 100 {"boardflags2", 0x000000e0, SRFL_PRHEX | SRFL_MORE, SROM5_BFL2, 0xffff}, 101 {"", 0, 0, SROM5_BFL3, 0xffff}, 102 {"boardflags2", 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL2, 0xffff}, 103 {"", 0, 0, SROM8_BFL3, 0xffff}, 104 {"boardtype", 0xfffffffc, SRFL_PRHEX, SROM_SSID, 0xffff}, 105 {"subvid", 0xfffffffc, SRFL_PRHEX, SROM_SVID, 0xffff}, 106 {"boardnum", 0x00000006, 0, SROM_MACLO_IL0, 0xffff}, 107 {"boardnum", 0x00000008, 0, SROM3_MACLO, 0xffff}, 108 {"boardnum", 0x00000010, 0, SROM4_MACLO, 0xffff}, 109 {"boardnum", 0x000000e0, 0, SROM5_MACLO, 0xffff}, 110 {"boardnum", 0x00000700, 0, SROM8_MACLO, 0xffff}, 111 {"cc", 0x00000002, 0, SROM_AABREV, SROM_CC_MASK}, 112 {"regrev", 0x00000008, 0, SROM_OPO, 0xff00}, 113 {"regrev", 0x00000010, 0, SROM4_REGREV, 0xffff}, 114 {"regrev", 0x000000e0, 0, SROM5_REGREV, 0xffff}, 115 {"regrev", 0x00000700, 0, SROM8_REGREV, 0xffff}, 116 {"ledbh0", 0x0000000e, SRFL_NOFFS, SROM_LEDBH10, 0x00ff}, 117 {"ledbh1", 0x0000000e, SRFL_NOFFS, SROM_LEDBH10, 0xff00}, 118 {"ledbh2", 0x0000000e, SRFL_NOFFS, SROM_LEDBH32, 0x00ff}, 119 {"ledbh3", 0x0000000e, SRFL_NOFFS, SROM_LEDBH32, 0xff00}, 120 {"ledbh0", 0x00000010, SRFL_NOFFS, SROM4_LEDBH10, 0x00ff}, 121 {"ledbh1", 0x00000010, SRFL_NOFFS, SROM4_LEDBH10, 0xff00}, 122 {"ledbh2", 0x00000010, SRFL_NOFFS, SROM4_LEDBH32, 0x00ff}, 123 {"ledbh3", 0x00000010, SRFL_NOFFS, SROM4_LEDBH32, 0xff00}, 124 {"ledbh0", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH10, 0x00ff}, 125 {"ledbh1", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH10, 0xff00}, 126 {"ledbh2", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH32, 0x00ff}, 127 {"ledbh3", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH32, 0xff00}, 128 {"ledbh0", 0x00000700, SRFL_NOFFS, SROM8_LEDBH10, 0x00ff}, 129 {"ledbh1", 0x00000700, SRFL_NOFFS, SROM8_LEDBH10, 0xff00}, 130 {"ledbh2", 0x00000700, SRFL_NOFFS, SROM8_LEDBH32, 0x00ff}, 131 {"ledbh3", 0x00000700, SRFL_NOFFS, SROM8_LEDBH32, 0xff00}, 132 {"pa0b0", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB0, 0xffff}, 133 {"pa0b1", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB1, 0xffff}, 134 {"pa0b2", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB2, 0xffff}, 135 {"pa0itssit", 0x0000000e, 0, SROM_ITT, 0x00ff}, 136 {"pa0maxpwr", 0x0000000e, 0, SROM_WL10MAXP, 0x00ff}, 137 {"pa0b0", 0x00000700, SRFL_PRHEX, SROM8_W0_PAB0, 0xffff}, 138 {"pa0b1", 0x00000700, SRFL_PRHEX, SROM8_W0_PAB1, 0xffff}, 139 {"pa0b2", 0x00000700, SRFL_PRHEX, SROM8_W0_PAB2, 0xffff}, 140 {"pa0itssit", 0x00000700, 0, SROM8_W0_ITTMAXP, 0xff00}, 141 {"pa0maxpwr", 0x00000700, 0, SROM8_W0_ITTMAXP, 0x00ff}, 142 {"opo", 0x0000000c, 0, SROM_OPO, 0x00ff}, 143 {"opo", 0x00000700, 0, SROM8_2G_OFDMPO, 0x00ff}, 144 {"aa2g", 0x0000000e, 0, SROM_AABREV, SROM_AA0_MASK}, 145 {"aa2g", 0x000000f0, 0, SROM4_AA, 0x00ff}, 146 {"aa2g", 0x00000700, 0, SROM8_AA, 0x00ff}, 147 {"aa5g", 0x0000000e, 0, SROM_AABREV, SROM_AA1_MASK}, 148 {"aa5g", 0x000000f0, 0, SROM4_AA, 0xff00}, 149 {"aa5g", 0x00000700, 0, SROM8_AA, 0xff00}, 150 {"ag0", 0x0000000e, 0, SROM_AG10, 0x00ff}, 151 {"ag1", 0x0000000e, 0, SROM_AG10, 0xff00}, 152 {"ag0", 0x000000f0, 0, SROM4_AG10, 0x00ff}, 153 {"ag1", 0x000000f0, 0, SROM4_AG10, 0xff00}, 154 {"ag2", 0x000000f0, 0, SROM4_AG32, 0x00ff}, 155 {"ag3", 0x000000f0, 0, SROM4_AG32, 0xff00}, 156 {"ag0", 0x00000700, 0, SROM8_AG10, 0x00ff}, 157 {"ag1", 0x00000700, 0, SROM8_AG10, 0xff00}, 158 {"ag2", 0x00000700, 0, SROM8_AG32, 0x00ff}, 159 {"ag3", 0x00000700, 0, SROM8_AG32, 0xff00}, 160 {"pa1b0", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB0, 0xffff}, 161 {"pa1b1", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB1, 0xffff}, 162 {"pa1b2", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB2, 0xffff}, 163 {"pa1lob0", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB0, 0xffff}, 164 {"pa1lob1", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB1, 0xffff}, 165 {"pa1lob2", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB2, 0xffff}, 166 {"pa1hib0", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB0, 0xffff}, 167 {"pa1hib1", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB1, 0xffff}, 168 {"pa1hib2", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB2, 0xffff}, 169 {"pa1itssit", 0x0000000e, 0, SROM_ITT, 0xff00}, 170 {"pa1maxpwr", 0x0000000e, 0, SROM_WL10MAXP, 0xff00}, 171 {"pa1lomaxpwr", 0x0000000c, 0, SROM_WL1LHMAXP, 0xff00}, 172 {"pa1himaxpwr", 0x0000000c, 0, SROM_WL1LHMAXP, 0x00ff}, 173 {"pa1b0", 0x00000700, SRFL_PRHEX, SROM8_W1_PAB0, 0xffff}, 174 {"pa1b1", 0x00000700, SRFL_PRHEX, SROM8_W1_PAB1, 0xffff}, 175 {"pa1b2", 0x00000700, SRFL_PRHEX, SROM8_W1_PAB2, 0xffff}, 176 {"pa1lob0", 0x00000700, SRFL_PRHEX, SROM8_W1_PAB0_LC, 0xffff}, 177 {"pa1lob1", 0x00000700, SRFL_PRHEX, SROM8_W1_PAB1_LC, 0xffff}, 178 {"pa1lob2", 0x00000700, SRFL_PRHEX, SROM8_W1_PAB2_LC, 0xffff}, 179 {"pa1hib0", 0x00000700, SRFL_PRHEX, SROM8_W1_PAB0_HC, 0xffff}, 180 {"pa1hib1", 0x00000700, SRFL_PRHEX, SROM8_W1_PAB1_HC, 0xffff}, 181 {"pa1hib2", 0x00000700, SRFL_PRHEX, SROM8_W1_PAB2_HC, 0xffff}, 182 {"pa1itssit", 0x00000700, 0, SROM8_W1_ITTMAXP, 0xff00}, 183 {"pa1maxpwr", 0x00000700, 0, SROM8_W1_ITTMAXP, 0x00ff}, 184 {"pa1lomaxpwr", 0x00000700, 0, SROM8_W1_MAXP_LCHC, 0xff00}, 185 {"pa1himaxpwr", 0x00000700, 0, SROM8_W1_MAXP_LCHC, 0x00ff}, 186 {"bxa2g", 0x00000008, 0, SROM_BXARSSI2G, 0x1800}, 187 {"rssisav2g", 0x00000008, 0, SROM_BXARSSI2G, 0x0700}, 188 {"rssismc2g", 0x00000008, 0, SROM_BXARSSI2G, 0x00f0}, 189 {"rssismf2g", 0x00000008, 0, SROM_BXARSSI2G, 0x000f}, 190 {"bxa2g", 0x00000700, 0, SROM8_BXARSSI2G, 0x1800}, 191 {"rssisav2g", 0x00000700, 0, SROM8_BXARSSI2G, 0x0700}, 192 {"rssismc2g", 0x00000700, 0, SROM8_BXARSSI2G, 0x00f0}, 193 {"rssismf2g", 0x00000700, 0, SROM8_BXARSSI2G, 0x000f}, 194 {"bxa5g", 0x00000008, 0, SROM_BXARSSI5G, 0x1800}, 195 {"rssisav5g", 0x00000008, 0, SROM_BXARSSI5G, 0x0700}, 196 {"rssismc5g", 0x00000008, 0, SROM_BXARSSI5G, 0x00f0}, 197 {"rssismf5g", 0x00000008, 0, SROM_BXARSSI5G, 0x000f}, 198 {"bxa5g", 0x00000700, 0, SROM8_BXARSSI5G, 0x1800}, 199 {"rssisav5g", 0x00000700, 0, SROM8_BXARSSI5G, 0x0700}, 200 {"rssismc5g", 0x00000700, 0, SROM8_BXARSSI5G, 0x00f0}, 201 {"rssismf5g", 0x00000700, 0, SROM8_BXARSSI5G, 0x000f}, 202 {"tri2g", 0x00000008, 0, SROM_TRI52G, 0x00ff}, 203 {"tri5g", 0x00000008, 0, SROM_TRI52G, 0xff00}, 204 {"tri5gl", 0x00000008, 0, SROM_TRI5GHL, 0x00ff}, 205 {"tri5gh", 0x00000008, 0, SROM_TRI5GHL, 0xff00}, 206 {"tri2g", 0x00000700, 0, SROM8_TRI52G, 0x00ff}, 207 {"tri5g", 0x00000700, 0, SROM8_TRI52G, 0xff00}, 208 {"tri5gl", 0x00000700, 0, SROM8_TRI5GHL, 0x00ff}, 209 {"tri5gh", 0x00000700, 0, SROM8_TRI5GHL, 0xff00}, 210 {"rxpo2g", 0x00000008, SRFL_PRSIGN, SROM_RXPO52G, 0x00ff}, 211 {"rxpo5g", 0x00000008, SRFL_PRSIGN, SROM_RXPO52G, 0xff00}, 212 {"rxpo2g", 0x00000700, SRFL_PRSIGN, SROM8_RXPO52G, 0x00ff}, 213 {"rxpo5g", 0x00000700, SRFL_PRSIGN, SROM8_RXPO52G, 0xff00}, 214 {"txchain", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_TXCHAIN_MASK}, 215 {"rxchain", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_RXCHAIN_MASK}, 216 {"antswitch", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_SWITCH_MASK}, 217 {"txchain", 0x00000700, SRFL_NOFFS, SROM8_TXRXC, SROM4_TXCHAIN_MASK}, 218 {"rxchain", 0x00000700, SRFL_NOFFS, SROM8_TXRXC, SROM4_RXCHAIN_MASK}, 219 {"antswitch", 0x00000700, SRFL_NOFFS, SROM8_TXRXC, SROM4_SWITCH_MASK}, 220 {"tssipos2g", 0x00000700, 0, SROM8_FEM2G, SROM8_FEM_TSSIPOS_MASK}, 221 {"extpagain2g", 0x00000700, 0, SROM8_FEM2G, SROM8_FEM_EXTPA_GAIN_MASK}, 222 {"pdetrange2g", 0x00000700, 0, SROM8_FEM2G, SROM8_FEM_PDET_RANGE_MASK}, 223 {"triso2g", 0x00000700, 0, SROM8_FEM2G, SROM8_FEM_TR_ISO_MASK}, 224 {"antswctl2g", 0x00000700, 0, SROM8_FEM2G, SROM8_FEM_ANTSWLUT_MASK}, 225 {"tssipos5g", 0x00000700, 0, SROM8_FEM5G, SROM8_FEM_TSSIPOS_MASK}, 226 {"extpagain5g", 0x00000700, 0, SROM8_FEM5G, SROM8_FEM_EXTPA_GAIN_MASK}, 227 {"pdetrange5g", 0x00000700, 0, SROM8_FEM5G, SROM8_FEM_PDET_RANGE_MASK}, 228 {"triso5g", 0x00000700, 0, SROM8_FEM5G, SROM8_FEM_TR_ISO_MASK}, 229 {"antswctl5g", 0x00000700, 0, SROM8_FEM5G, SROM8_FEM_ANTSWLUT_MASK}, 230 {"txpid2ga0", 0x000000f0, 0, SROM4_TXPID2G, 0x00ff}, 231 {"txpid2ga1", 0x000000f0, 0, SROM4_TXPID2G, 0xff00}, 232 {"txpid2ga2", 0x000000f0, 0, SROM4_TXPID2G + 1, 0x00ff}, 233 {"txpid2ga3", 0x000000f0, 0, SROM4_TXPID2G + 1, 0xff00}, 234 {"txpid5ga0", 0x000000f0, 0, SROM4_TXPID5G, 0x00ff}, 235 {"txpid5ga1", 0x000000f0, 0, SROM4_TXPID5G, 0xff00}, 236 {"txpid5ga2", 0x000000f0, 0, SROM4_TXPID5G + 1, 0x00ff}, 237 {"txpid5ga3", 0x000000f0, 0, SROM4_TXPID5G + 1, 0xff00}, 238 {"txpid5gla0", 0x000000f0, 0, SROM4_TXPID5GL, 0x00ff}, 239 {"txpid5gla1", 0x000000f0, 0, SROM4_TXPID5GL, 0xff00}, 240 {"txpid5gla2", 0x000000f0, 0, SROM4_TXPID5GL + 1, 0x00ff}, 241 {"txpid5gla3", 0x000000f0, 0, SROM4_TXPID5GL + 1, 0xff00}, 242 {"txpid5gha0", 0x000000f0, 0, SROM4_TXPID5GH, 0x00ff}, 243 {"txpid5gha1", 0x000000f0, 0, SROM4_TXPID5GH, 0xff00}, 244 {"txpid5gha2", 0x000000f0, 0, SROM4_TXPID5GH + 1, 0x00ff}, 245 {"txpid5gha3", 0x000000f0, 0, SROM4_TXPID5GH + 1, 0xff00}, 246 247 {"ccode", 0x0000000f, SRFL_CCODE, SROM_CCODE, 0xffff}, 248 {"ccode", 0x00000010, SRFL_CCODE, SROM4_CCODE, 0xffff}, 249 {"ccode", 0x000000e0, SRFL_CCODE, SROM5_CCODE, 0xffff}, 250 {"ccode", 0x00000700, SRFL_CCODE, SROM8_CCODE, 0xffff}, 251 {"macaddr", 0x00000700, SRFL_ETHADDR, SROM8_MACHI, 0xffff}, 252 {"macaddr", 0x000000e0, SRFL_ETHADDR, SROM5_MACHI, 0xffff}, 253 {"macaddr", 0x00000010, SRFL_ETHADDR, SROM4_MACHI, 0xffff}, 254 {"macaddr", 0x00000008, SRFL_ETHADDR, SROM3_MACHI, 0xffff}, 255 {"il0macaddr", 0x00000007, SRFL_ETHADDR, SROM_MACHI_IL0, 0xffff}, 256 {"et1macaddr", 0x00000007, SRFL_ETHADDR, SROM_MACHI_ET1, 0xffff}, 257 {"leddc", 0x00000700, SRFL_NOFFS | SRFL_LEDDC, SROM8_LEDDC, 0xffff}, 258 {"leddc", 0x000000e0, SRFL_NOFFS | SRFL_LEDDC, SROM5_LEDDC, 0xffff}, 259 {"leddc", 0x00000010, SRFL_NOFFS | SRFL_LEDDC, SROM4_LEDDC, 0xffff}, 260 {"leddc", 0x00000008, SRFL_NOFFS | SRFL_LEDDC, SROM3_LEDDC, 0xffff}, 261 262 {"tempthresh", 0x00000700, 0, SROM8_THERMAL, 0xff00}, 263 {"tempoffset", 0x00000700, 0, SROM8_THERMAL, 0x00ff}, 264 {"rawtempsense", 0x00000700, SRFL_PRHEX, SROM8_MPWR_RAWTS, 0x01ff}, 265 {"measpower", 0x00000700, SRFL_PRHEX, SROM8_MPWR_RAWTS, 0xfe00}, 266 {"tempsense_slope", 0x00000700, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX, 0x00ff}, 267 {"tempcorrx", 0x00000700, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX, 0xfc00}, 268 {"tempsense_option", 0x00000700, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX, 269 0x0300}, 270 {"freqoffset_corr", 0x00000700, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP, 0x000f}, 271 {"iqcal_swp_dis", 0x00000700, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP, 0x0010}, 272 {"hw_iqcal_en", 0x00000700, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP, 0x0020}, 273 {"elna2g", 0x00000700, 0, SROM8_EXTLNAGAIN, 0x00ff}, 274 {"elna5g", 0x00000700, 0, SROM8_EXTLNAGAIN, 0xff00}, 275 {"phycal_tempdelta", 0x00000700, 0, SROM8_PHYCAL_TEMPDELTA, 0x00ff}, 276 {"temps_period", 0x00000700, 0, SROM8_PHYCAL_TEMPDELTA, 0x0f00}, 277 {"temps_hysteresis", 0x00000700, 0, SROM8_PHYCAL_TEMPDELTA, 0xf000}, 278 {"measpower1", 0x00000700, SRFL_PRHEX, SROM8_MPWR_1_AND_2, 0x007f}, 279 {"measpower2", 0x00000700, SRFL_PRHEX, SROM8_MPWR_1_AND_2, 0x3f80}, 280 281 {"cck2gpo", 0x000000f0, 0, SROM4_2G_CCKPO, 0xffff}, 282 {"cck2gpo", 0x00000100, 0, SROM8_2G_CCKPO, 0xffff}, 283 {"ofdm2gpo", 0x000000f0, SRFL_MORE, SROM4_2G_OFDMPO, 0xffff}, 284 {"", 0, 0, SROM4_2G_OFDMPO + 1, 0xffff}, 285 {"ofdm5gpo", 0x000000f0, SRFL_MORE, SROM4_5G_OFDMPO, 0xffff}, 286 {"", 0, 0, SROM4_5G_OFDMPO + 1, 0xffff}, 287 {"ofdm5glpo", 0x000000f0, SRFL_MORE, SROM4_5GL_OFDMPO, 0xffff}, 288 {"", 0, 0, SROM4_5GL_OFDMPO + 1, 0xffff}, 289 {"ofdm5ghpo", 0x000000f0, SRFL_MORE, SROM4_5GH_OFDMPO, 0xffff}, 290 {"", 0, 0, SROM4_5GH_OFDMPO + 1, 0xffff}, 291 {"ofdm2gpo", 0x00000100, SRFL_MORE, SROM8_2G_OFDMPO, 0xffff}, 292 {"", 0, 0, SROM8_2G_OFDMPO + 1, 0xffff}, 293 {"ofdm5gpo", 0x00000100, SRFL_MORE, SROM8_5G_OFDMPO, 0xffff}, 294 {"", 0, 0, SROM8_5G_OFDMPO + 1, 0xffff}, 295 {"ofdm5glpo", 0x00000100, SRFL_MORE, SROM8_5GL_OFDMPO, 0xffff}, 296 {"", 0, 0, SROM8_5GL_OFDMPO + 1, 0xffff}, 297 {"ofdm5ghpo", 0x00000100, SRFL_MORE, SROM8_5GH_OFDMPO, 0xffff}, 298 {"", 0, 0, SROM8_5GH_OFDMPO + 1, 0xffff}, 299 {"mcs2gpo0", 0x000000f0, 0, SROM4_2G_MCSPO, 0xffff}, 300 {"mcs2gpo1", 0x000000f0, 0, SROM4_2G_MCSPO + 1, 0xffff}, 301 {"mcs2gpo2", 0x000000f0, 0, SROM4_2G_MCSPO + 2, 0xffff}, 302 {"mcs2gpo3", 0x000000f0, 0, SROM4_2G_MCSPO + 3, 0xffff}, 303 {"mcs2gpo4", 0x000000f0, 0, SROM4_2G_MCSPO + 4, 0xffff}, 304 {"mcs2gpo5", 0x000000f0, 0, SROM4_2G_MCSPO + 5, 0xffff}, 305 {"mcs2gpo6", 0x000000f0, 0, SROM4_2G_MCSPO + 6, 0xffff}, 306 {"mcs2gpo7", 0x000000f0, 0, SROM4_2G_MCSPO + 7, 0xffff}, 307 {"mcs5gpo0", 0x000000f0, 0, SROM4_5G_MCSPO, 0xffff}, 308 {"mcs5gpo1", 0x000000f0, 0, SROM4_5G_MCSPO + 1, 0xffff}, 309 {"mcs5gpo2", 0x000000f0, 0, SROM4_5G_MCSPO + 2, 0xffff}, 310 {"mcs5gpo3", 0x000000f0, 0, SROM4_5G_MCSPO + 3, 0xffff}, 311 {"mcs5gpo4", 0x000000f0, 0, SROM4_5G_MCSPO + 4, 0xffff}, 312 {"mcs5gpo5", 0x000000f0, 0, SROM4_5G_MCSPO + 5, 0xffff}, 313 {"mcs5gpo6", 0x000000f0, 0, SROM4_5G_MCSPO + 6, 0xffff}, 314 {"mcs5gpo7", 0x000000f0, 0, SROM4_5G_MCSPO + 7, 0xffff}, 315 {"mcs5glpo0", 0x000000f0, 0, SROM4_5GL_MCSPO, 0xffff}, 316 {"mcs5glpo1", 0x000000f0, 0, SROM4_5GL_MCSPO + 1, 0xffff}, 317 {"mcs5glpo2", 0x000000f0, 0, SROM4_5GL_MCSPO + 2, 0xffff}, 318 {"mcs5glpo3", 0x000000f0, 0, SROM4_5GL_MCSPO + 3, 0xffff}, 319 {"mcs5glpo4", 0x000000f0, 0, SROM4_5GL_MCSPO + 4, 0xffff}, 320 {"mcs5glpo5", 0x000000f0, 0, SROM4_5GL_MCSPO + 5, 0xffff}, 321 {"mcs5glpo6", 0x000000f0, 0, SROM4_5GL_MCSPO + 6, 0xffff}, 322 {"mcs5glpo7", 0x000000f0, 0, SROM4_5GL_MCSPO + 7, 0xffff}, 323 {"mcs5ghpo0", 0x000000f0, 0, SROM4_5GH_MCSPO, 0xffff}, 324 {"mcs5ghpo1", 0x000000f0, 0, SROM4_5GH_MCSPO + 1, 0xffff}, 325 {"mcs5ghpo2", 0x000000f0, 0, SROM4_5GH_MCSPO + 2, 0xffff}, 326 {"mcs5ghpo3", 0x000000f0, 0, SROM4_5GH_MCSPO + 3, 0xffff}, 327 {"mcs5ghpo4", 0x000000f0, 0, SROM4_5GH_MCSPO + 4, 0xffff}, 328 {"mcs5ghpo5", 0x000000f0, 0, SROM4_5GH_MCSPO + 5, 0xffff}, 329 {"mcs5ghpo6", 0x000000f0, 0, SROM4_5GH_MCSPO + 6, 0xffff}, 330 {"mcs5ghpo7", 0x000000f0, 0, SROM4_5GH_MCSPO + 7, 0xffff}, 331 {"mcs2gpo0", 0x00000100, 0, SROM8_2G_MCSPO, 0xffff}, 332 {"mcs2gpo1", 0x00000100, 0, SROM8_2G_MCSPO + 1, 0xffff}, 333 {"mcs2gpo2", 0x00000100, 0, SROM8_2G_MCSPO + 2, 0xffff}, 334 {"mcs2gpo3", 0x00000100, 0, SROM8_2G_MCSPO + 3, 0xffff}, 335 {"mcs2gpo4", 0x00000100, 0, SROM8_2G_MCSPO + 4, 0xffff}, 336 {"mcs2gpo5", 0x00000100, 0, SROM8_2G_MCSPO + 5, 0xffff}, 337 {"mcs2gpo6", 0x00000100, 0, SROM8_2G_MCSPO + 6, 0xffff}, 338 {"mcs2gpo7", 0x00000100, 0, SROM8_2G_MCSPO + 7, 0xffff}, 339 {"mcs5gpo0", 0x00000100, 0, SROM8_5G_MCSPO, 0xffff}, 340 {"mcs5gpo1", 0x00000100, 0, SROM8_5G_MCSPO + 1, 0xffff}, 341 {"mcs5gpo2", 0x00000100, 0, SROM8_5G_MCSPO + 2, 0xffff}, 342 {"mcs5gpo3", 0x00000100, 0, SROM8_5G_MCSPO + 3, 0xffff}, 343 {"mcs5gpo4", 0x00000100, 0, SROM8_5G_MCSPO + 4, 0xffff}, 344 {"mcs5gpo5", 0x00000100, 0, SROM8_5G_MCSPO + 5, 0xffff}, 345 {"mcs5gpo6", 0x00000100, 0, SROM8_5G_MCSPO + 6, 0xffff}, 346 {"mcs5gpo7", 0x00000100, 0, SROM8_5G_MCSPO + 7, 0xffff}, 347 {"mcs5glpo0", 0x00000100, 0, SROM8_5GL_MCSPO, 0xffff}, 348 {"mcs5glpo1", 0x00000100, 0, SROM8_5GL_MCSPO + 1, 0xffff}, 349 {"mcs5glpo2", 0x00000100, 0, SROM8_5GL_MCSPO + 2, 0xffff}, 350 {"mcs5glpo3", 0x00000100, 0, SROM8_5GL_MCSPO + 3, 0xffff}, 351 {"mcs5glpo4", 0x00000100, 0, SROM8_5GL_MCSPO + 4, 0xffff}, 352 {"mcs5glpo5", 0x00000100, 0, SROM8_5GL_MCSPO + 5, 0xffff}, 353 {"mcs5glpo6", 0x00000100, 0, SROM8_5GL_MCSPO + 6, 0xffff}, 354 {"mcs5glpo7", 0x00000100, 0, SROM8_5GL_MCSPO + 7, 0xffff}, 355 {"mcs5ghpo0", 0x00000100, 0, SROM8_5GH_MCSPO, 0xffff}, 356 {"mcs5ghpo1", 0x00000100, 0, SROM8_5GH_MCSPO + 1, 0xffff}, 357 {"mcs5ghpo2", 0x00000100, 0, SROM8_5GH_MCSPO + 2, 0xffff}, 358 {"mcs5ghpo3", 0x00000100, 0, SROM8_5GH_MCSPO + 3, 0xffff}, 359 {"mcs5ghpo4", 0x00000100, 0, SROM8_5GH_MCSPO + 4, 0xffff}, 360 {"mcs5ghpo5", 0x00000100, 0, SROM8_5GH_MCSPO + 5, 0xffff}, 361 {"mcs5ghpo6", 0x00000100, 0, SROM8_5GH_MCSPO + 6, 0xffff}, 362 {"mcs5ghpo7", 0x00000100, 0, SROM8_5GH_MCSPO + 7, 0xffff}, 363 {"cddpo", 0x000000f0, 0, SROM4_CDDPO, 0xffff}, 364 {"stbcpo", 0x000000f0, 0, SROM4_STBCPO, 0xffff}, 365 {"bw40po", 0x000000f0, 0, SROM4_BW40PO, 0xffff}, 366 {"bwduppo", 0x000000f0, 0, SROM4_BWDUPPO, 0xffff}, 367 {"cddpo", 0x00000100, 0, SROM8_CDDPO, 0xffff}, 368 {"stbcpo", 0x00000100, 0, SROM8_STBCPO, 0xffff}, 369 {"bw40po", 0x00000100, 0, SROM8_BW40PO, 0xffff}, 370 {"bwduppo", 0x00000100, 0, SROM8_BWDUPPO, 0xffff}, 371 372 /* power per rate from sromrev 9 */ 373 {"cckbw202gpo", 0x00000600, 0, SROM9_2GPO_CCKBW20, 0xffff}, 374 {"cckbw20ul2gpo", 0x00000600, 0, SROM9_2GPO_CCKBW20UL, 0xffff}, 375 {"legofdmbw202gpo", 0x00000600, SRFL_MORE, SROM9_2GPO_LOFDMBW20, 0xffff}, 376 {"", 0, 0, SROM9_2GPO_LOFDMBW20 + 1, 0xffff}, 377 {"legofdmbw20ul2gpo", 0x00000600, SRFL_MORE, SROM9_2GPO_LOFDMBW20UL, 378 0xffff}, 379 {"", 0, 0, SROM9_2GPO_LOFDMBW20UL + 1, 0xffff}, 380 {"legofdmbw205glpo", 0x00000600, SRFL_MORE, SROM9_5GLPO_LOFDMBW20, 0xffff}, 381 {"", 0, 0, SROM9_5GLPO_LOFDMBW20 + 1, 0xffff}, 382 {"legofdmbw20ul5glpo", 0x00000600, SRFL_MORE, SROM9_5GLPO_LOFDMBW20UL, 383 0xffff}, 384 {"", 0, 0, SROM9_5GLPO_LOFDMBW20UL + 1, 0xffff}, 385 {"legofdmbw205gmpo", 0x00000600, SRFL_MORE, SROM9_5GMPO_LOFDMBW20, 0xffff}, 386 {"", 0, 0, SROM9_5GMPO_LOFDMBW20 + 1, 0xffff}, 387 {"legofdmbw20ul5gmpo", 0x00000600, SRFL_MORE, SROM9_5GMPO_LOFDMBW20UL, 388 0xffff}, 389 {"", 0, 0, SROM9_5GMPO_LOFDMBW20UL + 1, 0xffff}, 390 {"legofdmbw205ghpo", 0x00000600, SRFL_MORE, SROM9_5GHPO_LOFDMBW20, 0xffff}, 391 {"", 0, 0, SROM9_5GHPO_LOFDMBW20 + 1, 0xffff}, 392 {"legofdmbw20ul5ghpo", 0x00000600, SRFL_MORE, SROM9_5GHPO_LOFDMBW20UL, 393 0xffff}, 394 {"", 0, 0, SROM9_5GHPO_LOFDMBW20UL + 1, 0xffff}, 395 {"mcsbw202gpo", 0x00000600, SRFL_MORE, SROM9_2GPO_MCSBW20, 0xffff}, 396 {"", 0, 0, SROM9_2GPO_MCSBW20 + 1, 0xffff}, 397 {"mcsbw20ul2gpo", 0x00000600, SRFL_MORE, SROM9_2GPO_MCSBW20UL, 0xffff}, 398 {"", 0, 0, SROM9_2GPO_MCSBW20UL + 1, 0xffff}, 399 {"mcsbw402gpo", 0x00000600, SRFL_MORE, SROM9_2GPO_MCSBW40, 0xffff}, 400 {"", 0, 0, SROM9_2GPO_MCSBW40 + 1, 0xffff}, 401 {"mcsbw205glpo", 0x00000600, SRFL_MORE, SROM9_5GLPO_MCSBW20, 0xffff}, 402 {"", 0, 0, SROM9_5GLPO_MCSBW20 + 1, 0xffff}, 403 {"mcsbw20ul5glpo", 0x00000600, SRFL_MORE, SROM9_5GLPO_MCSBW20UL, 0xffff}, 404 {"", 0, 0, SROM9_5GLPO_MCSBW20UL + 1, 0xffff}, 405 {"mcsbw405glpo", 0x00000600, SRFL_MORE, SROM9_5GLPO_MCSBW40, 0xffff}, 406 {"", 0, 0, SROM9_5GLPO_MCSBW40 + 1, 0xffff}, 407 {"mcsbw205gmpo", 0x00000600, SRFL_MORE, SROM9_5GMPO_MCSBW20, 0xffff}, 408 {"", 0, 0, SROM9_5GMPO_MCSBW20 + 1, 0xffff}, 409 {"mcsbw20ul5gmpo", 0x00000600, SRFL_MORE, SROM9_5GMPO_MCSBW20UL, 0xffff}, 410 {"", 0, 0, SROM9_5GMPO_MCSBW20UL + 1, 0xffff}, 411 {"mcsbw405gmpo", 0x00000600, SRFL_MORE, SROM9_5GMPO_MCSBW40, 0xffff}, 412 {"", 0, 0, SROM9_5GMPO_MCSBW40 + 1, 0xffff}, 413 {"mcsbw205ghpo", 0x00000600, SRFL_MORE, SROM9_5GHPO_MCSBW20, 0xffff}, 414 {"", 0, 0, SROM9_5GHPO_MCSBW20 + 1, 0xffff}, 415 {"mcsbw20ul5ghpo", 0x00000600, SRFL_MORE, SROM9_5GHPO_MCSBW20UL, 0xffff}, 416 {"", 0, 0, SROM9_5GHPO_MCSBW20UL + 1, 0xffff}, 417 {"mcsbw405ghpo", 0x00000600, SRFL_MORE, SROM9_5GHPO_MCSBW40, 0xffff}, 418 {"", 0, 0, SROM9_5GHPO_MCSBW40 + 1, 0xffff}, 419 {"mcs32po", 0x00000600, 0, SROM9_PO_MCS32, 0xffff}, 420 {"legofdm40duppo", 0x00000600, 0, SROM9_PO_LOFDM40DUP, 0xffff}, 421 {"pcieingress_war", 0x00000700, 0, SROM8_PCIEINGRESS_WAR, 0xf}, 422 {"eu_edthresh2g", 0x00000100, 0, SROM8_EU_EDCRSTH, 0x00ff}, 423 {"eu_edthresh5g", 0x00000100, 0, SROM8_EU_EDCRSTH, 0xff00}, 424 {"eu_edthresh2g", 0x00000200, 0, SROM9_EU_EDCRSTH, 0x00ff}, 425 {"eu_edthresh5g", 0x00000200, 0, SROM9_EU_EDCRSTH, 0xff00}, 426 {"rxgainerr2ga0", 0x00000700, 0, SROM8_RXGAINERR_2G, 0x003f}, 427 {"rxgainerr2ga0", 0x00000700, 0, SROM8_RXGAINERR_2G, 0x003f}, 428 {"rxgainerr2ga1", 0x00000700, 0, SROM8_RXGAINERR_2G, 0x07c0}, 429 {"rxgainerr2ga2", 0x00000700, 0, SROM8_RXGAINERR_2G, 0xf800}, 430 {"rxgainerr5gla0", 0x00000700, 0, SROM8_RXGAINERR_5GL, 0x003f}, 431 {"rxgainerr5gla1", 0x00000700, 0, SROM8_RXGAINERR_5GL, 0x07c0}, 432 {"rxgainerr5gla2", 0x00000700, 0, SROM8_RXGAINERR_5GL, 0xf800}, 433 {"rxgainerr5gma0", 0x00000700, 0, SROM8_RXGAINERR_5GM, 0x003f}, 434 {"rxgainerr5gma1", 0x00000700, 0, SROM8_RXGAINERR_5GM, 0x07c0}, 435 {"rxgainerr5gma2", 0x00000700, 0, SROM8_RXGAINERR_5GM, 0xf800}, 436 {"rxgainerr5gha0", 0x00000700, 0, SROM8_RXGAINERR_5GH, 0x003f}, 437 {"rxgainerr5gha1", 0x00000700, 0, SROM8_RXGAINERR_5GH, 0x07c0}, 438 {"rxgainerr5gha2", 0x00000700, 0, SROM8_RXGAINERR_5GH, 0xf800}, 439 {"rxgainerr5gua0", 0x00000700, 0, SROM8_RXGAINERR_5GU, 0x003f}, 440 {"rxgainerr5gua1", 0x00000700, 0, SROM8_RXGAINERR_5GU, 0x07c0}, 441 {"rxgainerr5gua2", 0x00000700, 0, SROM8_RXGAINERR_5GU, 0xf800}, 442 {"sar2g", 0x00000600, 0, SROM9_SAR, 0x00ff}, 443 {"sar5g", 0x00000600, 0, SROM9_SAR, 0xff00}, 444 {"noiselvl2ga0", 0x00000700, 0, SROM8_NOISELVL_2G, 0x001f}, 445 {"noiselvl2ga1", 0x00000700, 0, SROM8_NOISELVL_2G, 0x03e0}, 446 {"noiselvl2ga2", 0x00000700, 0, SROM8_NOISELVL_2G, 0x7c00}, 447 {"noiselvl5gla0", 0x00000700, 0, SROM8_NOISELVL_5GL, 0x001f}, 448 {"noiselvl5gla1", 0x00000700, 0, SROM8_NOISELVL_5GL, 0x03e0}, 449 {"noiselvl5gla2", 0x00000700, 0, SROM8_NOISELVL_5GL, 0x7c00}, 450 {"noiselvl5gma0", 0x00000700, 0, SROM8_NOISELVL_5GM, 0x001f}, 451 {"noiselvl5gma1", 0x00000700, 0, SROM8_NOISELVL_5GM, 0x03e0}, 452 {"noiselvl5gma2", 0x00000700, 0, SROM8_NOISELVL_5GM, 0x7c00}, 453 {"noiselvl5gha0", 0x00000700, 0, SROM8_NOISELVL_5GH, 0x001f}, 454 {"noiselvl5gha1", 0x00000700, 0, SROM8_NOISELVL_5GH, 0x03e0}, 455 {"noiselvl5gha2", 0x00000700, 0, SROM8_NOISELVL_5GH, 0x7c00}, 456 {"noiselvl5gua0", 0x00000700, 0, SROM8_NOISELVL_5GU, 0x001f}, 457 {"noiselvl5gua1", 0x00000700, 0, SROM8_NOISELVL_5GU, 0x03e0}, 458 {"noiselvl5gua2", 0x00000700, 0, SROM8_NOISELVL_5GU, 0x7c00}, 459 {"noisecaloffset", 0x00000300, 0, SROM8_NOISECALOFFSET, 0x00ff}, 460 {"noisecaloffset5g", 0x00000300, 0, SROM8_NOISECALOFFSET, 0xff00}, 461 {"subband5gver", 0x00000700, 0, SROM8_SUBBAND_PPR, 0x7}, 462 463 {"cckPwrOffset", 0x00000400, 0, SROM10_CCKPWROFFSET, 0xffff}, 464 {"eu_edthresh2g", 0x00000400, 0, SROM10_EU_EDCRSTH, 0x00ff}, 465 {"eu_edthresh5g", 0x00000400, 0, SROM10_EU_EDCRSTH, 0xff00}, 466 /* swctrlmap_2g array, note that the last element doesn't have SRFL_ARRAY 467 flag set */ 468 {"swctrlmap_2g", 0x00000400, SRFL_MORE | SRFL_PRHEX | SRFL_ARRAY, 469 SROM10_SWCTRLMAP_2G, 0xffff}, 470 {"", 0x00000400, SRFL_ARRAY, SROM10_SWCTRLMAP_2G + 1, 0xffff}, 471 {"", 0x00000400, SRFL_MORE | SRFL_PRHEX | SRFL_ARRAY, 472 SROM10_SWCTRLMAP_2G + 2, 0xffff}, 473 {"", 0x00000400, SRFL_ARRAY, SROM10_SWCTRLMAP_2G + 3, 0xffff}, 474 {"", 0x00000400, SRFL_MORE | SRFL_PRHEX | SRFL_ARRAY, 475 SROM10_SWCTRLMAP_2G + 4, 0xffff}, 476 {"", 0x00000400, SRFL_ARRAY, SROM10_SWCTRLMAP_2G + 5, 0xffff}, 477 {"", 0x00000400, SRFL_MORE | SRFL_PRHEX | SRFL_ARRAY, 478 SROM10_SWCTRLMAP_2G + 6, 0xffff}, 479 {"", 0x00000400, SRFL_ARRAY, SROM10_SWCTRLMAP_2G + 7, 0xffff}, 480 {"", 0x00000400, SRFL_PRHEX, SROM10_SWCTRLMAP_2G + 8, 0xffff}, 481 482 /* sromrev 11 */ 483 {"boardflags3", 0xfffff800, SRFL_PRHEX | SRFL_MORE, SROM11_BFL4, 0xffff}, 484 {"", 0, 0, SROM11_BFL5, 0xffff}, 485 {"boardnum", 0xfffff800, 0, SROM11_MACLO, 0xffff}, 486 {"macaddr", 0xfffff800, SRFL_ETHADDR, SROM11_MACHI, 0xffff}, 487 {"ccode", 0xfffff800, SRFL_CCODE, SROM11_CCODE, 0xffff}, 488 {"regrev", 0xfffff800, 0, SROM11_REGREV, 0xffff}, 489 {"ledbh0", 0xfffff800, SRFL_NOFFS, SROM11_LEDBH10, 0x00ff}, 490 {"ledbh1", 0xfffff800, SRFL_NOFFS, SROM11_LEDBH10, 0xff00}, 491 {"ledbh2", 0xfffff800, SRFL_NOFFS, SROM11_LEDBH32, 0x00ff}, 492 {"ledbh3", 0xfffff800, SRFL_NOFFS, SROM11_LEDBH32, 0xff00}, 493 {"leddc", 0xfffff800, SRFL_NOFFS | SRFL_LEDDC, SROM11_LEDDC, 0xffff}, 494 {"aa2g", 0xfffff800, 0, SROM11_AA, 0x00ff}, 495 {"aa5g", 0xfffff800, 0, SROM11_AA, 0xff00}, 496 {"agbg0", 0xfffff800, 0, SROM11_AGBG10, 0xff00}, 497 {"agbg1", 0xfffff800, 0, SROM11_AGBG10, 0x00ff}, 498 {"agbg2", 0xfffff800, 0, SROM11_AGBG2A0, 0xff00}, 499 {"aga0", 0xfffff800, 0, SROM11_AGBG2A0, 0x00ff}, 500 {"aga1", 0xfffff800, 0, SROM11_AGA21, 0xff00}, 501 {"aga2", 0xfffff800, 0, SROM11_AGA21, 0x00ff}, 502 {"txchain", 0xfffff800, SRFL_NOFFS, SROM11_TXRXC, SROM4_TXCHAIN_MASK}, 503 {"rxchain", 0xfffff800, SRFL_NOFFS, SROM11_TXRXC, SROM4_RXCHAIN_MASK}, 504 {"antswitch", 0xfffff800, SRFL_NOFFS, SROM11_TXRXC, SROM4_SWITCH_MASK}, 505 506 {"tssiposslope2g", 0xfffff800, 0, SROM11_FEM_CFG1, 0x0001}, 507 {"epagain2g", 0xfffff800, 0, SROM11_FEM_CFG1, 0x000e}, 508 {"pdgain2g", 0xfffff800, 0, SROM11_FEM_CFG1, 0x01f0}, 509 {"tworangetssi2g", 0xfffff800, 0, SROM11_FEM_CFG1, 0x0200}, 510 {"papdcap2g", 0xfffff800, 0, SROM11_FEM_CFG1, 0x0400}, 511 {"femctrl", 0xfffff800, 0, SROM11_FEM_CFG1, 0xf800}, 512 513 {"tssiposslope5g", 0xfffff800, 0, SROM11_FEM_CFG2, 0x0001}, 514 {"epagain5g", 0xfffff800, 0, SROM11_FEM_CFG2, 0x000e}, 515 {"pdgain5g", 0xfffff800, 0, SROM11_FEM_CFG2, 0x01f0}, 516 {"tworangetssi5g", 0xfffff800, 0, SROM11_FEM_CFG2, 0x0200}, 517 {"papdcap5g", 0xfffff800, 0, SROM11_FEM_CFG2, 0x0400}, 518 {"gainctrlsph", 0xfffff800, 0, SROM11_FEM_CFG2, 0xf800}, 519 520 {"tempthresh", 0xfffff800, 0, SROM11_THERMAL, 0xff00}, 521 {"tempoffset", 0xfffff800, 0, SROM11_THERMAL, 0x00ff}, 522 {"rawtempsense", 0xfffff800, SRFL_PRHEX, SROM11_MPWR_RAWTS, 0x01ff}, 523 {"measpower", 0xfffff800, SRFL_PRHEX, SROM11_MPWR_RAWTS, 0xfe00}, 524 {"tempsense_slope", 0xfffff800, SRFL_PRHEX, SROM11_TS_SLP_OPT_CORRX, 525 0x00ff}, 526 {"tempcorrx", 0xfffff800, SRFL_PRHEX, SROM11_TS_SLP_OPT_CORRX, 0xfc00}, 527 {"tempsense_option", 0xfffff800, SRFL_PRHEX, SROM11_TS_SLP_OPT_CORRX, 528 0x0300}, 529 {"xtalfreq", 0xfffff800, 0, SROM11_XTAL_FREQ, 0xffff}, 530 {"txpwrbckof", 0x00000800, SRFL_PRHEX, SROM11_PATH0 + SROM11_2G_MAXP, 531 0xff00}, 532 /* Special PA Params for 4350 5G Band, 40/80 MHz BW Ant #1 */ 533 {"pa5gbw4080a1", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, 534 SROM11_5GB0_4080_W0_A1, 0xffff}, 535 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB0_4080_W1_A1, 0xffff}, 536 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB0_4080_W2_A1, 0xffff}, 537 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB1_4080_W0_A1, 0xffff}, 538 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, 539 SROM11_PATH2 + SROM11_5GB1_4080_PA, 0xffff}, 540 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, 541 SROM11_PATH2 + SROM11_5GB1_4080_PA + 1, 0xffff}, 542 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, 543 SROM11_PATH2 + SROM11_5GB2_4080_PA, 0xffff}, 544 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, 545 SROM11_PATH2 + SROM11_5GB2_4080_PA + 1, 0xffff}, 546 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, 547 SROM11_PATH2 + SROM11_5GB2_4080_PA + 2, 0xffff}, 548 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, 549 SROM11_PATH2 + SROM11_5GB3_4080_PA, 0xffff}, 550 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, 551 SROM11_PATH2 + SROM11_5GB3_4080_PA + 1, 0xffff}, 552 {"", 0xfffff800, SRFL_PRHEX, SROM11_PATH2 + SROM11_5GB3_4080_PA + 2, 553 0xffff}, 554 {"phycal_tempdelta", 0xfffff800, 0, SROM11_PHYCAL_TEMPDELTA, 0x00ff}, 555 {"temps_period", 0xfffff800, 0, SROM11_PHYCAL_TEMPDELTA, 0x0f00}, 556 {"temps_hysteresis", 0xfffff800, 0, SROM11_PHYCAL_TEMPDELTA, 0xf000}, 557 {"measpower1", 0xfffff800, SRFL_PRHEX, SROM11_MPWR_1_AND_2, 0x007f}, 558 {"measpower2", 0xfffff800, SRFL_PRHEX, SROM11_MPWR_1_AND_2, 0x3f80}, 559 {"tssifloor2g", 0xfffff800, SRFL_PRHEX, SROM11_TSSIFLOOR_2G, 0x03ff}, 560 {"tssifloor5g", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_TSSIFLOOR_5GL, 561 0x03ff}, 562 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_TSSIFLOOR_5GM, 0x03ff}, 563 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_TSSIFLOOR_5GH, 0x03ff}, 564 {"", 0xfffff800, SRFL_PRHEX, SROM11_TSSIFLOOR_5GU, 0x03ff}, 565 {"pdoffset2g40ma0", 0xfffff800, 0, SROM11_PDOFF_2G_40M, 0x000f}, 566 {"pdoffset2g40ma1", 0xfffff800, 0, SROM11_PDOFF_2G_40M, 0x00f0}, 567 {"pdoffset2g40ma2", 0xfffff800, 0, SROM11_PDOFF_2G_40M, 0x0f00}, 568 {"pdoffset2g40mvalid", 0xfffff800, 0, SROM11_PDOFF_2G_40M, 0x8000}, 569 {"pdoffset40ma0", 0xfffff800, 0, SROM11_PDOFF_40M_A0, 0xffff}, 570 {"pdoffset40ma1", 0xfffff800, 0, SROM11_PDOFF_40M_A1, 0xffff}, 571 {"pdoffset40ma2", 0xfffff800, 0, SROM11_PDOFF_40M_A2, 0xffff}, 572 {"pdoffset80ma0", 0xfffff800, 0, SROM11_PDOFF_80M_A0, 0xffff}, 573 {"pdoffset80ma1", 0xfffff800, 0, SROM11_PDOFF_80M_A1, 0xffff}, 574 {"pdoffset80ma2", 0xfffff800, 0, SROM11_PDOFF_80M_A2, 0xffff}, 575 576 {"subband5gver", 0xfffff800, SRFL_PRHEX, SROM11_SUBBAND5GVER, 0xffff}, 577 {"paparambwver", 0xfffff800, 0, SROM11_MCSLR5GLPO, 0xf000}, 578 {"rx5ggainwar", 0xfffff800, 0, SROM11_MCSLR5GMPO, 0x2000}, 579 /* Special PA Params for 4350 5G Band, 40/80 MHz BW Ant #0 */ 580 {"pa5gbw4080a0", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, 581 SROM11_PATH2 + SROM11_5GB0_PA, 0xffff}, 582 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB0_PA + 1, 583 0xffff}, 584 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB0_PA + 2, 585 0xffff}, 586 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB1_PA, 587 0xffff}, 588 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB1_PA + 1, 589 0xffff}, 590 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB1_PA + 2, 591 0xffff}, 592 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB2_PA, 593 0xffff}, 594 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB2_PA + 1, 595 0xffff}, 596 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB2_PA + 2, 597 0xffff}, 598 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB3_PA, 599 0xffff}, 600 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB3_PA + 1, 601 0xffff}, 602 {"", 0xfffff800, SRFL_PRHEX, SROM11_PATH2 + SROM11_5GB3_PA + 2, 0xffff}, 603 /* Special PA Params for 4335 5G Band, 40 MHz BW */ 604 {"pa5gbw40a0", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, 605 SROM11_PATH1 + SROM11_5GB0_PA, 0xffff}, 606 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB0_PA + 1, 607 0xffff}, 608 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB0_PA + 2, 609 0xffff}, 610 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB1_PA, 611 0xffff}, 612 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB1_PA + 1, 613 0xffff}, 614 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB1_PA + 2, 615 0xffff}, 616 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB2_PA, 617 0xffff}, 618 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB2_PA + 1, 619 0xffff}, 620 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB2_PA + 2, 621 0xffff}, 622 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB3_PA, 623 0xffff}, 624 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_5GB3_PA + 1, 625 0xffff}, 626 {"", 0xfffff800, SRFL_PRHEX, SROM11_PATH1 + SROM11_5GB3_PA + 2, 0xffff}, 627 /* Special PA Params for 4335 5G Band, 80 MHz BW */ 628 {"pa5gbw80a0", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, 629 SROM11_PATH2 + SROM11_5GB0_PA, 0xffff}, 630 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB0_PA + 1, 631 0xffff}, 632 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB0_PA + 2, 633 0xffff}, 634 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB1_PA, 635 0xffff}, 636 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB1_PA + 1, 637 0xffff}, 638 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB1_PA + 2, 639 0xffff}, 640 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB2_PA, 641 0xffff}, 642 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB2_PA + 1, 643 0xffff}, 644 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB2_PA + 2, 645 0xffff}, 646 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB3_PA, 647 0xffff}, 648 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH2 + SROM11_5GB3_PA + 1, 649 0xffff}, 650 {"", 0xfffff800, SRFL_PRHEX, SROM11_PATH2 + SROM11_5GB3_PA + 2, 0xffff}, 651 /* Special PA Params for 4335 2G Band, CCK */ 652 {"pa2gccka0", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, 653 SROM11_PATH1 + SROM11_2G_PA, 0xffff}, 654 {"", 0xfffff800, SRFL_PRHEX | SRFL_ARRAY, SROM11_PATH1 + SROM11_2G_PA + 1, 655 0xffff}, 656 {"", 0xfffff800, SRFL_PRHEX, SROM11_PATH1 + SROM11_2G_PA + 2, 0xffff}, 657 658 /* power per rate */ 659 {"cckbw202gpo", 0xfffff800, 0, SROM11_CCKBW202GPO, 0xffff}, 660 {"cckbw20ul2gpo", 0xfffff800, 0, SROM11_CCKBW20UL2GPO, 0xffff}, 661 {"mcsbw202gpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW202GPO, 0xffff}, 662 {"", 0xfffff800, 0, SROM11_MCSBW202GPO_1, 0xffff}, 663 {"mcsbw402gpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW402GPO, 0xffff}, 664 {"", 0xfffff800, 0, SROM11_MCSBW402GPO_1, 0xffff}, 665 {"dot11agofdmhrbw202gpo", 0xfffff800, 0, SROM11_DOT11AGOFDMHRBW202GPO, 666 0xffff}, 667 {"ofdmlrbw202gpo", 0xfffff800, 0, SROM11_OFDMLRBW202GPO, 0xffff}, 668 {"mcsbw205glpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW205GLPO, 0xffff}, 669 {"", 0xfffff800, 0, SROM11_MCSBW205GLPO_1, 0xffff}, 670 {"mcsbw405glpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW405GLPO, 0xffff}, 671 {"", 0xfffff800, 0, SROM11_MCSBW405GLPO_1, 0xffff}, 672 {"mcsbw805glpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW805GLPO, 0xffff}, 673 {"", 0xfffff800, 0, SROM11_MCSBW805GLPO_1, 0xffff}, 674 {"mcsbw205gmpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW205GMPO, 0xffff}, 675 {"", 0xfffff800, 0, SROM11_MCSBW205GMPO_1, 0xffff}, 676 {"mcsbw405gmpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW405GMPO, 0xffff}, 677 {"", 0xfffff800, 0, SROM11_MCSBW405GMPO_1, 0xffff}, 678 {"mcsbw805gmpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW805GMPO, 0xffff}, 679 {"", 0xfffff800, 0, SROM11_MCSBW805GMPO_1, 0xffff}, 680 {"mcsbw205ghpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW205GHPO, 0xffff}, 681 {"", 0xfffff800, 0, SROM11_MCSBW205GHPO_1, 0xffff}, 682 {"mcsbw405ghpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW405GHPO, 0xffff}, 683 {"", 0xfffff800, 0, SROM11_MCSBW405GHPO_1, 0xffff}, 684 {"mcsbw805ghpo", 0xfffff800, SRFL_MORE, SROM11_MCSBW805GHPO, 0xffff}, 685 {"", 0xfffff800, 0, SROM11_MCSBW805GHPO_1, 0xffff}, 686 {"mcslr5glpo", 0xfffff800, 0, SROM11_MCSLR5GLPO, 0x0fff}, 687 {"mcslr5gmpo", 0xfffff800, 0, SROM11_MCSLR5GMPO, 0xffff}, 688 {"mcslr5ghpo", 0xfffff800, 0, SROM11_MCSLR5GHPO, 0xffff}, 689 {"sb20in40hrpo", 0xfffff800, 0, SROM11_SB20IN40HRPO, 0xffff}, 690 {"sb20in80and160hr5glpo", 0xfffff800, 0, SROM11_SB20IN80AND160HR5GLPO, 691 0xffff}, 692 {"sb40and80hr5glpo", 0xfffff800, 0, SROM11_SB40AND80HR5GLPO, 0xffff}, 693 {"sb20in80and160hr5gmpo", 0xfffff800, 0, SROM11_SB20IN80AND160HR5GMPO, 694 0xffff}, 695 {"sb40and80hr5gmpo", 0xfffff800, 0, SROM11_SB40AND80HR5GMPO, 0xffff}, 696 {"sb20in80and160hr5ghpo", 0xfffff800, 0, SROM11_SB20IN80AND160HR5GHPO, 697 0xffff}, 698 {"sb40and80hr5ghpo", 0xfffff800, 0, SROM11_SB40AND80HR5GHPO, 0xffff}, 699 {"sb20in40lrpo", 0xfffff800, 0, SROM11_SB20IN40LRPO, 0xffff}, 700 {"sb20in80and160lr5glpo", 0xfffff800, 0, SROM11_SB20IN80AND160LR5GLPO, 701 0xffff}, 702 {"sb40and80lr5glpo", 0xfffff800, 0, SROM11_SB40AND80LR5GLPO, 0xffff}, 703 {"sb20in80and160lr5gmpo", 0xfffff800, 0, SROM11_SB20IN80AND160LR5GMPO, 704 0xffff}, 705 {"sb40and80lr5gmpo", 0xfffff800, 0, SROM11_SB40AND80LR5GMPO, 0xffff}, 706 {"sb20in80and160lr5ghpo", 0xfffff800, 0, SROM11_SB20IN80AND160LR5GHPO, 707 0xffff}, 708 {"sb40and80lr5ghpo", 0xfffff800, 0, SROM11_SB40AND80LR5GHPO, 0xffff}, 709 {"dot11agduphrpo", 0xfffff800, 0, SROM11_DOT11AGDUPHRPO, 0xffff}, 710 {"dot11agduplrpo", 0xfffff800, 0, SROM11_DOT11AGDUPLRPO, 0xffff}, 711 712 /* Misc */ 713 {"sar2g", 0xfffff800, 0, SROM11_SAR, 0x00ff}, 714 {"sar5g", 0xfffff800, 0, SROM11_SAR, 0xff00}, 715 716 {"noiselvl2ga0", 0xfffff800, 0, SROM11_NOISELVL_2G, 0x001f}, 717 {"noiselvl2ga1", 0xfffff800, 0, SROM11_NOISELVL_2G, 0x03e0}, 718 {"noiselvl2ga2", 0xfffff800, 0, SROM11_NOISELVL_2G, 0x7c00}, 719 {"noiselvl5ga0", 0xfffff800, SRFL_ARRAY, SROM11_NOISELVL_5GL, 0x001f}, 720 {"", 0xfffff800, SRFL_ARRAY, SROM11_NOISELVL_5GM, 0x001f}, 721 {"", 0xfffff800, SRFL_ARRAY, SROM11_NOISELVL_5GH, 0x001f}, 722 {"", 0xfffff800, 0, SROM11_NOISELVL_5GU, 0x001f}, 723 {"noiselvl5ga1", 0xfffff800, SRFL_ARRAY, SROM11_NOISELVL_5GL, 0x03e0}, 724 {"", 0xfffff800, SRFL_ARRAY, SROM11_NOISELVL_5GM, 0x03e0}, 725 {"", 0xfffff800, SRFL_ARRAY, SROM11_NOISELVL_5GH, 0x03e0}, 726 {"", 0xfffff800, 0, SROM11_NOISELVL_5GU, 0x03e0}, 727 {"noiselvl5ga2", 0xfffff800, SRFL_ARRAY, SROM11_NOISELVL_5GL, 0x7c00}, 728 {"", 0xfffff800, SRFL_ARRAY, SROM11_NOISELVL_5GM, 0x7c00}, 729 {"", 0xfffff800, SRFL_ARRAY, SROM11_NOISELVL_5GH, 0x7c00}, 730 {"", 0xfffff800, 0, SROM11_NOISELVL_5GU, 0x7c00}, 731 {"eu_edthresh2g", 0x00000800, 0, SROM11_EU_EDCRSTH, 0x00ff}, 732 {"eu_edthresh5g", 0x00000800, 0, SROM11_EU_EDCRSTH, 0xff00}, 733 734 {"rxgainerr2ga0", 0xfffff800, 0, SROM11_RXGAINERR_2G, 0x003f}, 735 {"rxgainerr2ga1", 0xfffff800, 0, SROM11_RXGAINERR_2G, 0x07c0}, 736 {"rxgainerr2ga2", 0xfffff800, 0, SROM11_RXGAINERR_2G, 0xf800}, 737 {"rxgainerr5ga0", 0xfffff800, SRFL_ARRAY, SROM11_RXGAINERR_5GL, 0x003f}, 738 {"", 0xfffff800, SRFL_ARRAY, SROM11_RXGAINERR_5GM, 0x003f}, 739 {"", 0xfffff800, SRFL_ARRAY, SROM11_RXGAINERR_5GH, 0x003f}, 740 {"", 0xfffff800, 0, SROM11_RXGAINERR_5GU, 0x003f}, 741 {"rxgainerr5ga1", 0xfffff800, SRFL_ARRAY, SROM11_RXGAINERR_5GL, 0x07c0}, 742 {"", 0xfffff800, SRFL_ARRAY, SROM11_RXGAINERR_5GM, 0x07c0}, 743 {"", 0xfffff800, SRFL_ARRAY, SROM11_RXGAINERR_5GH, 0x07c0}, 744 {"", 0xfffff800, 0, SROM11_RXGAINERR_5GU, 0x07c0}, 745 {"rxgainerr5ga2", 0xfffff800, SRFL_ARRAY, SROM11_RXGAINERR_5GL, 0xf800}, 746 {"", 0xfffff800, SRFL_ARRAY, SROM11_RXGAINERR_5GM, 0xf800}, 747 {"", 0xfffff800, SRFL_ARRAY, SROM11_RXGAINERR_5GH, 0xf800}, 748 {"", 0xfffff800, 0, SROM11_RXGAINERR_5GU, 0xf800}, 749 {"rpcal2g", 0xfffff800, 0, SROM11_RPCAL_2G, 0xffff}, 750 {"rpcal5gb0", 0xfffff800, 0, SROM11_RPCAL_5GL, 0xffff}, 751 {"rpcal5gb1", 0xfffff800, 0, SROM11_RPCAL_5GM, 0xffff}, 752 {"rpcal5gb2", 0xfffff800, 0, SROM11_RPCAL_5GH, 0xffff}, 753 {"rpcal5gb3", 0xfffff800, 0, SROM11_RPCAL_5GU, 0xffff}, 754 {"txidxcap2g", 0xfffff800, 0, SROM11_TXIDXCAP2G, 0x0ff0}, 755 {"txidxcap5g", 0xfffff800, 0, SROM11_TXIDXCAP5G, 0x0ff0}, 756 {"pdoffsetcckma0", 0xfffff800, 0, SROM11_PDOFF_2G_CCK, 0x000f}, 757 {"pdoffsetcckma1", 0xfffff800, 0, SROM11_PDOFF_2G_CCK, 0x00f0}, 758 {"pdoffsetcckma2", 0xfffff800, 0, SROM11_PDOFF_2G_CCK, 0x0f00}, 759 760 /* sromrev 12 */ 761 {"boardflags4", 0xfffff000, SRFL_PRHEX | SRFL_MORE, SROM12_BFL6, 0xffff}, 762 {"", 0, 0, SROM12_BFL7, 0xffff}, 763 {"pdoffsetcck", 0xfffff000, 0, SROM12_PDOFF_2G_CCK, 0xffff}, 764 {"pdoffset20in40m5gb0", 0xfffff000, 0, SROM12_PDOFF_20in40M_5G_B0, 0xffff}, 765 {"pdoffset20in40m5gb1", 0xfffff000, 0, SROM12_PDOFF_20in40M_5G_B1, 0xffff}, 766 {"pdoffset20in40m5gb2", 0xfffff000, 0, SROM12_PDOFF_20in40M_5G_B2, 0xffff}, 767 {"pdoffset20in40m5gb3", 0xfffff000, 0, SROM12_PDOFF_20in40M_5G_B3, 0xffff}, 768 {"pdoffset20in40m5gb4", 0xfffff000, 0, SROM12_PDOFF_20in40M_5G_B4, 0xffff}, 769 {"pdoffset40in80m5gb0", 0xfffff000, 0, SROM12_PDOFF_40in80M_5G_B0, 0xffff}, 770 {"pdoffset40in80m5gb1", 0xfffff000, 0, SROM12_PDOFF_40in80M_5G_B1, 0xffff}, 771 {"pdoffset40in80m5gb2", 0xfffff000, 0, SROM12_PDOFF_40in80M_5G_B2, 0xffff}, 772 {"pdoffset40in80m5gb3", 0xfffff000, 0, SROM12_PDOFF_40in80M_5G_B3, 0xffff}, 773 {"pdoffset40in80m5gb4", 0xfffff000, 0, SROM12_PDOFF_40in80M_5G_B4, 0xffff}, 774 {"pdoffset20in80m5gb0", 0xfffff000, 0, SROM12_PDOFF_20in80M_5G_B0, 0xffff}, 775 {"pdoffset20in80m5gb1", 0xfffff000, 0, SROM12_PDOFF_20in80M_5G_B1, 0xffff}, 776 {"pdoffset20in80m5gb2", 0xfffff000, 0, SROM12_PDOFF_20in80M_5G_B2, 0xffff}, 777 {"pdoffset20in80m5gb3", 0xfffff000, 0, SROM12_PDOFF_20in80M_5G_B3, 0xffff}, 778 {"pdoffset20in80m5gb4", 0xfffff000, 0, SROM12_PDOFF_20in80M_5G_B4, 0xffff}, 779 780 /* power per rate */ 781 {"mcsbw205gx1po", 0xfffff000, SRFL_MORE, SROM12_MCSBW205GX1PO, 0xffff}, 782 {"", 0xfffff000, 0, SROM12_MCSBW205GX1PO_1, 0xffff}, 783 {"mcsbw405gx1po", 0xfffff000, SRFL_MORE, SROM12_MCSBW405GX1PO, 0xffff}, 784 {"", 0xfffff000, 0, SROM12_MCSBW405GX1PO_1, 0xffff}, 785 {"mcsbw805gx1po", 0xfffff000, SRFL_MORE, SROM12_MCSBW805GX1PO, 0xffff}, 786 {"", 0xfffff000, 0, SROM12_MCSBW805GX1PO_1, 0xffff}, 787 {"mcsbw205gx2po", 0xfffff000, SRFL_MORE, SROM12_MCSBW205GX2PO, 0xffff}, 788 {"", 0xfffff000, 0, SROM12_MCSBW205GX2PO_1, 0xffff}, 789 {"mcsbw405gx2po", 0xfffff000, SRFL_MORE, SROM12_MCSBW405GX2PO, 0xffff}, 790 {"", 0xfffff000, 0, SROM12_MCSBW405GX2PO_1, 0xffff}, 791 {"mcsbw805gx2po", 0xfffff000, SRFL_MORE, SROM12_MCSBW805GX2PO, 0xffff}, 792 {"", 0xfffff000, 0, SROM12_MCSBW805GX2PO_1, 0xffff}, 793 794 {"sb20in80and160hr5gx1po", 0xfffff000, 0, SROM12_SB20IN80AND160HR5GX1PO, 795 0xffff}, 796 {"sb40and80hr5gx1po", 0xfffff000, 0, SROM12_SB40AND80HR5GX1PO, 0xffff}, 797 {"sb20in80and160lr5gx1po", 0xfffff000, 0, SROM12_SB20IN80AND160LR5GX1PO, 798 0xffff}, 799 {"sb40and80hr5gx1po", 0xfffff000, 0, SROM12_SB40AND80HR5GX1PO, 0xffff}, 800 {"sb20in80and160hr5gx2po", 0xfffff000, 0, SROM12_SB20IN80AND160HR5GX2PO, 801 0xffff}, 802 {"sb40and80hr5gx2po", 0xfffff000, 0, SROM12_SB40AND80HR5GX2PO, 0xffff}, 803 {"sb20in80and160lr5gx2po", 0xfffff000, 0, SROM12_SB20IN80AND160LR5GX2PO, 804 0xffff}, 805 {"sb40and80hr5gx2po", 0xfffff000, 0, SROM12_SB40AND80HR5GX2PO, 0xffff}, 806 807 {"rxgains5gmelnagaina0", 0xfffff000, 0, SROM12_RXGAINS10, 0x0007}, 808 {"rxgains5gmelnagaina1", 0xfffff000, 0, SROM12_RXGAINS11, 0x0007}, 809 {"rxgains5gmelnagaina2", 0xfffff000, 0, SROM12_RXGAINS12, 0x0007}, 810 {"rxgains5gmtrisoa0", 0xfffff000, 0, SROM12_RXGAINS10, 0x0078}, 811 {"rxgains5gmtrisoa1", 0xfffff000, 0, SROM12_RXGAINS11, 0x0078}, 812 {"rxgains5gmtrisoa2", 0xfffff000, 0, SROM12_RXGAINS12, 0x0078}, 813 {"rxgains5gmtrelnabypa0", 0xfffff000, 0, SROM12_RXGAINS10, 0x0080}, 814 {"rxgains5gmtrelnabypa1", 0xfffff000, 0, SROM12_RXGAINS11, 0x0080}, 815 {"rxgains5gmtrelnabypa2", 0xfffff000, 0, SROM12_RXGAINS12, 0x0080}, 816 {"rxgains5ghelnagaina0", 0xfffff000, 0, SROM12_RXGAINS10, 0x0700}, 817 {"rxgains5ghelnagaina1", 0xfffff000, 0, SROM12_RXGAINS11, 0x0700}, 818 {"rxgains5ghelnagaina2", 0xfffff000, 0, SROM12_RXGAINS12, 0x0700}, 819 {"rxgains5ghtrisoa0", 0xfffff000, 0, SROM12_RXGAINS10, 0x7800}, 820 {"rxgains5ghtrisoa1", 0xfffff000, 0, SROM12_RXGAINS11, 0x7800}, 821 {"rxgains5ghtrisoa2", 0xfffff000, 0, SROM12_RXGAINS12, 0x7800}, 822 {"rxgains5ghtrelnabypa0", 0xfffff000, 0, SROM12_RXGAINS10, 0x8000}, 823 {"rxgains5ghtrelnabypa1", 0xfffff000, 0, SROM12_RXGAINS11, 0x8000}, 824 {"rxgains5ghtrelnabypa2", 0xfffff000, 0, SROM12_RXGAINS12, 0x8000}, 825 {"eu_edthresh2g", 0x00001000, 0, SROM12_EU_EDCRSTH, 0x00ff}, 826 {"eu_edthresh5g", 0x00001000, 0, SROM12_EU_EDCRSTH, 0xff00}, 827 828 {"gpdn", 0xfffff000, SRFL_PRHEX | SRFL_MORE, SROM12_GPDN_L, 0xffff}, 829 {"", 0, 0, SROM12_GPDN_H, 0xffff}, 830 831 {"rpcal2gcore3", 0xffffe000, 0, SROM13_RPCAL2GCORE3, 0x00ff}, 832 {"rpcal5gb0core3", 0xffffe000, 0, SROM13_RPCAL5GB01CORE3, 0x00ff}, 833 {"rpcal5gb1core3", 0xffffe000, 0, SROM13_RPCAL5GB01CORE3, 0xff00}, 834 {"rpcal5gb2core3", 0xffffe000, 0, SROM13_RPCAL5GB23CORE3, 0x00ff}, 835 {"rpcal5gb3core3", 0xffffe000, 0, SROM13_RPCAL5GB23CORE3, 0xff00}, 836 837 {"sw_txchain_mask", 0xffffe000, 0, SROM13_SW_TXRX_MASK, 0x000f}, 838 {"sw_rxchain_mask", 0xffffe000, 0, SROM13_SW_TXRX_MASK, 0x00f0}, 839 840 {"eu_edthresh2g", 0x00002000, 0, SROM13_EU_EDCRSTH, 0x00ff}, 841 {"eu_edthresh5g", 0x00002000, 0, SROM13_EU_EDCRSTH, 0xff00}, 842 843 {"agbg3", 0xffffe000, 0, SROM13_ANTGAIN_BANDBGA, 0xff00}, 844 {"aga3", 0xffffe000, 0, SROM13_ANTGAIN_BANDBGA, 0x00ff}, 845 {"noiselvl2ga3", 0xffffe000, 0, SROM13_NOISELVLCORE3, 0x001f}, 846 {"noiselvl5ga3", 0xffffe000, SRFL_ARRAY, SROM13_NOISELVLCORE3, 0x03e0}, 847 {"", 0xffffe000, SRFL_ARRAY, SROM13_NOISELVLCORE3, 0x7c00}, 848 {"", 0xffffe000, SRFL_ARRAY, SROM13_NOISELVLCORE3_1, 0x001f}, 849 {"", 0xffffe000, 0, SROM13_NOISELVLCORE3_1, 0x03e0}, 850 {"rxgainerr2ga3", 0xffffe000, 0, SROM13_RXGAINERRCORE3, 0x001f}, 851 {"rxgainerr5ga3", 0xffffe000, SRFL_ARRAY, SROM13_RXGAINERRCORE3, 0x03e0}, 852 {"", 0xffffe000, SRFL_ARRAY, SROM13_RXGAINERRCORE3, 0x7c00}, 853 {"", 0xffffe000, SRFL_ARRAY, SROM13_RXGAINERRCORE3_1, 0x001f}, 854 {"", 0xffffe000, 0, SROM13_RXGAINERRCORE3_1, 0x03e0}, 855 {"rxgains5gmelnagaina3", 0xffffe000, 0, SROM13_RXGAINS1CORE3, 0x0007}, 856 {"rxgains5gmtrisoa3", 0xffffe000, 0, SROM13_RXGAINS1CORE3, 0x0078}, 857 {"rxgains5gmtrelnabypa3", 0xffffe000, 0, SROM13_RXGAINS1CORE3, 0x0080}, 858 {"rxgains5ghelnagaina3", 0xffffe000, 0, SROM13_RXGAINS1CORE3, 0x0700}, 859 {"rxgains5ghtrisoa3", 0xffffe000, 0, SROM13_RXGAINS1CORE3, 0x7800}, 860 {"rxgains5ghtrelnabypa3", 0xffffe000, 0, SROM13_RXGAINS1CORE3, 0x8000}, 861 862 /* pdoffset */ 863 {"pdoffset20in40m5gcore3", 0xffffe000, 0, SROM13_PDOFFSET20IN40M5GCORE3, 864 0xffff}, 865 {"pdoffset20in40m5gcore3_1", 0xffffe000, 0, SROM13_PDOFFSET20IN40M5GCORE3_1, 866 0xffff}, 867 {"pdoffset20in80m5gcore3", 0xffffe000, 0, SROM13_PDOFFSET20IN80M5GCORE3, 868 0xffff}, 869 {"pdoffset20in80m5gcore3_1", 0xffffe000, 0, SROM13_PDOFFSET20IN80M5GCORE3_1, 870 0xffff}, 871 {"pdoffset40in80m5gcore3", 0xffffe000, 0, SROM13_PDOFFSET40IN80M5GCORE3, 872 0xffff}, 873 {"pdoffset40in80m5gcore3_1", 0xffffe000, 0, SROM13_PDOFFSET40IN80M5GCORE3_1, 874 0xffff}, 875 876 {"pdoffset20in40m2g", 0xffffe000, 0, SROM13_PDOFFSET20IN40M2G, 0xffff}, 877 {"pdoffset20in40m2gcore3", 0xffffe000, 0, SROM13_PDOFFSET20IN40M2GCORE3, 878 0xffff}, 879 {"pdoffsetcck20m", 0xffffe000, 0, SROM13_PDOFF_2G_CCK_20M, 0xffff}, 880 881 /* power per rate */ 882 {"mcs1024qam2gpo", 0xffffe000, 0, SROM13_MCS1024QAM2GPO, 0xffff}, 883 {"mcs1024qam5glpo", 0xffffe000, SRFL_MORE, SROM13_MCS1024QAM5GLPO, 0xffff}, 884 {"", 0xffffe000, 0, SROM13_MCS1024QAM5GLPO_1, 0xffff}, 885 {"mcs1024qam5gmpo", 0xffffe000, SRFL_MORE, SROM13_MCS1024QAM5GMPO, 0xffff}, 886 {"", 0xffffe000, 0, SROM13_MCS1024QAM5GMPO_1, 0xffff}, 887 {"mcs1024qam5ghpo", 0xffffe000, SRFL_MORE, SROM13_MCS1024QAM5GHPO, 0xffff}, 888 {"", 0xffffe000, 0, SROM13_MCS1024QAM5GHPO_1, 0xffff}, 889 {"mcs1024qam5gx1po", 0xffffe000, SRFL_MORE, SROM13_MCS1024QAM5GX1PO, 890 0xffff}, 891 {"", 0xffffe000, 0, SROM13_MCS1024QAM5GX1PO_1, 0xffff}, 892 {"mcs1024qam5gx2po", 0xffffe000, SRFL_MORE, SROM13_MCS1024QAM5GX2PO, 893 0xffff}, 894 {"", 0xffffe000, 0, SROM13_MCS1024QAM5GX2PO_1, 0xffff}, 895 896 {"mcsbw1605glpo", 0xffffe000, SRFL_MORE, SROM13_MCSBW1605GLPO, 0xffff}, 897 {"", 0xffffe000, 0, SROM13_MCSBW1605GLPO_1, 0xffff}, 898 {"mcsbw1605gmpo", 0xffffe000, SRFL_MORE, SROM13_MCSBW1605GMPO, 0xffff}, 899 {"", 0xffffe000, 0, SROM13_MCSBW1605GMPO_1, 0xffff}, 900 {"mcsbw1605ghpo", 0xffffe000, SRFL_MORE, SROM13_MCSBW1605GHPO, 0xffff}, 901 {"", 0xffffe000, 0, SROM13_MCSBW1605GHPO_1, 0xffff}, 902 {"mcsbw1605gx1po", 0xffffe000, SRFL_MORE, SROM13_MCSBW1605GX1PO, 0xffff}, 903 {"", 0xffffe000, 0, SROM13_MCSBW1605GX1PO_1, 0xffff}, 904 {"mcsbw1605gx2po", 0xffffe000, SRFL_MORE, SROM13_MCSBW1605GX2PO, 0xffff}, 905 {"", 0xffffe000, 0, SROM13_MCSBW1605GX2PO_1, 0xffff}, 906 907 {"ulbpproffs2g", 0xffffe000, 0, SROM13_ULBPPROFFS2G, 0xffff}, 908 909 {"mcs8poexp", 0xffffe000, SRFL_MORE, SROM13_MCS8POEXP, 0xffff}, 910 {"", 0xffffe000, 0, SROM13_MCS8POEXP_1, 0xffff}, 911 {"mcs9poexp", 0xffffe000, SRFL_MORE, SROM13_MCS9POEXP, 0xffff}, 912 {"", 0xffffe000, 0, SROM13_MCS9POEXP_1, 0xffff}, 913 {"mcs10poexp", 0xffffe000, SRFL_MORE, SROM13_MCS10POEXP, 0xffff}, 914 {"", 0xffffe000, 0, SROM13_MCS10POEXP_1, 0xffff}, 915 {"mcs11poexp", 0xffffe000, SRFL_MORE, SROM13_MCS11POEXP, 0xffff}, 916 {"", 0xffffe000, 0, SROM13_MCS11POEXP_1, 0xffff}, 917 918 {"ulbpdoffs5gb0a0", 0xffffe000, 0, SROM13_ULBPDOFFS5GB0A0, 0xffff}, 919 {"ulbpdoffs5gb0a1", 0xffffe000, 0, SROM13_ULBPDOFFS5GB0A1, 0xffff}, 920 {"ulbpdoffs5gb0a2", 0xffffe000, 0, SROM13_ULBPDOFFS5GB0A2, 0xffff}, 921 {"ulbpdoffs5gb0a3", 0xffffe000, 0, SROM13_ULBPDOFFS5GB0A3, 0xffff}, 922 {"ulbpdoffs5gb1a0", 0xffffe000, 0, SROM13_ULBPDOFFS5GB1A0, 0xffff}, 923 {"ulbpdoffs5gb1a1", 0xffffe000, 0, SROM13_ULBPDOFFS5GB1A1, 0xffff}, 924 {"ulbpdoffs5gb1a2", 0xffffe000, 0, SROM13_ULBPDOFFS5GB1A2, 0xffff}, 925 {"ulbpdoffs5gb1a3", 0xffffe000, 0, SROM13_ULBPDOFFS5GB1A3, 0xffff}, 926 {"ulbpdoffs5gb2a0", 0xffffe000, 0, SROM13_ULBPDOFFS5GB2A0, 0xffff}, 927 {"ulbpdoffs5gb2a1", 0xffffe000, 0, SROM13_ULBPDOFFS5GB2A1, 0xffff}, 928 {"ulbpdoffs5gb2a2", 0xffffe000, 0, SROM13_ULBPDOFFS5GB2A2, 0xffff}, 929 {"ulbpdoffs5gb2a3", 0xffffe000, 0, SROM13_ULBPDOFFS5GB2A3, 0xffff}, 930 {"ulbpdoffs5gb3a0", 0xffffe000, 0, SROM13_ULBPDOFFS5GB3A0, 0xffff}, 931 {"ulbpdoffs5gb3a1", 0xffffe000, 0, SROM13_ULBPDOFFS5GB3A1, 0xffff}, 932 {"ulbpdoffs5gb3a2", 0xffffe000, 0, SROM13_ULBPDOFFS5GB3A2, 0xffff}, 933 {"ulbpdoffs5gb3a3", 0xffffe000, 0, SROM13_ULBPDOFFS5GB3A3, 0xffff}, 934 {"ulbpdoffs5gb4a0", 0xffffe000, 0, SROM13_ULBPDOFFS5GB4A0, 0xffff}, 935 {"ulbpdoffs5gb4a1", 0xffffe000, 0, SROM13_ULBPDOFFS5GB4A1, 0xffff}, 936 {"ulbpdoffs5gb4a2", 0xffffe000, 0, SROM13_ULBPDOFFS5GB4A2, 0xffff}, 937 {"ulbpdoffs5gb4a3", 0xffffe000, 0, SROM13_ULBPDOFFS5GB4A3, 0xffff}, 938 {"ulbpdoffs2ga0", 0xffffe000, 0, SROM13_ULBPDOFFS2GA0, 0xffff}, 939 {"ulbpdoffs2ga1", 0xffffe000, 0, SROM13_ULBPDOFFS2GA1, 0xffff}, 940 {"ulbpdoffs2ga2", 0xffffe000, 0, SROM13_ULBPDOFFS2GA2, 0xffff}, 941 {"ulbpdoffs2ga3", 0xffffe000, 0, SROM13_ULBPDOFFS2GA3, 0xffff}, 942 943 {"rpcal5gb4", 0xffffe000, 0, SROM13_RPCAL5GB4, 0xffff}, 944 945 {"sb20in40hrlrpox", 0xffffe000, 0, SROM13_SB20IN40HRLRPOX, 0xffff}, 946 947 {"swctrlmap4_cfg", 0xffffe000, 0, SROM13_SWCTRLMAP4_CFG, 0xffff}, 948 {"swctrlmap4_TX2g_fem3to0", 0xffffe000, 0, SROM13_SWCTRLMAP4_TX2G_FEM3TO0, 949 0xffff}, 950 {"swctrlmap4_RX2g_fem3to0", 0xffffe000, 0, SROM13_SWCTRLMAP4_RX2G_FEM3TO0, 951 0xffff}, 952 {"swctrlmap4_RXByp2g_fem3to0", 0xffffe000, 0, 953 SROM13_SWCTRLMAP4_RXBYP2G_FEM3TO0, 0xffff}, 954 {"swctrlmap4_misc2g_fem3to0", 0xffffe000, 0, 955 SROM13_SWCTRLMAP4_MISC2G_FEM3TO0, 0xffff}, 956 {"swctrlmap4_TX5g_fem3to0", 0xffffe000, 0, SROM13_SWCTRLMAP4_TX5G_FEM3TO0, 957 0xffff}, 958 {"swctrlmap4_RX5g_fem3to0", 0xffffe000, 0, SROM13_SWCTRLMAP4_RX5G_FEM3TO0, 959 0xffff}, 960 {"swctrlmap4_RXByp5g_fem3to0", 0xffffe000, 0, 961 SROM13_SWCTRLMAP4_RXBYP5G_FEM3TO0, 0xffff}, 962 {"swctrlmap4_misc5g_fem3to0", 0xffffe000, 0, 963 SROM13_SWCTRLMAP4_MISC5G_FEM3TO0, 0xffff}, 964 {"swctrlmap4_TX2g_fem7to4", 0xffffe000, 0, SROM13_SWCTRLMAP4_TX2G_FEM7TO4, 965 0xffff}, 966 {"swctrlmap4_RX2g_fem7to4", 0xffffe000, 0, SROM13_SWCTRLMAP4_RX2G_FEM7TO4, 967 0xffff}, 968 {"swctrlmap4_RXByp2g_fem7to4", 0xffffe000, 0, 969 SROM13_SWCTRLMAP4_RXBYP2G_FEM7TO4, 0xffff}, 970 {"swctrlmap4_misc2g_fem7to4", 0xffffe000, 0, 971 SROM13_SWCTRLMAP4_MISC2G_FEM7TO4, 0xffff}, 972 {"swctrlmap4_TX5g_fem7to4", 0xffffe000, 0, SROM13_SWCTRLMAP4_TX5G_FEM7TO4, 973 0xffff}, 974 {"swctrlmap4_RX5g_fem7to4", 0xffffe000, 0, SROM13_SWCTRLMAP4_RX5G_FEM7TO4, 975 0xffff}, 976 {"swctrlmap4_RXByp5g_fem7to4", 0xffffe000, 0, 977 SROM13_SWCTRLMAP4_RXBYP5G_FEM7TO4, 0xffff}, 978 {"swctrlmap4_misc5g_fem7to4", 0xffffe000, 0, 979 SROM13_SWCTRLMAP4_MISC5G_FEM7TO4, 0xffff}, 980 {NULL, 0, 0, 0, 0}}; 981 #endif /* !defined(SROM15_MEMOPT) */ 982 983 static const sromvar_t pci_srom15vars[] = { 984 {"macaddr", 0x00008000, SRFL_ETHADDR, SROM15_MACHI, 0xffff}, 985 {"caldata_offset", 0x00008000, 0, SROM15_CAL_OFFSET_LOC, 0xffff}, 986 {"boardrev", 0x00008000, SRFL_PRHEX, SROM15_BRDREV, 0xffff}, 987 {"ccode", 0x00008000, SRFL_CCODE, SROM15_CCODE, 0xffff}, 988 {"regrev", 0x00008000, 0, SROM15_REGREV, 0xffff}, 989 {NULL, 0, 0, 0, 0}}; 990 991 static const sromvar_t pci_srom16vars[] = { 992 {"macaddr", 0x00010000, SRFL_ETHADDR, SROM16_MACHI, 0xffff}, 993 {"caldata_offset", 0x00010000, 0, SROM16_CALDATA_OFFSET_LOC, 0xffff}, 994 {"boardrev", 0x00010000, 0, SROM16_BOARDREV, 0xffff}, 995 {"ccode", 0x00010000, 0, SROM16_CCODE, 0xffff}, 996 {"regrev", 0x00010000, 0, SROM16_REGREV, 0xffff}, 997 {NULL, 0, 0, 0, 0}}; 998 999 static const sromvar_t pci_srom17vars[] = { 1000 {"boardrev", 0x00020000, SRFL_PRHEX, SROM17_BRDREV, 0xffff}, 1001 {"macaddr", 0x00020000, SRFL_ETHADDR, SROM17_MACADDR, 0xffff}, 1002 {"ccode", 0x00020000, SRFL_CCODE, SROM17_CCODE, 0xffff}, 1003 {"caldata_offset", 0x00020000, 0, SROM17_CALDATA, 0xffff}, 1004 {"gain_cal_temp", 0x00020000, SRFL_PRHEX, SROM17_GCALTMP, 0xffff}, 1005 {"rssi_delta_2gb0_c0", 0x00020000, PRHEX_N_MORE, SROM17_C0SRD202G, 0xffff}, 1006 {"", 0x00020000, 0, SROM17_C0SRD202G_1, 0xffff}, 1007 {"rssi_delta_5gl_c0", 0x00020000, PRHEX_N_MORE, SROM17_C0SRD205GL, 0xffff}, 1008 {"", 0x00020000, 0, SROM17_C0SRD205GL_1, 0xffff}, 1009 {"rssi_delta_5gml_c0", 0x00020000, PRHEX_N_MORE, SROM17_C0SRD205GML, 1010 0xffff}, 1011 {"", 0x00020000, 0, SROM17_C0SRD205GML_1, 0xffff}, 1012 {"rssi_delta_5gmu_c0", 0x00020000, PRHEX_N_MORE, SROM17_C0SRD205GMU, 1013 0xffff}, 1014 {"", 0x00020000, 0, SROM17_C0SRD205GMU_1, 0xffff}, 1015 {"rssi_delta_5gh_c0", 0x00020000, PRHEX_N_MORE, SROM17_C0SRD205GH, 0xffff}, 1016 {"", 0x00020000, 0, SROM17_C0SRD205GH_1, 0xffff}, 1017 {"rssi_delta_2gb0_c1", 0x00020000, PRHEX_N_MORE, SROM17_C1SRD202G, 0xffff}, 1018 {"", 0x00020000, 0, SROM17_C1SRD202G_1, 0xffff}, 1019 {"rssi_delta_5gl_c1", 0x00020000, PRHEX_N_MORE, SROM17_C1SRD205GL, 0xffff}, 1020 {"", 0x00020000, 0, SROM17_C1SRD205GL_1, 0xffff}, 1021 {"rssi_delta_5gml_c1", 0x00020000, PRHEX_N_MORE, SROM17_C1SRD205GML, 1022 0xffff}, 1023 {"", 0x00020000, 0, SROM17_C1SRD205GML_1, 0xffff}, 1024 {"rssi_delta_5gmu_c1", 0x00020000, PRHEX_N_MORE, SROM17_C1SRD205GMU, 1025 0xffff}, 1026 {"", 0x00020000, 0, SROM17_C1SRD205GMU_1, 0xffff}, 1027 {"rssi_delta_5gh_c1", 0x00020000, PRHEX_N_MORE, SROM17_C1SRD205GH, 0xffff}, 1028 {"", 0x00020000, 0, SROM17_C1SRD205GH_1, 0xffff}, 1029 {"txpa_trim_magic", 0x00020000, PRHEX_N_MORE, SROM17_TRAMMAGIC, 0xffff}, 1030 {"", 0x00020000, 0, SROM17_TRAMMAGIC_1, 0xffff}, 1031 {"txpa_trim_data", 0x00020000, SRFL_PRHEX, SROM17_TRAMDATA, 0xffff}, 1032 {NULL, 0, 0, 0, 0x00}}; 1033 1034 static const sromvar_t perpath_pci_sromvars[] = { 1035 {"maxp2ga", 0x000000f0, 0, SROM4_2G_ITT_MAXP, 0x00ff}, 1036 {"itt2ga", 0x000000f0, 0, SROM4_2G_ITT_MAXP, 0xff00}, 1037 {"itt5ga", 0x000000f0, 0, SROM4_5G_ITT_MAXP, 0xff00}, 1038 {"pa2gw0a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA, 0xffff}, 1039 {"pa2gw1a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 1, 0xffff}, 1040 {"pa2gw2a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 2, 0xffff}, 1041 {"pa2gw3a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 3, 0xffff}, 1042 {"maxp5ga", 0x000000f0, 0, SROM4_5G_ITT_MAXP, 0x00ff}, 1043 {"maxp5gha", 0x000000f0, 0, SROM4_5GLH_MAXP, 0x00ff}, 1044 {"maxp5gla", 0x000000f0, 0, SROM4_5GLH_MAXP, 0xff00}, 1045 {"pa5gw0a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA, 0xffff}, 1046 {"pa5gw1a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 1, 0xffff}, 1047 {"pa5gw2a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 2, 0xffff}, 1048 {"pa5gw3a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 3, 0xffff}, 1049 {"pa5glw0a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA, 0xffff}, 1050 {"pa5glw1a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 1, 0xffff}, 1051 {"pa5glw2a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 2, 0xffff}, 1052 {"pa5glw3a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 3, 0xffff}, 1053 {"pa5ghw0a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA, 0xffff}, 1054 {"pa5ghw1a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 1, 0xffff}, 1055 {"pa5ghw2a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 2, 0xffff}, 1056 {"pa5ghw3a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 3, 0xffff}, 1057 {"maxp2ga", 0x00000700, 0, SROM8_2G_ITT_MAXP, 0x00ff}, 1058 {"itt2ga", 0x00000700, 0, SROM8_2G_ITT_MAXP, 0xff00}, 1059 {"itt5ga", 0x00000700, 0, SROM8_5G_ITT_MAXP, 0xff00}, 1060 {"pa2gw0a", 0x00000700, SRFL_PRHEX, SROM8_2G_PA, 0xffff}, 1061 {"pa2gw1a", 0x00000700, SRFL_PRHEX, SROM8_2G_PA + 1, 0xffff}, 1062 {"pa2gw2a", 0x00000700, SRFL_PRHEX, SROM8_2G_PA + 2, 0xffff}, 1063 {"maxp5ga", 0x00000700, 0, SROM8_5G_ITT_MAXP, 0x00ff}, 1064 {"maxp5gha", 0x00000700, 0, SROM8_5GLH_MAXP, 0x00ff}, 1065 {"maxp5gla", 0x00000700, 0, SROM8_5GLH_MAXP, 0xff00}, 1066 {"pa5gw0a", 0x00000700, SRFL_PRHEX, SROM8_5G_PA, 0xffff}, 1067 {"pa5gw1a", 0x00000700, SRFL_PRHEX, SROM8_5G_PA + 1, 0xffff}, 1068 {"pa5gw2a", 0x00000700, SRFL_PRHEX, SROM8_5G_PA + 2, 0xffff}, 1069 {"pa5glw0a", 0x00000700, SRFL_PRHEX, SROM8_5GL_PA, 0xffff}, 1070 {"pa5glw1a", 0x00000700, SRFL_PRHEX, SROM8_5GL_PA + 1, 0xffff}, 1071 {"pa5glw2a", 0x00000700, SRFL_PRHEX, SROM8_5GL_PA + 2, 0xffff}, 1072 {"pa5ghw0a", 0x00000700, SRFL_PRHEX, SROM8_5GH_PA, 0xffff}, 1073 {"pa5ghw1a", 0x00000700, SRFL_PRHEX, SROM8_5GH_PA + 1, 0xffff}, 1074 {"pa5ghw2a", 0x00000700, SRFL_PRHEX, SROM8_5GH_PA + 2, 0xffff}, 1075 1076 /* sromrev 11 */ 1077 {"maxp2ga", 0xfffff800, 0, SROM11_2G_MAXP, 0x00ff}, 1078 {"pa2ga", 0x00000800, SRFL_PRHEX | SRFL_ARRAY, SROM11_2G_PA, 0xffff}, 1079 {"", 0x00000800, SRFL_PRHEX | SRFL_ARRAY, SROM11_2G_PA + 1, 0xffff}, 1080 {"", 0x00000800, SRFL_PRHEX, SROM11_2G_PA + 2, 0xffff}, 1081 {"rxgains5gmelnagaina", 0x00000800, 0, SROM11_RXGAINS1, 0x0007}, 1082 {"rxgains5gmtrisoa", 0x00000800, 0, SROM11_RXGAINS1, 0x0078}, 1083 {"rxgains5gmtrelnabypa", 0x00000800, 0, SROM11_RXGAINS1, 0x0080}, 1084 {"rxgains5ghelnagaina", 0x00000800, 0, SROM11_RXGAINS1, 0x0700}, 1085 {"rxgains5ghtrisoa", 0x00000800, 0, SROM11_RXGAINS1, 0x7800}, 1086 {"rxgains5ghtrelnabypa", 0x00000800, 0, SROM11_RXGAINS1, 0x8000}, 1087 {"rxgains2gelnagaina", 0x00000800, 0, SROM11_RXGAINS, 0x0007}, 1088 {"rxgains2gtrisoa", 0x00000800, 0, SROM11_RXGAINS, 0x0078}, 1089 {"rxgains2gtrelnabypa", 0x00000800, 0, SROM11_RXGAINS, 0x0080}, 1090 {"rxgains5gelnagaina", 0x00000800, 0, SROM11_RXGAINS, 0x0700}, 1091 {"rxgains5gtrisoa", 0x00000800, 0, SROM11_RXGAINS, 0x7800}, 1092 {"rxgains5gtrelnabypa", 0x00000800, 0, SROM11_RXGAINS, 0x8000}, 1093 {"maxp5ga", 0x00000800, SRFL_ARRAY, SROM11_5GB1B0_MAXP, 0x00ff}, 1094 {"", 0x00000800, SRFL_ARRAY, SROM11_5GB1B0_MAXP, 0xff00}, 1095 {"", 0x00000800, SRFL_ARRAY, SROM11_5GB3B2_MAXP, 0x00ff}, 1096 {"", 0x00000800, 0, SROM11_5GB3B2_MAXP, 0xff00}, 1097 {"pa5ga", 0x00000800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB0_PA, 0xffff}, 1098 {"", 0x00000800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB0_PA + 1, 0xffff}, 1099 {"", 0x00000800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB0_PA + 2, 0xffff}, 1100 {"", 0x00000800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB1_PA, 0xffff}, 1101 {"", 0x00000800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB1_PA + 1, 0xffff}, 1102 {"", 0x00000800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB1_PA + 2, 0xffff}, 1103 {"", 0x00000800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB2_PA, 0xffff}, 1104 {"", 0x00000800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB2_PA + 1, 0xffff}, 1105 {"", 0x00000800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB2_PA + 2, 0xffff}, 1106 {"", 0x00000800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB3_PA, 0xffff}, 1107 {"", 0x00000800, SRFL_PRHEX | SRFL_ARRAY, SROM11_5GB3_PA + 1, 0xffff}, 1108 {"", 0x00000800, SRFL_PRHEX, SROM11_5GB3_PA + 2, 0xffff}, 1109 1110 /* sromrev 12 */ 1111 {"maxp5gb4a", 0xfffff000, 0, SROM12_5GB42G_MAXP, 0x00ff00}, 1112 {"pa2ga", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_2GB0_PA_W0, 0x00ffff}, 1113 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_2GB0_PA_W1, 0x00ffff}, 1114 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_2GB0_PA_W2, 0x00ffff}, 1115 {"", 0xfffff000, SRFL_PRHEX, SROM12_2GB0_PA_W3, 0x00ffff}, 1116 1117 {"pa2g40a", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_2G40B0_PA_W0, 1118 0x00ffff}, 1119 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_2G40B0_PA_W1, 0x00ffff}, 1120 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_2G40B0_PA_W2, 0x00ffff}, 1121 {"", 0xfffff000, SRFL_PRHEX, SROM12_2G40B0_PA_W3, 0x00ffff}, 1122 {"maxp5gb0a", 0xfffff000, 0, SROM12_5GB1B0_MAXP, 0x00ff}, 1123 {"maxp5gb1a", 0xfffff000, 0, SROM12_5GB1B0_MAXP, 0x00ff00}, 1124 {"maxp5gb2a", 0xfffff000, 0, SROM12_5GB3B2_MAXP, 0x00ff}, 1125 {"maxp5gb3a", 0xfffff000, 0, SROM12_5GB3B2_MAXP, 0x00ff00}, 1126 1127 {"pa5ga", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB0_PA_W0, 0x00ffff}, 1128 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB0_PA_W1, 0x00ffff}, 1129 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB0_PA_W2, 0x00ffff}, 1130 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB0_PA_W3, 0x00ffff}, 1131 1132 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB1_PA_W0, 0x00ffff}, 1133 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB1_PA_W1, 0x00ffff}, 1134 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB1_PA_W2, 0x00ffff}, 1135 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB1_PA_W3, 0x00ffff}, 1136 1137 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB2_PA_W0, 0x00ffff}, 1138 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB2_PA_W1, 0x00ffff}, 1139 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB2_PA_W2, 0x00ffff}, 1140 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB2_PA_W3, 0x00ffff}, 1141 1142 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB3_PA_W0, 0x00ffff}, 1143 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB3_PA_W1, 0x00ffff}, 1144 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB3_PA_W2, 0x00ffff}, 1145 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB3_PA_W3, 0x00ffff}, 1146 1147 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB4_PA_W0, 0x00ffff}, 1148 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB4_PA_W1, 0x00ffff}, 1149 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5GB4_PA_W2, 0x00ffff}, 1150 {"", 0xfffff000, SRFL_PRHEX, SROM12_5GB4_PA_W3, 0x00ffff}, 1151 1152 {"pa5g40a", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B0_PA_W0, 1153 0x00ffff}, 1154 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B0_PA_W1, 0x00ffff}, 1155 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B0_PA_W2, 0x00ffff}, 1156 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B0_PA_W3, 0x00ffff}, 1157 1158 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B1_PA_W0, 0x00ffff}, 1159 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B1_PA_W1, 0x00ffff}, 1160 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B1_PA_W2, 0x00ffff}, 1161 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B1_PA_W3, 0x00ffff}, 1162 1163 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B2_PA_W0, 0x00ffff}, 1164 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B2_PA_W1, 0x00ffff}, 1165 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B2_PA_W2, 0x00ffff}, 1166 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B2_PA_W3, 0x00ffff}, 1167 1168 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B3_PA_W0, 0x00ffff}, 1169 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B3_PA_W1, 0x00ffff}, 1170 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B3_PA_W2, 0x00ffff}, 1171 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B3_PA_W3, 0x00ffff}, 1172 1173 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B4_PA_W0, 0x00ffff}, 1174 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B4_PA_W1, 0x00ffff}, 1175 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G40B4_PA_W2, 0x00ffff}, 1176 {"", 0xfffff000, SRFL_PRHEX, SROM12_5G40B4_PA_W3, 0x00ffff}, 1177 1178 {"pa5g80a", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B0_PA_W0, 1179 0x00ffff}, 1180 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B0_PA_W1, 0x00ffff}, 1181 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B0_PA_W2, 0x00ffff}, 1182 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B0_PA_W3, 0x00ffff}, 1183 1184 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B1_PA_W0, 0x00ffff}, 1185 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B1_PA_W1, 0x00ffff}, 1186 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B1_PA_W2, 0x00ffff}, 1187 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B1_PA_W3, 0x00ffff}, 1188 1189 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B2_PA_W0, 0x00ffff}, 1190 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B2_PA_W1, 0x00ffff}, 1191 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B2_PA_W2, 0x00ffff}, 1192 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B2_PA_W3, 0x00ffff}, 1193 1194 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B3_PA_W0, 0x00ffff}, 1195 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B3_PA_W1, 0x00ffff}, 1196 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B3_PA_W2, 0x00ffff}, 1197 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B3_PA_W3, 0x00ffff}, 1198 1199 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B4_PA_W0, 0x00ffff}, 1200 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B4_PA_W1, 0x00ffff}, 1201 {"", 0xfffff000, SRFL_PRHEX | SRFL_ARRAY, SROM12_5G80B4_PA_W2, 0x00ffff}, 1202 {"", 0xfffff000, SRFL_PRHEX, SROM12_5G80B4_PA_W3, 0x00ffff}, 1203 /* sromrev 13 */ 1204 {"rxgains2gelnagaina", 0xffffe000, 0, SROM13_RXGAINS, 0x0007}, 1205 {"rxgains2gtrisoa", 0xffffe000, 0, SROM13_RXGAINS, 0x0078}, 1206 {"rxgains2gtrelnabypa", 0xffffe000, 0, SROM13_RXGAINS, 0x0080}, 1207 {"rxgains5gelnagaina", 0xffffe000, 0, SROM13_RXGAINS, 0x0700}, 1208 {"rxgains5gtrisoa", 0xffffe000, 0, SROM13_RXGAINS, 0x7800}, 1209 {"rxgains5gtrelnabypa", 0xffffe000, 0, SROM13_RXGAINS, 0x8000}, 1210 {NULL, 0, 0, 0, 0}}; 1211 1212 #if !defined(PHY_TYPE_N) 1213 #define PHY_TYPE_N 4 /* N-Phy value */ 1214 #endif /* !(defined(PHY_TYPE_HT) && defined(PHY_TYPE_N)) */ 1215 #if !defined(PHY_TYPE_AC) 1216 #define PHY_TYPE_AC 11 /* AC-Phy value */ 1217 #endif /* !defined(PHY_TYPE_AC) */ 1218 #if !defined(PHY_TYPE_LCN20) 1219 #define PHY_TYPE_LCN20 12 /* LCN20-Phy value */ 1220 #endif /* !defined(PHY_TYPE_LCN20) */ 1221 #if !defined(PHY_TYPE_NULL) 1222 #define PHY_TYPE_NULL 0xf /* Invalid Phy value */ 1223 #endif /* !defined(PHY_TYPE_NULL) */ 1224 1225 typedef struct { 1226 uint16 phy_type; 1227 uint16 bandrange; 1228 uint16 chain; 1229 const char *vars; 1230 } pavars_t; 1231 1232 static const pavars_t pavars[] = { 1233 /* NPHY */ 1234 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_2G, 0, "pa2gw0a0 pa2gw1a0 pa2gw2a0"}, 1235 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_2G, 1, "pa2gw0a1 pa2gw1a1 pa2gw2a1"}, 1236 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5G_BAND0, 0, 1237 "pa5glw0a0 pa5glw1a0 pa5glw2a0"}, 1238 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5G_BAND0, 1, 1239 "pa5glw0a1 pa5glw1a1 pa5glw2a1"}, 1240 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5G_BAND1, 0, "pa5gw0a0 pa5gw1a0 pa5gw2a0"}, 1241 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5G_BAND1, 1, "pa5gw0a1 pa5gw1a1 pa5gw2a1"}, 1242 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5G_BAND2, 0, 1243 "pa5ghw0a0 pa5ghw1a0 pa5ghw2a0"}, 1244 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5G_BAND2, 1, 1245 "pa5ghw0a1 pa5ghw1a1 pa5ghw2a1"}, 1246 /* ACPHY */ 1247 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G, 0, "pa2ga0"}, 1248 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G, 1, "pa2ga1"}, 1249 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G, 2, "pa2ga2"}, 1250 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND, 0, "pa5ga0"}, 1251 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND, 1, "pa5ga1"}, 1252 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND, 2, "pa5ga2"}, 1253 /* LCN20PHY */ 1254 {PHY_TYPE_LCN20, WL_CHAN_FREQ_RANGE_2G, 0, "pa2ga0"}, 1255 {PHY_TYPE_NULL, 0, 0, ""}}; 1256 1257 static const pavars_t pavars_SROM12[] = { 1258 /* ACPHY */ 1259 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G, 0, "pa2ga0"}, 1260 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G, 1, "pa2ga1"}, 1261 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G, 2, "pa2ga2"}, 1262 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G_40, 0, "pa2g40a0"}, 1263 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G_40, 1, "pa2g40a1"}, 1264 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G_40, 2, "pa2g40a2"}, 1265 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND, 0, "pa5ga0"}, 1266 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND, 1, "pa5ga1"}, 1267 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND, 2, "pa5ga2"}, 1268 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND_40, 0, "pa5g40a0"}, 1269 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND_40, 1, "pa5g40a1"}, 1270 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND_40, 2, "pa5g40a2"}, 1271 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND_80, 0, "pa5g80a0"}, 1272 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND_80, 1, "pa5g80a1"}, 1273 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND_80, 2, "pa5g80a2"}, 1274 {PHY_TYPE_NULL, 0, 0, ""}}; 1275 1276 static const pavars_t pavars_SROM13[] = { 1277 /* ACPHY */ 1278 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G, 0, "pa2ga0"}, 1279 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G, 1, "pa2ga1"}, 1280 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G, 2, "pa2ga2"}, 1281 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G, 3, "pa2ga3"}, 1282 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G_40, 0, "pa2g40a0"}, 1283 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G_40, 1, "pa2g40a1"}, 1284 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G_40, 2, "pa2g40a2"}, 1285 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G_40, 3, "pa2g40a3"}, 1286 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND, 0, "pa5ga0"}, 1287 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND, 1, "pa5ga1"}, 1288 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND, 2, "pa5ga2"}, 1289 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND, 3, "pa5ga3"}, 1290 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND_40, 0, "pa5g40a0"}, 1291 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND_40, 1, "pa5g40a1"}, 1292 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND_40, 2, "pa5g40a2"}, 1293 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND_40, 3, "pa5g40a3"}, 1294 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND_80, 0, "pa5g80a0"}, 1295 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND_80, 1, "pa5g80a1"}, 1296 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND_80, 2, "pa5g80a2"}, 1297 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_5BAND_80, 3, "pa5g80a3"}, 1298 {PHY_TYPE_NULL, 0, 0, ""}}; 1299 1300 /* pavars table when paparambwver is 1 */ 1301 static const pavars_t pavars_bwver_1[] = { 1302 /* ACPHY */ 1303 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G, 0, "pa2ga0"}, 1304 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G, 1, "pa2gccka0"}, 1305 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G, 1, "pa2ga2"}, 1306 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND, 0, "pa5ga0"}, 1307 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND, 1, "pa5gbw40a0"}, 1308 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND, 2, "pa5gbw80a0"}, 1309 {PHY_TYPE_NULL, 0, 0, ""}}; 1310 1311 /* pavars table when paparambwver is 2 */ 1312 static const pavars_t pavars_bwver_2[] = { 1313 /* ACPHY */ 1314 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G, 0, "pa2ga0"}, 1315 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G, 1, "pa2ga1"}, 1316 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND, 0, "pa5ga0"}, 1317 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND, 1, "pa5ga1"}, 1318 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND, 2, "pa5gbw4080a0"}, 1319 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND, 3, "pa5gbw4080a1"}, 1320 {PHY_TYPE_NULL, 0, 0, ""}}; 1321 1322 /* pavars table when paparambwver is 3 */ 1323 static const pavars_t pavars_bwver_3[] = { 1324 /* ACPHY */ 1325 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G, 0, "pa2ga0"}, 1326 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G, 1, "pa2ga1"}, 1327 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G, 2, "pa2gccka0"}, 1328 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_2G, 3, "pa2gccka1"}, 1329 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND, 0, "pa5ga0"}, 1330 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND, 1, "pa5ga1"}, 1331 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND, 2, "pa5gbw4080a0"}, 1332 {PHY_TYPE_AC, WL_CHAN_FREQ_RANGE_5G_4BAND, 3, "pa5gbw4080a1"}, 1333 {PHY_TYPE_NULL, 0, 0, ""}}; 1334 1335 typedef struct { 1336 uint16 phy_type; 1337 uint16 bandrange; 1338 const char *vars; 1339 } povars_t; 1340 1341 static const povars_t povars[] = { 1342 /* NPHY */ 1343 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_2G, 1344 "mcs2gpo0 mcs2gpo1 mcs2gpo2 mcs2gpo3 " 1345 "mcs2gpo4 mcs2gpo5 mcs2gpo6 mcs2gpo7"}, 1346 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GL, 1347 "mcs5glpo0 mcs5glpo1 mcs5glpo2 mcs5glpo3 " 1348 "mcs5glpo4 mcs5glpo5 mcs5glpo6 mcs5glpo7"}, 1349 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GM, 1350 "mcs5gpo0 mcs5gpo1 mcs5gpo2 mcs5gpo3 " 1351 "mcs5gpo4 mcs5gpo5 mcs5gpo6 mcs5gpo7"}, 1352 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GH, 1353 "mcs5ghpo0 mcs5ghpo1 mcs5ghpo2 mcs5ghpo3 " 1354 "mcs5ghpo4 mcs5ghpo5 mcs5ghpo6 mcs5ghpo7"}, 1355 {PHY_TYPE_NULL, 0, ""}}; 1356 1357 typedef struct { 1358 uint8 tag; /* Broadcom subtag name */ 1359 uint32 revmask; /* Supported cis_sromrev bitmask. Some of the parameters in 1360 * different tuples have the same name. Therefore, the MFGc 1361 * tool needs to know which tuple to generate when seeing 1362 * these parameters (given that we know sromrev from user 1363 * input, like the nvram file). 1364 */ 1365 uint8 len; /* Length field of the tuple, note that it includes the 1366 * subtag name (1 byte): 1 + tuple content length 1367 */ 1368 const char *params; 1369 } cis_tuple_t; 1370 1371 #define OTP_RAW (0xff - 1) /* Reserved tuple number for wrvar Raw input */ 1372 #define OTP_VERS_1 (0xff - 2) /* CISTPL_VERS_1 */ 1373 #define OTP_MANFID (0xff - 3) /* CISTPL_MANFID */ 1374 #define OTP_RAW1 (0xff - 4) /* Like RAW, but comes first */ 1375 1376 /** this array is used by CIS creating/writing applications */ 1377 static const cis_tuple_t cis_hnbuvars[] = 1378 { 1379 /* tag revmask len params */ 1380 {OTP_RAW1, 0xffffffff, 0, ""}, /* special case */ 1381 {OTP_VERS_1, 0xffffffff, 0, 1382 "smanf sproductname"}, /* special case (non BRCM tuple) */ 1383 {OTP_MANFID, 0xffffffff, 4, 1384 "2manfid 2prodid"}, /* special case (non BRCM tuple) */ 1385 /* Unified OTP: tupple to embed USB manfid inside SDIO CIS */ 1386 {HNBU_UMANFID, 0xffffffff, 8, "8usbmanfid"}, 1387 {HNBU_SROMREV, 0xffffffff, 2, "1sromrev"}, 1388 /* NOTE: subdevid is also written to boardtype. 1389 * Need to write HNBU_BOARDTYPE to change it if it is different. 1390 */ 1391 {HNBU_CHIPID, 0xffffffff, 11, 1392 "2vendid 2devid 2chiprev 2subvendid 2subdevid"}, 1393 {HNBU_BOARDREV, 0xffffffff, 3, "2boardrev"}, 1394 {HNBU_PAPARMS, 0xffffffff, 10, 1395 "2pa0b0 2pa0b1 2pa0b2 1pa0itssit 1pa0maxpwr 1opo"}, 1396 {HNBU_AA, 0xffffffff, 3, "1aa2g 1aa5g"}, 1397 {HNBU_AA, 0xffffffff, 3, "1aa0 1aa1"}, /* backward compatibility */ 1398 {HNBU_AG, 0xffffffff, 5, "1ag0 1ag1 1ag2 1ag3"}, 1399 {HNBU_BOARDFLAGS, 0xffffffff, 21, 1400 "4boardflags 4boardflags2 4boardflags3 " 1401 "4boardflags4 4boardflags5 "}, 1402 {HNBU_LEDS, 0xffffffff, 17, 1403 "1ledbh0 1ledbh1 1ledbh2 1ledbh3 1ledbh4 1ledbh5 " 1404 "1ledbh6 1ledbh7 1ledbh8 1ledbh9 1ledbh10 1ledbh11 1ledbh12 1ledbh13 " 1405 "1ledbh14 1ledbh15"}, 1406 {HNBU_CCODE, 0xffffffff, 4, "2ccode 1cctl"}, 1407 {HNBU_CCKPO, 0xffffffff, 3, "2cckpo"}, 1408 {HNBU_OFDMPO, 0xffffffff, 5, "4ofdmpo"}, 1409 {HNBU_PAPARMS5G, 0xffffffff, 23, 1410 "2pa1b0 2pa1b1 2pa1b2 2pa1lob0 2pa1lob1 2pa1lob2 " 1411 "2pa1hib0 2pa1hib1 2pa1hib2 1pa1itssit " 1412 "1pa1maxpwr 1pa1lomaxpwr 1pa1himaxpwr"}, 1413 {HNBU_RDLID, 0xffffffff, 3, "2rdlid"}, 1414 {HNBU_RSSISMBXA2G, 0xffffffff, 3, 1415 "0rssismf2g 0rssismc2g " 1416 "0rssisav2g 0bxa2g"}, /* special case */ 1417 {HNBU_RSSISMBXA5G, 0xffffffff, 3, 1418 "0rssismf5g 0rssismc5g " 1419 "0rssisav5g 0bxa5g"}, /* special case */ 1420 {HNBU_XTALFREQ, 0xffffffff, 5, "4xtalfreq"}, 1421 {HNBU_TRI2G, 0xffffffff, 2, "1tri2g"}, 1422 {HNBU_TRI5G, 0xffffffff, 4, "1tri5gl 1tri5g 1tri5gh"}, 1423 {HNBU_RXPO2G, 0xffffffff, 2, "1rxpo2g"}, 1424 {HNBU_RXPO5G, 0xffffffff, 2, "1rxpo5g"}, 1425 {HNBU_BOARDNUM, 0xffffffff, 3, "2boardnum"}, 1426 {HNBU_MACADDR, 0xffffffff, 7, "6macaddr"}, /* special case */ 1427 {HNBU_RDLSN, 0xffffffff, 3, "2rdlsn"}, 1428 {HNBU_BOARDTYPE, 0xffffffff, 3, "2boardtype"}, 1429 {HNBU_LEDDC, 0xffffffff, 3, "2leddc"}, 1430 {HNBU_RDLRNDIS, 0xffffffff, 2, "1rdlndis"}, 1431 {HNBU_CHAINSWITCH, 0xffffffff, 5, "1txchain 1rxchain 2antswitch"}, 1432 {HNBU_REGREV, 0xffffffff, 3, "2regrev"}, 1433 {HNBU_FEM, 0x000007fe, 5, 1434 "0antswctl2g 0triso2g 0pdetrange2g 0extpagain2g " 1435 "0tssipos2g 0antswctl5g 0triso5g 0pdetrange5g 0extpagain5g " 1436 "0tssipos5g"}, /* special case */ 1437 {HNBU_PAPARMS_C0, 0x000007fe, 31, 1438 "1maxp2ga0 1itt2ga0 2pa2gw0a0 2pa2gw1a0 " 1439 "2pa2gw2a0 1maxp5ga0 1itt5ga0 1maxp5gha0 1maxp5gla0 2pa5gw0a0 " 1440 "2pa5gw1a0 2pa5gw2a0 " 1441 "2pa5glw0a0 2pa5glw1a0 2pa5glw2a0 2pa5ghw0a0 2pa5ghw1a0 2pa5ghw2a0"}, 1442 {HNBU_PAPARMS_C1, 0x000007fe, 31, 1443 "1maxp2ga1 1itt2ga1 2pa2gw0a1 2pa2gw1a1 " 1444 "2pa2gw2a1 1maxp5ga1 1itt5ga1 1maxp5gha1 1maxp5gla1 2pa5gw0a1 " 1445 "2pa5gw1a1 2pa5gw2a1 " 1446 "2pa5glw0a1 2pa5glw1a1 2pa5glw2a1 2pa5ghw0a1 2pa5ghw1a1 2pa5ghw2a1"}, 1447 {HNBU_PO_CCKOFDM, 0xffffffff, 19, 1448 "2cck2gpo 4ofdm2gpo 4ofdm5gpo 4ofdm5glpo " 1449 "4ofdm5ghpo"}, 1450 {HNBU_PO_MCS2G, 0xffffffff, 17, 1451 "2mcs2gpo0 2mcs2gpo1 2mcs2gpo2 2mcs2gpo3 " 1452 "2mcs2gpo4 2mcs2gpo5 2mcs2gpo6 2mcs2gpo7"}, 1453 {HNBU_PO_MCS5GM, 0xffffffff, 17, 1454 "2mcs5gpo0 2mcs5gpo1 2mcs5gpo2 2mcs5gpo3 " 1455 "2mcs5gpo4 2mcs5gpo5 2mcs5gpo6 2mcs5gpo7"}, 1456 {HNBU_PO_MCS5GLH, 0xffffffff, 33, 1457 "2mcs5glpo0 2mcs5glpo1 2mcs5glpo2 2mcs5glpo3 " 1458 "2mcs5glpo4 2mcs5glpo5 2mcs5glpo6 2mcs5glpo7 " 1459 "2mcs5ghpo0 2mcs5ghpo1 2mcs5ghpo2 2mcs5ghpo3 " 1460 "2mcs5ghpo4 2mcs5ghpo5 2mcs5ghpo6 2mcs5ghpo7"}, 1461 {HNBU_CCKFILTTYPE, 0xffffffff, 2, "1cckdigfilttype"}, 1462 {HNBU_PO_CDD, 0xffffffff, 3, "2cddpo"}, 1463 {HNBU_PO_STBC, 0xffffffff, 3, "2stbcpo"}, 1464 {HNBU_PO_40M, 0xffffffff, 3, "2bw40po"}, 1465 {HNBU_PO_40MDUP, 0xffffffff, 3, "2bwduppo"}, 1466 {HNBU_RDLRWU, 0xffffffff, 2, "1rdlrwu"}, 1467 {HNBU_WPS, 0xffffffff, 3, "1wpsgpio 1wpsled"}, 1468 {HNBU_USBFS, 0xffffffff, 2, "1usbfs"}, 1469 {HNBU_ELNA2G, 0xffffffff, 2, "1elna2g"}, 1470 {HNBU_ELNA5G, 0xffffffff, 2, "1elna5g"}, 1471 {HNBU_CUSTOM1, 0xffffffff, 5, "4customvar1"}, 1472 {OTP_RAW, 0xffffffff, 0, ""}, /* special case */ 1473 {HNBU_OFDMPO5G, 0xffffffff, 13, "4ofdm5gpo 4ofdm5glpo 4ofdm5ghpo"}, 1474 {HNBU_USBEPNUM, 0xffffffff, 3, "2usbepnum"}, 1475 {HNBU_CCKBW202GPO, 0xffffffff, 7, 1476 "2cckbw202gpo 2cckbw20ul2gpo 2cckbw20in802gpo"}, 1477 {HNBU_LEGOFDMBW202GPO, 0xffffffff, 9, 1478 "4legofdmbw202gpo 4legofdmbw20ul2gpo"}, 1479 {HNBU_LEGOFDMBW205GPO, 0xffffffff, 25, 1480 "4legofdmbw205glpo 4legofdmbw20ul5glpo " 1481 "4legofdmbw205gmpo 4legofdmbw20ul5gmpo 4legofdmbw205ghpo " 1482 "4legofdmbw20ul5ghpo"}, 1483 {HNBU_MCS2GPO, 0xffffffff, 17, 1484 "4mcsbw202gpo 4mcsbw20ul2gpo 4mcsbw402gpo 4mcsbw802gpo"}, 1485 {HNBU_MCS5GLPO, 0xffffffff, 13, 1486 "4mcsbw205glpo 4mcsbw20ul5glpo 4mcsbw405glpo"}, 1487 {HNBU_MCS5GMPO, 0xffffffff, 13, 1488 "4mcsbw205gmpo 4mcsbw20ul5gmpo 4mcsbw405gmpo"}, 1489 {HNBU_MCS5GHPO, 0xffffffff, 13, 1490 "4mcsbw205ghpo 4mcsbw20ul5ghpo 4mcsbw405ghpo"}, 1491 {HNBU_MCS32PO, 0xffffffff, 3, "2mcs32po"}, 1492 {HNBU_LEG40DUPPO, 0xffffffff, 3, "2legofdm40duppo"}, 1493 {HNBU_TEMPTHRESH, 0xffffffff, 7, 1494 "1tempthresh 0temps_period 0temps_hysteresis " 1495 "1tempoffset 1tempsense_slope 0tempcorrx 0tempsense_option " 1496 "1phycal_tempdelta"}, /* special case */ 1497 {HNBU_MUXENAB, 0xffffffff, 2, "1muxenab"}, 1498 {HNBU_FEM_CFG, 0xfffff800, 5, 1499 "0femctrl 0papdcap2g 0tworangetssi2g 0pdgain2g " 1500 "0epagain2g 0tssiposslope2g 0gainctrlsph 0papdcap5g 0tworangetssi5g " 1501 "0pdgain5g 0epagain5g " 1502 "0tssiposslope5g"}, /* special case */ 1503 {HNBU_ACPA_C0, 0x00001800, 39, 1504 "2subband5gver 2maxp2ga0 2*3pa2ga0 " 1505 "1*4maxp5ga0 2*12pa5ga0"}, 1506 {HNBU_ACPA_C1, 0x00001800, 37, 1507 "2maxp2ga1 2*3pa2ga1 1*4maxp5ga1 2*12pa5ga1"}, 1508 {HNBU_ACPA_C2, 0x00001800, 37, 1509 "2maxp2ga2 2*3pa2ga2 1*4maxp5ga2 2*12pa5ga2"}, 1510 {HNBU_MEAS_PWR, 0xfffff800, 5, 1511 "1measpower 1measpower1 1measpower2 2rawtempsense"}, 1512 {HNBU_PDOFF, 0xfffff800, 13, 1513 "2pdoffset40ma0 2pdoffset40ma1 2pdoffset40ma2 " 1514 "2pdoffset80ma0 2pdoffset80ma1 2pdoffset80ma2"}, 1515 {HNBU_ACPPR_2GPO, 0xfffff800, 13, 1516 "2dot11agofdmhrbw202gpo 2ofdmlrbw202gpo " 1517 "2sb20in40dot11agofdm2gpo 2sb20in80dot11agofdm2gpo " 1518 "2sb20in40ofdmlrbw202gpo " 1519 "2sb20in80ofdmlrbw202gpo"}, 1520 {HNBU_ACPPR_5GPO, 0xfffff800, 59, 1521 "4mcsbw805glpo 4mcsbw1605glpo 4mcsbw805gmpo " 1522 "4mcsbw1605gmpo 4mcsbw805ghpo 4mcsbw1605ghpo 2mcslr5glpo 2mcslr5gmpo " 1523 "2mcslr5ghpo " 1524 "4mcsbw80p805glpo 4mcsbw80p805gmpo 4mcsbw80p805ghpo 4mcsbw80p805gx1po " 1525 "2mcslr5gx1po " 1526 "2mcslr5g80p80po 4mcsbw805gx1po 4mcsbw1605gx1po"}, 1527 {HNBU_MCS5Gx1PO, 0xfffff800, 9, "4mcsbw205gx1po 4mcsbw405gx1po"}, 1528 {HNBU_ACPPR_SBPO, 0xfffff800, 49, 1529 "2sb20in40hrpo 2sb20in80and160hr5glpo " 1530 "2sb40and80hr5glpo 2sb20in80and160hr5gmpo 2sb40and80hr5gmpo " 1531 "2sb20in80and160hr5ghpo " 1532 "2sb40and80hr5ghpo 2sb20in40lrpo 2sb20in80and160lr5glpo " 1533 "2sb40and80lr5glpo " 1534 "2sb20in80and160lr5gmpo 2sb40and80lr5gmpo 2sb20in80and160lr5ghpo " 1535 "2sb40and80lr5ghpo " 1536 "4dot11agduphrpo 4dot11agduplrpo 2sb20in40and80hrpo " 1537 "2sb20in40and80lrpo " 1538 "2sb20in80and160hr5gx1po 2sb20in80and160lr5gx1po 2sb40and80hr5gx1po " 1539 "2sb40and80lr5gx1po "}, 1540 {HNBU_ACPPR_SB8080_PO, 0xfffff800, 23, 1541 "2sb2040and80in80p80hr5glpo " 1542 "2sb2040and80in80p80lr5glpo 2sb2040and80in80p80hr5gmpo " 1543 "2sb2040and80in80p80lr5gmpo 2sb2040and80in80p80hr5ghpo " 1544 "2sb2040and80in80p80lr5ghpo " 1545 "2sb2040and80in80p80hr5gx1po 2sb2040and80in80p80lr5gx1po " 1546 "2sb20in80p80hr5gpo " 1547 "2sb20in80p80lr5gpo 2dot11agduppo"}, 1548 {HNBU_NOISELVL, 0xfffff800, 16, 1549 "1noiselvl2ga0 1noiselvl2ga1 1noiselvl2ga2 " 1550 "1*4noiselvl5ga0 1*4noiselvl5ga1 1*4noiselvl5ga2"}, 1551 {HNBU_RXGAIN_ERR, 0xfffff800, 16, 1552 "1rxgainerr2ga0 1rxgainerr2ga1 1rxgainerr2ga2 " 1553 "1*4rxgainerr5ga0 1*4rxgainerr5ga1 1*4rxgainerr5ga2"}, 1554 {HNBU_AGBGA, 0xfffff800, 7, "1agbg0 1agbg1 1agbg2 1aga0 1aga1 1aga2"}, 1555 {HNBU_USBDESC_COMPOSITE, 0xffffffff, 3, "2usbdesc_composite"}, 1556 {HNBU_UUID, 0xffffffff, 17, "16uuid"}, 1557 {HNBU_WOWLGPIO, 0xffffffff, 2, "1wowl_gpio"}, 1558 {HNBU_ACRXGAINS_C0, 0xfffff800, 5, 1559 "0rxgains5gtrelnabypa0 0rxgains5gtrisoa0 " 1560 "0rxgains5gelnagaina0 0rxgains2gtrelnabypa0 0rxgains2gtrisoa0 " 1561 "0rxgains2gelnagaina0 " 1562 "0rxgains5ghtrelnabypa0 0rxgains5ghtrisoa0 0rxgains5ghelnagaina0 " 1563 "0rxgains5gmtrelnabypa0 " 1564 "0rxgains5gmtrisoa0 0rxgains5gmelnagaina0"}, /* special case */ 1565 {HNBU_ACRXGAINS_C1, 0xfffff800, 5, 1566 "0rxgains5gtrelnabypa1 0rxgains5gtrisoa1 " 1567 "0rxgains5gelnagaina1 0rxgains2gtrelnabypa1 0rxgains2gtrisoa1 " 1568 "0rxgains2gelnagaina1 " 1569 "0rxgains5ghtrelnabypa1 0rxgains5ghtrisoa1 0rxgains5ghelnagaina1 " 1570 "0rxgains5gmtrelnabypa1 " 1571 "0rxgains5gmtrisoa1 0rxgains5gmelnagaina1"}, /* special case */ 1572 {HNBU_ACRXGAINS_C2, 0xfffff800, 5, 1573 "0rxgains5gtrelnabypa2 0rxgains5gtrisoa2 " 1574 "0rxgains5gelnagaina2 0rxgains2gtrelnabypa2 0rxgains2gtrisoa2 " 1575 "0rxgains2gelnagaina2 " 1576 "0rxgains5ghtrelnabypa2 0rxgains5ghtrisoa2 0rxgains5ghelnagaina2 " 1577 "0rxgains5gmtrelnabypa2 " 1578 "0rxgains5gmtrisoa2 0rxgains5gmelnagaina2"}, /* special case */ 1579 {HNBU_TXDUTY, 0xfffff800, 9, 1580 "2tx_duty_cycle_ofdm_40_5g " 1581 "2tx_duty_cycle_thresh_40_5g 2tx_duty_cycle_ofdm_80_5g " 1582 "2tx_duty_cycle_thresh_80_5g"}, 1583 {HNBU_PDOFF_2G, 0xfffff800, 3, 1584 "0pdoffset2g40ma0 0pdoffset2g40ma1 " 1585 "0pdoffset2g40ma2 0pdoffset2g40mvalid"}, 1586 {HNBU_ACPA_CCK_C0, 0xfffff800, 7, "2*3pa2gccka0"}, 1587 {HNBU_ACPA_CCK_C1, 0xfffff800, 7, "2*3pa2gccka1"}, 1588 {HNBU_ACPA_40, 0xfffff800, 25, "2*12pa5gbw40a0"}, 1589 {HNBU_ACPA_80, 0xfffff800, 25, "2*12pa5gbw80a0"}, 1590 {HNBU_ACPA_4080, 0xfffff800, 49, "2*12pa5gbw4080a0 2*12pa5gbw4080a1"}, 1591 {HNBU_ACPA_4X4C0, 0xffffe000, 23, 1592 "1maxp2ga0 2*4pa2ga0 2*4pa2g40a0 " 1593 "1maxp5gb0a0 1maxp5gb1a0 1maxp5gb2a0 1maxp5gb3a0 1maxp5gb4a0"}, 1594 {HNBU_ACPA_4X4C1, 0xffffe000, 23, 1595 "1maxp2ga1 2*4pa2ga1 2*4pa2g40a1 " 1596 "1maxp5gb0a1 1maxp5gb1a1 1maxp5gb2a1 1maxp5gb3a1 1maxp5gb4a1"}, 1597 {HNBU_ACPA_4X4C2, 0xffffe000, 23, 1598 "1maxp2ga2 2*4pa2ga2 2*4pa2g40a2 " 1599 "1maxp5gb0a2 1maxp5gb1a2 1maxp5gb2a2 1maxp5gb3a2 1maxp5gb4a2"}, 1600 {HNBU_ACPA_4X4C3, 0xffffe000, 23, 1601 "1maxp2ga3 2*4pa2ga3 2*4pa2g40a3 " 1602 "1maxp5gb0a3 1maxp5gb1a3 1maxp5gb2a3 1maxp5gb3a3 1maxp5gb4a3"}, 1603 {HNBU_ACPA_BW20_4X4C0, 0xffffe000, 41, "2*20pa5ga0"}, 1604 {HNBU_ACPA_BW40_4X4C0, 0xffffe000, 41, "2*20pa5g40a0"}, 1605 {HNBU_ACPA_BW80_4X4C0, 0xffffe000, 41, "2*20pa5g80a0"}, 1606 {HNBU_ACPA_BW20_4X4C1, 0xffffe000, 41, "2*20pa5ga1"}, 1607 {HNBU_ACPA_BW40_4X4C1, 0xffffe000, 41, "2*20pa5g40a1"}, 1608 {HNBU_ACPA_BW80_4X4C1, 0xffffe000, 41, "2*20pa5g80a1"}, 1609 {HNBU_ACPA_BW20_4X4C2, 0xffffe000, 41, "2*20pa5ga2"}, 1610 {HNBU_ACPA_BW40_4X4C2, 0xffffe000, 41, "2*20pa5g40a2"}, 1611 {HNBU_ACPA_BW80_4X4C2, 0xffffe000, 41, "2*20pa5g80a2"}, 1612 {HNBU_ACPA_BW20_4X4C3, 0xffffe000, 41, "2*20pa5ga3"}, 1613 {HNBU_ACPA_BW40_4X4C3, 0xffffe000, 41, "2*20pa5g40a3"}, 1614 {HNBU_ACPA_BW80_4X4C3, 0xffffe000, 41, "2*20pa5g80a3"}, 1615 {HNBU_SUBBAND5GVER, 0xfffff800, 3, "2subband5gver"}, 1616 {HNBU_PAPARAMBWVER, 0xfffff800, 2, "1paparambwver"}, 1617 {HNBU_TXBFRPCALS, 0xfffff800, 11, 1618 "2rpcal2g 2rpcal5gb0 2rpcal5gb1 2rpcal5gb2 2rpcal5gb3"}, /* txbf 1619 rpcalvars 1620 */ 1621 {HNBU_GPIO_PULL_DOWN, 0xffffffff, 5, "4gpdn"}, 1622 {HNBU_MACADDR2, 0xffffffff, 7, "6macaddr2"}, /* special case */ 1623 {0xFF, 0xffffffff, 0, ""}}; 1624 1625 #endif /* _bcmsrom_tbl_h_ */ 1626