1 /* 2 * pcicfg.h: PCI configuration constants and structures. 3 * 4 * Copyright (C) 1999-2019, Broadcom. 5 * 6 * Unless you and Broadcom execute a separate written software license 7 * agreement governing use of this software, this software is licensed to you 8 * under the terms of the GNU General Public License version 2 (the "GPL"), 9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 10 * following added to such license: 11 * 12 * As a special exception, the copyright holders of this software give you 13 * permission to link this software with independent modules, and to copy and 14 * distribute the resulting executable under terms of your choice, provided that 15 * you also meet, for each linked independent module, the terms and conditions 16 * of the license of that module. An independent module is a module which is 17 * not derived from this software. The special exception does not apply to any 18 * modifications of the software. 19 * 20 * Notwithstanding the above, under no circumstances may you combine this 21 * software in any way with any other Broadcom software provided under a license 22 * other than the GPL, without Broadcom's express prior written consent. 23 * 24 * 25 * <<Broadcom-WL-IPTag/Open:>> 26 * 27 * $Id: pcicfg.h 795237 2018-12-18 03:26:49Z $ 28 */ 29 30 #ifndef _h_pcicfg_ 31 #define _h_pcicfg_ 32 33 /* pci config status reg has a bit to indicate that capability ptr is present */ 34 35 #define PCI_CAPPTR_PRESENT 0x0010 36 37 /* A structure for the config registers is nice, but in most 38 * systems the config space is not memory mapped, so we need 39 * field offsetts. :-( 40 */ 41 #define PCI_CFG_VID 0 42 #define PCI_CFG_DID 2 43 #define PCI_CFG_CMD 4 44 #define PCI_CFG_STAT 6 45 #define PCI_CFG_REV 8 46 #define PCI_CFG_PROGIF 9 47 #define PCI_CFG_SUBCL 0xa 48 #define PCI_CFG_BASECL 0xb 49 #define PCI_CFG_CLSZ 0xc 50 #define PCI_CFG_LATTIM 0xd 51 #define PCI_CFG_HDR 0xe 52 #define PCI_CFG_BIST 0xf 53 #define PCI_CFG_BAR0 0x10 54 /* 55 * PCI_CFG_BAR1 is wrongly defined to be 0x14 whereas it should be 56 * 0x18 as per the PCIe full dongle spec. Need to modify the values below 57 * correctly at a later point of time 58 */ 59 #define PCI_CFG_BAR1 0x14 60 #define PCI_CFG_BAR2 0x18 61 #define PCI_CFG_BAR3 0x1c 62 #define PCI_CFG_BAR4 0x20 63 #define PCI_CFG_BAR5 0x24 64 #define PCI_CFG_CIS 0x28 65 #define PCI_CFG_SVID 0x2c 66 #define PCI_CFG_SSID 0x2e 67 #define PCI_CFG_ROMBAR 0x30 68 #define PCI_CFG_CAPPTR 0x34 69 #define PCI_CFG_INT 0x3c 70 #define PCI_CFG_PIN 0x3d 71 #define PCI_CFG_MINGNT 0x3e 72 #define PCI_CFG_MAXLAT 0x3f 73 #define PCI_CFG_DEVCTRL 0xd8 74 #define PCI_CFG_TLCNTRL_5 0x814 75 76 /* PCI CAPABILITY DEFINES */ 77 #define PCI_CAP_POWERMGMTCAP_ID 0x01 78 #define PCI_CAP_MSICAP_ID 0x05 79 #define PCI_CAP_VENDSPEC_ID 0x09 80 #define PCI_CAP_PCIECAP_ID 0x10 81 #define PCI_CAP_MSIXCAP_ID 0x11 82 83 /* Data structure to define the Message Signalled Interrupt facility 84 * Valid for PCI and PCIE configurations 85 */ 86 typedef struct _pciconfig_cap_msi { 87 uint8 capID; 88 uint8 nextptr; 89 uint16 msgctrl; 90 uint32 msgaddr; 91 } pciconfig_cap_msi; 92 #define MSI_ENABLE 0x1 /* bit 0 of msgctrl */ 93 94 /* Data structure to define the Power managment facility 95 * Valid for PCI and PCIE configurations 96 */ 97 typedef struct _pciconfig_cap_pwrmgmt { 98 uint8 capID; 99 uint8 nextptr; 100 uint16 pme_cap; 101 uint16 pme_sts_ctrl; 102 uint8 pme_bridge_ext; 103 uint8 data; 104 } pciconfig_cap_pwrmgmt; 105 106 #define PME_CAP_PM_STATES \ 107 (0x1f << 27) /* Bits 31:27 states that can generate PME */ 108 #define PME_CSR_OFFSET 0x4 /* 4-bytes offset */ 109 #define PME_CSR_PME_EN (1 << 8) /* Bit 8 Enable generating of PME */ 110 #define PME_CSR_PME_STAT (1 << 15) /* Bit 15 PME got asserted */ 111 112 /* Data structure to define the PCIE capability */ 113 typedef struct _pciconfig_cap_pcie { 114 uint8 capID; 115 uint8 nextptr; 116 uint16 pcie_cap; 117 uint32 dev_cap; 118 uint16 dev_ctrl; 119 uint16 dev_status; 120 uint32 link_cap; 121 uint16 link_ctrl; 122 uint16 link_status; 123 uint32 slot_cap; 124 uint16 slot_ctrl; 125 uint16 slot_status; 126 uint16 root_ctrl; 127 uint16 root_cap; 128 uint32 root_status; 129 } pciconfig_cap_pcie; 130 131 /* PCIE Enhanced CAPABILITY DEFINES */ 132 #define PCIE_EXTCFG_OFFSET 0x100 133 #define PCIE_ADVERRREP_CAPID 0x0001 134 #define PCIE_VC_CAPID 0x0002 135 #define PCIE_DEVSNUM_CAPID 0x0003 136 #define PCIE_PWRBUDGET_CAPID 0x0004 137 138 /* PCIE Extended configuration */ 139 #define PCIE_ADV_CORR_ERR_MASK 0x114 140 #define PCIE_ADV_CORR_ERR_MASK_OFFSET 0x14 141 #define CORR_ERR_RE (1 << 0) /* Receiver */ 142 #define CORR_ERR_BT (1 << 6) /* Bad TLP */ 143 #define CORR_ERR_BD (1 << 7) /* Bad DLLP */ 144 #define CORR_ERR_RR (1 << 8) /* REPLAY_NUM rollover */ 145 #define CORR_ERR_RT (1 << 12) /* Reply timer timeout */ 146 #define CORR_ERR_AE (1 << 13) /* Adviosry Non-Fital Error Mask */ 147 #define ALL_CORR_ERRORS \ 148 (CORR_ERR_RE | CORR_ERR_BT | CORR_ERR_BD | CORR_ERR_RR | CORR_ERR_RT) 149 150 /* PCIE Root Control Register bits (Host mode only) */ 151 #define PCIE_RC_CORR_SERR_EN 0x0001 152 #define PCIE_RC_NONFATAL_SERR_EN 0x0002 153 #define PCIE_RC_FATAL_SERR_EN 0x0004 154 #define PCIE_RC_PME_INT_EN 0x0008 155 #define PCIE_RC_CRS_EN 0x0010 156 157 /* PCIE Root Capability Register bits (Host mode only) */ 158 #define PCIE_RC_CRS_VISIBILITY 0x0001 159 160 /* PCIe PMCSR Register bits */ 161 #define PCIE_PMCSR_PMESTAT 0x8000 162 163 /* Header to define the PCIE specific capabilities in the extended config space 164 */ 165 typedef struct _pcie_enhanced_caphdr { 166 uint16 capID; 167 uint16 cap_ver : 4; 168 uint16 next_ptr : 12; 169 } pcie_enhanced_caphdr; 170 171 #define PCIE_CFG_PMCSR 0x4C 172 #define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */ 173 #define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */ 174 #define PCI_SPROM_CONTROL 0x88 /* sprom property control */ 175 #define PCIE_CFG_SUBSYSTEM_CONTROL \ 176 0x88 /* used as subsystem control in PCIE devices */ 177 #define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */ 178 #define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */ 179 #define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */ 180 #define PCI_TO_SB_MB 0x98 /* signal backplane interrupts */ 181 #define PCI_BACKPLANE_ADDR \ 182 0xa0 /* address an arbitrary location on the system backplane */ 183 #define PCI_BACKPLANE_DATA \ 184 0xa4 /* data at the location specified by above address */ 185 #define PCI_CLK_CTL_ST \ 186 0xa8 /* pci config space clock control/status (>=rev14) */ 187 #define PCI_BAR0_WIN2 \ 188 0xac /* backplane addres space accessed by second 4KB of BAR0 */ 189 #define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */ 190 #define PCIE_CFG_DEVICE_CAPABILITY \ 191 0xb0 /* used as device capability in PCIE devices */ 192 #define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */ 193 #define PCIE_CFG_DEVICE_CONTROL \ 194 0xb4 /* 0xb4 is used as device control in PCIE devices */ 195 #define PCIE_DC_AER_CORR_EN (1u << 0u) 196 #define PCIE_DC_AER_NON_FATAL_EN (1u << 1u) 197 #define PCIE_DC_AER_FATAL_EN (1u << 2u) 198 #define PCIE_DC_AER_UNSUP_EN (1u << 3u) 199 200 #define PCI_BAR0_WIN2_OFFSET 0x1000u 201 #define PCIE2_BAR0_CORE2_WIN2_OFFSET 0x5000u 202 203 #define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */ 204 #define PCI_L1SS_CTRL2 0x24c /* The L1 PM Substates Control register */ 205 206 /* Private Registers */ 207 #define PCI_STAT_CTRL 0xa80 208 #define PCI_L0_EVENTCNT 0xa84 209 #define PCI_L0_STATETMR 0xa88 210 #define PCI_L1_EVENTCNT 0xa8c 211 #define PCI_L1_STATETMR 0xa90 212 #define PCI_L1_1_EVENTCNT 0xa94 213 #define PCI_L1_1_STATETMR 0xa98 214 #define PCI_L1_2_EVENTCNT 0xa9c 215 #define PCI_L1_2_STATETMR 0xaa0 216 #define PCI_L2_EVENTCNT 0xaa4 217 #define PCI_L2_STATETMR 0xaa8 218 219 #define PCI_LINK_STATUS 0x4dc 220 #define PCI_LINK_SPEED_MASK (15u << 0u) 221 #define PCI_LINK_SPEED_SHIFT (0) 222 #define PCIE_LNK_SPEED_GEN1 0x1 223 #define PCIE_LNK_SPEED_GEN2 0x2 224 #define PCIE_LNK_SPEED_GEN3 0x3 225 226 #define PCI_PL_SPARE \ 227 0x1808 /* Config to Increase external clkreq deasserted minimum time */ 228 #define PCI_CONFIG_EXT_CLK_MIN_TIME_MASK (1u << 31u) 229 #define PCI_CONFIG_EXT_CLK_MIN_TIME_SHIFT (31) 230 231 #define PCI_ADV_ERR_CAP 0x100 232 #define PCI_UC_ERR_STATUS 0x104 233 #define PCI_UNCORR_ERR_MASK 0x108 234 #define PCI_UCORR_ERR_SEVR 0x10c 235 #define PCI_CORR_ERR_STATUS 0x110 236 #define PCI_CORR_ERR_MASK 0x114 237 #define PCI_ERR_CAP_CTRL 0x118 238 #define PCI_TLP_HDR_LOG1 0x11c 239 #define PCI_TLP_HDR_LOG2 0x120 240 #define PCI_TLP_HDR_LOG3 0x124 241 #define PCI_TLP_HDR_LOG4 0x128 242 #define PCI_TL_CTRL_5 0x814 243 #define PCI_TL_HDR_FC_ST 0x980 244 #define PCI_TL_TGT_CRDT_ST 0x990 245 #define PCI_TL_SMLOGIC_ST 0x998 246 #define PCI_DL_ATTN_VEC 0x1040 247 #define PCI_DL_STATUS 0x1048 248 249 #define PCI_PHY_CTL_0 0x1800 250 #define PCI_SLOW_PMCLK_EXT_RLOCK (1 << 7) 251 252 #define PCI_LINK_STATE_DEBUG 0x1c24 253 #define PCI_RECOVERY_HIST 0x1ce4 254 #define PCI_PHY_LTSSM_HIST_0 0x1cec 255 #define PCI_PHY_LTSSM_HIST_1 0x1cf0 256 #define PCI_PHY_LTSSM_HIST_2 0x1cf4 257 #define PCI_PHY_LTSSM_HIST_3 0x1cf8 258 #define PCI_PHY_DBG_CLKREG_0 0x1e10 259 #define PCI_PHY_DBG_CLKREG_1 0x1e14 260 #define PCI_PHY_DBG_CLKREG_2 0x1e18 261 #define PCI_PHY_DBG_CLKREG_3 0x1e1c 262 263 /* Bit settings for PCIE_CFG_SUBSYSTEM_CONTROL register */ 264 #define PCIE_BAR1COHERENTACCEN_BIT 8 265 #define PCIE_BAR2COHERENTACCEN_BIT 9 266 #define PCIE_SSRESET_STATUS_BIT 13 267 #define PCIE_SSRESET_DISABLE_BIT 14 268 #define PCIE_SSRESET_DIS_ENUM_RST_BIT 15 269 270 #define PCIE_BARCOHERENTACCEN_MASK 0x300 271 272 /* Bit settings for PCI_UC_ERR_STATUS register */ 273 #define PCI_UC_ERR_URES (1 << 20) /* Unsupported Request Error Status */ 274 #define PCI_UC_ERR_ECRCS (1 << 19) /* ECRC Error Status */ 275 #define PCI_UC_ERR_MTLPS (1 << 18) /* Malformed TLP Status */ 276 #define PCI_UC_ERR_ROS (1 << 17) /* Receiver Overflow Status */ 277 #define PCI_UC_ERR_UCS (1 << 16) /* Unexpected Completion Status */ 278 #define PCI_UC_ERR_CAS (1 << 15) /* Completer Abort Status */ 279 #define PCI_UC_ERR_CTS (1 << 14) /* Completer Timeout Status */ 280 #define PCI_UC_ERR_FCPES (1 << 13) /* Flow Control Protocol Error Status */ 281 #define PCI_UC_ERR_PTLPS (1 << 12) /* Poisoned TLP Status */ 282 #define PCI_UC_ERR_DLPES (1 << 4) /* Data Link Protocol Error Status */ 283 284 #define PCI_DL_STATUS_PHY_LINKUP (1 << 13) /* Status of LINK */ 285 286 #define PCI_PMCR_REFUP 0x1814 /* Trefup time */ 287 #define PCI_PMCR_TREFUP_LO_MASK 0x3f 288 #define PCI_PMCR_TREFUP_LO_SHIFT 24 289 #define PCI_PMCR_TREFUP_LO_BITS 6 290 #define PCI_PMCR_TREFUP_HI_MASK 0xf 291 #define PCI_PMCR_TREFUP_HI_SHIFT 5 292 #define PCI_PMCR_TREFUP_HI_BITS 4 293 #define PCI_PMCR_TREFUP_MAX 0x400 294 #define PCI_PMCR_TREFUP_MAX_SCALE 0x2000 295 296 #define PCI_PMCR_REFUP_EXT 0x1818 /* Trefup extend Max */ 297 #define PCI_PMCR_TREFUP_EXT_SHIFT 22 298 #define PCI_PMCR_TREFUP_EXT_SCALE 3 299 #define PCI_PMCR_TREFUP_EXT_ON 1 300 #define PCI_PMCR_TREFUP_EXT_OFF 0 301 302 #define PCI_TPOWER_SCALE_MASK 0x3 303 #define PCI_TPOWER_SCALE_SHIFT 3 /* 0:1 is scale and 2 is rsvd */ 304 305 #define PCI_BAR0_SHADOW_OFFSET \ 306 (2 * 1024) /* bar0 + 2K accesses sprom shadow (in pci core) */ 307 #define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom \ 308 */ 309 #define PCI_BAR0_PCIREGS_OFFSET \ 310 (6 * 1024) /* bar0 + 6K accesses pci core registers */ 311 #define PCI_BAR0_PCISBR_OFFSET \ 312 (4 * 1024) /* pci core SB registers are at the end of the \ 313 * 8KB window, so their address is the "regular" \ 314 * address plus 4K \ 315 */ 316 /* 317 * PCIE GEN2 changed some of the above locations for 318 * Bar0WrapperBase, SecondaryBAR0Window and SecondaryBAR0WrapperBase 319 * BAR0 maps 32K of register space 320 */ 321 #define PCIE2_BAR0_WIN2 \ 322 0x70 /* backplane addres space accessed by second 4KB of BAR0 */ 323 #define PCIE2_BAR0_CORE2_WIN \ 324 0x74 /* backplane addres space accessed by second 4KB of BAR0 */ 325 #define PCIE2_BAR0_CORE2_WIN2 \ 326 0x78 /* backplane addres space accessed by second 4KB of BAR0 */ 327 #define PCIE2_BAR0_WINSZ 0x8000 328 329 #define PCI_BAR0_WIN2_OFFSET 0x1000u 330 #define PCI_CORE_ENUM_OFFSET 0x2000u 331 #define PCI_CC_CORE_ENUM_OFFSET 0x3000u 332 #define PCI_SEC_BAR0_WIN_OFFSET 0x4000u 333 #define PCI_SEC_BAR0_WRAP_OFFSET 0x5000u 334 #define PCI_CORE_ENUM2_OFFSET 0x6000u 335 #define PCI_CC_CORE_ENUM2_OFFSET 0x7000u 336 #define PCI_LAST_OFFSET 0x8000u 337 338 #define PCI_BAR0_WINSZ (16 * 1024) /* bar0 window size Match with corerev 13 \ 339 */ 340 /* On pci corerev >= 13 and all pcie, the bar0 is now 16KB and it maps: */ 341 #define PCI_16KB0_PCIREGS_OFFSET \ 342 (8 * 1024) /* bar0 + 8K accesses pci/pcie core registers */ 343 #define PCI_16KB0_CCREGS_OFFSET \ 344 (12 * 1024) /* bar0 + 12K accesses chipc core registers */ 345 #define PCI_16KBB0_WINSZ (16 * 1024) /* bar0 window size */ 346 #define PCI_SECOND_BAR0_OFFSET (16 * 1024) /* secondary bar 0 window */ 347 348 /* On AI chips we have a second window to map DMP regs are mapped: */ 349 #define PCI_16KB0_WIN2_OFFSET (4 * 1024) /* bar0 + 4K is "Window 2" */ 350 351 /* PCI_INT_STATUS */ 352 #define PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */ 353 354 /* PCI_INT_MASK */ 355 #define PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */ 356 #define PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */ 357 #define PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */ 358 #define PCI_CTO_INT_SHIFT 16 /* backplane SBErr interrupt mask */ 359 #define PCI_CTO_INT_MASK \ 360 (1 << PCI_CTO_INT_SHIFT) /* backplane SBErr interrupt mask */ 361 362 /* PCI_SPROM_CONTROL */ 363 #define SPROM_SZ_MSK 0x02 /* SPROM Size Mask */ 364 #define SPROM_LOCKED 0x08 /* SPROM Locked */ 365 #define SPROM_BLANK 0x04 /* indicating a blank SPROM */ 366 #define SPROM_WRITEEN 0x10 /* SPROM write enable */ 367 #define SPROM_BOOTROM_WE 0x20 /* external bootrom write enable */ 368 #define SPROM_BACKPLANE_EN 0x40 /* Enable indirect backplane access */ 369 #define SPROM_OTPIN_USE 0x80 /* device OTP In use */ 370 #define SPROM_CFG_TO_SB_RST 0x400 /* backplane reset */ 371 372 /* Bits in PCI command and status regs */ 373 #define PCI_CMD_IO 0x00000001 /* I/O enable */ 374 #define PCI_CMD_MEMORY 0x00000002 /* Memory enable */ 375 #define PCI_CMD_MASTER 0x00000004 /* Master enable */ 376 #define PCI_CMD_SPECIAL 0x00000008 /* Special cycles enable */ 377 #define PCI_CMD_INVALIDATE 0x00000010 /* Invalidate? */ 378 #define PCI_CMD_VGA_PAL 0x00000040 /* VGA Palate */ 379 #define PCI_STAT_TA 0x08000000 /* target abort status */ 380 381 /* Header types */ 382 #define PCI_HEADER_MULTI 0x80 383 #define PCI_HEADER_MASK 0x7f 384 typedef enum { 385 PCI_HEADER_NORMAL, 386 PCI_HEADER_BRIDGE, 387 PCI_HEADER_CARDBUS 388 } pci_header_types; 389 390 #define PCI_CONFIG_SPACE_SIZE 256 391 392 #define DWORD_ALIGN(x) (x & ~(0x03)) 393 #define BYTE_POS(x) (x & 0x3) 394 #define WORD_POS(x) (x & 0x1) 395 396 #define BYTE_SHIFT(x) (8 * BYTE_POS(x)) 397 #define WORD_SHIFT(x) (16 * WORD_POS(x)) 398 399 #define BYTE_VAL(a, x) ((a >> BYTE_SHIFT(x)) & 0xFF) 400 #define WORD_VAL(a, x) ((a >> WORD_SHIFT(x)) & 0xFFFF) 401 402 #define read_pci_cfg_byte(a) \ 403 (BYTE_VAL(OSL_PCI_READ_CONFIG(osh, DWORD_ALIGN(a), 4), a) & 0xff) 404 405 #define read_pci_cfg_word(a) \ 406 (WORD_VAL(OSL_PCI_READ_CONFIG(osh, DWORD_ALIGN(a), 4), a) & 0xffff) 407 408 #define write_pci_cfg_byte(a, val) \ 409 do { \ 410 uint32 tmpval; \ 411 tmpval = (OSL_PCI_READ_CONFIG(osh, DWORD_ALIGN(a), 4) & \ 412 ~0xFF << BYTE_POS(a)) | \ 413 val << BYTE_POS(a); \ 414 OSL_PCI_WRITE_CONFIG(osh, DWORD_ALIGN(a), 4, tmpval); \ 415 } while (0) 416 417 #define write_pci_cfg_word(a, val) \ 418 do { \ 419 uint32 tmpval; \ 420 tmpval = (OSL_PCI_READ_CONFIG(osh, DWORD_ALIGN(a), 4) & \ 421 ~0xFFFF << WORD_POS(a)) | \ 422 val << WORD_POS(a); \ 423 OSL_PCI_WRITE_CONFIG(osh, DWORD_ALIGN(a), 4, tmpval); \ 424 } while (0) 425 426 #endif /* _h_pcicfg_ */ 427